Si4412DY Vishay Siliconix N-Channel 30-V (D-S) Rated MOSFET FEATURES PRODUCT SUMMARY VDS (V) RDS(on) (Ω) 30 • Halogen-free According to IEC 61249-2-21 Definition • TrenchFET® Power MOSFET • Compliant to RoHS Directive 2002/95/EC ID (A) 0.028 at VGS = 10 V ± 7.0 0.042 at VGS = 4.5 V ± 5.8 SO-8 D S 1 8 D S 2 7 D S 3 6 D G 4 5 D G Top View S Ordering Information: Si4412DY-T1-E3 (Lead (Pb)-free) Si4412DY-T1-GE3 (Lead (Pb)-free and Halogen-free) N-Channel MOSFET ABSOLUTE MAXIMUM RATINGS TA = 25 °C, unless otherwise noted Parameter Symbol Limit Drain-Source Voltage VDS 30 Gate-Source Voltage VGS ± 20 Continuous Drain Current (TJ = 150 °C)a TA = 25 °C TA = 70 °C Pulsed Drain Current Continuous Source Current (Diode Conduction)a Maximum Power Dissipationa Operating Junction and Storage Temperature Range TA = 25 °C TA = 70 °C ID V ± 7.0 ± 5.8 IDM ± 30 IS 2.3 PD Unit 2.5 1.6 A W TJ, Tstg - 55 to 150 Symbol Limit Unit RthJA 50 °C/W °C THERMAL RESISTANCE RATINGS Parameter Maximum Junction-to-Ambienta Notes: a. Surface Mounted on FR4 board, t ≤ 10 s. Document Number: 70154 S09-0705-Rev. D, 27-Apr-09 www.vishay.com 1 Si4412DY Vishay Siliconix SPECIFICATIONS TJ = 25 °C, unless otherwise noted Parameter Symbol Test Conditions Min. 1.0 Typ.a Max. Unit ± 100 nA Static VGS(th) VDS = VGS, ID = 250 µA Gate-Body Leakage IGSS VDS = 0 V, VGS = ± 20 V Zero Gate Voltage Drain Current IDSS On-State Drain Currentb ID(on) Gate Threshold Voltage Drain-Source On-State Resistanceb Forward Transconductanceb Diode Forward Voltageb RDS(on) V VDS = 30 V, VGS = 0 V 2 VDS = 30 V, VGS = 0 V, TJ = 55 °C 25 VDS ≥ 5 V, VGS = 10 V 30 µA A VGS = 10 V, ID = 7.0 A 0.021 0.028 VGS = 4.5 V, ID = 3.5 A 0.030 0.042 gfs VDS = 15 V, ID = 7.0 A 16 VSD IS = 2 A, VGS = 0 V 0.75 1.1 19.5 29 Ω S V Dynamica Total Gate Charge Qg Gate-Source Charge Qgs Gate-Drain Charge Qgd 2.7 Turn-On Delay Time td(on) 9 Rise Time Turn-Off Delay Time tr td(off) Fall Time tf Source-Drain Reverse Recovery Time trr VDS = 15 V, VGS = 10 V, ID = 2 A VDD = 25 V, RL = 25 Ω ID ≅ 1 A, VGEN = 10 V, Rg = 6 Ω IF = 2 A, dI/dt = 100 A/µs nC 3.4 15 12 20 38 55 19 28 45 80 ns Notes: a. Guaranteed by design, not subject to production testing. b. Pulse test; pulse width ≤ 300 µs, duty cycle ≤ 2 %. Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. www.vishay.com 2 Document Number: 70154 S09-0705-Rev. D, 27-Apr-09 Si4412DY Vishay Siliconix TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted 30 30 V GS = 10 V, 9 V, 8 V, 7 V, 6 V, 5 V 4V 24 I D - Drain Current (A) I D - Drain Current (A) 24 18 12 6 18 12 6 TC = 125 °C 3V 25 °C 0 0 1 2 3 4 5 0 1 V DS - Drain-to-Source Voltage (V) 2 3 4 5 6 VGS - Gate-to-Source Voltage (V) Output Characteristics Transfer Characteristics 0.05 1500 0.04 1200 C - Capacitance (pF) R DS(on) - On-Resistance (Ω) - 55 °C 0 VGS = 4.5 V 0.03 VGS = 10 V 0.02 C iss 900 C oss 600 300 0.01 C rss 0 0 0 6 12 18 24 30 0 6 12 24 30 VDS - Drain-to-Source Voltage (V) I D - Drain Current (A) On-Resistance vs. Drain Current Capacitance 10 2.0 VDS = 15 V ID = 2 A 1.6 6 4 2 ( Nor m al i zed) 8 R DS(on) - O n- Resistance VGS - Gate-to-Source Voltage (V) 18 VGS = 10 V ID = 7 A 1.2 0.8 0.4 0 0 4 8 12 Q g - Total Gate Charge (nC) Gate Charge Document Number: 70154 S09-0705-Rev. D, 27-Apr-09 16 20 0 - 50 - 25 0 25 50 75 100 125 150 TJ - Junction Temperature (°C) On-Resistance vs. Junction Temperature www.vishay.com 3 Si4412DY Vishay Siliconix TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted 0.10 RDS(on) - On-Resistance (Ω) I S - Source Current (A) 30 10 T J = 150 °C TJ = 25 °C 0.08 0.06 0.04 ID = 7 A 0.02 0 1 0 0.2 0.4 0.6 0.8 1.0 1.2 0 1.4 4 6 8 10 VSD - Source-to-Drain Voltage (V) VGS - Gate-to-Source Voltage (V) Source-Drain Diode Forward Voltage On-Resistance vs. Gate-to-Source Voltage 50 0.4 0.2 40 I D = 250 µA 0.0 Power (W) VGS(th) Variance (V) 2 - 0.2 - 0.4 30 20 - 0.6 10 - 0.8 - 1.0 - 50 - 25 0 25 50 75 100 125 150 0 0.01 0.10 1.00 10.00 Time (s) T J - Temperature (°C) Single Pulse Power Threshold Voltage 2 N or m al i zed E f f ect iv e Tr a n si ent T her m al Im p edance 1 Duty Cycle = 0.5 0.2 Notes: 0.1 PDM 0.1 t1 0.05 t2 1. Duty Cycle, D = t1 t2 2. Per Unit Base = RthJA = 50 °C/W 3. TJM - TA = P DM ZthJA(t) 0.02 Single Pulse 4. Surface Mounted 0.01 10 -4 10 -3 10 -2 10 -1 Square Wave Pulse Duration (s) 1 10 30 Normalized Thermal Transient Impedance, Junction-to-Ambient Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability data, see www.vishay.com/ppg?70154. www.vishay.com 4 Document Number: 70154 S09-0705-Rev. D, 27-Apr-09 Package Information Vishay Siliconix SOIC (NARROW): 8-LEAD JEDEC Part Number: MS-012 8 6 7 5 E 1 3 2 H 4 S h x 45 D C 0.25 mm (Gage Plane) A e B All Leads q A1 L 0.004" MILLIMETERS INCHES DIM Min Max Min Max A 1.35 1.75 0.053 0.069 A1 0.10 0.20 0.004 0.008 B 0.35 0.51 0.014 0.020 C 0.19 0.25 0.0075 0.010 D 4.80 5.00 0.189 0.196 E 3.80 4.00 0.150 e 0.101 mm 1.27 BSC 0.157 0.050 BSC H 5.80 6.20 0.228 0.244 h 0.25 0.50 0.010 0.020 L 0.50 0.93 0.020 0.037 q 0° 8° 0° 8° S 0.44 0.64 0.018 0.026 ECN: C-06527-Rev. I, 11-Sep-06 DWG: 5498 Document Number: 71192 11-Sep-06 www.vishay.com 1 VISHAY SILICONIX TrenchFET® Power MOSFETs Application Note 808 Mounting LITTLE FOOT®, SO-8 Power MOSFETs Wharton McDaniel Surface-mounted LITTLE FOOT power MOSFETs use integrated circuit and small-signal packages which have been been modified to provide the heat transfer capabilities required by power devices. Leadframe materials and design, molding compounds, and die attach materials have been changed, while the footprint of the packages remains the same. See Application Note 826, Recommended Minimum Pad Patterns With Outline Drawing Access for Vishay Siliconix MOSFETs, (http://www.vishay.com/ppg?72286), for the basis of the pad design for a LITTLE FOOT SO-8 power MOSFET. In converting this recommended minimum pad to the pad set for a power MOSFET, designers must make two connections: an electrical connection and a thermal connection, to draw heat away from the package. 0.288 7.3 0.050 1.27 0.196 5.0 0.027 0.69 0.078 1.98 0.2 5.07 Figure 1. Single MOSFET SO-8 Pad Pattern With Copper Spreading Document Number: 70740 Revision: 18-Jun-07 0.050 1.27 0.088 2.25 0.088 2.25 0.027 0.69 0.078 1.98 0.2 5.07 Figure 2. Dual MOSFET SO-8 Pad Pattern With Copper Spreading The minimum recommended pad patterns for the single-MOSFET SO-8 with copper spreading (Figure 1) and dual-MOSFET SO-8 with copper spreading (Figure 2) show the starting point for utilizing the board area available for the heat-spreading copper. To create this pattern, a plane of copper overlies the drain pins. The copper plane connects the drain pins electrically, but more importantly provides planar copper to draw heat from the drain leads and start the process of spreading the heat so it can be dissipated into the ambient air. These patterns use all the available area underneath the body for this purpose. Since surface-mounted packages are small, and reflow soldering is the most common way in which these are affixed to the PC board, “thermal” connections from the planar copper to the pads have not been used. Even if additional planar copper area is used, there should be no problems in the soldering process. The actual solder connections are defined by the solder mask openings. By combining the basic footprint with the copper plane on the drain pins, the solder mask generation occurs automatically. A final item to keep in mind is the width of the power traces. The absolute minimum power trace width must be determined by the amount of current it has to carry. For thermal reasons, this minimum width should be at least 0.020 inches. The use of wide traces connected to the drain plane provides a low impedance path for heat to move away from the device. www.vishay.com 1 APPLICATION NOTE In the case of the SO-8 package, the thermal connections are very simple. Pins 5, 6, 7, and 8 are the drain of the MOSFET for a single MOSFET package and are connected together. In a dual package, pins 5 and 6 are one drain, and pins 7 and 8 are the other drain. For a small-signal device or integrated circuit, typical connections would be made with traces that are 0.020 inches wide. Since the drain pins serve the additional function of providing the thermal connection to the package, this level of connection is inadequate. The total cross section of the copper may be adequate to carry the current required for the application, but it presents a large thermal impedance. Also, heat spreads in a circular fashion from the heat source. In this case the drain pins are the heat sources when looking at heat spread on the PC board. 0.288 7.3 Application Note 826 Vishay Siliconix RECOMMENDED MINIMUM PADS FOR SO-8 0.172 (4.369) 0.028 0.022 0.050 (0.559) (1.270) 0.152 (3.861) 0.047 (1.194) 0.246 (6.248) (0.711) Recommended Minimum Pads Dimensions in Inches/(mm) Return to Index APPLICATION NOTE Return to Index www.vishay.com 22 Document Number: 72606 Revision: 21-Jan-08 Legal Disclaimer Notice www.vishay.com Vishay Disclaimer ALL PRODUCT, PRODUCT SPECIFICATIONS AND DATA ARE SUBJECT TO CHANGE WITHOUT NOTICE TO IMPROVE RELIABILITY, FUNCTION OR DESIGN OR OTHERWISE. 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Material Category Policy Vishay Intertechnology, Inc. hereby certifies that all its products that are identified as RoHS-Compliant fulfill the definitions and restrictions defined under Directive 2011/65/EU of The European Parliament and of the Council of June 8, 2011 on the restriction of the use of certain hazardous substances in electrical and electronic equipment (EEE) - recast, unless otherwise specified as non-compliant. Please note that some Vishay documentation may still make reference to RoHS Directive 2002/95/EC. We confirm that all the products identified as being compliant to Directive 2002/95/EC conform to Directive 2011/65/EU. Vishay Intertechnology, Inc. hereby certifies that all its products that are identified as Halogen-Free follow Halogen-Free requirements as per JEDEC JS709A standards. Please note that some Vishay documentation may still make reference to the IEC 61249-2-21 definition. We confirm that all the products identified as being compliant to IEC 61249-2-21 conform to JEDEC JS709A standards. Revision: 02-Oct-12 1 Document Number: 91000