KM23C64000T CMOS MASK ROM 64M-Bit (8Mx8 /4Mx16) CMOS MASK ROM FEATURES GENERAL DESCRIPTION • Switchable organization 8,388,608 x 8(byte mode) 4,194,304 x 16(word mode) • Fast access time : 120ns(Max.) • Supply voltage : single +5V • Current consumption Operating : 70mA(Max.) Standby : 50µA(Max.) • Fully static operation • All inputs and outputs TTL compatible • Three state outputs • Package : KM23C64000T : 44-TSOP2-400 The KM23C64000T is a fully static mask programmable ROM fabricated using silicon gate CMOS process technology, and is organized either as 8,388,608 x 8 bit(byte mode) or as 4,194,304 x 16 bit(word mode) depending on BHE voltage level.(See mode selection table) This device operates with a 5V single power supply, and all inputs and outputs are TTL compatible. Because of its asynchronous operation, it requires no external clock assuring extremely easy operation. It is suitable for use in program memory of microprocessor, and data memory, character generator. The KM23C64000T is packaged in a 44-TSOP2. FUNCTIONAL BLOCK DIAGRAM PIN CONFIGURATION A21 X BUFFERS AND DECODER . . . . . . . . MEMORY CELL MATRIX (4,194,304x16/ 8,388,608x8) Y BUFFERS AND DECODER A0 SENSE AMP. BUFFERS A21 1 44 A20 A18 2 43 A19 A17 3 42 A8 A7 4 41 A9 A6 5 40 A10 A5 6 39 A11 A4 7 38 A12 A3 8 37 A13 A2 9 36 A14 A1 10 A0 A-1 . . . CE Q0/Q8 CONTROL LOGIC OE Pin Function A0 - A21 Address Inputs Q0 - Q14 Data Outputs Q15 /A-1 Output 15(Word mode)/ LSB Address(Byte mode) BHE 35 A15 TSOP2 Word/Byte selection CE Chip Enable OE Output Enable VCC Power (+5V) VSS Ground 34 A16 CE 12 33 BHE VSS 13 32 VSS OE 14 31 Q15/A-1 Q0 15 30 Q7 Q8 16 29 Q14 Q1 17 BHE Pin Name Q7/Q 15 11 28 Q6 Q9 18 27 Q13 Q2 19 26 Q5 Q10 20 25 Q12 24 Q4 Q3 21 Q11 22 23 VCC KM23C64000T KM23C64000T CMOS MASK ROM ABSOLUTE MAXIMUM RATINGS Item Symbol Rating Unit Remark VIN -0.3 to +4.5 V - Voltage on Any Pin Relative to VSS Temperature Under Bias TBIAS -10 to +85 °C - Storage Temperature TSTG -55 to +150 °C - NOTE : Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded. Functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS(Voltage reference to VSS, TA= 0 Item to 70°C) Symbol Min Typ Max Unit Supply Voltage VCC 4.5 5.0 5.5 V Supply Voltage VSS 0 0 0 V DC CHARACTERISTICS Min Max Unit Operating Current Parameter Symbol ICC CE=OE=VIL, all outputs open - 70 mA Standby Current(TTL) ISB1 CE=VIH, all outputs open - 1 mA Standby Current(CMOS) ISB2 CE=VCC, all outputs open - 50 µA ILI VIN=0 to VCC - 10 µA Output Leakage Current ILO VOUT=0 to VCC Input High Voltage, All Inputs VIH Input Leakage Current Test Conditions - 10 µA 2.2 VCC+0.3 V Input Low Voltage, All Inputs VIL -0.3 0.8 V Output High Voltage Level VOH IOH=-400µA 2.4 - V Output Low Voltage Level VOL IOL=2.1mA - 0.4 V NOTE : Minimum DC Voltage(VIL) is -0.3V an input pins. During transitions, this level may undershoot to -2.0V for periods <20ns. Maximum DC voltage on input pins(VIH ) is VCC+0.3V which, during transitions, may overshoot to VCC+2.0V for periods <20ns. MODE SELECTION CE OE BHE Q15/A-1 H X X L H X H L L L Mode Data Power X Standby High-Z Standby X Operating High-Z Active Output Operating Q0~Q15 : Dout Active Operating Q0~Q7 : Dout Q8~Q14 : High-Z Active Input CAPACITANCE(TA=25°C, f=1.0MHz) Item Output Capacitance Input Capacitance Symbol Test Conditions COUT VOUT=0V - 12 pF CIN VIN=0V - 12 pF NOTE : Capacitance is periodically sampled and not 100% tested. Min Max Unit KM23C64000T CMOS MASK ROM AC CHARACTERISTICS(TA= 0 to 70°C, VCC=5V±10%, unless otherwise noted.) TEST CONDITIONS Item Value Input Pulse Levels 0.6V to 2.4V Input Rise and Fall Times 10ns Input and Output timing Levels 0.8V and 2.0V Output Loads 1 TTL Gate and CL=100pF READ CYCLE Item Symbol KM23C64000T-12 KM23C64000T-15 Min Min Max 120 Max 150 Unit Read Cycle Time tRC Chip Enable Access Time tACE 120 150 ns Address Access Time tAA 120 150 ns Output Enable Access Time tOE 60 70 ns Output or Chip Disable to Output High-Z tDF 20 30 ns Output Hold from Address Change tOH 0 ns 0 ns TIMING DIAGRAM READ ADD A0~A21 A-1(*1) ADD2 ADD1 tRC tDF(*3) tACE CE tOE tAA OE tOH DOUT D0~D7 D8~D15(*2) VALID DATA VALID DATA NOTES : *1. Byte Mode only. A-1 is Least Significant Bit Address.(BHE = VIL) *2. Word Mode only.(BHE=VIH) *3. tDF is defined as the time at which the outputs achieve the open circuit condition and is not referenced to V OH or VOL level. KM23C64000T CMOS MASK ROM PACKAGE DIMENSIONS (Unit : mm/inch) 44-TSOP2-400 0~8° 0.25 ( ) 0.010 #44 #23 10.16 0.400 0.45 ~0.75 0.018 ~ 0.030 11.76±0.20 0.463±0.008 ( #1 #22 1.00±0.10 0.039±0.004 1.20 MAX. 0.047 ( 0.805 ) 0.032 0.35±0.10 0.014±0.004 0.80 0.0315 0.05 MIN. 0.002 18.81 MAX. 0.741 18.41±0.10 0.725±0.004 0.10 MAX 0.004 + 0.10 - 0.05 + 0.004 0.006 - 0.002 0.15 0.50 ) 0.020