SAMSUNG KM416V1000C

KM416C1000C, KM416C1200C
KM416V1000C, KM416V1200C
CMOS DRAM
1M x 16Bit CMOS Dynamic RAM with Fast Page Mode
DESCRIPTION
This is a family of 1,048,576 x 16 bit Fast Page Mode CMOS DRAMs. Fast Page Mode offers high speed random access of memory
cells within the same row. Power supply voltage (+5.0V or +3.3V), refresh cycle (1K Ref. or 4K Ref.), access time (-5 or -6), power consumption(Normal or Low power) and package type(SOJ or TSOP-II) are optional features of this family. All of this family have CASbefore-RAS refresh, RAS-only refresh and Hidden refresh capabilities. Furthermore, Self-refresh operation is available in L-version. This
1Mx16 Fast Page Mode DRAM family is fabricated using Samsung′s advanced CMOS process to realize high band-width, low power
consumption and high reliability. It may be used as graphic memory unit for microcomputer, personal computer and portable machines.
FEATURES
• Fast Page Mode operation
• Part Identification
• 2 CAS Byte/Word Read/Write operation
• CAS-before-RAS refresh capability
- KM416C1000C/C-L (5V, 4K Ref.)
- KM416C1200C/C-L (5V, 1K Ref.)
- KM416V1000C/C-L (3.3V, 4K Ref.)
- KM416V1200C/C-L (3.3V, 1K Ref.)
• RAS-only and Hidden refresh capability
• Self-refresh capability (L-ver only)
• TTL(5V)/LVTTL(3.3V) compatible inputs and outputs
• Early Write or output enable controlled write
• Active Power Dissipation
• JEDEC Standard pinout
Unit : mW
3.3V
Speed
• Available in 42-pin SOJ 400mil and 50(44)-pin TSOP(II)
5V
4K
1K
4K
1K
400mil packages
• Single +5V±10% power supply (5V product)
-5
324
504
495
770
• Single +3.3V±0.3V power supply (3.3V product)
-6
288
468
440
715
FUNCTIONAL BLOCK DIAGRAM
• Refresh Cycles
VCC
C1000C
5V
V1000C
3.3V
C1200C
5V
V1200C
3.3V
Refresh
cycle
Refresh period
Normal
4K
L-ver
64ms
RAS
UCAS
LCAS
W
Control
Clocks
Vcc
Vss
VBB Generator
Lower
Data in
Buffer
128ms
1K
Refresh Timer
16ms
Row Decoder
Refresh Control
Refresh Counter
• Perfomance Range
Speed
tRAC
tCAC
tRC
tPC
Remark
-5
50ns
15ns
90ns
35ns
5V/3.3V
-6
60ns
15ns
110ns
40ns
5V/3.3V
A0-A11
(A0 - A9) *1
A0 - A7
(A0 - A9) *1
Memory Array
1,048,576 x16
Cells
Row Address Buffer
Col. Address Buffer
Column Decoder
Note) *1 : 1K Refresh
SAMSUNG ELECTRONICS CO., LTD. reserves the right to
change products and specifications without notice.
Sense Amps & I/O
Part
NO.
Lower
Data out
Buffer
Upper
Data in
Buffer
Upper
Data out
Buffer
DQ0
to
DQ7
OE
DQ8
to
DQ15
KM416C1000C, KM416C1200C
KM416V1000C, KM416V1200C
CMOS DRAM
PIN CONFIGURATION (Top Views)
•KM416C/V10(2)00CT
•KM416C/V10(2)00CJ
VCC
DQ0
DQ1
DQ2
DQ3
VCC
DQ4
DQ5
DQ6
DQ7
N.C
N.C
W
RAS
*A11(N.C)
*A10(N.C)
A0
A1
A2
A3
VCC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
VSS
DQ15
DQ14
DQ13
DQ12
VSS
DQ11
DQ10
DQ9
DQ8
N.C
LCAS
UCAS
OE
A9
A8
A7
A6
A5
A4
VSS
VCC
DQ0
DQ1
DQ2
DQ3
VCC
DQ4
DQ5
DQ6
DQ7
N.C
1
2
3
4
5
6
7
8
9
10
11
44
43
42
41
40
39
38
37
36
35
34
VSS
DQ15
DQ14
DQ13
DQ12
VSS
DQ11
DQ10
DQ9
DQ8
N.C
N.C
N.C
W
RAS
*A11(N.C)
*A10(N.C)
A0
A1
A2
A3
VCC
12
13
14
15
16
17
18
19
20
21
22
33
32
31
30
29
28
27
26
25
24
23
N.C
LCAS
UCAS
OE
A9
A8
A7
A6
A5
A4
VSS
*A10 and A11 are N.C for KM416C/V1200C(5V/3.3V, 1K Ref. product)
J : 400mil 42 SOJ
T : 400mil 50(44) TSOP II
Pin Name
Pin Function
A0 - A11
Address Inputs (4K Product)
A0 - A9
Address Inputs (1K Product)
DQ0 - 15
Data In/Out
VSS
Ground
RAS
Row Address Strobe
UCAS
Upper Column Address Strobe
LCAS
Lower Column Address Strobe
W
Read/Write Input
OE
Data Output Enable
VCC
Power(+5V)
Power(+3.3V)
N.C
No Connection
KM416C1000C, KM416C1200C
KM416V1000C, KM416V1200C
CMOS DRAM
ABSOLUTE MAXIMUM RATINGS
Parameter
Rating
Symbol
Units
3.3V
5V
VIN, VOUT
-0.5 to +4.6
-1.0 to +7.0
V
Voltage on VCC supply relative to VSS
VCC
-0.5 to +4.6
-1.0 to +7.0
V
Storage Temperature
Tstg
-55 to +150
-55 to +150
°C
Power Dissipation
PD
1
1
W
Short Circuit Output Current
IOS
50
50
mA
Voltage on any pin relative to VSS
* Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded. Functional operation should be restricted
to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS (Voltage referenced to Vss, TA= 0 to 70°C)
Parameter
3.3V
Symbol
5V
Units
Min
Typ
Max
Min
Typ
Max
Supply Voltage
VCC
3.0
3.3
3.6
4.5
5.0
5.5
V
Ground
VSS
0
0
0
0
0
0
V
Input High Voltage
VIH
2.0
-
VCC+0.3*1
2.4
-
VCC+1.0*1
V
Input Low Voltage
VIL
-0.3*2
-
0.8
-1.0*2
-
0.8
V
*1 : VCC+1.3V/15ns(3.3V), VCC+2.0V/20ns(5V), Pulse width is measured at VCC
*2 : -1.3V/15ns(3.3V), -2.0V/20ns(5V), Pulse width is measured at VSS
DC AND OPERATING CHARACTERISTICS (Recommended operating conditions unless otherwise noted.)
Max
3.3V
5V
Parameter
Symbol
Min
Max
Units
Input Leakage Current (Any input 0≤VIN≤VIN+0.3V,
all other input pins not under test=0 Volt)
II(L)
-5
5
uA
Output Leakage Current
(Data out is disabled, 0V≤VOUT ≤VCC)
IO(L)
-5
5
uA
Output High Voltage Level(IOH=-2mA)
VOH
2.4
-
V
Output Low Voltage Level(IOL=2mA)
VOL
-
0.4
V
Input Leakage Current (Any input 0≤VIN≤VIN+0.5V,
all other input pins not under test=0 Volt)
II(L)
-5
5
uA
Output Leakage Current
(Data out is disabled, 0V≤VOUT ≤VCC)
IO(L)
-5
5
uA
Output High Voltage Level(IOH=-5mA)
VOH
2.4
-
V
Output Low Voltage Level(IOL=4.2mA)
VOL
-
0.4
V
KM416C1000C, KM416C1200C
KM416V1000C, KM416V1200C
CMOS DRAM
DC AND OPERATING CHARACTERISTICS (Continued)
Max
Symbol
Power
Speed
Units
KM416V1000C
KM416V1200C
KM416C1000C
KM416C1200C
ICC1
Don′t care
-5
-6
90
80
140
130
90
80
140
130
mA
mA
ICC2
Normal
L
Don′t care
1
1
1
1
2
1
2
1
mA
mA
ICC3
Don′t care
-5
-6
90
80
140
130
90
80
140
130
mA
mA
ICC4
Don′t care
-5
-6
90
80
90
80
90
80
90
80
mA
mA
ICC5
Normal
L
Don′t care
0.5
200
0.5
200
1
200
1
200
mA
uA
ICC6
Don′t care
-5
-6
90
80
140
130
90
80
140
130
mA
mA
ICC7
L
Don′t care
300
200
350
250
uA
ICCS
L
Don′t care
150
150
200
200
uA
ICC1 * : Operating Current (RAS and UCAS, LCAS cycling @tRC=min.)
ICC2 : Standby Current (RAS=UCAS=LCAS=W=VIH)
ICC3 * : RAS-only Refresh Current (UCAS=LCAS=VIH, RAS cycling @tRC=min.)
ICC4 * : Fast Page Mode Current (RAS=VIL, UCAS or LCAS, Address cycling @tPC=min.)
ICC5 : Standby Current (RAS=UCAS=LCAS=W=VCC-0.2V)
ICC6 * : CAS-Before-RAS Refresh Current (RAS, UCAS or LCAS cycling @tRC=min.)
ICC7 : Battery back-up current, Average power supply current, Battery back-up mode
Input high voltage(VIH)=VCC-0.2V, Input low voltage(VIL)=0.2V, UCAS, LCAS=0.2V,
DQ=Don′t care, TRC=31.25us(4K/L-ver), 125us(1K/L-ver),
TRAS =TRAS min~300ns
ICCS : Self Refresh Current
RAS=UCAS=LCAS=VIL, W=OE=A0 ~ A11=VCC-0.2V or 0.2V,
DQ0 ~ DQ15=VCC-0.2V, 0.2V or Open
*Note : ICC1 , ICC3 , ICC4 and ICC6 are dependent on output loading and cycle rates. Specified values are obtained with the output open.
ICC is specified as an average current. In ICC1 , ICC3 and ICC6, address can be changed maximum once while RAS=VIL. In ICC4 ,
address can be changed maximum once within one fast page mode cycle time, tPC.
KM416C1000C, KM416C1200C
KM416V1000C, KM416V1200C
CMOS DRAM
CAPACITANCE (TA=25°C, VCC=5V or 3.3V, f=1MHz)
Parameter
Symbol
Min
Max
Units
Input capacitance [A0 ~ A11]
CIN1
-
5
pF
Input capacitance [RAS, UCAS, LCAS, W, OE]
CIN2
-
7
pF
Output capacitance [DQ0 - DQ15]
CDQ
-
7
pF
AC CHARACTERISTICS (0°C≤TA≤70°C, See note 1,2)
Test condition (5V device) : VCC=5.0V±10%, Vih/Vil=2.4/0.8V, Voh/Vol=2.4/0.4V
Test condition (3.3V device) : VCC=3.3V±0.3V, Vih/Vil=2.2/0.7V, Voh/Vol=2.0/0.8V
Parameter
-5
Symbol
Min
-6
Max
Min
Units
Notes
Max
Random read or write cycle time
tRC
90
110
ns
Read-modify-write cycle time
tRWC
133
155
ns
Access time from RAS
tRAC
50
60
ns
3,4,10
Access time from CAS
tCAC
15
15
ns
3,4,5
30
ns
3,10
ns
3
Access time from column address
tAA
CAS to output in Low-Z
tCLZ
0
Output buffer turn-off delay
tOFF
0
13
0
15
ns
6
Transition time (rise and fall)
tT
3
50
3
50
ns
2
RAS precharge time
tRP
30
RAS pulse width
tRAS
50
RAS hold time
tRSH
13
15
ns
CAS hold time
tCSH
50
60
ns
CAS pulse width
tCAS
13
10K
15
10K
ns
RAS to CAS delay time
tRCD
20
37
20
45
ns
4
RAS to column address delay time
25
15
30
ns
10
25
0
40
10K
60
ns
10K
ns
tRAD
15
CAS to RAS precharge time
tCRP
5
5
ns
Row address set-up time
tASR
0
0
ns
Row address hold time
tRAH
10
10
ns
Column address set-up time
tASC
0
0
ns
11
Column address hold time
tCAH
10
10
ns
11
Column address to RAS lead time
tRAL
25
30
ns
Read command set-up time
tRCS
0
0
ns
Read command hold time referenced to CAS
tRCH
0
0
ns
8
Read command hold time referenced to RAS
tRRH
0
0
ns
8
Write command hold time
tWCH
10
10
ns
Write command pulse width
tWP
10
10
ns
Write command to RAS lead time
tRWL
13
15
ns
Write command to CAS lead time
tCWL
13
15
ns
KM416C1000C, KM416C1200C
KM416V1000C, KM416V1200C
CMOS DRAM
AC CHARACTERISTICS (Continued)
Parameter
-5
Symbol
Min
-6
Max
Min
Units
Notes
Max
Data set-up time
tDS
0
0
ns
9,17
Data hold time
tDH
10
10
ns
9,17
Refresh period (1K, Normal)
tREF
16
16
ms
Refresh period (4K, Normal)
tREF
64
64
ms
Refresh period (L-ver)
tREF
128
128
ms
Write command set-up time
tWCS
0
0
ns
7
CAS to W delay time
tCWD
36
40
ns
7,13
RAS to W delay time
tRWD
73
85
ns
7
Column address to W delay time
tAWD
48
55
ns
7
CAS precharge to W delay time
tCPWD
53
60
ns
7
CAS set-up time (CAS-before-RAS refresh)
tCSR
5
5
ns
15
CAS hold time (CAS-before-RAS refresh)
tCHR
10
10
ns
16
RAS to CAS precharge time
tRPC
5
5
ns
Access time from CAS precharge
tCPA
Fast Page mode cycle time
tPC
35
40
ns
Fast Page read-modify-write cycle time
tPRWC
76
80
ns
30
CAS precharge time (Fast Page cycle)
tCP
10
RAS pulse width (Fast Page cycle)
tRASP
50
RAS hold time from CAS precharge
tRHCP
30
OE access time
tOEA
OE to data delay
tOED
Output buffer turn off delay time from OE
35
10
200K
60
ns
200K
35
13
13
ns
ns
3
ns
tOEZ
0
OE command hold time
tOEH
13
15
ns
RAS pulse width (C-B-R self refresh)
tRASS
100
100
us
0
12
ns
ns
15
15
13
3
15
ns
18,19,20
RAS precharge time (C-B-R self refresh)
tRPS
90
110
ns
18,19,20
CAS hold time (C-B-R self refresh)
tCHS
-50
-50
ns
18,19,20
KM416C1000C, KM416C1200C
KM416V1000C, KM416V1200C
CMOS DRAM
NOTES
1. An initial pause of 200us is required after power-up followed by any 8 RAS-only refresh or CAS-before-RAS refresh cycles
before proper device operation is achieved.
2. Input voltage levels are Vih/Vil. VIH(min) and VIL(max) are reference levels for measuring timing of input signals.
Transition times are measured between VIH(min) and VIL(max) and are assumed to be 5ns for all inputs.
3. Measured with a load equivalent to 2 TTL(5V)/1TTL(3.3V) loads and 100pF.
4. Operation within the tRCD (max) limit insures that tRAC (max) can be met. tRCD (max) is specified as a reference point only.
If tRCD is greater than the specified tRCD (max) limit, then access time is controlled exclusively by tCAC .
5. Assumes that tRCD ≥tRCD (max).
6. This parameter defines the time at which the output achieves the open circuit condition and is not referenced to Voh or Vol.
7. tWCS , tRWD , tCWD , tAWD and tCPWD are non restrictive operating parameters. They are included in the data sheet as electrical
characteristics only. If tWCS ≥tWCS (min), the cycle is an early write cycle and the data output will remain high impedance for the
duration of the cycle. If tCWD ≥tCWD (min), tRWD ≥tRWD (min), tAWD ≥tAWD (min) and tCPWD ≥tCPWD (min), then the cycle is a readmodify-write cycle and the data output will contain the data read from the selected address. If neither of the above conditions
is satisfied, the condition of the data out is indeterminate.
8. Either tRCH or tRRH must be satisfied for a read cycle.
9. These parameters are referenced to CAS falling edge in early write cycles and to W falling edge in OE controlled write cycle
and read-modify-write cycles.
10. Operation within the tRAD (max) limit insures that tRAC (max) can be met. tRAD (max) is specified as a reference point only.
If tRAD is greater than the specified tRAD (max) limit, then access time is controlled by tAA.
11. tASC , tCAH are referenced to the earlier CAS falling edge.
12. tCP is specified from the later CAS rising edge in the previous cycle to the earlier CAS falling edge in the next cycle.
KM416C/V10(2)00C/C-L Truth Table
RAS
LCAS
UCAS
W
OE
DQ0 - DQ7
DQ8-DQ15
STATE
H
X
X
X
X
Hi-Z
Hi-Z
Standby
L
H
H
X
X
Hi-Z
Hi-Z
Refresh
L
L
H
H
L
DQ-OUT
Hi-Z
Byte Read
L
H
L
H
L
Hi-Z
DQ-OUT
Byte Read
L
L
L
H
L
DQ-OUT
DQ-OUT
Word Read
L
L
H
L
H
DQ-IN
-
Byte Write
L
H
L
L
H
-
DQ-IN
Byte Write
L
L
L
L
H
DQ-IN
DQ-IN
Word Write
L
L
L
H
H
Hi-Z
Hi-Z
-
KM416C1000C, KM416C1200C
KM416V1000C, KM416V1200C
CMOS DRAM
13. tCWD is referenced to the later CAS falling edge at word read-modify-write cycle.
14. tCWL is specified from W falling edge to the earlier CAS rising edge.
15. tCSR is referenced to the earlier CAS falling edge before RAS transition low.
16. tCHR is referenced to the later CAS rising edge after RAS transition low.
RAS
LCAS
UCAS
tCSR
tCHR
17. tDS, tDH is independently specified for lower byte DQ(0-7), upper byte DQ(8-15)
18. If tRASS ≥100us, then RAS precharge time must use tRPS instead of tRP.
19. For RAS-only refresh and burst CAS-before-RAS refresh mode, 4096(4K)/1024(1K) cycles of burst refresh must be executed
within 64ms/16ms before and after self refresh, in order to meet refresh specification.
20. For distributed CAS-before-RAS with 15.6us interval CAS-before-RAS refresh should be executed with in 15.6us immediately
before and after self refresh in order to meet refresh specification.
KM416C1000C, KM416C1200C
KM416V1000C, KM416V1200C
CMOS DRAM
WORD READ CYCLE
tRC
tRAS
RAS
VIL -
tCSH
tCRP
UCAS
tRCD
tCRP
tRSH
VIH -
tCAS
VIL -
tCSH
tCRP
LCAS
tRP
VIH -
tRCD
tCRP
tRSH
tCAS
VIH VIL -
tRAD
tASR
A
VIH VIL -
tRAH
tRAL
tASC
tCAH
COLUMN
ADDRESS
ROW
ADDRESS
tRCH
tRCS
W
tRRH
VIH VIL -
tAA
OE
VIH -
tOEA
VIL -
DQ0 ~ DQ7
VOH VOL -
tRAC
tCAC
tCLZ
OPEN
tOFF
tOEZ
DATA-OUT
tOFF
tCAC
DQ8 ~ DQ15
VOH VOL -
tRAC
OPEN
tCLZ
tOEZ
DATA-OUT
Don′t care
Undefined
KM416C1000C, KM416C1200C
KM416V1000C, KM416V1200C
CMOS DRAM
LOWER BYTE READ CYCLE
NOTE : DIN = OPEN
tRC
tRAS
RAS
tRP
VIH VIL -
tCRP
UCAS
tRPC
VIH VIL -
tCSH
tCRP
LCAS
tRSH
tCAS
VIH VIL -
tRAD
tASR
A
tRCD
VIH VIL -
tRAH
tASC
ROW
ADDRESS
tRAL
tCAH
COLUMN
ADDRESS
tRCH
tRCS
W
tRRH
VIH VIL -
tOFF
tAA
OE
VIH -
tOEA
VIL -
DQ0 ~ DQ7
VOH VOL DQ8 ~ DQ15
VOH VOL -
tOEZ
tRAC
tCAC
tCLZ
OPEN
DATA-OUT
OPEN
Don′t care
Undefined
KM416C1000C, KM416C1200C
KM416V1000C, KM416V1200C
CMOS DRAM
UPPER BYTE READ CYCLE
NOTE : DIN = OPEN
tRC
tRAS
RAS
VIL -
tCSH
tCRP
UCAS
tRP
VIH -
tRCD
tCRP
tRSH
tCAS
VIH VIL -
tRPC
tCRP
LCAS
VIH VIL -
tRAD
tRAL
tASR
A
VIH VIL -
tRAH
tASC
ROW
ADDRESS
tCAH
COLUMN
ADDRESS
tRCH
tRCS
W
tRRH
VIH VIL -
tOFF
tAA
OE
VIH -
tOEA
VIL -
DQ0 ~ DQ7
VOH -
OPEN
VOL DQ8 ~ DQ15
VOH VOL -
tOEZ
tCAC
tRAC
OPEN
tCLZ
DATA-OUT
Don′t care
Undefined
KM416C1000C, KM416C1200C
KM416V1000C, KM416V1200C
CMOS DRAM
WORD WRITE CYCLE ( EARLY WRITE )
NOTE : DOUT = OPEN
tRC
tRAS
RAS
VIL -
tCSH
tCRP
UCAS
tRCD
tRSH
VIH -
tCRP
tCAS
VIL -
tCSH
tCRP
LCAS
tRP
VIH -
tRCD
tRSH
VIH -
tCRP
tCAS
VIL -
tRAD
tASR
A
VIH VIL -
tRAH
tRAL
tASC
ROW
ADDRESS
tCAH
COLUMN
ADDRESS
tWCS
W
OE
VIH -
tWCH
tWP
VIL -
VIH VIL -
DQ0 ~ DQ7
VIH -
tDS
DATA-IN
VIL -
DQ8 ~ DQ15
VIH -
tDH
tDS
tDH
DATA-IN
VIL -
Don′t care
Undefined
KM416C1000C, KM416C1200C
KM416V1000C, KM416V1200C
CMOS DRAM
LOWER BYTE WRITE CYCLE ( EARLY WRITE )
NOTE : DOUT = OPEN
tRC
tRAS
RAS
tRP
VIH VIL -
tCRP
UCAS
tRPC
VIH VIL -
tCSH
tCRP
LCAS
tRCD
tRSH
VIH -
tCRP
tCAS
VIL -
tRAD
tASR
A
VIH VIL -
tRAH
tRAL
tASC
tCAH
COLUMN
ADDRESS
ROW
ADDRESS
tWCS
W
OE
VIH -
tWCH
tWP
VIL -
VIH VIL -
DQ0 ~ DQ7
VIH VIL -
tDS
tDH
DATA-IN
DQ8 ~ DQ15
VIH VIL -
Don′t care
Undefined
KM416C1000C, KM416C1200C
KM416V1000C, KM416V1200C
CMOS DRAM
UPPER BYTE WRITE CYCLE ( EARLY WRITE )
NOTE : DOUT = OPEN
tRAS
RAS
VIL -
tCSH
tRCD
tCRP
tRSH
VIH -
tCAS
VIL -
tCRP
LCAS
tRP
VIH -
tCRP
UCAS
tRC
tRPC
VIH VIL -
tRAD
tASR
A
VIH VIL -
tRAH
tRAL
tASC
ROW
ADDRESS
tCAH
COLUMN
ADDRESS
tWCS
W
OE
VIH -
tWCH
tWP
VIL -
VIH VIL -
DQ0 ~ DQ7
VIH VIL -
DQ8 ~ DQ15
VIH VIL -
tDS
tDH
DATA-IN
Don′t care
Undefined
KM416C1000C, KM416C1200C
KM416V1000C, KM416V1200C
CMOS DRAM
WORD WRITE CYCLE ( OE CONTROLLED WRITE )
NOTE : DOUT = OPEN
tRC
tRAS
RAS
VIL -
tCSH
tCRP
UCAS
tRCD
tRSH
VIH -
tCRP
tCAS
VIL -
tCSH
tCRP
LCAS
tRP
VIH -
tRCD
tRSH
VIH -
tCRP
tCAS
VIL -
tRAD
tASR
A
VIH VIL -
tRAH
tRAL
tASC
ROW
ADDRESS
tCAH
COLUMN
ADDRESS
tCWL
tRWL
W
OE
VIH -
tWP
VIL -
VIH VIL -
DQ0 ~ DQ7
VIH -
tOEH
tOED
tDS
DATA-IN
VIL -
DQ8 ~ DQ15
VIH -
tDH
tDS
tDH
DATA-IN
VIL -
Don′t care
Undefined
KM416C1000C, KM416C1200C
KM416V1000C, KM416V1200C
CMOS DRAM
LOWER BYTE WRITE CYCLE ( OE CONTROLLED WRITE )
NOTE : DOUT = OPEN
tRC
tRAS
RAS
VIL -
tRPC
tCRP
UCAS
VIH VIL -
tCSH
tCRP
LCAS
tRP
VIH -
tRCD
tRSH
VIH -
tCRP
tCAS
VIL -
tRAD
tASR
A
VIH VIL -
tRAH
tRAL
tASC
ROW
ADDRESS
tCAH
COLUMN
ADDRESS
tCWL
tRWL
W
OE
VIH -
tWP
VIL -
VIH VIL -
DQ0 ~ DQ7
VIH VIL -
tOEH
tOED
tDS
tDH
DATA-IN
DQ8 ~ DQ15
VIH VIL -
Don′t care
Undefined
KM416C1000C, KM416C1200C
KM416V1000C, KM416V1200C
CMOS DRAM
UPPER BYTE WRITE CYCLE ( OE CONTROLLED WRITE )
NOTE : DOUT = OPEN
tRC
tRAS
RAS
VIL -
tCSH
tCRP
UCAS
tRP
VIH -
tRCD
tCAS
VIL -
tCRP
LCAS
tCRP
tRSH
VIH -
tRPC
VIH VIL -
tRAD
tASR
A
VIH VIL -
tRAH
tRAL
tASC
tCAH
COLUMN
ADDRESS
ROW
ADDRESS
tCWL
W
OE
tRWL
VIH -
tWP
VIL -
VIH VIL -
tOEH
tOED
DQ0 ~ DQ7
VIH VIL -
DQ8 ~ DQ15
VIH VIL -
tDS
tDH
DATA-IN
Don′t care
Undefined
KM416C1000C, KM416C1200C
KM416V1000C, KM416V1200C
CMOS DRAM
WORD READ - MODIFY - WRITE CYCLE
tRWC
tRAS
RAS
VIL -
tCRP
UCAS
tRCD
tRSH
VIH -
tCAS
VIL -
tCRP
LCAS
tRP
VIH -
tRCD
tRSH
VIH -
tCAS
VIL -
tRAD
tCSH
tASR
A
VIH VIL -
tRAH
ROW
ADDR
tASC
tCAH
COLUMN
ADDRESS
tRWL
tAWD
tCWL
tCWD
W
OE
VIH -
tWP
VIL -
tRWD
tOEA
VIH VIL -
tCLZ
tCAC
tAA
DQ0 ~ DQ7
VI/OH -
tRAC
tOED
tOEZ
VALID
DATA-OUT
VI/OL -
tDS
tDH
VALID
DATA-IN
tCLZ
tCAC
DQ8 ~ DQ15
VI/OH VI/OL -
tAA
tRAC
tOED
tOEZ
VALID
DATA-OUT
tDS
tDH
VALID
DATA-IN
Don′t care
Undefined
KM416C1000C, KM416C1200C
KM416V1000C, KM416V1200C
CMOS DRAM
LOWER-BYTE READ - MODIFY - WRITE CYCLE
tRWC
tRAS
RAS
tRP
VIH VIL -
tRPC
tCRP
UCAS
VIH VIL -
tCRP
LCAS
tRCD
tRSH
VIH -
tCAS
VIL -
tRAD
tCSH
tASR
A
VIH VIL -
tRAH
ROW
ADDR
tASC
tCAH
COLUMN
ADDRESS
tRWL
tAWD
tCWD
W
OE
tCWL
VIH -
tWP
VIL -
tRWD
tOEA
VIH VIL -
tCLZ
tCAC
tAA
DQ0 ~ DQ7
VI/OH VI/OL DQ8 ~ DQ15
VI/OH VI/OL -
tRAC
tOED
tOEZ
VALID
DATA-OUT
tDS
tDH
VALID
DATA-IN
OPEN
Don′t care
Undefined
KM416C1000C, KM416C1200C
KM416V1000C, KM416V1200C
CMOS DRAM
UPPER-BYTE READ - MODIFY - WRITE CYCLE
tRWC
tRP
tRAS
RAS
VIH VIL -
tCRP
UCAS
tRCD
tRSH
VIH -
tCAS
VIL -
tCRP
LCAS
VIH VIL -
tRAD
tASR
A
tRPC
VIH VIL -
tRAH
ROW
ADDR
tASC
tCSH
tCAH
COLUMN
ADDRESS
tRWL
tAWD
tCWL
tCWD
W
OE
VIH -
tWP
VIL -
tRWD
tOEA
VIH VIL -
DQ0 ~ DQ7
VI/OH -
OPEN
VI/OL -
tCLZ
tCAC
DQ8 ~ DQ15
VI/OH VI/OL -
tAA
tRAC
tOED
tOEZ
VALID
DATA-OUT
tDS
tDH
VALID
DATA-IN
Don′t care
Undefined
KM416C1000C, KM416C1200C
KM416V1000C, KM416V1200C
CMOS DRAM
FAST PAGE MODE WORD READ CYCLE
tRP
tRASP
RAS
VIH VIL -
¡ó
tRHCP
tCSH
tPC
tCRP
UCAS
tRCD
tPC
tCP
tCAS
VIH -
tPC
tCP
tCAS
tCP
tCAS
tRPC
tCAS
VIL -
tRAL
tCRP
tCP
tRCD
LCAS
tCAS
VIH -
VIH VIL -
tRAD
tRAH tASC
ROW
ADDR
tCAH
COLUMN
ADDRESS
tRCS
W
tCAS
tCP
tCAS
tASC
tCAH
tASC
COLUMN
ADDRESS
tRCH
tCAH
tASC
COLUMN
ADDR
tRCS
tRCH
tCAH
COLUMN
ADDRESS
tRCS
tRCH
tRCS
tRRH
tRCH
VIH VIL -
tCAC
tAA
OE
tRPC
tCAS
VIL -
tASR
A
tCP
tOEA
VIH -
tCAC
tAA
tAA
tCPA
tCPA
tOEA
tCAC
tAA
tCPA
tOEA
tOEA
VIL -
tCAC
DQ0 ~ DQ7
VOH -
tOFF
tRAC
tOEZ
VALID
DATA-OUT
VOL -
tCLZ
tCAC
DQ8 ~ DQ15
VOH -
tOEZ
VALID
DATA-OUT
tOFF
tOEZ
VALID
DATA-OUT
tOFF
tOEZ
VALID
DATA-OUT
tOFF
tOEZ
VALID
DATA-OUT
tOFF
tOEZ
VALID
DATA-OUT
tOFF
tRAC
VOL -
tOFF
tOFF
tOEZ
VALID
DATA-OUT
tOEZ
VALID
DATA-OUT
tCLZ
Don′t care
Undefined
KM416C1000C, KM416C1200C
KM416V1000C, KM416V1200C
CMOS DRAM
FAST PAGE MODE LOWER BYTE READ CYCLE
tRASP
RAS
tRP
VIH VIL -
¡ó
tRHCP
tCRP
UCAS
tRPC
VIH VIL -
tPC
tCRP
LCAS
tPC
tCP
tCAS
tCP
tCAS
tCAS
VIH VIL -
tRAD
tRAH tASC tCAH
ROW
ADDR
tASC tCAH
COLUMN
ADDRESS
tASC
COLUMN
ADDRESS
tCAH
tRCS
tRCH
tASC
COLUMN
ADDR
tCAH
COLUMN
ADDRESS
tRCS
tRCH
tRCH
tRCS
tRRH
tRCH
VIH VIL -
tCAC
tCAC
tAA
OE
tRPC
tCAS
VIL -
tRCS
W
tPC
tCP
tRCD
VIH -
tASR
A
tRAL
tCSH
tAA
tOEA
VIH -
tCAC
tAA
tAA
tCPA
tOEA
tCPA
tOEA
tCPA
tOEA
tOFF
tOEZ
tOFF
tOEZ
VIL -
DQ0 ~ DQ7
VOH -
tCAC
tRAC
VALID
DATA-OUT
VOL -
VALID
DATA-OUT
tOFF
tOEZ
VALID
DATA-OUT
tOFF
tOEZ
VALID
DATA-OUT
tCLZ
DQ8 ~ DQ15
VOH VOL -
OPEN
Don′t care
Undefined
KM416C1000C, KM416C1200C
KM416V1000C, KM416V1200C
CMOS DRAM
FAST PAGE MODE UPPER BYTE READ CYCLE
tRP
tRASP
RAS
VIH VIL -
¡ó
tCSH
tCRP
UCAS
tRHCP
tPC
tRCD
tCP
tCAS
VIH -
tPC
tPC
tCP
tCAS
tCP
tCAS
tRPC
tCAS
VIL -
tCRP
LCAS
tRPC
VIH -
tRAL
VIL -
tRAD
tASR
A
VIH VIL -
tRAH tASC
ROW
ADDR
tCAH
COLUMN
ADDRESS
tCAH
tASC
COLUMN
ADDRESS
tCAH
tRCH
tCAH
COLUMN
ADDRESS
tRCS
tRCH
tRCH
tRCS
tRRH
tRCH
VIH VIL -
tCAC
OE
tASC
COLUMN
ADDR
tRCS
tRCS
W
tASC
tAA
tCPA
tOEA
tAA
tOEA
VIH -
tCAC
tCAC
tAA
tAA
tCPA
tOEA
tCPA
tOEA
VIL -
DQ0 ~ DQ7
VOH -
OPEN
VOL -
DQ8 ~ DQ15
VOH -
tCAC
tRAC
tOFF
tOEZ
VALID
DATA-OUT
VOL -
tOFF
tOEZ
VALID
DATA-OUT
tOFF
tOEZ
VALID
DATA-OUT
tOFF
tOEZ
VALID
DATA-OUT
tCLZ
Don′t care
Undefined
KM416C1000C, KM416C1200C
KM416V1000C, KM416V1200C
CMOS DRAM
FAST PAGE MODE WORD WRITE CYCLE ( EARLY WRITE )
NOTE : DOUT = OPEN
tRASP
RAS
tRHCP
VIL -
¡ó
tPC
tCRP
UCAS
tRCD
tPC
tCP
VIH -
tRSH
tCP
tCAS
tCRP
tCAS
VIL -
tCAS
¡ó
tPC
tCRP
LCAS
tRP
VIH -
VIH -
tRSH
tPC
tCP
tRCD
tCP
tCAS
tCAS
VIL -
tCAS
¡ó
tRAD
tRAL
tCSH
tASR
A
VIH VIL -
tRAH
tASC
tCAH
OE
VIH -
tCAH
tASC
tCAH
¡ó
ROW
ADDR
COLUMN
ADDRESS
COLUMN
ADDRESS
tWCS
W
tASC
tWCH
tWCS
tWP
¡ó
tWCH
tWP
COLUMN
ADDRESS
tWCS
¡ó
tWCH
tWP
VIL -
¡ó
VIH VIL -
DQ0 ~ DQ7
VIH -
¡ó
tDS
VIL -
tDS
tDH
tDS
tDH
¡ó
VALID
DATA-IN
VIL -
DQ8 ~ DQ15
VIH -
tDH
tDS
tDH
VALID
DATA-IN
tDS
¡ó
tDH
VALID
DATA-IN
tDS
tDH
¡ó
VALID
DATA-IN
VALID
DATA-IN
¡ó
VALID
DATA-IN
Don′t care
Undefined
KM416C1000C, KM416C1200C
KM416V1000C, KM416V1200C
CMOS DRAM
FAST PAGE MODE LOWER BYTE WRITE CYCLE ( EARLY WRITE )
NOTE : DOUT = OPEN
tRASP
RAS
tRP
VIH -
tRHCP
VIL -
¡ó
tRPC
tCRP
UCAS
¡ó
VIH VIL -
tPC
tCRP
LCAS
tRCD
tPC
tCP
VIH -
tRSH
tCP
tCAS
tCAS
VIL -
tCAS
¡ó
tRAD
tRAL
tCSH
tASR
A
VIH VIL -
tRAH
tASC
tCAH
OE
VIH -
tCAH
tASC
tCAH
¡ó
ROW
ADDR
COLUMN
ADDRESS
COLUMN
ADDRESS
tWCS
W
tASC
tWCH
tWCS
tWP
¡ó
tWCH
tWP
COLUMN
ADDRESS
tWCS
¡ó
tWCH
tWP
VIL -
¡ó
VIH VIL -
DQ0 ~ DQ7
VIH VIL -
¡ó
tDS
tDH
tDS
tDH
tDS
tDH
¡ó
VALID
DATA-IN
VALID
DATA-IN
¡ó
VALID
DATA-IN
DQ8 ~ DQ15
VIH VIL -
Don′t care
Undefined
KM416C1000C, KM416C1200C
KM416V1000C, KM416V1200C
CMOS DRAM
FAST PAGE MODE UPPER BYTE WRITE CYCLE ( EARLY WRITE )
NOTE : DOUT = OPEN
tRASP
RAS
tRHCP
VIL -
¡ó
tPC
tCRP
UCAS
tRP
VIH -
tRCD
tPC
tCP
VIH -
tRSH
tCP
tCAS
tCAS
VIL -
tCAS
¡ó
tRPC
tCRP
LCAS
VIH VIL -
tRAD
tRAL
tCSH
tASR
A
VIH VIL -
tRAH
tASC
tCAH
OE
VIH -
tCAH
tASC
tCAH
¡ó
ROW
ADDR.
COLUMN
ADDRESS
COLUMN
ADDRESS
tWCS
W
tASC
tWCH
tWCS
tWP
¡ó
tWCH
tWP
COLUMN
ADDRESS
tWCS
¡ó
tWCH
tWP
VIL -
¡ó
VIH VIL -
¡ó
DQ0 ~ DQ7
VIH -
¡ó
VIL -
DQ8 ~ DQ15
VIH VIL -
¡ó
tDS
tDH
tDS
tDH
tDS
tDH
¡ó
VALID
DATA-IN
VALID
DATA-IN
¡ó
VALID
DATA-IN
Don′t care
Undefined
KM416C1000C, KM416C1200C
KM416V1000C, KM416V1200C
CMOS DRAM
FAST PAGE MODE WORD READ-MODIFY-WRITE CYCLE
tRP
tRASP
RAS
VIH -
tCSH
VIL -
tCRP
UCAS
tRSH
tCRP
tCP
VIH -
tCAS
tCAS
VIL -
tCRP
LCAS
tPRWC
tRCD
tRCD
tCRP
tCP
VIH -
tCAS
tCAS
VIL -
tRAD
tRAH
tASR
A
VIH VIL -
tRAL
tCAH
tCAH
tASC
tASC
ROW
ADDR
COL.
ADDR
COL.
ADDR
tRCS
W
OE
tCWL
VIH -
tWP
VIL -
tWP
tCWD
tAWD
tRWD
VIH -
tCWD
tAWD
tCPWD
tOEA
tOEA
VIL -
tOED
tCAC
tCAC
tAA
DQ0 ~ DQ7
VI/OH VI/OL -
tDS
tRAC
tCLZ
VALID
DATA-IN
tOED
tAA
tOEZ
VALID
DATA-OUT
tCAC
tCAC
VI/OL -
tDH
tDS
tOEZ
tCLZ
tRAC
tOED
tAA
tDH
tOEZ
VALID
DATA-OUT
DQ8 ~ DQ15
VI/OH -
tRWL
tCWL
tRCS
tDH
tCLZ
tOED
tDH
tAA
tDS
VALID
DATA-IN
tDS
tOEZ
tCLZ
VALID
DATA-OUT
VALID
DATA-IN
VALID
DATA-OUT
VALID
DATA-IN
Don′t care
Undefined
KM416C1000C, KM416C1200C
KM416V1000C, KM416V1200C
CMOS DRAM
FAST PAGE MODE LOWER BYTE READ - MODIFY - WRITE CYCLE
tRP
tRASP
RAS
tCSH
VIH VIL -
tCRP
UCAS
VIH VIL -
tCRP
LCAS
tRPC
tPRWC
tRCD
VIH -
tRSH
tCP
tCAS
tCAS
VIL -
tRAD
tRAH
tASR
A
VIH VIL -
tRAL
tCAH
OE
tCAH
tASC
tASC
ROW
ADDR
COL.
ADDR
COL.
ADDR
tRCS
W
tCRP
tCWL
VIH -
tWP
VIL -
tWP
tCWD
tAWD
tRWD
VIH -
tCWD
tAWD
tCPWD
tOEA
tOEA
VIL -
tOED
tCAC
tCAC
tAA
DQ0 ~ DQ7
VI/OH VI/OL -
tRAC
tOEZ
tDH
tCLZ
VI/OL -
tOED
tDH
tAA
tDS
tDS
tOEZ
tCLZ
VALID
DATA-OUT
DQ8 ~ DQ15
VI/OH -
tRWL
tCWL
tRCS
VALID
DATA-IN
VALID
DATA-OUT
VALID
DATA-IN
OPEN
Don′t care
Undefined
KM416C1000C, KM416C1200C
KM416V1000C, KM416V1200C
CMOS DRAM
FAST PAGE MODE UPPER BYTE READ - MODIFY - WRITE CYCLE
tRP
tRASP
RAS
tCSH
VIH VIL -
tCRP
UCAS
tPRWC
tRCD
VIH -
tRSH
tCP
tCAS
tCRP
tCAS
VIL -
tRPC
tCRP
LCAS
VIH VIL -
tRAD
tRAH
tASR
A
VIH VIL -
tRAL
tCAH
tASC
tASC
ROW
ADDR
COL.
ADDR
COL.
ADDR
tRCS
W
OE
tCAH
tCWL
tRWL
tCWL
tRCS
tWP
VIH VIL -
tWP
tCWD
tAWD
tRWD
VIH -
tCWD
tAWD
tCPWD
tOEA
tOEA
VIL -
DQ0 ~ DQ7
VI/OH -
OPEN
VI/OL -
tOED
tOED
tCAC
tAA
DQ8 ~ DQ15
VI/OH VI/OL -
tRAC
tCAC
tDH
tOEZ
tAA
tDS
tDH
tOEZ
tDS
tCLZ
tCLZ
VALID
DATA-OUT
VALID
DATA-IN
VALID
DATA-OUT
VALID
DATA-IN
Don′t care
Undefined
KM416C1000C, KM416C1200C
KM416V1000C, KM416V1200C
CMOS DRAM
RAS - ONLY REFRESH CYCLE
NOTE : W, OE , DIN = Don′t care
DOUT = OPEN
tRC
VIH -
RAS
tRP
tRAS
VIL -
tRPC
tCRP
VIH -
UCAS
VIL -
tCRP
VIH -
LCAS
VIL -
tASR
VIH -
A
VIL -
tRAH
ROW
ADDR
CAS - BEFORE - RAS REFRESH CYCLE
NOTE : OE , A = Don′t care
tRC
tRP
VIH -
RAS
VIL -
tRP
tRAS
tCRP
tRPC
tCP
UCAS
tCSR
VIH -
tCHR
VIL -
tCP
LCAS
tCSR
VIH -
tCHR
VIL -
DQ0 ~ DQ7
VOH VOL DQ8 ~ DQ15
VOH VOL -
tOFF
OPEN
OPEN
Don′t care
Undefined
KM416C1000C, KM416C1200C
KM416V1000C, KM416V1200C
CMOS DRAM
HIDDEN REFRESH CYCLE ( READ )
tRC
RAS
tRAS
VIH -
tRSH
tCHR
tRCD
tRSH
tCHR
VIL -
VIH VIL -
tRAD
tASR
A
tRCD
VIH -
tCRP
LCAS
VIH VIL -
tRAH
tRAL
tASC
tCAH
ROW
ADDRESS
COLUMN
ADDRESS
tWRH
tRCS
W
tRP
tRAS
VIL -
tCRP
UCAS
tRC
tRP
VIH VIL -
tAA
OE
VIH -
tOEA
VIL -
tOFF
tCAC
tCLZ
DQ0 ~ DQ7
VOH VOL -
DQ8 ~ DQ15
VOH VOL -
tRAC
tOEZ
OPEN
DATA-OUT
OPEN
DATA-IN
DATA-OUT
Don′t care
Undefined
KM416C1000C, KM416C1200C
KM416V1000C, KM416V1200C
CMOS DRAM
HIDDEN REFRESH CYCLE ( WRITE )
NOTE : DOUT = OPEN
tRC
RAS
VIL -
tRCD
tRSH
tCHR
tRCD
tRSH
tCHR
VIH VIL -
tCRP
LCAS
tRP
tRAS
tRAS
VIH -
tCRP
UCAS
tRC
tRP
VIH VIL -
tRAD
tASR
A
VIH VIL -
tRAH
tASC
tRAL
tCAH
COLUMN
ADDRESS
ROW
ADDRESS
tWRH
W
OE
VIH -
tWRP
tWCS
tWCH
tWP
VIL -
VIH VIL -
DQ0 ~ DQ7
VIH -
tDS
DATA-IN
VIL DQ8 ~ DQ15
VIH VIL -
tDH
tDS
tDH
DATA-IN
Don′t care
Undefined
KM416C1000C, KM416C1200C
KM416V1000C, KM416V1200C
CMOS DRAM
CAS - BEFORE - RAS SELF REFRESH CYCLE
NOTE : OE , A = Don′t care
tRP
tRAS
tRPS
VIH -
RAS
VIL -
tRPC
tRPC
tCP
UCAS
VIH -
tCSR
tCHS
tCSR
tCHS
VIL -
tCP
LCAS
VIH VIL -
DQ0 ~ DQ7
VOH VOL DQ8 ~ DQ15
VOH VOL -
tOFF
OPEN
OPEN
Don′t care
Undefined
KM416C1000C, KM416C1200C
KM416V1000C, KM416V1200C
CMOS DRAM
PACKAGE DIMENSION
42 SOJ 400mil
Units : Inches (millimeters)
0.360 (9.15)
0.380 (9.65)
0.400 (10.16)
0.435 (11.06)
0.445 (11.30)
#42
0.006 (0.15)
0.012 (0.30)
#1
0.148 (3.76)
MAX
0.027 (0.69)
MIN
1.091 (27.71)
MAX
1.070 (27.19)
1.080 (27.43)
0.0375 (0.95)
0.050 (1.27)
0.026 (0.66)
0.032 (0.81)
0.015 (0.38)
0.021 (0.53)
50(44) TSOP(II) 400mil
0.400 (10.16)
0.455 (11.56)
0.471 (11.96)
Units : Inches (millimeters)
0.004 (0.10)
0.010 (0.25)
0.841 (21.35)
MAX
0.821 (20.85)
0.829 (21.05)
0.034 (0.875)
0.0315 (0.80)
0.047 (1.20)
MAX
0.010 (0.25)
TYP
0.002 (0.05)
MIN
0.010 (0.25)
0.018 (0.45)
0.018 (0.45)
0.030 (0.75)
0~8
O