SAMSUNG KMM5364003CSWG

DRAM MODULE
KMM5364003CSW/CSWG
4Byte 4Mx36 SIMM
(4Mx16 & Quad CAS 4Mx4 base)
Revision 0.0
June 1999
DRAM MODULE
Revision History
Version 0.0 (June 1999)
• The 4th. generation of 64Mb DRAM components are applied for this module.
KMM5364003CSW/CSWG
DRAM MODULE
KMM5364003CSW/CSWG
KMM5364003CSW/CSWG Fast Page Mode
4M x 36 DRAM SIMM Using 4Mx16 & Quad CAS 4Mx4, 4K Refresh, 5V
GENERAL DESCRIPTION
FEATURES
The Samsung KMM5364003C is a 4Mx36bits Dynamic RAM
high density memory module. The Samsung KMM5364003C
consists of two CMOS 4Mx16bits and one CMOS Quad CAS
4Mx4bits DRAMs in TSOP packages mounted on a 72-pin
glass-epoxy substrate. A 0.1 or 0.22uF decoupling capacitor
is mounted on the printed circuit board for each DRAM. The
KMM5364003C is a Single In-line Memory Module with edge
connections and is intended for mounting into 72 pin edge
connector sockets.
• Part Identification
PERFORMANCE RANGE
• JEDEC standard PDpin & pinout
- KMM5364003CSW(4K cycles/64ms Ref, TSOP, Solder)
- KMM5364003CSWG(4K cycles/64ms Ref, TSOP, Gold)
• Fast Page Mode Operation
• CAS-before-RAS & Hidden Refresh capability
• RAS-only refresh capability
• TTL compatible inputs and outputs
• Single +5V±10% power supply
• PCB : Height(1000mil), single sided component
Speed
tRAC
tCAC
tRC
tPC
-5
50ns
13ns
90ns
35ns
-6
60ns
15ns
110ns
40ns
PIN CONFIGURATIONS
Pin
Symbol
Pin
Symbol
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
VSS
DQ0
DQ18
DQ1
DQ19
DQ2
DQ20
DQ3
DQ21
Vcc
NC
A0
A1
A2
A3
A4
A5
A6
A10
DQ4
DQ22
DQ5
DQ23
DQ6
DQ24
DQ7
DQ25
A7
A11
Vcc
A8
A9
NC
RAS2
DQ26
DQ8
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
DQ17
DQ35
Vss
CAS0
CAS2
CAS3
CAS1
RAS0
NC
NC
W
NC
DQ9
DQ27
DQ10
DQ28
DQ11
DQ29
DQ12
DQ30
DQ13
DQ31
Vcc
DQ32
DQ14
DQ33
DQ15
DQ34
DQ16
NC
PD1
PD2
PD3
PD4
NC
Vss
PIN NAMES
Pin Name
Function
A0 - A11
Address Inputs
DQ0 - 35
Data In/Out
W
Read/Write Enable
RAS0, RAS2
Row Address Strobe
CAS0 - CAS3
Column Address Strobe
PD1 -PD4
Presence Detect
Vcc
Power(+5V)
Vss
Ground
NC
No Connection
PRESENCE DETECT PINS (Optional)
Pin
50NS
60NS
PD1
PD2
PD3
PD4
Vss
NC
Vss
Vss
Vss
NC
NC
NC
SAMSUNG ELECTRONICS CO., LTD. reserves the right to
change products and specifications without notice.
DRAM MODULE
KMM5364003CSW/CSWG
FUNCTIONAL BLOCK DIAGRAM
RAS
RAS0/RAS2
47Ω
LCAS
CAS0
47Ω
CAS1
UCAS
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ0
DQ1
DQ2
DQ3
DQ8
DQ17
DQ26
DQ35
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ27
DQ28
DQ29
DQ30
DQ31
DQ32
DQ33
DQ34
U0
OE
W A0-A11
RAS
CAS0
CAS1
U1
CAS2
CAS3
W A0-A11
RAS
47Ω
LCAS
CAS2
47Ω
CAS3
UCAS
U2
OE
W A0-A11
W
A0-A11
Vcc
0.1 or 0.22uF Capacitor
for each DRAM
Vss
To all DRAMs
DRAM MODULE
KMM5364003CSW/CSWG
ABSOLUTE MAXIMUM RATINGS *
Item
Voltage on any pin relative to VSS
Voltage on VCC supply relative to VSS
Storage Temperature
Power Dissipation
Short Circuit Output Current
Symbol
VIN, VOUT
VCC
Tstg
Pd
IOS
Rating
-1 to +7.0
-1 to +7.0
-55 to +125
3
50
Unit
V
V
°C
W
mA
* Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to
the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for intended
periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS (Voltage referenced to VSS, TA = 0 to 70°C)
Item
Symbol
Min
VCC
VSS
VIH
VIL
4.5
0
2.4
Supply Voltage
Ground
Input High Voltage
Input Low Voltage
-1.0
*2
Typ
Max
Unit
5.0
0
-
5.5
0
V
V
V
V
VCC*1
0.8
*1 : VCC+2.0V at pulse width≤20ns, which is measured at VCC.
*2 : -2.0V at pulse width≤20ns, which is measured at VSS.
DC AND OPERATING CHARACTERISTICS (Recommended operating conditions unless otherwise noted)
Symbol
Speed
ICC1
KMM5364003CSW/CSWG
Unit
Min
Max
-5
-6
-
330
300
mA
mA
ICC2
Don′t care
-
6
mA
ICC3
-5
-6
-
330
300
mA
mA
ICC4
-5
-6
-
220
190
mA
mA
ICC5
Don′t care
-
3
mA
ICC6
-5
-6
-
330
300
mA
mA
II(L)
IO(L)
Don′t care
-10
-5
10
5
uA
uA
VOH
VOL
Don′t care
2.4
-
0.4
V
V
ICC1 : Operating Current * (RAS, CAS, Address cycling @tRC=min)
ICC2 : Standby Current (RAS=CAS=W=V IH)
ICC3 : RAS Only Refresh Current * (CAS=VIH, RAS cycling @tRC=min)
ICC4 : Fast Page Mode Current * (RAS=VIL, CAS cycling : tPC=min)
ICC5 : Standby Current (RAS=CAS=W=Vcc-0.2V)
ICC6 : CAS-Before-RAS Refresh Current * (RAS and CAS cycling @tRC=min)
I(IL) : Input Leakage Current (Any input 0≤VIN≤Vcc+0.5V, all other pins not under test=0 V)
I(OL) : Output Leakage Current(Data Out is disabled, 0V≤VOUT≤Vcc)
VOH : Output High Voltage Level (IOH = -5mA)
VOL : Output Low Voltage Level (IOL = 4.2mA)
* NOTE : ICC1, ICC3, ICC4 and I CC6 are dependent on output loading and cycle rates. Specified values are obtained with the output open.
ICC is specified as an average current. In ICC1 and ICC3, address can be changed maximum once while RAS=VIL. In ICC4,
address can be changed maximum once within one Fast page mode cycle time, tPC.
DRAM MODULE
KMM5364003CSW/CSWG
CAPACITANCE (TA = 25°C, VCC=5V, f = 1MHz)
Item
Input capacitance[A0-A11]
Input capacitance[W]
Input capacitance[RAS0/RAS2]
Input capacitance[CAS0 - CAS3]
Input/Output capacitance[DQ0 - 35]
Symbol
CIN1
CIN2
CIN3
CIN4
CDQ
Min
Max
-
25
31
31
24
17
Unit
pF
pF
pF
pF
pF
AC CHARACTERISTICS (0°C≤TA≤70°C, VCC=5.0V±10%. See notes 1,2.)
Test condition : Vih/Vil=2.6/0.8V, Voh/Vol=2.4/0.4V, output loading CL=100pF
Parameter
Random read or write cycle time
Access time from RAS
Access time from CAS
Access time from column address
CAS to output in Low-Z
Output buffer turn-off delay
Transition time(rise and fall)
RAS precharge time
RAS pulse width
RAS hold time
CAS hold time
CAS pulse width
RAS to CAS delay time
RAS to column address delay time
CAS to RAS precharge time
Row address set-up time
Row address hold time
Column address set-up time
Column address hold time
Column address to RAS lead time
Read command set-up time
Read command hold referenced to CAS
Read command hold referenced to RAS
Write command hold time
Write command pulse width
Write command to RAS lead time
Write command to CAS lead time
Data set-up time
Data hold time
Refresh period
Write command set-up time
CAS setup time(CAS-before-RAS refresh)
CAS hold time(CAS-before-RAS refresh)
RAS to CAS precharge time
Access time from CAS precharge
Symbol
tRC
tRAC
tCAC
tAA
tCLZ
tOFF
tT
tRP
tRAS
tRSH
tCSH
tCAS
tRCD
tRAD
tCRP
tASR
tRAH
tASC
tCAH
tRAL
tRCS
tRCH
tRRH
tWCH
tWP
tRWL
tCWL
tDS
tDH
tREF
tWCS
tCSR
tCHR
tRPC
tCPA
-5
Min
-6
Max
90
Max
110
Unit
Note
ns
50
60
ns
3,4,10
13
15
ns
3,4,5
25
30
ns
3,10
0
0
0
13
1
50
30
50
Min
ns
3
0
15
ns
6
1
50
ns
2
40
10K
60
13
15
50
60
ns
10K
ns
ns
ns
13
10K
15
10K
ns
20
37
20
45
ns
4
15
25
15
30
ns
10
5
5
ns
0
0
ns
10
10
ns
0
0
ns
10
10
ns
25
30
ns
0
0
ns
0
0
ns
8
0
0
ns
8
10
10
ns
10
10
ns
15
15
ns
13
15
ns
0
0
ns
9
ns
9
10
10
64
0
64
ms
0
ns
ns
5
5
10
10
ns
5
5
ns
30
35
ns
7
3
DRAM MODULE
KMM5364003CSW/CSWG
AC CHARACTERISTICS (0°C≤TA≤70°C, VCC=5.0V±10%. See notes 1,2.)
Test condition : Vih/Vil=2.6/0.8V, Voh/Vol=2.4/0.4V, output loading CL=100pF
Parameter
Fast page mode cycle time
CAS precharge time(Fast page cycle)
RAS pulse width(Fast page cycle)
W to RAS precharge time(C-B-R refresh)
W to RAS hold time(C-B-R refresh)
Symbol
tPC
tCP
tRASP
tWRP
tWRH
-5
Min
-6
Max
35
Max
40
10
50
Min
60
Note
ns
10
200K
Unit
ns
200K
ns
10
10
ns
10
10
ns
NOTES
1. An initial pause of 200us is required after power-up followed
by any 8 RAS-only or CAS-before-RAS refresh cycles before
proper device operation is achieved.
6. This parameter defines the time at which the output achieves
the open circuit condition and is not referenced to VOH or
VOL.
2. Input voltage levels are Vih/Vil. VIH(min) and VIL(max) are reference levels for measuring timing of input signals. Transition
times are measured between VIH(min) and VIL(max) and are
assumed to be 5ns for all inputs.
7. tWCS is non-restrictive operating parameter. It is included in
the data sheet as electrical characteristics only. If
tWCS≥tWCS(min), the cycle is an early write cycle and the
data out pin will remain high impedance for the duration of
the cycle.
3. Measured with a load equivalent to 2 TTL loads and 100pF.
8. Either tRCH or tRRH must be satisfied for a read cycle.
4. Operation within the tRCD(max) limit insures that tRAC(max)
can be met. tRCD(max) is specified as a reference point only.
If tRCD is greater than the specified tRCD(max) limit, then
access time is controlled exclusively by tCAC.
5. Assumes that tRCD≥tRCD(max).
9. These parameters are referenced to the CAS leading edge in
early write cycles.
10. Operation within the tRAD(max) limit insures that tRAC(max)
can be met. tRAD(max) is specified as reference point only. If
tRAD is greater than the specified tRAD(max) limit, then
access time is controlled by tAA.
DRAM MODULE
KMM5364003CSW/CSWG
READ CYCLE
tRC
tRAS
RAS
tRP
VIH VIL -
tCSH
tCRP
CAS
tRCD
tCRP
tRSH
tCAS
VIH VIL -
tRAD
tASR
A
VIH VIL -
tRAH
tASC
tRAL
tCAH
COLUMN
ADDRESS
ROW
ADDRESS
tRCH
tRCS
W
tRRH
VIH VIL -
tOFF
tAA
OE
VIH -
tOEZ
tOEA
VIL -
tCAC
DQ
VOH VOL -
tRAC
OPEN
tCLZ
DATA-OUT
Don′t care
Undefined
DRAM MODULE
KMM5364003CSW/CSWG
WRITE CYCLE ( EARLY WRITE )
NOTE : DOUT = OPEN
tRAS
RAS
tRC
tRP
VIH VIL -
tCSH
tCRP
CAS
tRCD
tRSH
tCAS
VIH VIL -
tRAD
tASR
A
tCRP
VIH VIL -
tRAH
tASC
ROW
ADDRESS
tRAL
tCAH
COLUMN
ADDRESS
tCWL
tRWL
tWCS
W
OE
tWP
VIL -
VIH VIL -
tDS
DQ
tWCH
VIH -
VIH VIL -
tDH
DATA-IN
Don′t care
Undefined
DRAM MODULE
KMM5364003CSW/CSWG
WRITE CYCLE ( OE CONTROLLED WRITE )
NOTE : DOUT = OPEN
tRC
tRAS
RAS
tRP
VIH VIL -
tCSH
tCRP
CAS
tRSH
tCAS
VIH VIL -
VIH VIL -
tCRP
tRAD
tASR
A
tRCD
tRAH
tRAL
tASC
tCAH
COLUMN
ADDRESS
ROW
ADDRESS
tCWL
tRWL
W
OE
VIH -
tWP
VIL -
VIH VIL -
tOED
tOEH
tDS
DQ
VIH VIL -
tDH
DATA-IN
Don′t care
Undefined
DRAM MODULE
KMM5364003CSW/CSWG
READ - MODIFY - WRTIE CYCLE
tRWC
tRP
tRAS
VIH -
RAS
VIL -
tCRP
tRCD
tRSH
tCAS
VIH -
CAS
tRAD
VIL -
tASR
tRAH
tASC
tCAH
tCSH
VIH -
A
VIL -
ROW
ADDR
COLUMN
ADDRESS
tRWL
tCWL
tAWD
tCWD
W
OE
VIH -
tWP
VIL -
tRWD
tOEA
VIH VIL -
tCLZ
tCAC
tAA
DQ
VI/OH VI/OL -
tOED
tOEZ
tRAC
VALID
DATA-OUT
tDS
tDH
VALID
DATA-IN
Don′t care
Undefined
DRAM MODULE
KMM5364003CSW/CSWG
FAST PAGE READ CYCLE
NOTE : DOUT = OPEN
tRP
tRASP
RAS
VIH -
tRHCP
VIL -
¡ó
tCRP
CAS
VIH -
VIH VIL -
tCP
tCAS
tCAS
tRAD
tASC
VIL -
tASR
A
tPC
tCP
tRCD
tRSH
tCAS
¡ó
tCSH
tRAH
tCAH
ROW
ADDR
tASC
COLUMN
ADDRESS
tCAH
COLUMN
ADDRESS
tASC
¡ó
tCAH
COLUMN
ADDRESS
¡ó
tRRH
tRCS
W
tRCH
tRCS
VIL -
tCAC
tOEA
VIH VIL -
VOH VOL -
tCAC
tOEA
¡ó
¡ó
tAA
tAA
DQ
tRCH
¡ó
VIH -
tCAC
tOEA
OE
tRCS
tRAC
tCLZ
tOEZ
VALID
DATA-OUT
tOFF
tCLZ
tOEZ
VALID
DATA-OUT
tAA
tOFF
tCLZ
tOFF
tOEZ
VALID
DATA-OUT
Don′t care
Undefined
DRAM MODULE
KMM5364003CSW/CSWG
FAST PAGE WRITE CYCLE ( EARLY WRITE )
NOTE : DOUT = OPEN
tRP
tRASP
RAS
tRHCP
VIH VIL -
¡ó
tPC
tCRP
CAS
VIH -
tRAD
tASC
VIH VIL -
tCSH
tCAH
tRAH
ROW
ADDR
tASC
COLUMN
ADDRESS
VIH -
tWCH
tCAH
tASC
¡ó
tWCS
tWP
¡ó
tWCH
tWP
tCAH
COLUMN
ADDRESS
tWCS
¡ó
tWCH
tWP
VIL -
¡ó
VIL -
VIH VIL -
tCWL
tRWL
tCWL
VIH -
¡ó
tDS
DQ
tCAS
COLUMN
ADDRESS
tCWL
OE
tRSH
¡ó
tWCS
W
tCP
tCAS
tCAS
VIL -
tASR
A
tPC
tCP
tRCD
tDH
VALID
DATA-IN
tDS
tDH
VALID
DATA-IN
tDS
tDH
¡ó
VALID
DATA-IN
¡ó
Don′t care
Undefined
DRAM MODULE
KMM5364003CSW/CSWG
FAST PAGE READ - MODIFY - WRITE CYCLE
tRP
tRASP
RAS
VIH -
tCSH
VIL -
tRSH
tRCD
CAS
tCP
VIH -
tCRP
tCAS
tCAS
VIL -
tRAD
tPRWC
tRAH
tASR
A
VIH VIL -
ROW
ADDR
tCAH
tASC
COL.
ADDR
COL.
ADDR
tRWL
tRCS
W
tRAL
tCAH
tASC
tCWL
VIH -
tCWL
tWP
VIL -
tWP
tCWD
tCWD
tAWD
OE
tAWD
tCPWD
tRWD
tOEA
VIH -
tOEA
VIL -
tOED
tCAC
tCAC
tAA
tRAC
DQ
tOEZ
tDH
tOED
tDH
tAA
tDS
tDS
tOEZ
VI/OH VI/OL -
tCLZ
tCLZ
VALID
DATA-OUT
VALID
DATA-IN
VALID
DATA-OUT
VALID
DATA-IN
Don′t care
Undefined
DRAM MODULE
KMM5364003CSW/CSWG
RAS - ONLY REFRESH CYCLE
NOTE : W, OE, DIN = Don′t care
DOUT = OPEN
tRAS
RAS
tRC
tRP
VIH VIL -
tRPC
tCRP
CAS
VIH VIL -
tASR
A
tCRP
VIH VIL -
tRAH
ROW
ADDR
CAS - BEFORE - RAS REFRESH CYCLE
NOTE : OE, A = Don′t care
tRC
tRP
RAS
tRAS
tRP
VIH VIL -
tRPC
tCP
CAS
tRPC
tCSR
VIH -
tWRP
W
tCHR
VIL -
tWRH
VIH VIL -
tOFF
DQ
VOH VOL -
OPEN
Don′t care
Undefined
DRAM MODULE
KMM5364003CSW/CSWG
HIDDEN REFRESH CYCLE ( READ )
tRC
tRC
tRP
tRAS
RAS
VIH VIL -
tCRP
CAS
tRP
tRAS
tRCD
tRSH
tCHR
VIH VIL -
tRAD
tASR
A
VIH VIL -
tRAH
tASC
ROW
ADDRESS
tCAH
COLUMN
ADDRESS
tWRH
tRCS
W
tRRH
tWRP
VIH VIL -
tAA
OE
VIH -
tOEA
VIL -
tOFF
tCAC
tRAC
DQ
VOH VOL -
OPEN
tCLZ
tOEZ
DATA-OUT
Don′t care
Undefined
DRAM MODULE
KMM5364003CSW/CSWG
HIDDEN REFRESH CYCLE ( WRITE )
NOTE : DOUT = OPEN
tRC
RAS
VIH -
tRP
tRCD
tRSH
tCHR
VIH VIL -
tRAD
tASR
A
tRAS
VIL -
tCRP
CAS
tRC
tRP
tRAS
VIH VIL -
tRAH
tASC
ROW
ADDRESS
tCAH
COLUMN
ADDRESS
tWRH
tWRP
W
OE
VIH -
tWCS
tWCH
tWP
VIL -
VIH VIL -
tDS
DQ
VIH VIL -
tDH
DATA-IN
Don′t care
Undefined
DRAM MODULE
KMM5364003CSW/CSWG
CAS-BEFORE-RAS REFRESH COUNTER TEST CYCLE
tRP
VIH -
RAS
tRAS
VIL VIH -
CAS
tCPT
tCSR
tRSH
tCAS
tCHR
VIL -
tRAL
tASC
VIH -
A
VIL -
READ CYCLE
tWRP
tWRH
tRRH
tAA
tRCS
tRCH
tCAC
VIH -
W
VIL VIH -
OE
VIL -
tOEA
tCLZ
VOH -
DQ
tCAH
COLUMN
ADDRESS
tOEZ
DATA-OUT
VOL -
WRITE CYCLE
W
tOFF
tWRP
tRWL
tWRH
VIH -
tCWL
tWCS
tWCH
VIL -
tWP
OE
VIH VIL -
tDS
DQ
tDH
VIH DATA-IN
VIL -
READ-MODIFY-WRITE
tWRP
W
tWRH
tAWD
tRCS
tCWL
tCWD
VIH -
tRWL
tWP
tCAC
VIL -
tAA
tOEA
OE
VIH -
tOED
VIL -
tCLZ
DQ
tOEZ
tDH
tDS
VI/OH VI/OL VALID
DATA-OUT
VALID
DATA-IN
Don′t care
NOTE : This timing diagram is applied to all devices besides 16M DRAM 4th & 64M DRAM.
Undefined
DRAM MODULE
KMM5364003CSW/CSWG
CAS - BEFORE - RAS SELF REFRESH CYCLE
NOTE : OE, A = Don′t care
tRP
RAS
tRASS
tRPS
VIH VIL -
tRPC
tRPC
tCP
CAS
tCHS
VIH -
tCSR
VIL -
tOFF
DQ
VOH -
OPEN
VOL -
tWRP
W
tWRH
VIH VIL -
TEST MODE IN CYCLE
NOTE : OE, A = Don′t care
tRC
tRP
RAS
tRAS
tRP
VIH VIL -
tRPC
tCP
CAS
tRPC
VIH -
tCSR
tWTS
W
tCHR
VIL -
tWTH
VIH VIL -
tOFF
DQ
VOH VOL -
OPEN
Don′t care
Undefined
DRAM MODULE
KMM5364003CSW/CSWG
PACKAGE DIMENSIONS
Units : Inches (millimeters)
4.250(107.95)
3.984(101.19)
.133(3.38)
.125 DIA±.002(3.18±.051)
R.062(1.57)
.400(10.16)
1.000(25.40)
.250(6.35)
.080(2.03)
.250(6.35)
R.062±.004(R1.57±.10)
.250(6.35)
3.750(95.25)
( Front view )
( Back view )
Gold/Solder Plating Lead
.100(2.54)
MAX
.010(.25)MAX
.050(1.27)
.041±.004(1.04±.10)
0.125 MIN
(3.20MIN)
.054(1.37)
.047(1.19)
Tolerances : ±.005(.13) unless otherwise specified
NOTE : The used device is 4Mx16 & Quad CAS 4Mx4 DRAM, TSOPII
DRAM Part No. : KMM5364003CSW/CSWG -- KM416C4100CS & KM44C4003CS(300 mil)