KM44C4005C, KM44C4105C CMOS DRAM 4M x 4Bit CMOS Quad CAS DRAM with Extended Data Out DESCRIPTION This is a family of 4,194,304 x 4 bit Quad CAS with Extended Data Out Mode CMOS DRAMs. Extended Data Out Mode offers high speed random access of memory cells within the same row, so called Hyper Page Mode. Refresh cycle (2K Ref. or 4K Ref.), access time (-5 or -6), power consumption(Normal or Low power) and package type(SOJ or TSOP-II) are optional features of this family. All of this family have CAS-before-RAS refresh, RAS-only refresh and Hidden refresh capabilities. Furthermore, Self-refresh operation is available in L-version. Four separate CAS pins provide for seperate I/O operation allowing this device to operate in parity mode. This 4Mx4 Extended Data Out Quad CAS DRAM family is fabricated using Samsung′s advanced CMOS process to realize high bandwidth, low power consumption and high reliability. FEATURES • Extended Data Out mode operation • Part Identification (Fast Page Mode with Extended Data Out) • Four separate CAS pins provide for separate I/O operation - KM44C4005C/C-L (5V, 4K Ref.) - KM44C4105C/C-L (5V, 2K Ref.) • CAS-before-RAS refresh capability • RAS-only and Hidden refresh capability • Self-refresh capability (L-ver only) • Fast parallel test mode capability • Active Power Dissipation • TTL compatible inputs and outputs Unit : mW • Early Write or output enable controlled write Refresh Cycle Speed 4K 2K -5 495 605 -6 440 550 • JEDEC Standard pinout • Available in Plastic SOJ and TSOP(II) packages • Single +5V±10% power supply FUNCTIONAL BLOCK DIAGRAM • Refresh Cycles Part NO. Refresh cycle Refresh period Normal C4005C 4K 64ms C4105C 2K 32ms L-ver RAS CAS0 - 3 W Control Clocks Vcc Vss VBB Generator 128ms Data in Refresh Control • Performance Range Refresh Counter Speed tRAC tCAC tRC tHPC -5 50ns 13ns 84ns 20ns -6 60ns 15ns 104ns 25ns A0-A11 (A0 - A10) *1 A0 - A9 (A0 - A10) *1 Memory Array 4,194,304 x 4 Cells Row Address Buffer Col. Address Buffer Buffer Row Decoder Column Decoder Note) *1 : 2K Refresh SAMSUNG ELECTRONICS CO., LTD. reserves the right to change products and specifications without notice. Sense Amps & I/O Refresh Timer DQ0 to DQ3 Data out Buffer OE KM44C4005C, KM44C4105C CMOS DRAM PIN CONFIGURATION (Top Views) •KM44C40(1)05CK VCC DQ0 DQ1 W RAS *A11(N.C) CAS0 CAS1 A10 A0 A1 A2 A3 VCC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 •KM44C40(1)05CS VSS DQ3 DQ2 CAS3 OE A9 CAS2 N.C A8 A7 A6 A5 A4 VSS VCC DQ0 DQ1 W RAS *A11(N.C) CAS0 CAS1 A10 A0 A1 A2 A3 VCC *A11 is N.C for KM44C4105C(5V, 2K Ref. product) K : 300mil 28 SOJ S : 300mil 28 TSOP II Pin Name Pin Function A0 - A11 Address Inputs (4K Product) A0 - A10 Address Inputs (2K Product) DQ0 - 3 Data In/Out VSS Ground RAS Row Address Strobe CAS0~CAS3 Column Address Strobe W Read/Write Input OE Data Output Enable VCC Power(+5.0V) N.C No Connection 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VSS DQ3 DQ2 CAS3 OE A9 CAS2 N.C A8 A7 A6 A5 A4 VSS KM44C4005C, KM44C4105C CMOS DRAM ABSOLUTE MAXIMUM RATINGS Parameter Symbol Rating Units VIN, VOUT -1.0 to +7.0 V Voltage on VCC supply relative to VSS VCC -1.0 to +7.0 V Storage Temperature Tstg -55 to +150 °C Power Dissipation PD 1 W Short Circuit Output Current IOS 50 mA Voltage on any pin relative to VSS * Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded. Functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS (Voltage referenced to Vss, TA= 0 to 70°C) Parameter Symbol Min Typ Max Units Supply Voltage VCC 4.5 5.0 5.5 V Ground VSS 0 0 0 V Input High Voltage VIH 2.4 - VCC+1.0*1 V Input Low Voltage VIL -1.0*2 - 0.8 V *1 : VCC+2.0V/20ns, Pulse width is measured at VCC *2 : -2.0/20ns, Pulse width is measured at VSS DC AND OPERATING CHARACTERISTICS (Recommended operating conditions unless otherwise noted.) Parameter Symbol Min Max Units Input Leakage Current (Any input 0≤VIN≤VIN+0.5V, all other input pins not under test=0 Volt) II(L) -5 5 uA Output Leakage Current (Data out is disabled, 0V≤VOUT ≤VCC) IO(L) -5 5 uA Output High Voltage Level(IOH=-5mA) VOH 2.4 - V Output Low Voltage Level(IOL=4.2mA) VOL - 0.4 V KM44C4005C, KM44C4105C CMOS DRAM DC AND OPERATING CHARACTERISTICS (Continued) Symbol Power Speed ICC1 Don′t care ICC2 Max Units KM44C4005C KM44C4105C -5 -6 90 80 110 100 mA mA mA Normal L Don′t care 2 1 2 1 mA mA ICC3 Don′t care -5 -6 90 80 110 100 mA mA mA ICC4 Don′t care -5 -6 80 70 90 80 mA mA mA ICC5 Normal L Don′t care 1 250 1 250 mA uA ICC6 Don′t care -5 -6 90 80 110 100 mA mA mA ICC7 L Don′t care 300 300 uA ICCS L Don′t care 250 250 uA ICC1 * : Operating Current (RAS and CAS cycling @tRC=min.) ICC2 : Standby Current (RAS=CAS=W=VIH) ICC3 * : RAS-only Refresh Current (CAS=VIH, RAS cycling @tRC=min.) ICC4 * : Hyper Page Mode Current (RAS=VIL, CAS, Address cycling @tHPC =min.) ICC5 : Standby Current (RAS=CAS=W=VCC-0.2V) ICC6 * : CAS-Before-RAS Refresh Current (RAS and CAS cycling @tRC=min.) ICC7 : Battery back-up current, Average power supply current, Battery back-up mode Input high voltage(VIH)=VCC-0.2V, Input low voltage(VIL)=0.2V, CAS=0.2V, DQ=Don′t care, TRC=31.25us(4K/L-ver), 62.5us(2K/L-ver), TRAS =TRAS min~300ns ICCS : Self Refresh Current RAS=CAS=0.2V, W=OE=A0 ~ A11=VCC-0.2V or 0.2V, DQ0 ~ DQ3=VCC-0.2V, 0.2V or Open *Note : ICC1 , ICC3 , ICC4 and ICC6 are dependent on output loading and cycle rates. Specified values are obtained with the output open. ICC is specified as an average current. In ICC1 , ICC3 and ICC6 address can be changed maximum once while RAS=VIL. In ICC4 , address can be changed maximum once within one Hyper page mode cycle time, tHPC . KM44C4005C, KM44C4105C CMOS DRAM CAPACITANCE (TA=25°C, VCC=5V, f=1MHz) Parameter Symbol Min Max Units Input capacitance [A0 ~ A11] CIN1 - 5 pF Input capacitance [RAS, CASx, W, OE] CIN2 - 7 pF Output capacitance [DQ0 - DQ3] CDQ - 7 pF AC CHARACTERISTICS (0°C≤TA≤70°C, See note 1,2) Test condition : VCC=5.0V±10%, Vih/Vil=2.4/0.8V, Voh/Vol=2.0/0.8V Parameter -5 Symbol Min -6 Max Min Units Notes Max Random read or write cycle time tRC 84 104 ns Read-modify-write cycle time tRWC 106 140 ns Access time from RAS tRAC 50 60 ns 3,4,10 Access time from CAS tCAC 13 15 ns 3,4,5,20 Access time from column address tAA 25 30 ns 3,10 CAS to output in Low-Z ns 3,20 ns 6,13 ns 3 ns 2 tCLZ 3 Output buffer turn-off delay from CAS tCEZ 3 3 OE to output in Low-Z tOLZ 3 Transition time (rise and fall) tT 2 RAS precharge time tRP 30 RAS pulse width tRAS 50 RAS hold time tRSH 13 15 ns 16 CAS hold time tCSH 38 45 ns 19 CAS pulse width tCAS 8 10K 10 10K ns 25 RAS to CAS delay time tRCD 20 37 20 45 ns 4,18 RAS to column address delay time tRAD 15 25 15 30 ns 10 CAS to RAS precharge time tCRP 5 5 ns 17 Row address set-up time tASR 0 0 ns Row address hold time tRAH 10 10 ns Column address set-up time tASC 0 0 ns 18 Column address hold time tCAH 8 10 ns 18 Column address to RAS lead time tRAL 25 30 ns Read command set-up time tRCS 0 0 ns Read command hold time referenced to CAS tRCH 0 0 ns 8,17 Read command hold time referenced to RAS tRRH 0 0 ns 8 Write command hold time tWCH 10 10 ns 16 13 3 15 3 50 2 50 40 10K 60 ns 10K ns Write command pulse width tWP 10 10 ns Write command to RAS lead time tRWL 13 15 ns Write command to CAS lead time tCWL 8 10 ns 19 KM44C4005C, KM44C4105C CMOS DRAM AC CHARACTERISTICS (Continued) Parameter -5 Symbol Min -6 Max Min Units Notes Max Data set-up time tDS 0 0 ns 9 Data hold time tDH 8 10 ns 9 Refresh period (2K, Normal) tREF 32 32 ms Refresh period (4K, Normal) tREF 64 64 ms Refresh period (L-ver) tREF 128 ms Write command set-up time 128 tWCS 0 0 ns 7,18 CAS to W delay time tCWD 30 34 ns 7,16 RAS to W delay time tRWD 67 79 ns 7 Column address to W delay time tAWD 42 49 ns 7 CAS precharge to W delay time tCPWD 47 54 ns 7 CAS set-up time (CAS -before-RAS refresh) tCSR 5 5 ns 18 CAS hold time (CAS -before-RAS refresh) tCHR 10 10 ns 17 RAS to CAS precharge time tRPC 5 5 ns 18 Access time from CAS precharge tCPA Hyper Page mode cycle time tHPC 20 Hyper Page read-modify-write cycle time 28 35 24 ns 3,17 ns 14,21 tHPRWC 62 71 ns 14,21 CAS precharge time (Hyper Page cycle) tCP 8 10 ns 22 RAS pulse width (Hyper Page cycle) tRASP 50 RAS hold time from CAS precharge tRHCP 30 200K 60 200K 35 13 ns ns OE access time tOEA OE to data delay tOED Output buffer turn off delay time from OE tOEZ 3 OE command hold time tOEH 13 15 ns Write command set-up time (Test mode in) tWTS 10 10 ns 11 11 13 15 15 13 3 15 ns 23 ns 24 ns 6 Write command hold time (Test mode in) tWTH 10 10 ns W to RAS precharge time(C-B-R refresh) tWRP 10 10 ns W to RAS hold time(C-B-R refresh) tWRH 10 10 ns Output data hold time tDOH 5 5 ns Output buffer turn off delay from RAS tREZ 3 13 Output buffer turn off delay from W tWEZ 3 13 W to data delay tWED 15 15 ns OE to CAS hold time tOCH 5 5 ns CAS hold time to OE tCHO 5 5 ns OE precharge time tOEP 5 5 ns W pulse width (Hyper Page Cycle) tWPE 5 5 ns RAS pulse width (C-B-R self refresh) tRASS 100 100 us 27,28,29 RAS precharge time (C-B-R self refresh) tRPS 90 110 ns 27,28,29 CAS hold time (C-B-R self refresh) tCHS -50 -50 ns 27,28,29 Hold time CAS low to CAS high tCLCH 5 5 ns 15,26 3 15 3 15 ns 6,13 ns 6 KM44C4005C, KM44C4105C CMOS DRAM TEST MODE CYCLE Parameter ( Note 11 ) -5 Symbol Min -6 Max Min Units Notes Max Random read or write cycle time tRC 89 109 ns Read-modify-write cycle time tRWC 121 145 ns Access time from RAS tRAC 55 65 ns 3,4,10,12 Access time from CAS tCAC 18 20 ns 3,4,5,12 Access time from column address tAA 3,10,12 RAS pulse width CAS pulse width 35 ns tRAS 55 10K 30 65 10K ns tCAS 13 10K 15 10K ns RAS hold time tRSH 18 20 ns CAS hold time tCSH 43 50 ns Column address to RAS lead time tRAL 30 35 ns CAS to W delay time tCWD 35 39 ns 7 RAS to W delay time tRWD 72 84 ns 7 Column address to W delay time tAWD 47 54 ns 7 CAS precharge to W delay time tCPWD 52 59 ns 7 Hyper Page mode cycle time tHPC 25 30 ns 14 Hyper Page read-modify-write cycle time ns 14 tHPRWC 52 RAS pulse width (Hyper Page cycle) tRASP 55 Access time from CAS precharge tCPA OE access time tOEA OE to data delay OE command hold time 61 200K 65 33 18 200K ns 40 ns 20 ns tOED 18 20 ns tOEH 18 20 ns 3 KM44C4005C, KM44C4105C CMOS DRAM NOTES 1. An initial pause of 200us is required after power-up followed by any 8 RAS-only refresh or CAS-before-RAS refresh cycles before proper device operation is achieved. 2. VIH(min) and VIL(max) are reference levels for measuring timing of input signals. Transition times are measured between VIH(min) and VIL(max) and are assumed to be 2ns for all inputs. 3. Measured with a load equivalent to 2 TTL loads and 100pF. 4. Operation within the tRCD (max) limit insures that tRAC (max) can be met. tRCD (max) is specified as a reference point only. If tRCD is greater than the specified tRCD (max) limit, then access time is controlled exclusively by tCAC . 5. Assumes the tRCD ≥tRCD (max). 6. This parameter defines the time at which the output achieves the open circuit condition and is not referenced to Voh or Vol. 7. tWCS , tRWD , tCWD , tAWD and tCPWD are non restrictive operating parameters. They are included in the data sheet as electrical characteristics only. If tWCS ≥tWCS (min), the cycle is an early write cycle and the data output will remain high impedance for the duration of the cycle. If tCWD ≥tCWD (min), tRWD ≥tRWD (min), tAWD ≥tAWD (min) and tCPWD ≥tCPWD (min), then the cycle is a readmodify-write cycle and the data output will contain the data read from the selected address. If neither of the above conditions is satisfied, the condition of the data out is indeterminate. 8. tRCH and tRRH must be satisfied for a read cycle. 9. These parameters are referenced to the first CAS falling edge in early write cycles and to W falling edge in OE controlled write cycle and read-modify-write cycles. 10. Operation within the tRAD (max) limit insures that tRAC (max) can be met. tRAD (max) is specified as a reference point only. If tRAD is greater than the specified tRAD (max) limit, then access time is controlled by tAA. 11. These specifications are applied in the test mode. 12. In test mode read cycle, the values of tRAC, tAA and tCAC are delayed by 2ns to 5ns for the specified values. These parameters should be specified in test mode cycles by adding 5ns to the specified value in this data sheet. 13. If RAS goes high before CAS high going, the open circuit condition of the output is achieved by CAS high going. If CAS goes high before RAS high going, the open circuit condition of the output is achieved by RAS high going. 14. tASC ≥6ns, Assume tT = 2.0ns. 15. In order to hold the address latched by the first CAS going low, the parameter tCLCH must be met. 16. The last CASx edge to go low. 17. The last CASx edge to go high. 18. The first CASx edge to go low. 19. The first CASx edge to go high. 20. Output parameter is refrenced to corresponding CASx input. 21. The last rising CASx edge to next cycle′s last rising CASx edge. 22. The last rising CASx edge to first falling CASx edge. 23. The first DQx controlled by the first CASx to go low. 24. The last DQx controlled by the last CASx to go high. 25. Each CASx must meet minimum pulse width. 26. The last falling CASx edge to the first rising CASx edge. 27. If tRASS ≥100us, then RAS precharge time must use tRPS instead of tRP. 28. For RAS-only refresh and burst CAS-before-RAS refresh mode, 4096(4K)/2048(2K) cycles of burst refresh must be executed within 64ms/32ms before and after self refresh, in order to meet refresh specification. 29. For distributed CAS-before-RAS with 15.6us interval, CAS-before-RAS refresh should be executed with in 15.6us immediately before and after self refresh in order to meet refresh specification. KM44C4005C, KM44C4105C CMOS DRAM READ CYCLE tRC tRAS RAS tRP VIH VIL - tCSH tCRP CAS0 tCRP tRCD tRSH VIH - tCAS VIL - tCRP CAS1 VIH VIL - tCRP CAS2 VIH VIL - tCRP CAS3 tCLCH VIH VIL - tRAD tASR A VIH VIL - tRAH tASC ROW ADDRESS tRAL tCAH COLUMN ADDRESS tRCH tRCS W tRRH VIH - tROH VIL - tAA OE VIH - tOEA VIL - DQ0 ~ DQ3 VIH VIL - tOEZ tCAC tCLZ tREZ tCEZ tRAC OPEN DATA-OUT tOLZ tWEZ Don′t care Undefined KM44C4005C, KM44C4105C CMOS DRAM WRITE CYCLE ( EARLY WRITE ) NOTE : DOUT = OPEN tRC tRAS RAS tRP VIH VIL - tCSH tCRP CAS0 tCRP tRCD tRSH VIH - tCAS VIL - tCRP CAS1 VIH VIL - tCRP CAS2 VIH VIL - tCRP CAS3 tCLCH VIH VIL - tCSH tRAD tASR A VIH VIL - tRAH tASC ROW ADDRESS tRAL tCAH COLUMN ADDRESS tWCS W OE VIH - tWCH tWP VIL - VIH VIL - DQ0 ~ DQ3 VIH VIL - tDS tDH DATA-IN Don′t care Undefined KM44C4005C, KM44C4105C CMOS DRAM WRITE CYCLE ( OE CONTROLLED WRITE ) NOTE : DOUT = OPEN tRC tRAS RAS tRP VIH VIL - tCSH tCRP CAS0 tRCD tCRP tRSH tCAS VIH VIL - tCRP CAS1 VIH VIL - tCRP CAS2 VIH VIL - tCRP CAS3 tCLCH VIH VIL - tRAD tASR A VIH VIL - tRAH tRAL tASC tCAH COLUMN ADDRESS ROW ADDRESS tCWL tRWL W OE VIH - tWP VIL - VIH VIL - DQ0 ~ DQ3 VIH VIL - tOED tOEH tDS tDH DATA-IN Don′t care Undefined KM44C4005C, KM44C4105C CMOS DRAM READ - MODIFY - WRTIE CYCLE tRC tRAS RAS tRP VIH VIL - tCSH tCRP CAS0 tCRP tRCD tRSH VIH - tCAS VIL - tCRP CAS1 VIH VIL - tCRP CAS2 VIH VIL - tCRP CAS3 tCLCH VIH VIL - tRAD tASR A VIH VIL - tRAH tRAL tASC ROW ADDRESS tCAH COLUMN ADDRESS tRWL tAWD tCWD W OE tCWL VIH - tWP VIL - tRWD tOEA VIH VIL - DQ0 ~ DQ3 VIH - tCLZ tCAC tAA tOED tOEZ tRAC VALID DATA-OUT VIL - tDS tDH VALID DATA-IN tOLZ Don′t care Undefined KM44C4005C, KM44C4105C CMOS DRAM HYPER PAGE MODE READ CYCLE tRP tRASP RAS VIH - tRHCP VIL - tCRP CAS0 VIH - tCP tCAS tCAS VIL - tHPC tCP tRCD tASC tRSH tCAS ¡ó tCLCH VIH CAS1 ¡ó tHPC tCLCH VIL VIH - CAS2 VIL - ¡ó tRAL VIH CAS3 tRAD VIL - tASR A VIH VIL - ROW ADDR tRAH OE tASC COLUMN ADDRESS tRCS W ¡ó tCSH tASC tCAH tCAH tASC tCAH ¡ó COLUMN ADDRESS tRCH tRCH tRCS tAA tOEA tAA tCPA ¡ó VIH VIL - tRRH tRCH tRCS ¡ó VIH VIL - COLUMN ADDRESS ¡ó tAA tCPA ¡ó tCAC DQ0 DQ1 VIH - tRAC tCLZ VALID DATA-OUT VIL VIH - tOEZ tOEZ tCLZ VALID DATA-OUT ¡ó tOEZ VALID DATA-OUT tCLZ VIL - VALID DATA-OUT ¡ó VALID DATA-OUT ¡ó VALID DATA-OUT tRAC DQ2 DQ3 VIH VIL VIH VIL - tOLZ VALID DATA-OUT tCLZ ¡ó VALID DATA-OUT Don't care Undefined KM44C4005C, KM44C4105C CMOS DRAM HYPER PAGE MODE WRITE CYCLE ( EARLY WRITE ) NOTE : DOUT = OPEN tRP tRASP RAS tRHCP VIH VIL - CAS0 CAS1 CAS2 CAS3 OE VIL VIH - VIH - tCAS tCAS VIL - ¡ó VIH VIL - VIH VIL - tCAS tRAD tASC ¡ó tCSH tCAH tRAH ROW ADDR tASC COLUMN ADDRESS VIH - tWCH tCAH tASC ¡ó COLUMN ADDRESS tWCS ¡ó tWCH tWP tCAH COLUMN ADDRESS tWCS ¡ó tWCH tWP tWP VIL - ¡ó VIH VIL - ¡ó VIH VIL VIH VIL VIH VIL - tDH tDS VIH VIL - tDH tDS tDH ¡ó VALID DATA-IN VALID DATA-IN ¡ó tDH VALID DATA-IN tDS tDH ¡ó VALID DATA-IN tDH ¡ó tDS VALID DATA-IN tDH ¡ó VALID DATA-IN VALID DATA-IN tDS DQ3 tCAS VIL - tDS DQ2 ¡ó tCAS tDS DQ1 tRSH tCAS ¡ó tDS DQ0 tCP tCAS tCAS tWCS W tHPC tCP tRCD VIH - tASR A ¡ó tHPC tCRP ¡ó tDH ¡ó VALID DATA-IN ¡ó Don′t care Undefined KM44C4005C, KM44C4105C CMOS DRAM HYPER PAGE READ - MODIFY - WRITE CYCLE tRP tRASP RAS VIH - tPRWC VIL - tRSH CAS0 CAS1 CAS2 CAS3 VIH - VIH - tCLCH tCAS VIL VIH - tCAS tCAS VIL VIH - tCAS tCLCH VIL - VIH VIL - tCSH tRAD tRAH tASC tRAL tCAH tCAH tASC COL. ADDR ROW ADDR COL. ADDR tRCS W tCAS tCAS VIL - tASR A tRWL tCWL tCWL VIH - tWP VIL - tWP tCWD tCWD tAWD OE tCRP tCP tRCD tAWD tRWD tOEA VIH - tOEA VIL - tOED tCAC tCAC tAA DQ0 ~ DQ3 tRAC tOEZ tDH tOED tDH tAA tDS tDS tOEZ VIH VIL - tCLZ tCLZ VALID DATA-OUT VALID DATA-IN VALID DATA-OUT VALID DATA-IN Don′t care Undefined KM44C4005C, KM44C4105C CMOS DRAM RAS - ONLY REFRESH CYCLE* NOTE : W, OE, DIN = Don′t care DOUT = OPEN tRAS RAS tRC tRP VIH VIL - tRPC tCRP CASX VIH VIL - tASR A tCRP VIH VIL - tRAH ROW ADDR CAS - BEFORE - RAS REFRESH CYCLE NOTE : OE, A = Don′t care tRC tRP RAS tRAS tRP VIH VIL - tRPC tCP CASX tRPC tCSR VIH - tWRP W tCHR VIL - tWRH VIH VIL - DQ0 ~ DQ3 VIH - tCEZ OPEN VIL Don′t care Undefined KM44C4005C, KM44C4105C CMOS DRAM HIDDEN REFRESH CYCLE ( READ ) tRC tRC tRP tRAS RAS VIH VIL - tCRP CASX tRP tRAS tRCD tRSH tCHR VIH VIL - tRAD tASR A VIH VIL - tRAH tASC ROW ADDRESS tCAH COLUMN ADDRESS tWRH tRCS W VIH VIL - tAA OE VIH - tOEA VIL - tCEZ tCAC tRAC DQX VIH VIL - OPEN tCLZ tOEZ DATA-OUT Don′t care Undefined KM44C4005C, KM44C4105C CMOS DRAM HIDDEN REFRESH CYCLE ( WRITE ) NOTE : DOUT = OPEN tRC RAS VIH - tRP tRCD tRSH tCHR VIH VIL - tRAD tASR A tRAS VIL - tCRP CASX tRC tRP tRAS VIH VIL - tRAH tASC tCAH ROW ADDRESS COLUMN ADDRESS tWRH tWRP tWCS W OE VIH - tWCH tWP VIL - VIH VIL - tDS DQX VIH VIL - tDH DATA-IN Don′t care Undefined KM44C4005C, KM44C4105C CMOS DRAM CAS - BEFORE - RAS SELF REFRESH CYCLE NOTE : OE, A = Don′t care, WE=Vcc-0.2V tRP RAS tRASS tRPS VIH VIL - tRPC tRPC tCP CASX tCHS VIH - tCSR VIL - DQ0 ~ DQ3 VOH - tCEZ OPEN VOL - TEST MODE IN CYCLE NOTE : OE, A = Don′t care tRC tRP RAS tRAS tRP VIH VIL - tCRP tCP CASX tRPC VIH - tCSR tWTS W tCHR VIL - tWTH VIH VIL - DQ0 ~ DQ3 VIH VIL - tCEZ OPEN Don′t care Undefined KM44C4005C, KM44C4105C CMOS DRAM PACKAGE DIMENSION 28 SOJ 300mil Units : Inches (millimeters) 0.280 (7.11) 0.260 (6.61) 0.300 (7.62) 0.330 (8.39) 0.340 (8.63) #28 0.006 (0.15) 0.012 (0.30) #1 0.148 (3.76) MAX 0.027 (0.69) MIN 0.741 (18.82) MAX 0.720 (18.30) 0.730 (18.54) 0.0375 (0.95) 0.050 (1.27) 0.026 (0.66) 0.032 (0.81) 0.015 (0.38) 0.021 (0.53) 28 TSOP(II) 300mil 0.300 (7.62) 0.355 (9.02) 0.371 (9.42) Units : Inches (millimeters) 0.004 (0.10) 0.010 (0.25) 0.741 (18.81) MAX 0.721 (18.31) 0.729 (18.51) 0.037 (0.95) 0.050 (1.27) 0.047 (1.20) MAX 0.002 (0.05) MIN 0.012 (0.30) 0.020 (0.50) 0.010 (0.25) TYP 0.018 (0.45) 0.030 (0.75) 0~8 O