DRAM MODULE M466F0804DT1-L M466F0804DT1-L EDO Mode 8M x 64 DRAM SODIMM Using 4Mx16, 4K Refresh 3.3V, Low power/Self-Refresh GENERAL DESCRIPTION FEATURES The Samsung M466F0804DT1-L is a 8Mx64bits Dynamic RAM high density memory module. The • Part Identification Samsung - M466F0804DT1-L(4096 cycles/128ms, TSOP, L-ver) M466F0804DT1-L consists of eight CMOS 4Mx16bits DRAMs • Extended Data Out Mode Operation in TSOP 400mil packages and a 2K EEPROM in • New JEDEC standard proposal with EEPROM 8-pin TSSOP package mounted on a 144-pin glass-epoxy sub- • Serial Presense Detect with EEPROM strate. A 0.1uF decoupling capacitor is mounted on the • CAS-before-RAS Refresh capability printed circuit board for each DRAM. The M466F0804DT1-L • Self -refresh capability is a Small Out-line Dual in-line Memory Module and is • RAS-only and Hidden refresh capability intended for mounting into 144 pin edge connector sockets. • LVTTL compatible inputs and outputs • Single +3.3V±0.3V power supply PERFORMANCE RANGE • PCB : Height(1000mil), double sided component Speed tRAC tCAC tRC tHPC -L50 50ns 13ns 84ns 20ns -L60 60ns 15ns 104ns 25ns PIN CONFIGURATIONS PIN NAMES Pin Front Pin Back Pin Front Pin Back Pin Front Pin Back Pin Name VSS DQ0 DQ1 DQ2 DQ3 VCC DQ4 DQ5 DQ6 DQ7 VSS CAS0 CAS1 VCC A0 A1 A2 VSS DQ8 DQ9 DQ10 DQ11 VCC DQ12 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 VSS DQ32 DQ33 DQ34 DQ35 VCC DQ36 DQ37 DQ38 DQ39 VSS CAS4 CAS5 VCC A3 A4 A5 VSS DQ40 DQ41 DQ42 DQ43 VCC DQ44 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 DQ13 DQ14 DQ15 VSS RSVD RSVD RFU VCC RFU W RAS0 RAS1 OE VSS RSVD RSVD VCC DQ16 DQ17 DQ18 DQ19 VSS DQ20 DQ21 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 DQ45 DQ46 DQ47 VSS RSVD RSVD RFU VCC RFU RFU RFU RFU RFU VSS RSVD RSVD VCC DQ48 DQ49 DQ50 DQ51 VSS DQ52 DQ53 97 99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 DQ22 DQ23 VCC A6 A8 VSS A9 A10 VCC CAS2 CAS3 VSS DQ24 DQ25 DQ26 DQ27 VCC DQ28 DQ29 DQ30 DQ31 VSS SDA VCC 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 DQ54 DQ55 VCC A7 A11 VSS NC NC VCC CAS6 CAS7 Vss DQ56 DQ57 DQ58 DQ59 VCC DQ60 DQ61 DQ62 DQ63 Vss SCL VCC A0 to 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 Function Address Inputs DQ0 - DQ63 Data In/Out W Read/Write Enable OE Output Enable RAS0, RAS1 Row Address Strobe CAS0 - CAS7 Column Address Strobe VCC Power(+3.3V) VSS Ground NC No Connection SDA Serial Address / Data I/O SCL Serial Clock RSVD Reserved Use RFU Reserved for Future Use REV. 0.1 Oct. 2000 DRAM MODULE M466F0804DT1-L FUNCTIONAL BLOCK DIAGRAM RAS0 RAS1 W OE A0-A11 DQ0~15 DQ32~47 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 LCAS DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 UCAS DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 UCAS DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 LCAS DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 LCAS DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 UCAS DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 LCAS CAS0 U0 CAS1 UCAS LCAS DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 U4 U2 LCAS UCAS DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 UCAS CAS5 LCAS CAS6 UCAS CAS7 DQ48~63 U1 CAS3 CAS4 U6 DQ16~31 CAS2 LCAS DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 U5 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 U3 U7 UCAS DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 Serial PD VCC 0.1uF Capacitor for each DRAM To all DRAMs SCL A0 A1 A2 SDA Vss Vss REV. 0.1 Oct. 2000 DRAM MODULE M466F0804DT1-L ABSOLUTE MAXIMUM RATINGS * Item Symbol Rating Unit Voltage on any pin relative VSS VIN, VOUT -0.5 to +4.6 V Voltage on VCC supply relative to VSS VCC -0.5 to +4.6 V Storage Temperature Tstg -55 to +125 °C Power Dissipation PD 8 W Short Circuit Output Current IOS 50 mA * Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for intended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS (Voltage referenced to VSS, TA = 0 to 70°C) Item Supply Voltage Ground Input High Voltage Input Low Voltage Symbol VCC VSS VIH VIL Min 3.0 0 2.0 -0.3*2 Typ 3.3 0 - Max 3.6 0 VCC+0.3*1 0.8 Unit V V V V *1 : VCC+1.3V at pulse width≤15ns, which is measured at VCC. *2 : -1.3V at pulse width≤15ns, which is measured at VSS. DC AND OPERATING CHARACTERISTICS (Recommended operating conditions unless otherwise noted) ICC1 ICC2 ICC3 ICC4 ICC5 ICC6 ICC7 ICCS I(IL) I(OL) VOH VOL Symbol Speed ICC1 M466F0804DT1-L Unit Min Max -50 -60 - 484 444 mA mA ICC2 Don′t care - 8 mA ICC3 -50 -60 - 484 444 mA mA ICC4 -50 -60 - 364 324 mA mA ICC5 Don′t care - 1.6 mA ICC6 -50 -60 - 484 444 mA mA ICC7 ICCS Don′t care - 2.8 2.8 mA mA II(L) IO(L) Don′t care -10 -10 10 10 uA uA VOH VOL Don′t care 2.4 - 0.4 V V : Operating Current * (RAS, CAS, Address cycling @tRC=min) : Standby Current (RAS=CAS=W=VIH) : RAS Only Refresh Current * (CAS=VIH, RAS cycling @ tRC=min) : Extended Data Out Mode Current * (RAS=VIL, CAS cycling : tHPC=min) : Standby Current (RAS=CAS=W=VCC-0.2V) : CAS-Before-RAS Refresh Current * (RAS and CAS cycling @tRC=min) : Battery back-up current. Average power supply, Battery back-up mode. Input high voltage(VIH)=VCC-0.2V, Input low voltage(VIL )=0.2V, UCAS,LCAS=0.2V, DQ=Don′t care, tRC=31.25us, tRAS=tRASmin~300ns : Self Refresh Current, RAS=UCAS=LCAS=VIL, W=OE=A0~A11=VCC-0.2V or 0.2V, DQ~DQ63=VCC-0.2V or Open : Input Leakage Current (Any input 0≤VIN≤Vcc+0.3V, all other pins not under test=0 V) : Output Leakage Current(Data Out is disabled, 0V≤VOUT≤VCC) : Output High Voltage Level (IOH = -2mA) : Output Low Voltage Level (IOL = 2mA) * NOTE : ICC1, ICC3, ICC4 and ICC6 are dependent on output loading and cycle rates. Specified values are obtained with the output open. ICC is specified as an average current. In ICC1 and ICC3, address can be changed maximum once while RAS=VIL. In ICC4 , address can be changed maximum once within one EDO mode cycle time, tHPC. REV. 0.1 Oct. 2000 DRAM MODULE M466F0804DT1-L CAPACITANCE (TA = 25°C, VCC=3.3V, f = 1MHz) Item Input capacitance[A0-A11] Input capacitance[W, OE] Input capacitance[RAS0, RAS1] Input capacitance[CAS0 - CAS7] Input/Output capacitance[DQ0 - 63] Symbol Min Max Unit CIN1 CIN2 CIN3 CIN4 CDQ - 50 66 38 24 24 pF pF pF pF pF AC CHARACTERISTICS (0°C≤TA≤70°C, VCC=3.3V±0.3V. See notes 1,2.) Test condition : Vih/Vil=2.2/0.7V, Voh/Vol=2.0/0.8V, output loading CL=100pF Parameter -50 Symbol Min Random read or write cycle time Read-modify-write cycle time Access time from RAS Access time from CAS Access time from column address CAS to output in Low-Z OE to output in Low-Z Output buffer turn-off delay from CAS Transition time(rise and fall) RAS precharge time RAS pulse width RAS hold time CAS hold time CAS pulse width RAS to CAS delay time RAS to column address delay time CAS to RAS precharge time Row address set-up time Row address hold time Column address set-up time Column address hold time Column address to RAS lead time Read command set-up time Read command hold referenced to CAS Read command hold referenced to RAS Write command set-up time Write command hold time Write command pulse width Write command to RAS lead time Write command to CAS lead time Data set-up time Data hold time Refresh period CAS to W dealy time RAS to W dealy time tRC tRWC tRAC tCAC tAA tCLZ tOLZ tCEZ tT tRP tRAS tRSH tCSH tCAS tRCD tRAD tCRP tASR tRAH tASC tCAH tRAL tRCS tRCH tRRH tWCS tWCH tWP tRWL tCWL tDS tDH tREF tCWD tRWD -60 Max Min 84 104 128 153 Unit Note Max ns ns 50 60 ns 3,4,9 13 15 ns 3,4,5 25 30 ns 3,9 ns 3 3 3 3 ns 3 3 13 3 3 13 ns 3,11 1 50 1 50 ns 2 10K ns 30 50 40 10K 60 8 10 38 40 8 10K 10 ns ns ns 10K ns 17 37 20 45 ns 4 12 25 15 30 ns 9 5 5 ns 0 0 ns 7 10 ns 0 0 ns 12 12 7 10 ns 25 30 ns 0 0 ns 0 0 ns 7 0 0 ns 7 0 0 ns 6 7 10 ns 6 7 10 ns 8 10 ns 7 10 ns 15 0 0 ns 8,18 ns 8,18 7 10 128 128 ms 33 38 ns 6,14 70 84 ns 6 REV. 0.1 Oct. 2000 DRAM MODULE M466F0804DT1-L AC CHARACTERISTICS (0°C≤TA≤70°C, VCC=3.3V±0.3V. See notes 1,2.) Test condition : Vih/Vil=2.2/0.7V, Voh/Vol=2.0/0.8V, output loading CL=100pF Parameter -50 Symbol Min Column address to W delay time CAS precharge to W delay time CAS setup time (CAS-before-RAS refresh) CAS hold time (CAS-before-RAS refresh) RAS to CAS precharge time Access time from CAS precharge Hyper page mode cycle time Hyper page mode read-modify write cycle time CAS precharge time (Hyper page cycle) RAS pulse width (Hyper page cycle) RAS hold time from CAS precharge W to RAS precharge time (C-B-R refresh) W to RAS hold time (C-B-R refresh) OE access time OE to data delay Output buffer turn off delay time from OE OE command hold time Output data hold time Output buffer turn off delay from RAS Output buffer turn off delay from W W to data delay OE to CAS hold time CAS hold time to OE OE precharge time W pulse width(Hyper page cycle) RAS pulse width (C-B-R self refresh) RAS precharge time (C-B-R self refresh) CAS hold time (C-B-R self refresh) tAWD tCPWD tCSR tCHR tRPC tCPA tHPC tHPRWC tCP tRASP tRHCP tWRP tWRH tOEA tOED tOEZ tOEH tDOH tREZ tWEZ tWED tOCH tCHO tOEP tWPE tRASS tRPS tCHS -60 Max Min Unit Note Max 45 53 ns 6 47 58 ns 6 5 5 ns 16 10 10 ns 17 5 5 ns ns 3 20 28 25 ns 10 67 73 ns 10 ns 13 7 50 35 10 200K 60 200K ns 30 35 ns 10 10 ns 10 10 ns 13 10 3 15 13 13 3 5 5 5 5 3 13 3 13 15 3 ns 13 ns ns ns 3 15 3 15 15 ns ns 11 ns ns 5 5 ns 5 5 ns 5 5 ns 5 5 ns 100 100 us 19,20,21 90 110 ns 19,20,21 -50 -50 ns 19,20,21 REV. 0.1 Oct. 2000 DRAM MODULE M466F0804DT1-L NOTES 1. An initial pause of 200us is required after power-up followed by any 8 RAS-only or CAS-before-RAS refresh cycles before proper device operation is achieved. 2. Input voltage levels are Vih/Vil. VIH(min) and VIL(max) are reference levels for measuring timing of input signals. Transition times are measured between VIH(min) and V IL(max) and are assumed to be 5ns for all inputs. 10. tASC≥6ns, Assume tT=2.0ns 11. If RAS goes high before CAS high going, the open circuit condition of the output is achieved by CAS high going. If CAS goes high before RAS high going , the open circuit condition of the output is achieved by RAS going. 12. tASC is referenced to the earlier CAS falling edge and tCAH is referenced to the later CAS falling edge. 3. Measured with a load equivalent to 1 TTL loads and 100pF. 4. Operation within the tRCD(max) limit insures that tRAC(max) can be met. tRCD(max) is specified as a reference point only. If tRCD is greater than the specified tRCD(max) limit, then access time is controlled exclusively by tCAC. 5. Assumes that tRCD ≥tRCD(max). 6. tWCS, tRWD, tCWD, tAWD and tCPWD are non-restrictive operating parameter. They are included in the data sheet as electrical characteristics only. If tWCS≥tWCS(min), the cycle is an early write cycle and the data out pin will remain high impedance for the duration of the cycle. If tRWD≥tRWD(min), tCWD≥tCWD(min), tAWD ≥tAWD(min) and tCPWD≥tCPWD(min). The cycle is a read-modify-write cycle and the data out will contain data read from the selected cell. If neither of the above sets of conditions is satisfied, the condition of data out(at access time) is indeterminate. 13. tCP is specified from the last CAS rising edge in the previous cycle to the first CAS falling edge in the next cycle. 14. tCWD is referenced to the later CAS falling edge at word readmodify-write cycle. 15. tCWL is specified from W falling edge to the earlier CAS rising edge. 16. tCSR is referenced to earlier CAS falling edge to the RAS falling edge. 17. tCHR is referenced to the later CAS rising from RAS falling edge. 18. tDS, tDH is specified by the earlier CAS falling edge. 19. If tRASS≥100us, then RAS precharge time must use tRPS instead of tRP. 7. Either tRCH or tRRH must be satisfied for a read cycle. 8. These parameters are referenced to the CAS leading edge in early write cycles. 9. Operation within the tRAD(max) limit insures that tRAC(max) can be met. tRAD(max) is specified as reference point only. If tRAD is greater than the specified tRAD (max) limit access time is controlled by tAA. 20. For RAS-only refresh and burst CAS-before-RAS refresh mode, 4096 cycles of burst refresh must be executed within 64ms before and after self refresh, in order to meet refresh specification. 21. For distributed CAS-before-RAS with 15.6us interval CASbefore-RAS should be executed with in 15.6us immediately before and after self refresh in order to meet refresh specification. REV. 0.1 Oct. 2000 DRAM MODULE M466F0804DT1-L READ CYCLE tRC tRAS RAS VIL - tCSH tCRP CAS tRP VIH - tRCD tCRP tRSH VIH - tCAS VIL - tRAD tASR A VIH VIL - tRAH tRAL tASC tCAH COLUMN ADDRESS ROW ADDRESS tRCH tRCS W tRRH VIH VIL - tWEZ tCEZ tAA OE VIH - tOEZ tOEA VIL - tOLZ tCAC DQ VOH VOL - tRAC OPEN tCLZ tREZ DATA-OUT Don′t care Undefined REV. 0.1 Oct. 2000 DRAM MODULE M466F0804DT1-L WRITE CYCLE ( EARLY WRITE ) NOTE : D OUT = OPEN tRC tRAS RAS tRP VIH VIL - tCSH tCRP CAS tRSH VIH - VIH VIL - tCRP tCAS VIL - tRAD tASR A tRCD tRAH tASC ROW ADDRESS tRAL tCAH COLUMN ADDRESS tCWL tRWL tWCS W OE VIH VIL - VIH VIL - tDS DQ tWCH tWP VIH VIL - tDH DATA-IN Don′t care Undefined REV. 0.1 Oct. 2000 DRAM MODULE M466F0804DT1-L WRITE CYCLE ( OE CONTROLLED WRITE ) NOTE : DOUT = OPEN tRC tRAS RAS VIL - tCSH tCRP CAS tRP VIH - tRCD tRSH tCAS VIH - tCRP VIL - tRAD tRAL tASR A VIH VIL - tRAH tASC tCAH ROW ADDRESS COLUMN ADDRESS tCWL tRWL W OE tWP VIH VIL - VIH VIL - tOED tDS DQ VIH - tOEH tDH DATA-IN VIL - Don′t care Undefined REV. 0.1 Oct. 2000 DRAM MODULE M466F0804DT1-L READ - MODIFY - WRITE CYCLE tRAS RAS tRWC VIL - tCRP tRCD tRSH VIH - CAS tRP VIH - tCAS VIL - tRAD tASR tRAH tASC tCAH tCSH A VIH VIL - ROW ADDR COLUMN ADDRESS tAWD tRWL tCWD W tCWL VIH - tWP VIL - tRWD OE tOEA VIH VIL - tOLZ tCLZ tCAC tAA DQ VI/OH VI/OL - tOED tOEZ tRAC VALID DATA-OUT tDS tDH VALID DATA-IN Don′t care Undefined REV. 0.1 Oct. 2000 DRAM MODULE M466F0804DT1-L HYPER PAGE READ CYCLE tRP tRASP RAS VIH VIL - ¡ó tCSH tCRP CAS VIL - VIL - tHPC tCP tCAS tHPC tCP tCAS tCP tCAS tCAS tRAD tASR A tRCD VIH - VIH - tRHCP tHPC tRAH tASC ROW ADDR tCAH tASC COLUMN ADDRESS tCAH COLUMN ADDRESS tASC tCAH COLUMN ADDR tASC tCAH tREZ COLUMN ADDRESS tRRH tRCS W tRCH VIH - tCPA VIL - tCAC tAA tCPA tCAC tAA OE VIH - tAA tCPA tOCH tOEA tAA tCHO tOEP tOEA VIL - tOEP tCAC tDOH tRAC DQ tCAC tCAC VOH VOL - VALID DATA-OUT tOLZ tCLZ tOEZ tOEA tOEZ tOEZ VALID DATA-OUT VALID DATA-OUT VALID DATA-OUT Don′t care Undefined REV. 0.1 Oct. 2000 DRAM MODULE M466F0804DT1-L HYPER PAGE WRITE CYCLE ( EARLY WRITE ) NOTE : DOUT = OPEN tRP tRASP RAS VIH - tRHCP VIL - ¡ó tHPC tCRP CAS tRCD tHPC tCP VIH - tCAS VIL - tRSH tCP tCAS tCAS tRAD ¡ó tCSH tASR A VIH VIL - tRAH ROW ADDR. tASC tCAH COLUMN ADDRESS tWCS W VIH - tASC tWCH COLUMN ADDRESS tWCS tWP ¡ó tCAH COLUMN ADDRESS tWCS ¡ó tWCH tWP VIL - tCWL tCWL tRWL VIH - ¡ó VIL - ¡ó tDS DQ tASC ¡ó tWCH tWP tCWL OE tCAH VIH VIL - tDH tDS tDH tDS tDH ¡ó VALID DATA-IN VALID DATA-IN ¡ó VALID DATA-IN Don′t care Undefined REV. 0.1 Oct. 2000 DRAM MODULE M466F0804DT1-L HYPER PAGE READ-MODIFY-WRITE CYCLE RAS tCSH tHPRWC tRCD tCAS VIL - VIH VIL - tCAS tRAD tRAH ROW ADDR tCAH tASC tCAH tASC COL. ADDR tRWL tCWL tCWL VIH - tWP VIL - tWP tCWD tCWD tAWD tRWD OE tRAL COL. ADDR tRCS W tCRP tCP VIH - tASR A tRSH VIL - tCRP CAS tRP tRASP VIH - VIH - tAWD tCPWD tOEA tOEA VIL - tOED tOED tCAC tAA tDH tOEZ tCAC tAA tDS tDH tOEZ tDS tRAC DQ VI/OH VI/OL - tCLZ tCLZ tOLZ VALID DATA-OUT VALID DATA-IN tOLZ VALID DATA-OUT VALID DATA-IN Don′t care Undefined REV. 0.1 Oct. 2000 DRAM MODULE M466F0804DT1-L HYPER PAGE READ AND WRITE MIXED CYCLE tRP tRASP RAS VIH - READ(tCAC ) READ(tCPA) tHPC tHPC tCP tCP CAS VIH VIL - VIH VIL - tCAS tRAD tASR A tRAH tASC ROW ADDR tCAH COLUMN ADDRESS tRCS W READ(tAA) WRITE VIL - tCAS tRCS tCAH tASC COLUMN ADDRESS tRCH tCAS tCAS tCAH tASC tHPC tCP COL. ADDR tRCH tASC tCAH COL. ADDR tWCH tRCH tWCS VIH VIL - tWPE tCLZ tWED tCPA OE VIH VIL - tOEA tCAC tAA DQ VI/OH VI/OL - tWEZ tDH tWEZ tDS VALID VALID DATA-IN tREZ tAA tRAC VALID DATA-OUT DATA-OUT VALID DATA-OUT Don′t care Undefined REV. 0.1 Oct. 2000 DRAM MODULE M466F0804DT1-L RAS - ONLY REFRESH CYCLE* NOTE : W, OE, DIN = Don′t care DOUT = OPEN tRC RAS VIH - tRP tRAS VIL - tRPC tCRP CAS VIH VIL - tASR A tCRP VIH VIL - tRAH ROW ADDR CAS - BEFORE - RAS REFRESH CYCLE NOTE : OE , A = Don′t care tRC tRP RAS VIH VIL - tRPC tCP CAS tRAS VIH - tRPC tCSR tCHR VIL - tWRP W tRP tWRH VIH VIL - tCEZ DQ VOH VOL - OPEN Don′t care Undefined * In RAS-only refresh cycle of 64Mb A-dile & B-die, when CAS signal transits from Low to High, the valid data may be cut off. REV. 0.1 Oct. 2000 DRAM MODULE M466F0804DT1-L HIDDEN REFRESH CYCLE ( READ ) tRC RAS tRAS VIH - tRP tRAS VIL - tCRP CAS tRC tRP tRCD tRSH tCHR VIH VIL - tRAD tASR A VIH VIL - tRAH tASC tCAH COLUMN ADDRESS ROW ADDRESS tRCS W tRRH tWRH tWRP VIH VIL - tAA OE VIH - tOEA VIL - tCEZ tOLZ tCAC tCLZ tRAC DQ VOH VOL - OPEN tREZ tWEZ tOEZ DATA-OUT Don′t care Undefined REV. 0.1 Oct. 2000 DRAM MODULE M466F0804DT1-L HIDDEN REFRESH CYCLE ( WRITE ) NOTE : DOUT = OPEN tRC RAS tRAS VIH - tRP tRAS VIL - tCRP CAS tRC tRP tRCD tRSH tCHR VIH VIL - tRAD tASR A VIH VIL - tRAH tASC ROW ADDRESS tCAH COLUMN ADDRESS tWRP tWCS W OE VIH - tWCH tWP VIL - VIH VIL - tDS DQ tWRH VIH VIL - tDH DATA-IN Don′t care Undefined REV. 0.1 Oct. 2000 DRAM MODULE M466F0804DT1-L CAS-BEFORE-RAS REFRESH COUNTER TEST CYCLE tRP RAS CAS VIH - tRAS VIL VIH - tCPT tCSR tRSH tCAS tCHR VIL - tRAL tASC A VIH VIL - READ CYCLE W OE tWRP tWRH tRRH tAA tRCS tRCH tCAC VIH VIL VIH VIL - tOEA tCLZ VOH - DQ tCAH COLUMN ADDRESS tOEZ W tWEZ DATA-OUT VOL - WRITE CYCLE tCEZ tREZ tWRP tRWL tWRH tCWL tWCS VIH - tWCH VIL - tWP OE VIH VIL - tDS DQ tDH VIH DATA-IN VIL - READ-MODIFY-WRITE tWRP W tWRH tAWD tRCS tCWL tCWD VIH - tRWL tWP tCAC VIL - tAA tOEA OE VIH - tOED VIL - tCLZ DQ tOEZ tDH tDS VI/OH VI/OL VALID DATA-OUT VALID DATA-IN NOTE : This timing diagram is applied to all devices besides 64M DRAM based modules. Don′t care Undefined REV. 0.1 Oct. 2000 DRAM MODULE M466F0804DT1-L CAS - BEFORE - RAS SELF REFRESH CYCLE NOTE : OE, A = Don′t care tRP RAS VIL - tRPS tRPC tRPC tCP CAS tRASS VIH - VIH - tCHS tCSR VIL - tCEZ DQ W VOH - OPEN VOL - VIH VIL - tWRP tWRH TEST MODE IN CYCLE NOTE : OE , A = Don′t care tRC tRP RAS tRP tRAS VIH VIL - tRPC tRPC tCP CAS tCSR VIH - tWTS W tCHR VIL - tWTH VIH VIL - tCEZ DQ VOH VOL - OPEN Don′t care Undefined REV. 0.1 Oct. 2000 DRAM MODULE M466F0804DT1-L PACKAGE DIMENSIONS Units : Inches (millimeters) 2.66(67.60) 2-R 0.078 Min (2.00 Min) 0.24 (6.0) 0.79 (20.00) 2.50(63.60) 0.13(3.30) 0.91(23.20) 1.29(32.80) 0.10 (2.50) 1.01 (25.654) 0.16±0.039 (4.00±0.1) 2-φ 0.07 (1.80) 0.18 (4.60) 0.083 (2.10) ( Front view ) Z Y 1.15 (3.70) 0.150Max (3.81Max) 0.04±0.0039 (1.00±0.10) 0.10 Min 0.162 Min (4.11 Min) (2.25 Min) ( Back view ) 0.06±0.0039 (1.50±0.1) 0.008±0.006 (0.200±0.150) 0.160±0.0039 (4.00±0.1) Detail Z 0.024±0.001 (0.60±0.05) 0.03 TYP (0.80 TYP) Detail Y Tolerances : ±.005(.13) unless otherwise specified The used device is 4Mx16 DRAM with EDO mode, TSOP II DRAM Part No. : K4E641612D-T REV. 0.1 Oct. 2000