PRELIMINARY CMOS SRAM KM681000B Family 128K x8 bit Low Power CMOS Static RAM FEATURES ¡Ü ¡Ü ¡Ü ¡Ü ¡Ü ¡Ü GENERAL DESCRIPTION Process Technology : 0.6§- CMOS Organization : 128Kx8 Power Supply Voltage : Single 5.0V ¡¾ 10% Low Data Retention Voltage : 2V(Min) Three state output and TTL Compatible Package Type : JEDEC Standard 32-DIP, 32-SOP, 32-TSOP I R/F The KM681000B family is fabricated by SAMSUNG's advanced CMOS process technology. The family can support various operating temperature ranges and have various package types for user flexibility of system design. The family also support low data retention voltage for battery back-up operation with low data retention current. PRODUCT FAMILY Power Dissipation Product Family KM681000BL Operating Temperature Speed Commercial(0~7¡É) 55/70ns 32-DIP,32-SOP 32-TSOP I R/F 100§Ë Extended(-25~85¡É) 70/100ns 32-SOP 32-TSOP I R/F 100§Ë Industrial(-40~85¡É) 70/100ns 32-SOP 32-TSOP I R/F 100§Ë PKG Type KM681000BL-L KM681000BLE KM681000BLE-L KM681000BLI KM681000BLI-L PIN DESCRIPTION N.C 1 32 VCC 2 31 A15 A14 3 30 CS2 4 29 WE A7 5 28 A13 A6 6 27 A8 32-DIP 32-SOP 26 A9 25 A11 9 24 OE A2 10 23 A10 A1 11 22 CS1 A5 7 A4 8 A3 A0 12 21 I/O8 I/O1 13 20 I/O7 I/O2 14 19 I/O6 I/O3 15 18 I/O5 VSS 16 17 I/O4 50§Ë 50§Ë FUNCTIONAL BLOCK DIAGRAM 1 32 2 31 3 30 4 29 5 28 27 6 7 8 9 10 32-TSOP Type I - Forward 26 25 24 23 11 22 12 21 13 20 14 19 15 18 16 17 OE A10 CS1 I/O8 I/O7 I/O6 I/O5 I/O4 VSS I/O3 I/O2 I/O1 A0 A1 A2 A3 A0~3, A8~11 Y-Decoder A4~7, A12~16 I/O1~8 A4 A5 A6 A7 A12 A14 A16 NC VCC A15 CS2 WE A13 A8 A9 A11 70mA 16 17 15 18 14 19 13 20 12 21 22 11 10 9 8 32-TSOP Type I-Reverse 23 24 25 7 26 6 27 5 28 4 29 3 30 2 31 1 32 A3 A2 A1 A0 I/O1 I/O2 I/O3 VSS I/O4 I/O5 I/O6 I/O7 I/O8 CS1 A10 OE Cell Array I/O Buffer Name Function A0~A16 Address Inputs WE Write Enable Input CS1,CS2 Chip Select Inputs OE Output Enable Input I/O1~I/O18 Data Inputs/Outputs Vcc Power Vss Ground N.C No Connection Control Logic A12 Operating (ICC2) 20§Ë X-Decoder A16 A11 A9 A8 A13 WE CS2 A15 VCC NC A16 A14 A12 A7 A6 A5 A4 Standby (ISB1, Max) CS1,CS2 WE,OE Revision 0.3 April 1996 PRELIMINARY CMOS SRAM KM681000B Family PRODUCT LIST & ORDERING INFORMATION PRODUCT LIST Commercial Temp Product (0~70¡É) Extended Temp Products (-25~85¡É) Part Name Industrial Temp Products (-40~85¡É) Part Name Function Function Part Name KM681000BLP-5 32-DIP,55ns,L-pwr KM681000BLGE-7 32-SOP,70ns,L-pwr KM681000BLGI-7 32-SOP,70ns,L-pwr Function KM681000BLP-5L 32-DIP,55ns,LL-pwr KM681000BLGE-7L 32-SOP,70ns,LL-pwr KM681000BLGI-7L 32-SOP,70ns,LL-pwr KM681000BLP-7 32-DIP,70ns,L-pwr KM681000BLGE-10 32-SOP,100ns,L-pwr KM681000BLGI-10 32-SOP,100ns,L-pwr KM681000BLP-7L 32-DIP,70ns,LL-pwr KM681000BLGE-10L 32-SOP,100ns,LL-pwr KM681000BLGI-10L 32-SOP,100ns,LL-pwr KM681000BLG-5 32-SOP,55ns,L-pwr KM681000BLTE-7 32-TSOP F,70ns,L-pwr KM681000BLTI-7 32-TSOP F,70ns,L-pwr KM681000BLG-5L 32-SOP,55ns,LL-pwr KM681000BLTE-7L 32-TSOP F,70ns,LL-pwr KM681000BLTI-7L 32-TSOP F,70ns,LL-pwr KM681000BLG-7 32-SOP,70ns,L-pwr KM681000BLTE-10 32-TSOP F,100ns,L-pwr KM681000BLTI-10 32-TSOP F,100ns,L-pwr KM681000BLG-7L 32-SOP,70ns,LL-pwr KM681000BLTE-10L 32-TSOP F,100ns,LL-pwr KM681000BLTI-10L 32-TSOP F,100ns,LL-pwr KM681000BLT-5 32-TSOP F,55ns,L-pwr KM681000BLRE-7 32-TSOP R,70ns,L-pwr KM681000BLRI-7 32-TSOP R,70ns,L-pwr KM681000BLT-5L 32-TSOP F,55ns,LL-pwr KM681000BLRE-7L 32-TSOP R,70ns,LL-pwr KM681000BLRI-7L 32-TSOP R,70ns,LL-pwr KM681000BLT-7 32-TSOP F,70ns,L-pwr KM681000BLRE-10 32-TSOP R,100ns,L-pwr KM681000BLRI-10 32-TSOP R,100ns,L-pwr KM681000BLT-7L 32-TSOP F,70ns,LL-pwr KM681000BLRE-10L 32-TSOP R,100ns,LL-pwr KM681000BLRI-10L 32-TSOP R,100ns,LL-pwr KM681000BLR-5 32-TSOP R,55ns,L-pwr KM681000BLR-5L 32-TSOP R,55ns,LL-pwr KM681000BLR-7 32-TSOP R,70ns,L-pwr KM681000BLR-7L 32-TSOP R,70ns,LL-pwr ORDERING INFORMATION KM6 8 X 1000 B X X X - XX X L-Low Low Power, Blank-Low Power or High Power Access Time : 5=55ns, 7=70ns, 10=100ns Operating temperature : Blank=Commerial, I=Industrial, E=Extended, Package Type : P-DIP, G=SOP, T=TSOP Forward, R=TSOP Reverse L-Low Power or Low Low Power, Blank-High Power Die Version : B=3¢¥ rd generation Density : 1000=1Mbit Bank=5V, V=3.0~3.6V, U=2.7~3.3V Organization : 8=x8 SEC Standard SRAM Revision 0.3 April 1996 PRELIMINARY CMOS SRAM KM681000B Family ABSOLUTE MAXIMUM RATINGS* Item Symbol Ratings Unit Remark VIN,VOUT -0.5 to 7.0 V - Voltage on Vcc supply relative to Vss VCC -0.5 to 7.0 V - Power Dissipation PD 1.0 W - TSTG -65 to 150 ¡É - 0 to 70 ¡É KM681000BL/L-L -25 to 85 ¡É KM681000BLE/LE-L -40 to 85 ¡É KM681000BLI/LI-L 260¡É, 10sec (Lead Only) - - Voltage on any pin relative to Vss Storage temperature Operating Temperature TA Soldering temperature and time TSOLDER * Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stres s rating only and functional operation of the device at these or any other conditions above those indicated in the operating section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. RECOMMENDED DC OPERATING CONDITIONS* Item Symbol Min Typ** Max Unit Supply voltage Vcc 4.5 5.0 5.5 V Ground Vss 0 0 0 V Input high voltage VIH 2.2 - Vcc+0.5 V Input low voltage VIL -0.5*** - 0.8 V * 1) Commercial Product : TA=0 to 70¡É, unless otherwise specified 2) Extended Product : TA=-25 to 85¡É, unless otherwise specified 3) Industrial Product : TA=-40 to 85¡É, unless otherwise specified ** TA=25¡É *** VIL(min)=-3.0V for ¡Â 50ns pulse width CAPACITANCE* (f=1MHz, T A=25¡É) Item Symbol Test Condition Min Max Unit Input capacitance CIN Vin=0V - 6 pF Input/Output capacitance CIO Vio=0V - 8 pF * Capacitance is sampled not 100% tested Revision 0.3 April 1996 PRELIMINARY CMOS SRAM KM681000B Family DC AND OPERATING CHARACTERISTICS Item Symbol Test Conditions* Mi Typ** Max Unit Input leakage current ILI VIN=Vss to Vcc -1 - 1 §Ë Output leakage current ILO CS1=VIH or CS2=VIL or WE=VIL, VIO=Vss to Vcc -1 - 1 §Ë Operating power supply current ICC CS1=VIL, CS2=VIH, VIN=VIH or VIL, IIO=0mA - 7 15** mA ICC1 Cycle time=1§Á 100% duty CS1¡Â0.2V, CS2¡ÃVCC-0.2V - - 10*** mA ICC2 IIO=0mA CS1=VIL,CS2=VIH Min cycle, 100% duty - - 70 mA Output low voltage VOL IOL=2.1mA - - 0.4 V Output high voltage VOH IOH=-1.0mA 2.4 - - V Standby Current(TTL) ISB CS1=VIH, CS2=VIL - - 3 mA L (Low Power) LL (Low Low Power) - - 100 20 L (Low Power) LL (Low Low Power) - - 100 50 L (Low Power) LL (Low Low Power) - - 100 50 §Ë §Ë §Ë §Ë §Ë §Ë Average operating current KM681000BL KM681000BL-L Standby Current (CMOS) KM681000BLE KM681000BLE-L ISB1 KM681000BLI KM681000BLI-L CS1¡ÃVcc-0.2V CS2¡ÃVcc-0.2V or CS2¡Â0.2V Other input=0~Vcc * 1) Commercial Product : TA=0 to 70¡É, Vcc=5.0V¡¾10%, unless otherwise specified 2) Extended Product : TA=-25 to 85¡É, Vcc=5.0V¡¾10%, unless otherwise specified 2) Industrial Product : TA=-40 to 85¡É, Vcc=5.0V¡¾10%, unless otherwise specified ** 20mA for Exteneded and Industrial Products *** 15mA for Extended and Industrial Products A.C CHARACTERISTICS TEST CONDITIONS(1.Test Load and Test Input/Output Reference)* Item Value Remark 0.8 to 2.4V - Input rising & falling time 5ns - input and output reference voltage 1.5V - CL=100pF+1TTL - Input pulse level Output load (See right) CL* * Including scope and jig capacitance * See DC Operating conditions Revision 0.3 April 1996 PRELIMINARY CMOS SRAM KM681000B Family TEST CONDITIONS(2. Temperature and Vcc Conditions) Product Family Temperature Power Supply(Vcc) Speed Bin Comments KM681000BL/L-L 0~70¡É 5.0V¡¾10% 55/70ns Commercial KM681000BLE/LE-L -25~85¡É 5.0V¡¾10% 70/100ns Extended KM681000BLI/LI-L -40~85¡É 5.0V¡¾10% 70/100ns Industrial PARAMETER LIST FOR EACH SPEED BIN Speed Bins Parameter List Read 55ns 70ns Units 100ns Min Max Min Max Min Max Read cycle time tRC 55 - 70 - 100 - ns Address access time tAA - 55 - 70 - 100 ns Chip select to output tCO1,tCO2 - 55 - 70 - 100 ns tOE - 25 - 35 - 50 ns tLZ1,tLZ2 10 - 10 - 10 - ns Output enable to low-Z output tOLZ 5 - 5 - 5 - ns Chip disable to high-Z output tHZ1,tHZ2 0 20 0 25 0 30 ns Output disable to high-Z output tOHZ 0 20 0 25 0 30 ns Output hold from address change tOH 10 - 10 - 10 - ns Write cycle time tWC 55 - 70 - 100 - ns Chip select to end of write tCW 45 - 60 - 80 - ns Address set-up time tAS 0 - 0 - 0 - ns Address valid to end of write tAW 45 - 60 - 80 - ns Write pulse width tWP 40 - 50 - 60 - ns Write recovery time tWR 0 - 0 - 0 - ns Write to output high-Z tWHZ 0 20 0 25 0 30 ns Data to write time overlap tDW 25 - 30 - 40 - ns Data hold from write time tDH 0 - 0 - 0 - ns End write to output low-Z tOW 5 - 5 - 5 - ns Output enable to valid output Chip select to low-Z output Write Symbol Revision 0.3 April 1996 PRELIMINARY CMOS SRAM KM681000B Family DATA RETENTION CHARACTERISTICS Item Vcc for data retention Symbol VDR Test Condition* IDR KM681000BLE KM681000BLE-L Vcc=3.0V CS1¡ÃVcc-0.2V KM681000BLI KM681000BLI-L Data retention set-up time Recovery time Typ** Max Unit 2.0 - 5.5 V L-Ver LL-Ver - 1 0.5 50 10 L-Ver LL-Ver - - 50 25 L-Ver LL-Ver - - 50 25 0 - - 5 - - CS1***¡ÃVcc-0.2V KM681000BL KM681000BL-L Data retention current Min tRDR tRDR See data retention waveform §Ë ms * 1) Commercial Product : TA=0 to 70¡É, unless otherwise specified 2) Extended Product : TA=-25 to 85¡É, unless otherwise specified 2) Industrial Product : TA=-40 to 85¡É, unless otherwise specified ** TA=25¡É *** CS1¡ÃVCC-0.2V,CS2¡ÃVCC-0.2V(CS1 controlled) or CS2¡Â0.2V(CS2 controlled) DATA RETENTION TIMING DIAGRAM 1) CS1 Controlled tSDR Data Retention Mode tRDR VCC 4.5V 2.2V VDR CS1¡Ã VCC - 0.2V CS1 GND 2) CS2 controlled Data Retention Mode VCC 4.5V CS2 tSDR tRDR VDR CS2 ¡Â 0.2V 0.4V GND Revision 0.3 April 1996 PRELIMINARY CMOS SRAM KM681000B Family TIMMING DIAGRAMS TIMING WAVEFORM OF READ CYCLE (1) (Address Controlled) (CS1=OE=VIL, CS2= WE= VIH) tRC Address tAA tOH Data Out Data Valid Previous Data Valid TIMING WAVEFORM OF READ CYCLE(WE=VIH) tRC Address tOH tAA tCO1 CS1 CS2 tCO2 tHZ(1,2) tOE OE tOLZ tOHZ Data out High-Z tLZ Data Valid NOTES (READ CYCLE) 1. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage le vels. 2. At any given temperature and voltage condition, tHZ(max.) is less than tLZ(min.) both for a given device and from device to device. Revision 0.3 April 1996 PRELIMINARY CMOS SRAM KM681000B Family TIMING WAVEFORM OF WRITE CYCLE (1) (WE Controlled) tWC Address tWR1(4) tCW(2) CS1 tAW CS2 tCW(2) tWP(1) WE tAS(3) tDW Data in Data Valid tWHZ Data out tDH tOW Data Undefined TIMING WAVEFORM OF WRITE CYCLE (2) (CS1 Controlled) tWC Address tWR1(4) tAS(3) tCW(2) CS1 tAW CS2 tWP(1) WE tDW Data in Data out tDH Data Valid High-Z High-Z Revision 0.3 April 1996 PRELIMINARY CMOS SRAM KM681000B Family TIMING WAVEFORM OF WRITE CYCLE (2) (CS2 Controlled) tWC Address tWR2(4) tAS(3) tCW(2) CS1 tAW CS2 tCW(2) tWP(1) WE tDH tDW Data in Data Valid Data out High-Z High-Z NOTES (WRITE CYCLE) 1. A write occurs during the overlap of low CS1, high CS2 and low WE. A write begins at the latest transition among CS1 going low, CS2 going high and WE going low. A write ends at the earliest transition among CS1 going high, CS2 going low and WE going high, tWP is measured from the beginning or write to the end of write. 2. tCW is measured from the later of CS1 going low or CS2 going high to the end of write. 3. tAS is measured from the address calid to the beginning of write. 4. tWR is measured from the end of write to the address change. tWR1 applied in case a write ends at CS1, or WE going high, tWR2 applied in case a write ends at CS2 going to low. FUNCTIONAL DESCRIPTION CS1 CS2 WE OE Mode I/O Pin Current Mode H X X X Power Down High-Z ISB,ISB1 X L X X Power Down High-Z ISB,ISB1 L H H H Output Disable High-Z ICC L H H L Read Dout ICC L H L X Write Din ICC * X means don't care Revision 0.3 April 1996 PRELIMINARY CMOS SRAM KM681000B Family Units :MillimeterS(Inches) PACKAGE DIMENSIONS 32 DUAL INLINE PACKAGE (600mil) +0.10 -0.05 0.010+0.004 -0.002 0.25 #17 #1 #16 15.24 0.600 #32 13.60 ¡¾ 0.20 0.535 ¡¾ 0.008 5.08 0.200 MAX 4.191 ¡¾ 0.20 1.650 ¡¾ 0.008 ( 0.46 ¡¾ 0.10 0.018 ¡¾ 0.004 1.52 ¡¾ 0.10 0.060 ¡¾ 0.004 1.91 ) 0.075 0~15¡É 3.81 ¡¾ 0.20 0.150 ¡¾ 0.008 42.31 1.666 MAX 2.54 0.100 3.30 ¡¾ 0.30 0.130 ¡¾ 0.012 0.38 MIN 0.015 32 PLASTIC SMALL OUTLINE PACKAGE (525mil) 0~8¡É #17 14.12 ¡¾ 0.30 0.556 ¡¾ 0.012 #1 #16 2.74 ¡¾ 0.20 0.108 ¡¾ 0.008 3.00 0.118 MAX 20.87MAX 0.822 20.47 ¡¾ 0.20 0.806 ¡¾ 0.008 11.43 ¡¾ 0.20 0.450 ¡¾ 0.008 0.20 +0.10 -0.05 0.008+0.004 -0.002 13.34 0.525 #32 0.80 ¡¾ 0.20 0.031 ¡¾ 0.008 0.10 MAX 0.004 MAX ( 0.71 ) 0.028 +0.100 -0.050 0.016 +0.004 -0.002 0.41 1.27 0.050 0.05 0.002 MIN Revision 0.3 April 1996 PRELIMINARY CMOS SRAM KM681000B Family Units :MillimeterS(Inches) PACKAGE DIMENSIONS 32 THIN SMALL OUTLINE PACKAGE TYPE I (0820F) +0.10 -0.05 +0.004 0.008-0.002 0.20 20.00 ¡¾ 0.20 0.787 ¡¾ 0.008 #1 #32 8.40 0.331 MAX 0.50 0.0197 #16 0.25 0.010 TYP 0.25 ) 0.010 8.00 0.315 ( #17 1.00 ¡¾ 0.10 0.039 ¡¾ 0.004 1.20 MAX 0.047 18.40 ¡¾ 0.10 0.724 ¡¾ 0.004 +0.10 -0.05 0.006+0.004 -0.002 0.05 0.002 MIN 0.004 MAX 1.10 MAX 0.15 0~8¡É 0.45 ~0.75 0.018 ~0.030 ( 0.50 ) 0.020 32 THIN SMALL OUTLINE PACKAGE TYPE I (0820R) +0.10 -0.05 0.008+0.004 -0.002 0.20 20.00 ¡¾ 0.20 0.787 ¡¾ 0.008 #16 #17 0.50 0.0197 #1 0.25 ) 0.010 8.00 0.315 8.40 0.331 MAX ( #32 1.00 ¡¾ 0.10 0.039 ¡¾ 0.004 0.05 0.002 MIN 1.20 0.047 MAX 18.40 ¡¾ 0.10 0.724 ¡¾ 0.004 +0.10 -0.05 0.006 +0.004 -0.002 0.15 0~8¡É 0.45 ~0.75 0.018 ~0.030 ( 0.10 MAX 0.004 MAX 0.25 0.010 TYP 0.50 ) 0.020 Revision 0.3 April 1996