KM62V256D, KM62U256D Family CMOS SRAM Document Title 32Kx8 bit Low Power and Low Voltage CMOS Static RAM Revision History Revision No. History Draft Data Remark 0.0 Initial draft April 1, 1997 Preliminary 1.0 Finalize - Add 70ns part in KM62U256D Family - Show ICC read only, and increased value ICC = 2mA →ICC Read = 5mA - Seperate ICC1 read and write ICC1 = 5mA→ICC1 Read = 5mA, ICC1 Write = 10mA - Improved standby current(ISB1) Commercial part : 10µA→5µA Extended and Industrial part : 20µA→5µA - Improved VIL(Min.) : 0.4V→0.6V - Improved power dissipation : 0.7W→1W November 12, 1997 Final The attached datasheets are provided by SAMSUNG Electronics. SAMSUNG Electronics CO, LTD. reserve the right to change the specifications and products. SAMSUNG Electronics will answer to your questions about device. If you have any questions, please contact the SAMSUNG branch offices. 1 Revision 1.0 November 1997 KM62V256D, KM62U256D Family CMOS SRAM 32Kx8 bit Low Power and Low Voltage CMOS Static RAM FEATURES GENERAL DESCRIPTION • Process Technology : TFT • Organization : 32Kx8 • Power Supply Voltage KM62V256D family : 2.7~3.3V KM62U256D family : 3.0~3.6V • Low Data Retention Voltage : 2V(Min) • Three state output and TTL Compatible • Package Type : 28-SOP-450 28-TSOP1-0813.4F/R The KM62V256D and KM62U256D families are fabricated by SAMSUNG′s advanced CMOS process technology. The families support various operating temperature range and have various package types for user flexibility of system design. The families also support low data retention voltage for battery back-up operation with low data retention current. PRODUCT FAMILY Product Family Operating Temperature KM62V256DL-L Commercial(0~70°C) KM62U256DL-L KM62V256DLE-L Extended(-25~85°C) VCC Range Speed (ns) 3.0V ~3.6V 701)/100 2.7V ~ 3.3V 701)/85/100 3.0V ~3.6V 701)/100 KM62U256DLE-L 2.7V ~ 3.3V 70 /85/100 KM62V256DLI-L 3.0V ~3.6V 701)/100 2.7V ~ 3.3V 701)/85/100 Industrial(-40~85°C) KM62U256DLI-L Power Dissipation Standby (ISB1, Max) Operating (Icc2) 5µA 35mA PKG Type 28-SOP2) 28-TSOP1-F/R 1) 1. The parameter is measured with 30pF test load. 2. KM62V256D Family support SOP package without 100ns speed bin. PIN DESCRIPTION A14 1 28 A12 2 27 A7 3 26 A6 4 25 A5 5 24 A4 6 23 A3 7 A2 8 A1 9 20 A0 10 19 I/O1 11 18 I/O2 28-SOP 12 OE A11 A9 A8 VCC A13 WE WE VCC A13 A14 A12 A8 A7 A6 A9 A5 A4 A11 A3 22 OE 21 A10 17 I/O3 13 16 VSS 14 15 FUNCTIONAL BLOCK DIAGRAM 1 28 2 27 3 26 4 25 5 24 6 23 28-TSOP Type1 - Forward 7 8 22 21 9 20 10 19 11 18 12 17 13 16 14 15 14 15 13 16 12 17 11 18 10 19 A10 CS I/O8 I/O7 I/O6 I/O5 I/O4 Clk gen. Precharge circuit. A13 A8 A12 VSS I/O3 I/O2 I/O1 A0 A1 A2 A14 A4 Memory array 256 rows 128×8 columns Row select A5 A6 A7 A3 A4 CS A5 A6 I/O8 A7 A12 I/O7 A14 I/O6 VCC WE I/O5 A13 A8 I/O4 A9 A11 OE 9 20 28-TSOP Type1 - Reverse 8 7 21 22 6 23 5 24 4 25 3 26 2 27 1 28 A2 A1 A0 I/O1 I/O2 I/O3 VSS I/O4 I/O5 I/O6 I/O7 I/O8 CS A10 I/O Circuit Data cont I/O1 I/O8 Column select Data cont A10 A3 A0 A1 A2 A9 A11 CS Pin Name Function Pin Name Function WE CS Chip Select Input OE Output Enable Input I/O1~I/O8 Control logic Data Inputs/Outputs OE WE A0~A14 Vcc Power Write Enable Input Vss Ground Address Inputs NC No connect SAMSUNG ELECTRONICS CO., LTD. reserves the right to change products and specifications without notice. 2 Revision 1.0 November 1997 KM62V256D, KM62U256D Family CMOS SRAM PRODUCT LIST Commercial Temperature Products (0~70°C) Part Name Extended Temperature Products (-25~85°C) Function Part Name Industrial Temperature Products (-40~85°C) Function Part Name Function KM62V256DLG-7L 28-SOP, 70ns, 3.3V KM62V256DLGE-7L 28-SOP, 70ns, 3.3V KM62V256DLGI-7L 28-SOP, 70ns, 3.3V KM62V256DLTG-7L 28-TSOP F, 70ns, 3.3V KM62V256DLTGE-7L 28-TSOP F, 70ns, 3.3V KM62V256DLTGI-7L 28-TSOP F, 70ns, 3.3V KM62V256DLTG-10L 28-TSOP F, 100ns, 3.3V KM62V256DLTGE-10L 28-TSOP F, 100ns, 3.3V KM62V256DLTGI-10L 28-TSOP F, 100ns, 3.3V KM62V256DLRG-7L 28-TSOP R, 70ns, 3.3V KM62V256DLRGE-7L 28-TSOP R, 70ns, 3.3V KM62V256DLRGI-7L 28-TSOP R, 70ns, 3.3V KM62V256DLRG-10L 28-TSOP R, 100ns, 3.3V KM62V256DLRGE-10L 28-TSOP R, 100ns, 3.3V KM62V256DLRGI-10L 28-TSOP R, 100ns, 3.3V KM62U256DLG-7L 28-SOP, 70ns, 3.0V KM62U256DLGE-7L 28-SOP, 70ns, 3.0V KM62U256DLGI-7L 28-SOP, 70ns, 3.0V KM62U256DLG-8L 28-SOP, 85ns, 3.0V KM62U256DLGE-8L 28-SOP, 85ns, 3.0V KM62U256DLGI-8L 28-SOP, 85ns, 3.0V KM62U256DLG-10L 28-SOP, 100ns, 3.0V KM62U256DLGE-10L 28-SOP, 100ns, 3.0V KM62U256DLGI-10L 28-SOP, 100ns, 3.0V KM62U256DLTG-7L 28-TSOP F, 70ns, 3.0V KM62U256DLTGE-7L 28-TSOP F, 70ns, 3.0V KM62U256DLTGI-7L 28-TSOP F, 70ns, 3.0V KM62U256DLTG-8L 28-TSOP F, 85ns, 3.0V KM62U256DLTGE-8L 28-TSOP F, 85ns, 3.0V KM62U256DLTGI-8L 28-TSOP F, 85ns, 3.0V KM62U256DLTG-10L 28-TSOP F, 100ns, 3.0V KM62U256DLTGE-10L 28-TSOP F, 100ns, 3.0V KM62U256DLTGI-10L 28-TSOP F, 100ns, 3.0V KM62U256DLRGE-7L 28-TSOP R, 70ns, 3.0V KM62U256DLRGI-7L 28-TSOP R, 70ns, 3.0V 28-TSOP R, 85ns, 3.0V KM62U256DLRGE-8L 28-TSOP R, 85ns, 3.0V KM62U256DLRGI-8L 28-TSOP R, 85ns, 3.0V KM62U256DLRG-7L 28-TSOP R, 70ns, 3.0V KM62U256DLRG-8L KM62U256DLRG-10L 28-TSOP R, 100ns, 3.0V KM62U256DLRGE-10L 28-TSOP R, 100ns, 3.0V KM62U256DLRGI-10L 28-TSOP R, 100ns, 3.0V FUNCTIONAL DESCRIPTION CS OE WE I/O Mode Power H X X High-Z Deselected Standby L H H High-Z Output Disabled Active L L H Dout Read Active L Din Write Active 1) L 1) X 1) 1. X means don′t care (Must be in high or low states) ABSOLUTE MAXIMUM RATINGS1) Item Symbol Ratings Unit Remark VIN,VOUT -0.5 to VCC+0.5 V - Voltage on Vcc supply relative to Vss VCC -0.5 to 4.6 V - Power Dissipation PD 1.0 W - TSTG -65 to 150 °C - 0 to 70 °C KM62V256DL, KM62U256DL TA -25 to 85 °C KM62V256DLE, KM62U256DLE -40 to 85 °C KM62V256DLI, KM62U256DLI TSOLDER 260°C, 10sec (Lead Only) - - Voltage on any pin relative to Vss Storage temperature Operating Temperature Soldering temperature and time 1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Functional operation should be restricted to recommended operating condition. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 3 Revision 1.0 November 1997 KM62V256D, KM62U256D Family CMOS SRAM RECOMMENDED DC OPERATING CONDITIONS1) Item Symbol Supply voltage Vcc Product Min Typ Max Unit KM62V256D Family 3.0 3.3 3.6 KM62U256D Family 2.7 3.0 3.3 0 0 0 V V Ground Vss ALL Input high voltage VIH KM62V256D, KM62U256D Family 2.2 - Vcc+0.3 V Input low voltage VIL KM62V256D, KM62U256D Family -0.33) - 0.6 V Note: 1. Commercial Product : TA=0 to 70°C, otherwise specified Industrial Product : TA=-40 to 85°C, otherwise specified 2. Overshoot : VCC+3.0V in case of pulse width≤30ns 3. Undershoot : -3.0V in case of pulse width≤30ns 4. Overshoot and undershoot are sampled, not 100% tested CAPACITANCE1) (f=1MHz, TA=25°C) Item Symbol Test Condition Min Max Unit Input capacitance CIN VIN=0V - 8 pF Input/Output capacitance CIO VIO=0V - 10 pF 1. Capacitance is sampled, not 100% tested DC AND OPERATING CHARACTERISTICS Item Symbol Test Conditions Min Typ Max Unit Input leakage current ILI VIN=Vss to Vcc -1 - 1 µA Output leakage current ILO CS=VIH or OE=VIH or WE=VIL, VIO=VSS to Vcc -1 - 1 µA Operating power supply current ICC IIO=0mA, CS=VIL, VIN=VIH or VIL, Read mA Average operating current ICC1 Cycle time=1µs, 100% duty, IIO=0mA CS≤0.2V, VIN≤0.2V, VIN≥Vcc -0.2V Read - 2 5 - 1.5 5 6 10 Write mA ICC2 Cycle time=Min,100% duty, IIO=0mA, CS=VIL, VIN=VIH or VIL - 23 35 mA Output low voltage VOL IOL=2.1mA - - 0.4 V Output high voltage VOH IOH=-1.0mA 2.4 - - V Standby Current(TTL) ISB CS=VIH, Other inputs=VIH or VIL - - 0.3 mA Standby Current (CMOS) ISB1 CS≥Vcc-0.2V, Other inputs=0~Vcc - 0.1 5 µA 4 Revision 1.0 November 1997 KM62V256D, KM62U256D Family CMOS SRAM AC OPERATING CONDITIONS TEST CONDITIONS (Test Load and Test Input/Output Reference) Input pulse level : 0.4 to 2.4V Input rising and falling time : 5ns Input and output reference voltage : 1.5V Output load (See right) :CL=100pF+1TTL CL1)=30pF+1TTL CL1) 1. Including scope and jig capacitance 1. Refer to AC CHARACTERISTICS AC CHARACTERISTICS (KM62V256D Family:Vcc=3.0~3.6V, KM62U256D Family:Vcc=2.7~3.3V Commercial product :TA=0 to 70°C, Extended product :TA=-25 to 85°C, Industrial product :TA=-40 to 85°C) Speed Bins Parameter List Symbol Write Units 100ns Min Max Min Max Min Max tRC 70 - 85 - 100 - ns Address access time tAA - 70 - 85 - 100 ns Chip select to output tCO - 70 - 85 - 100 ns Output enable to valid output tOE - 35 - 40 - 50 ns Chip select to low-Z output tLZ 10 - 10 - 10 - ns Output enable to low-Z output tOLZ 5 - 5 - 5 - ns Chip disable to high-Z output tHZ 0 30 0 30 0 35 ns Output disable to high-Z output tOHZ 0 30 0 30 0 35 ns Read cycle time Read 85ns 701)ns Output hold from address tOH 5 - 10 - 15 - ns Write cycle time tWC 70 - 85 - 100 - ns Chip select to end of write tCW 60 - 70 - 80 - ns Address set-up time tAS 0 - 0 - 0 - ns Address valid to end of write tAW 60 - 70 - 80 - ns Write pulse width tWP 50 - 60 - 70 - ns Write recovery time tWR 0 - 0 - 0 - ns Write to output high-Z tWHZ 0 25 0 25 0 35 ns Data to write time overlap tDW 30 - 35 - 40 - ns Data hold from write time tDH 0 - 0 - 0 - ns End write to output low-Z tOW 5 - 10 - 10 - ns 1. The parameter is measured with 30pF test load DATA RETENTION CHARACTERISTICS Item Symbol Test Condition Vcc for data retention VDR CS≥Vcc-0.2V Data retention current IDR Vcc=3.0V, CS≥Vcc-0.2V Data retention set-up time tSDR Recovery time tRDR See data retention waveform 5 Min Typ Max Unit 2.0 - 3.6 V 5 µA 0 - - 5 - - ms Revision 1.0 November 1997 KM62V256D, KM62U256D Family CMOS SRAM TIMMING DIAGRAMS TIMING WAVEFORM OF READ CYCLE(1) (Address Controlled, CS=OE=VIL, WE=VIH) tRC Address tAA tOH Data Out Data Valid Previous Data Valid TIMING WAVEFORM OF READ CYCLE(2) (WE=VIH) tRC Address tOH tAA tCO CS tHZ tOE OE Data out High-Z tOHZ tOLZ tLZ Data Valid NOTES (READ CYCLE) 1. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels. 2. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to device interconnection. 6 Revision 1.0 November 1997 KM62V256D, KM62U256D Family CMOS SRAM TIMING WAVEFORM OF WRITE CYCLE(1) (WE Controlled) tWC Address tCW(2) tWR(4) CS tAW tWP(1) WE tAS(3) tDW tDH Data Valid Data in tWHZ Data out tOW Data Undefined TIMING WAVEFORM OF WRITE CYCLE(2) (CS Controlled) tWC Address tAS(3) tCW(2) tWR(4) CS tAW tWP(1) WE tDW Data in Data out tDH Data Valid High-Z High-Z NOTES (WRITE CYCLE) 1. A write occurs during the overlap of a low CS and a low WE. A write begins at the latest transition among CS going Low and WE going low : A write end at the earliest transition among CS going high and WE going high, tWP is measured from the begining of write to the end of write. 2. tCW is measured from the CS going low to end of write. 3. tAS is measured from the address valid to the beginning of write. 4. tWR is measured from the end of write to the address change. tWR applied in case a write ends as CS or WE going high. DATA RETENTION WAVE FORM CS controlled VCC tSDR Data Retention Mode tRDR 3.0/2.7V 2.2V VDR CS≥VCC - 0.2V CS GND 7 Revision 1.0 November 1997 KM62V256D, KM62U256D Family CMOS SRAM PACKAGE DIMENSIONS Units :millimeter(inch) 28 PIN PLASTIC SMALL OUTLINE PACKAGE(450mil) 0~8° #15 11.81±0.30 0.465±0.012 #1 8.38±0.20 0.330±0.008 #14 2.59±0.20 0.102±0.008 18.69 MAX 0.736 +0.10 -0.05 0.006 +0.004 -0.002 0.15 11.43 0.450 #28 1.02±0.20 0.040±0.008 3.00 0.118 MAX 18.29±0.20 0.720±0.008 0.10 MAX 0.004 MAX ( 0.89 ) 0.035 0.41±0.10 0.016±0.004 1.27 0.050 0.05 MIN 0.002 8 Revision 1.0 November 1997 KM62V256D, KM62U256D Family CMOS SRAM PACKAGE DIMENSIONS Units :millimeter(inch) +0.10 -0.05 +0.004 0.008-0.002 0.20 0.10 MAX 0.004 MAX 28 PIN THIN SMALL OUTLINE PACKAGE TYPE1 (0813.4F) 13.40±0.20 0.528±0.008 #1 #28 0.55 0.0217 #14 0.25 0.010 TYP 0.425 ) 0.017 8.00 0.315 8.40 0.331 MAX ( #15 11.80±0.10 0.465±0.004 +0.10 -0.05 0.006+0.004 -0.002 0.15 1.00±0.10 0.039±0.004 0.05 0.002 MIN 0~8° 1.20 0.047 MAX 0.45 ~0.75 0.018 ~0.030 0.50 ) 0.020 0.10 MAX 0.004 MAX ( 28 PIN THIN SMALL OUTLINE PACKAGE TYPE1 (0813.4R) +0.10 -0.05 +0.004 0.008-0.002 0.20 13.40±0.20 0.528±0.008 #14 #15 0.55 0.0217 #1 0.25 0.010 TYP 0.425 ) 0.017 8.00 0.315 8.40 0.331 MAX ( #28 11.80±0.10 0.465±0.004 +0.10 -0.05 0.006+0.004 -0.002 0.15 1.00±0.10 0.039±0.004 0.05 0.002 MIN 1.20 0.047 MAX 0~8° 0.45 ~0.75 0.018 ~0.030 ( 9 0.50 ) 0.020 Revision 1.0 November 1997