PRELIMINARY CMOS SRAM KM68257C/CL Document Title 32Kx8 Bit High Speed Static RAM(5V Operating), Evolutionary Pin out. Operated at Commercial Temperature Range. Revision History Rev No. History Draft Data Remark Rev. 0.0 Initial release with Preliminary. Apr. 1st, 1994 Preliminary Rev. 1.0 Release to final Data Sheet. 1. Delete Preliminary May 14th,1994 Final Rev. 2.0 Update A.C parameters 2.1. Updated A.C parameters Previous spec. Updated spec. Items (12/15/20ns part) (12/15/20ns part) tOE - / 8/10ns - / 7 /9 ns tCW - /12/ - ns - /11/ - ns tHZ 8/10/10ns 6/7/8ns tOHZ - / 8 / - ns - / 7 / - ns tDW - / 9 / - ns - / 8 / - ns 2.2. Add Voh1=3.95V with the test condition as Vcc=5V±5% at 25°C Oct. 4th, 1994 Final Rev. 3.0 3.1. Add 28-TSOP1 Package. 3.2. Add L-version. 3.3. Add Data Rentention Characteristics. Feb. 22th, 1996 Final The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any questions, please contact the SAMSUNG branch office near your office, call or contact Headquarters. -1- Rev 3.0 February-1996 PRELIMINARY CMOS SRAM KM68257C/CL 32K x 8 Bit High-Speed CMOS Static RAM GENERAL DESCRIPTION FEATURES ¡Ü ¡Ü ¡Ü ¡Ü ¡Ü ¡Ü ¡Ü ¡Ü ¡Ü Fast Access Time 12, 15, 20§À(Max.) Low Power Dissipation Standby (TTL) : 40§Ì(Max.) (CMOS) : 2§Ì(Max.) 0.1§Ì(Max.)- L-ver. only Operating KM68257C/CL - 12 : 165§Ì(Max.) KM68257C/CL - 15 : 150§Ì(Max.) KM68257C/CL - 20 : 140§Ì(Max.) Single 5.0V±10% Power Supply TTL Compatible Inputs and Outputs I/O Compatible with 3.3V Device Fully Static Operation - No Clock or Refresh required Three State Outputs Low Data Retention Voltage : 2V(Min.)- L-ver. only Standard Pin Configuration KM68257C/CLP : 28-DIP-300 KM68257C/CLJ : 28-SOJ-300 KM68257C/CLTG : 28-TSOP1-0813, 4F The KM68257C is a 262,144-bit high-speed Static Random Access Memory organized as 32,768 words by 8 bits. The KM68257C uses 8 common input and output lines and has an output enable pin which operates faster than address access time at read cycle. The device is fabricated using SAMSUNG's advanced CMOS process and designed for high-speed circuit technology. It is particularly well suited for use in high-density high-speed system applications. The KM68257C is packaged in a 300 mil 28-pin plastic DIP, SOJ or TSOP1 forward. PIN CONFIGURATION(Top View) OE A11 A9 A8 A13 WE Vcc A14 A12 A7 A6 A5 A4 A3 FUNCTIONAL BLOCK DIAGRAM Clk Gen. I/O1 ~ I/O8 Row Select A3 A4 A5 A6 A7 A8 A12 A13 A14 Pre-Charge-Circuit Memory Array 512 Rows 64x8 Columns 1 2 3 4 5 6 7 8 9 10 11 12 13 14 TSOP1 A14 1 28 Vcc A12 2 27 WE A7 3 26 A13 A6 4 25 A8 A5 5 24 A9 A4 6 23 A11 A3 7 Data Cont. I/O Circuit Column Select CLK Gen. A0 A1 A2 A9 A10 CS I/O8 I/O7 I/O6 I/O5 I/O4 Vss I/O3 I/O2 I/O1 A0 A1 A2 28 27 26 25 24 23 22 21 20 19 18 17 16 15 SOJ/DIP 22 OE A2 8 21 A10 A1 9 20 CS A0 10 19 I/O8 I/O1 11 18 I/O7 I/O2 12 17 I/O6 I/O3 13 16 I/O5 Vss 14 15 I/O4 A10 A11 PIN FUNCTION Pin Name CS A0 - A14 WE OE WE Write Enable CS Chip Select OE I/O1 ~ I/O8 -2- Pin Function Address Inputs Output Enable Data Inputs/Outputs VCC Power(+5.0V) VSS Ground Rev 3.0 February-1996 PRELIMINARY CMOS SRAM KM68257C/CL ABSOLUTE MAXIMUM RATINGS* Parameter Symbol Rating Unit VIN, VOUT -0.5 to 7.0 V Voltage on VCC Supply Relative to VSS VCC -0.5 to 7.0 V Power Dissipation PD 1.0 W TSTG -65 to 150 °C TA 0 to 70 °C Voltage on Any Pin Relative to VSS Storage Temperature Operating Temperature * Stresses greater than those listed under "Absolute Maximum Rating" may cause permanent damage to the device. This is a stress ra ting only and functional operation of the device at these at these or any other conditions above those indicated in the operating sections of thi s specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. RECOMMENDED DC OPERATING CONDITIONS(TA=0 to 70°C) Symbol Min Typ Max Unit Supply Voltage Parameter VCC 4.5 5.0 5.5 V Ground VSS 0 0 0 V Input Low Voltage VIH 2.2 - VCC+0.5** V Input Low Voltage VIL -0.5* - 0.8 V * VIL(Min) = -2.0(Pulse Width ≤10ns) for I≤20§Ì ** VIH(Max) = V CC+2.0V(Pulse Width ≤10ns) for I≤20§Ì DC AND OPERATING CHARACTERISTICS(TA=0 to 70°C,VCC=5.0V±10% unless otherwise specified) Parameter Symbol Test Conditions Min Max Unit Input Leakage Current ILI VIN = VSS to VCC -2 2 µA Output Leakage Current ILO CS=VIH or OE=VIH or WE=VIL VOUT = VSS to VCC -2 2 µA 12ns - 165 ICC Min. Cycle, 100% Duty CS=VIL, VIN = VIH or VIL, IOUT=0mA 15ns - 150 20ns - 140 Operating Current ISB Standby Current Output Low Voltage Level Output High Voltage Level - 40 Normal - 2 L-ver - 0.1 Min. Cycle, CS=VIH §Ì §Ì ISB1 f=0MHz, CS≥VCC-0.2V, VIN≥VCC-0.2V or VIN≤0.2V VOL IOL=8mA - 0.4 V VOH IOH=-4mA 2.4 - V - 3.95 V VOH1* IOH1=0.1mA §Ì * VCC=5.0V±5% Temp.=25°C CAPACITANCE*(TA =25°C, f=1.0MHz) Symbol Test Conditions MIN Max Unit Input/Output Capacitance Item CI/O VI/O=0V - 8 pF Input Capacitance CIN VIN=0V - 7 pF * NOTE : Capacitance is sampled and not 100% tested. -3- Rev 3.0 February-1996 PRELIMINARY CMOS SRAM KM68257C/CL AC CHARACTERISTICS(TA=0 to 70°C, VCC=5.0V±10%, unless otherwise noted.) TEST CONDITIONS Parameter Value Input Pulse Levels 0V to 3V Input Rise and Fall Times 3§À Input and Output timing Reference Levels 1.5V Output Loads See below Output Loads(A) Output Loads(B) for tHZ, tLZ, tWHZ, tOW, tOLZ & tOHZ +5V +5.0V 480Ω 480Ω DOUT 255Ω DOUT 255Ω 30pF* 5pF* * Including Scope and Jig Capacitance READ CYCLE Parameter Symbol KM68257C/CL-12 KM68257C/CL-15 KM68257C/CL-20 Min Max Min Max Min Max Unit Read Cycle Time tRC 12 - 15 - 20 - §À Address Access Time tAA - 12 - 15 - 20 §À Chip Select to Output tCO - 12 - 15 - 20 §À Output Enable to Valid Output tOE - 6 - 7 - 9 §À Chip Enable to Low-Z Output Access tLZ 3 - 3 - 3 - §À Output Enable to Low-Z Output tOLZ 0 - 0 - 0 - §À Chip Disable to High-Z Output tHZ 0 6 0 7 0 10 §À Output Disable to High-Z Output tOHZ 0 6 0 7 0 10 §À Output Hold from Address Change tOH 3 - 3 - 3 - §À Chip Selection to Power Up Time tPU 0 - 0 - 0 - §À Chip Selection to Power DownTime tPD - 12 - 15 - 20 §À -4- Rev 3.0 February-1996 PRELIMINARY CMOS SRAM KM68257C/CL WRITE CYCLE Parameter Symbol KM68257C/CL-12 KM68257C/CL-15 KM68257C/CL-20 Min Max Min Max Min Max Unit Write Cycle Time tWC 12 - 15 - 20 - §À Chip Select to End of Write tCW 9 - 11 - 13 - §À Address Setup Time tAS 0 - 0 - 0 - §À Address Valid to End of Write tAW 9 - 12 - 13 - §À Write Pulse Width(OE High) tWP 9 - 12 - 13 - §À Write Pulse Width(OE Low) tWP1 12 - 15 - 20 - §À Write Recovery Time tWR 0 - 0 - 0 - §À Write to Output High-Z tWHZ 0 6 0 8 0 8 §À Data to Write Time Overlap tDW 7 - 8 - 10 - §À Data Hold from Write Time tDH 0 - 0 - 0 - §À End Write to Output Low-Z tOW 0 - 0 - 0 - §À TIMING DIAGRAMS TIMING WAVE FORM OF READ CYCLE(1)(Address Controlled, CS=OE=VIL, WE=VIH) tRC ADD tAA tOH Data Out Previous Data Valid Data Valid -5- Rev 3.0 February-1996 PRELIMINARY CMOS SRAM KM68257C/CL TIMING WAVE FORM OF READ CYCLE(2)(WE=VIH) tRC ADD tAA tCO tHZ(3,4,5) CS tOHZ tOE OE tOLZ tOH tLZ(4,5) Data Valid Data Out Vcc Icc Current ISB tPU tPD 50% 50% NOTES(READ CYCLE) 1. WE is high for read cycle. 2. All read cycle timing is referenced from the last valid address to the first transition address. 3. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit condition and are not referenced to V OH or VOL Levels. 4. At any given temperature and voltage condition, t HZ(Max.) is less than t LZ (Min.) both for a given device and from device to device. 5. Transition is measured ±200§Æ from steady state voltage with Load(B). This parameter is sampled and not 100% tested. 6. Device is continuously selected with CS=VIL. 7. Address valid prior to coincident with CS transition low. 8. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycl e. TIMING WAVE FORM OF WRITE CYCLE(1)(OE=Clock) tWC ADD tAW tWR(5) OE tCW(3) CS tAS(4) tWP(2) WE tDW Data In High-Z tDH Data Valid tOHZ(6) High-Z(8) Data Out -6- Rev 3.0 February-1996 PRELIMINARY CMOS SRAM KM68257C/CL TIMING WAVE FORM OF WRITE CYCLE(2)(OE=Low Fixed) tWC ADD tWR(5) tAW tCW(3) CS tWP1(2) tAS(4) tOH WE tDW Data In High-Z tDH Data Valid tWHZ(6) tOW (10) (9) High-Z(8) Data Out TIMING WAVE FORM OF WRITE CYCLE(3)(CS=Controlled) tWC ADD tWR(5) tAW tCW(3) CS tAS(4) tWP(2) WE tDW Data In High-Z Data Valid tLZ Data Out tDH High-Z tWHZ(6) High-Z High-Z(8) -7- Rev 3.0 February-1996 PRELIMINARY CMOS SRAM KM68257C/CL NOTES(WRITE CYCLE) 1. All write cycle timing is referenced from the last valid address to the first transition address. 2. A write occurs during the overlap of a low CS and WE. A write begins at the latest transition CS going low and WE going low ; A write ends at the earliest transition CS going high or WE going high. t WP is measured from the beginning of write to the end of write. 3. tCW is measured from the later of CS going low to end of write. 4. tAS is measured from the address valid to the beginning of write. 5. tWR is measured from the end of write to the address change. t WR applied in case a write ends as CS or WE going high. 6. If OE, CS and WE are in the Read Mode during this period, the I/O pins are in the output low-Z state. Inputs of opposite phase of the output mus t not be applied because bus contention can occur. 7. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycl e. 8. If CS goes low simultaneously with WE going or after WE going low, the outputs remain high impedance state. 9. Dout is the read data of the new address. 10. When CS is low : I/O pins are in the output state. The input signals in the opposite phase leading to the output should not be applied. FUNCTIONAL DESCRIPTION CS WE OE Mode I/O Pin Supply Current H X X* Not Select High-Z ISB, ISB1 L H H Output Disable High-Z ICC L H L Read DOUT ICC L L X Write DIN ICC * NOTE : X means Don't Care. DATA RETENTION CHARACTERISTICS*(TA = 0 to 70°C) Parameter Symbol Test Condition VCC for Data Retention VDR CS≥VCC - 0.2V Data Retention Current IDR VCC = 3.0V, CS≥VCC - 0.2V VIN≥VCC - 0.2V or VIN≤0.2V Data Retention Set-Up Time tSDR Recovery Time tRDR See Data Retention Wave form(below) Min. Typ. Max. Unit 2.0 - 5.5 V - - 0.07 §Ì 0 - - ns 5 - - ms * L-Ver only. DATA RETENTION WAVE FORM(CS Controlled) VCC tSDR Data Retention Mode tRDR 4.5V 2.2V VDR CS≥VCC - 0.2V CS GND -8- Rev 3.0 February-1996 PRELIMINARY CMOS SRAM KM68257C/CL PACKAGE DIMENSIONS 28-DIP-300 Units : Inches (millimeters) +0.10 -0.05 +0.004 0.010 -0.002 0.25 #15 #1 #14 7.62 0.300 #28 7.01±0.20 0.276±0.008 0~15¡É 3.81±0.20 0.150±0.008 34.69 1.366MAX 5.08 0.200MAX 34.29±0.20 1.350±0.008 ( 0.65 ) 0.025 +0.30 -0.25 0.125+0.012 -0.010 3.18 0.46±0.10 0.018±0.004 1.27±0.10 0.050±0.004 2.54 0.100 0.51 MIN 0.020 28-SOJ-300 #15 7.62 0.300 #28 8.51±0.12 0.335±0.005 6.86±0.25 0.270±0.010 0.20 +0.10 -0.05 0.008+0.004 -0.002 #1 #14 0.69 MIN 0.027 18.82 MAX 0.741 18.41±0.12 0.725±0.005 ( 1.30 ) 0.051 3.76 MAX 0.148 0.10 0.004MAX 0.43 ( 0.95 ) 0.0375 +0.10 -0.05 0.017+0.004 -0.002 +0.10 -0.05 +0.004 0.028 -0.002 0.71 1.27 0.050 -9- ( 1.30 ) 0.051 Rev 3.0 February-1996 PRELIMINARY CMOS SRAM KM68257C/CL PACKAGE DIMENSIONS 28-TSOP1-0813.4F 1.10 MAX 0.004 MAX Units : Inches (millimeters) +0.10 -0.05 0.008+0.004 -0.002 0.20 13.40±0.20 0.528±0.008 #1 #28 0.55 0.0217 #14 0.25 0.010 TYP 0.425 ) 0.017 8.00 0.315 8.40 0.331 MAX ( #15 11.80±0.10 0.465±0.004 +0.10 -0.05 0.006+0.004 -0.002 0.15 1.00±0.10 0.039±0.004 0.05 0.002 MIN 1.20 0.047 MAX 0~8¡É 0.45 ~0.75 0.018 ~0.030 ( - 10 0.50 ) 0.020 Rev 3.0 February-1996