KM68512A Family CMOS SRAM Document Title 64Kx8 bit Low Power CMOS Static RAM Revision History History Draft Data Remark 0.0 Initial draft Novemer 28, 1993 Design target 0.1 Revision May 13, 1994 Preliminary 1.0 Finalize December 1, 1994 Final 2.0 Revision - Add 45ns part with 30pf test load. August 12, 1995 Final 3.0 Revision - Change Data Sheet format : One data sheets for industrial and commercial product April 15, 1996 Final 4.0 Revision - Change Data Sheet format - Remove 45ns part from commercial product and 100ns part from industrial product - Remove low power part form TSOP package January 9, 1998 Final Revision No. The attached data, sheets are provided by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications and products. SAMSUNG Electronics will answer to your questions about device. If you have any questions, please contact the SAMSUNG branch offices. 1 Revision 4.0 January 1997 KM68512A Family CMOS SRAM 64Kx8 bit Low Power CMOS Static RAM FEATURES GENERAL DESCRIPTION • Process Technology: Poly Load • Organization: 64Kx8 • Power Supply Voltage: 4.5~5.5V • Low Data Retention Voltage: 2V(Min) • Three state output and TTL Compatible • Package Type: 32-SOP-525, 32-TSOP1-0820F The KM68512A families are fabricated by SAMSUNG′s advanced CMOS process technology. The families support various operating temperature ranges and have various package types for user flexibility of system design. The families also support low data retention voltage for battery back-up operation with low data retention current. PRODUCT FAMILY Power Dissipation Product Family KM68512AL Operating Temperature VCC Range Commercial (0~70°C) KM68512AL-L Speed Standby (ISB1, Max) 100µA 55/70ns 20µA 4.5 to 5.5V KM68512ALI Industrial (-40~85°C) 32-SOP 32-TSOP1-F 70mA 100µA 70ns KM68512ALI-L 50µA PIN DESCRIPTION N.C 1 32 VCC N.C 2 31 A15 A14 3 30 CS2 A12 4 29 WE A7 5 28 A13 A6 6 27 A8 A5 7 26 A9 A4 8 25 A11 A3 9 24 OE A2 10 23 A10 A1 11 22 CS1 A0 12 21 I/O8 I/O1 13 20 I/O7 I/O2 14 19 I/O6 I/O3 15 18 I/O5 VSS 16 17 I/O4 32-SOP PKG Type Operating (ICC2, Max) FUNCTIONAL BLOCK DIAGRAM Clk gen. A11 A9 A8 A13 WE CS2 A15 VCC NC NC A14 A12 A7 A6 A5 A4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32-TSOP Type1 - Forward 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 Precharge circuit. A3 OE A10 CS1 I/O8 I/O7 I/O6 I/O5 I/O4 VSS I/O3 I/O2 I/O1 A0 A1 A2 A3 A4 A5 A6 A7 Memory array 512 rows 128×8 columns Row select A12 A13 A14 A15 Data cont I/O1 I/O8 I/O Circuit Column select Data cont Name CS1, CS 2 Function OE Output Enable Input WE Write Enable Input A0~A15 I/O1~I/O8 A0 Chip Select Inputs A1 A2 A8 A9 A10 A11 CS1 CS2 WE Address Inputs Control Logic OE Data Inputs/Outputs Vcc Power Vss Ground N.C No Connection SAMSUNG ELECTRONICS CO., LTD. reserves the right to change products and specifications without notice. 2 Revision 4.0 January 1997 KM68512A Family CMOS SRAM PRODUCT LIST Commercial Temperature Products(0~70°C) Industrial Temperature Products(-40~85°C) Part Name Function KM68512ALG-5 32-SOP, 55ns, L-pwr KM68512ALGI-7 Part Name 32-SOP, 70ns, L-pwr Function KM68512ALG-5L 32-SOP, 55ns, LL-pwr KM68512ALGI-7L 32-SOP, 70ns, LL-pwr KM68512ALG-7 32-SOP, 70ns, L-pwr KM68512ALG-7L 32-SOP, 70ns, LL-pwr KM68512ALTI-7L 32-TSOP1-F, 70ns, LL-pwr KM68512ALT-5L 32-TSOP1-F, 55ns, LL-pwr KM68512ALT-7L 32-TSOP1-F, 70ns, LL-pwr FUNCTIONAL DESCRIPTION CS1 CS2 OE WE I/O Pin Mode Power H X1) X1) X1) High-Z Deselected Standby X1) L X1) X1) High-Z Deselected Standby L H H H High-Z Output Disabled Active L H L H Dout Read Active L H X1) L Din Write Active 1. X means don′t care.(Must be low or high state) ABSOLUTE MAXIMUM RATINGS1) Item Voltage on any pin relative to Vss Voltage on Vcc supply relative to Vss Power Dissipation Storage temperature Operating Temperature Soldering temperature and time Symbol Ratings Unit Remark VIN,VOUT -0.5 to 7.0 V - VCC -0.5 to 7.0 V - PD 1.0 W - TSTG -65 to 150 °C - 0 to 70 °C KM68512A -40 to 85 °C KM68512AI 260°C, 10sec(Lead Only) - - TA TSOLDER 1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Functional operation should be restricted to recommended operating condition. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 3 Revision 4.0 January 1997 KM68512A Family CMOS SRAM RECOMMENDED DC OPERATING CONDITIONS1) Item Symbol Min Typ Max Unit Supply voltage Vcc 4.5 5.0 5.5 V Ground Vss 0 0 0 Input high voltage VIH 2.2 - Input low voltage VIL -0.53) - V Vcc+0.5V V 2) 0.8 V Note 1. Commercial Product : TA=0 to 70°C, unless otherwise specified Industrial Product : TA=-40 to 85°C, unless otherwise specified 2. Overshoot : V CC+3.0V in case of pulse width≤30ns 3. Undershoot : -3.0V in case of pulse width≤30ns 4. Overshoot and undershoot are sampled, not 100% tested CAPACITANCE1)(f=1MHz, TA=25°C) Item Symbol Test Condition Min Max Unit Input capacitance CIN VIN=0V - 6 pF Input/Output capacitance CIO VIO=0V - 8 pF 1. Capacitance is sampled, not 100% tested DC AND OPERATING CHARACTERISTICS Item Input leakage current Symbol Test Conditions Min Typ Max Unit VIN=Vss to Vcc -1 Output leakage current ILO CS 1=VIH or CS 2=VIL or OE=VIH or WE=VIL, VIO=Vss to Vcc -1 - 1 µA Operating power supply current ICC IIO=0mA, CS1=VIL, CS2=VIH, VIN=VIH or VIL - 7 15 mA ICC1 Cycle time=1µs, 100% duty, IIO=0mA CS 1≤0.2V, CS2≥VCC-0.2V, VIN≤0.2V or VIN≥Vcc -0.2V - - 10 mA ICC2 Cycle time=Min, 100% duty, IIO=0mA, CS1=VIL, CS 2=VIH, VIN=VIH or VIL - - 70 mA Output low voltage VOL IOL=2.1mA - - 0.4 V Output high voltage VOH IOH=-1.0mA 2.4 - - V Standby Current(TTL) ISB CS 1=VIH, CS2=VIL, Other inputs =VIH or VIL - - 3 mA - 2 1 100 20 µA ISB1 Low Power CS 1≥Vcc-0.2V, CS2≥Vcc-0.2V or CS2≤0.2V Low Low Power Other inputs =0 ~ Vcc Low Power Low Low Power - 2 1 100 50 µA Average operating current Standby Current (CMOS) KM68512AL/L-L KM68512ALI/LI-L 4 - 1 µA ILI Revision 4.0 January 1997 KM68512A Family CMOS SRAM AC OPERATING CONDITIONS TEST CONDITIONS( Test Load and Input/Output Reference) Input pulse level : 0.8 to 2.4V Input rising and falling time : 5ns Input and output reference voltage :1.5V Output load(see right) : CL=100pF+1TTL CL1) 1. Including scope and jig capacitance AC CHARACTERISTICS (Vcc=4.5~5.5V, KM68512A Family:TA=0 to 70°C, KM68512AI Family:TA=-40 to 85°C) Speed Bins Parameter List Symbol Write Units 70ns Max Min Max tRC 55 - 70 - ns Address access time tAA - 55 - 70 ns Chip select to output tCO1, tCO2 - 55 - 70 ns Read cycle time Read 55ns Min Output enable to valid output tOE - 25 - 35 ns Chip select to low-Z output tLZ 10 - 10 - ns Output enable to low-Z output tOLZ 5 - 5 - ns Chip disable to high-Z output tHZ 0 20 0 25 ns Output disable to high-Z output tOHZ 0 20 0 25 ns Output hold from address change tOH 10 - 10 - ns Write cycle time tWC 55 - 70 - ns Chip select to end of write tCW 45 - 60 - ns Address set-up time tAS 0 - 0 - ns Address valid to end of write tAW 45 - 60 - ns Write pulse width tWP 40 - 50 - ns Write recovery time tWR 0 - 0 - ns Write to output high-Z tWHZ 0 20 0 25 ns Data to write time overlap tDW 25 - 30 - ns Data hold from write time tDH 0 - 0 - ns End write to output low-Z tOW 5 - 5 - ns Typ Max Unit V DATA RETENTION CHARACTERISTICS Item Vcc for data retention Symbol CS ≥Vcc-0.2V VDR KM68512AL/L-L Data retention current IDR KM68512ALI/LI-L Data retention set-up time tSDR Recovery time tRDR Min Test Condition 2.0 - 5.5 L-Ver LL-Ver - 1 0.5 50 10 L-Ver LL-Ver - - 50 25 0 - - 5 - - 11) Vcc=3.0V CS1≥Vcc-0.2V CS2≥Vcc-0.2V or CS2≤0.2V See data retention waveform µA ms 1. CS1≥Vcc-0.2V, CS2 ≥Vcc-0.2V( CS1 controlled) or CS2≤0.2V(CS2 controlled). 5 Revision 4.0 January 1997 KM68512A Family CMOS SRAM TIMMING DIAGRAMS TIMING WAVEFORM OF READ CYCLE(1) (Address Controlled, CS1=OE=VIL, WE=VIH) tRC Address tAA tOH Data Out Data Valid Previous Data Valid TIMING WAVEFORM OF READ CYCLE(2) (WE=VIH) tRC Address tOH tAA tCO1 CS 1 tHZ(1,2) CS 2 tCO2 tOE OE Data out High-Z tOHZ tOLZ tLZ Data Valid NOTES (READ CYCLE) 1. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels. 2. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to device interconnection. 6 Revision 4.0 January 1997 KM68512A Family CMOS SRAM TIMING WAVEFORM OF WRITE CYCLE(1) (WE Controlled) tWC Address tCW(2) tWR(4) CS1 tAW CS2 tCW(2) tWP(1) WE tAS(3) tDW tDH Data Valid Data in tWHZ Data out tOW Data Undefined TIMING WAVEFORM OF WRITE CYCLE(2) (CS1 Controlled) tWC Address tAS(3) tCW(2) tWR(4) CS1 tAW CS2 tWP(1) WE tDW Data in Data out tDH Data Valid High-Z High-Z 7 Revision 4.0 January 1997 KM68512A Family CMOS SRAM TIMING WAVEFORM OF WRITE CYCLE(3) (CS2 Controlled) tWC Address tAS(3) tCW(2) tWR(4) CS 1 tAW CS 2 tCW(2) tWP(1) WE tDW Data Valid Data in Data out tDH High-Z High-Z NOTES (WRITE CYCLE) 1. A write occurs during the overlap of a low CS1, a high CS 2 and a low WE. A write begins at the latest transition among CS1 goes low, CS2 going high and WE going low : A write end at the earliest transition among CS1 going high, CS2 going low and WE going high, tWP is measured from the begining of write to the end of write. 2. t CW is measured from the CS1 going low or CS2 going high to the end of write. 3. t AS is measured from the address valid to the beginning of write. 4. tWR is measured from the end of write to the address change. tWR(1) applied in case a write ends as CS1 or WE going high tWR(2) applied in case a write ends as CS2 going to low. DATA RETENTION WAVE FORM CS1 controlled VCC tSDR Data Retention Mode tRDR 4.5V 2.2V VDR CS1≥VCC - 0.2V CS1 GND CS2 controlled Data Retention Mode VCC 4.5V CS2 tSDR tRDR VDR 0.4V CS2≤0.2V GND 8 Revision 4.0 January 1997 KM68512A Family CMOS SRAM PACKAGE DIMENSIONS Units: millimeter(Inch) 32 PIN SMALL OUTLINE PACKAGE (525mil) 0~8° #17 14.12±0.30 0.556±0.012 #1 13.34 0.525 #32 11.43±0.20 0.450±0.008 #16 2.74±0.20 0.108±0.008 3.00 0.118 MAX 20.87 MAX 0.822 20.47±0.20 0.806±0.008 0.80±0.20 0.031±0.008 0.20 +0.10 -0.05 0.008+0.004 -0.002 0.10 MAX 0.004 MAX +0.100 -0.050 +0.004 0.016 -0.002 0.41 ( 0.71 ) 0.028 1.27 0.050 0.05 MIN 0.002 32-THIN SMALL OUTLINE PACKAGE TYPE I (0820F) +0.10 -0.05 0.008+0.004 -0.002 0.20 20.00±0.20 0.787±0.008 #1 #32 MAX 8.40 0.331 0.50 0.0197 #16 0.25 0.010 TYP #17 18.40±0.10 0.724±0.004 0.25 ) 0.010 8.00 0.315 ( 1.00±0.10 0.039±0.004 1.20 0.047 MAX +0.10 -0.05 0.006+0.004 -0.002 0.05 0.002 MIN 0~8° 0.45 ~0.75 0.018 ~0.030 ( 9 0.10 MAX 0.004 MAX 0.15 0.50 ) 0.020 Revision 4.0 January 1997