KM718V887 256Kx18 Synchronous SRAM Document Title 256Kx18-Bit Synchronous Burst SRAM Revision History History Draft Date Remark 0.0 Initial draft May. 15. 1997 Preliminary 0.1 Modify power down cycle timing & Interleaved read timing, Insert Note 4 at AC timing characteristics. Change ISB1 value from 10mA to 30mA. Change ISB2 value from 10mA to 20mA. February. 11. 1998 Preliminary 0.2 Change Undershoot spec from -3.0V(pulse width≤20ns) to -2.0V(pulse width≤tCYC/2) Add Overshoot spec 4.6V((pulse width≤tCYC/2) Change VIH max from 5.5V to VDD+0.5V April. 14. 1998 Preliminary 0.3 May 13. 1998 Change ISB2 value from 20mA to 30mA. Change VDD condition from VDD=3.3V+10%/-5% to VDD=3.3V+0.3V/-0.165V. 1.0 Final spec Release May 15. 1998 Final 2.0 Add VDDQ Supply voltage( 2.5V ) Dec. 02. 1998 Final Rev. No. Preliminary The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any questions, please contact the SAMSUNG branch office near your office, call or contact Headquarters. -1- December 1998 Rev. 2.0 KM718V887 256Kx18 Synchronous SRAM 256Kx18-Bit Synchronous Burst SRAM FEATURES GENERAL DESCRIPTION • Synchronous Operation. • On-Chip Address Counter. • Write Self-Timed Cycle. • On-Chip Address and Control Registers. • VDD= 3.3V+0.3V/-0.165V Power Supply. • VDDQ Supply Voltage 3.3V+0.3V/-0.165V for 3.3V I/O The KM718V887 is a 4,718,592 bit Synchronous Static Random Access Memory designed for support zero wait state performance for advanced Pentium/Power PC address pipelining. And with CS1 high, ADSP is blocked to control signal. It is organized as 256K words of 18 bits and integrates address and control registers, a 2-bit burst address counter and high output drive circuitry onto a single integrated circuit for reduced components count implementation of high performance cache RAM applications. Write cycles are internally self-timed and synchronous. The self-timed write feature eliminates complex off chip write pulse shaping logic, simplifying the cache design and further reducing the component count. Burst cycle can be initiated with either the address status processor(ADSP) or address status cache controller(ADSC) inputs. Subsequent burst addresses are generated internally in the system′s burst sequence and are controlled by the burst address advance(ADV) input. ZZ pin controls Power Down State and reduces Stand-by current regardless of CLK. The KM718V887 is implemented in SAMSUNG′s high performance CMOS technology and is available in a 100pin TQFP package. Multiple power and ground pins are utilized to minimize ground bounce. or 2.5V+0.4V/-0.125V for 2.5V I/O. • 5V Tolerant Inputs except I/O Pins. • Byte Writable Function. • Global Write Enable Controls a full bus-width write. • Power Down State via ZZ Signal. • Asynchronous Output Enable Control. • ADSP, ADSC, ADV Burst Control Pins. • LBO Pin allows a choice of either a interleaved burst or a linear burst. • Three Chip Enables for simple depth expansion with No Data Contention. • TTL-Level Three-State Output. • 100-TQFP-1420A FAST ACCESS TIMES PARAMETER Cycle Time Symbol -7 -8 -9 Unit tCYC 8.5 10 12 ns Clock Access Time tCD 7.5 8 9 ns Output Enable Access Time tOE 3.5 3.5 3.5 ns LOGIC BLOCK DIAGRAM CLK LBO BURST CONTROL 256Kx18 MEMORY ARRAY A′0~A′1 A0 ~ A1 A0~A17 ADSP ADDRESS REGISTER A2~A17 DATA-IN REGISTER CONTROL REGISTER CS1 CS2 CS2 GW BW WEa BURST ADDRESS COUNTER LOGIC CONTROL REGISTER ADV ADSC OUTPUT BUFFER CONTROL LOGIC WEb OE ZZ DQa0 ~ DQb7 DQPa, DQPb -2- December 1998 Rev. 2.0 KM718V887 256Kx18 Synchronous SRAM A6 A7 CS1 CS2 N.C. N.C. WEb WEa CS2 VDD VSS CLK GW BW OE ADSC ADSP ADV A8 A9 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 100 Pin TQFP 47 48 49 50 A14 A15 A16 A17 41 VDD 46 40 VSS A13 39 N.C. 45 38 N.C. A12 37 A0 44 36 A1 A11 35 A2 43 34 A3 N.C. 33 A4 42 32 N.C. 31 (20mm x 14mm) A5 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 LBO N.C. N.C. N.C. VDDQ VSSQ N.C. N.C. DQb0 DQb1 VSSQ VDDQ DQb2 DQb3 N.C. VDD N.C. VSS DQb4 DQb5 VDDQ VSSQ DQb6 DQb7 DQPb N.C. VSSQ VDDQ N.C. N.C. N.C. 100 PIN CONFIGURATION(TOP VIEW) 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 A10 N.C. N.C. VDDQ VSSQ N.C. DQPa DQa7 DQa6 VSSQ VDDQ DQa5 DQa4 VSS N.C. VDD ZZ DQa3 DQa2 VDDQ VSSQ DQa1 DQa0 N.C. N.C. VSSQ VDDQ N.C. N.C. N.C. PIN NAME SYMBOL PIN NAME A0 - A17 Address Inputs ADV ADSP ADSC CLK CS1 CS2 CS2 WEx OE GW BW ZZ LBO Burst Address Advance Address Status Processor Address Status Controller Clock Chip Select Chip Select Chip Select Byte Write Inputs Output Enable Global Write Enable Byte Write Enable Power Down Input Burst Mode Control TQFP PIN NO. 32,33,34,35,36,37, 44,45,46,47,48,49, 50,80,81,82,99,100 83 84 85 89 98 97 92 93,94 86 88 87 64 31 SYMBOL PIN NAME VDD VSS N.C. Power Supply(+3.3V) Ground No Connect DQa0~a7 DQb0~b7 DQPa, Pb VDDQ Data Inputs/Outputs VSSQ -3- Output Power Supply (2.5V or 3.3V) Output Ground TQFP PIN NO. 15,41,65,91 17,40,67,90 1,2,3,6,7,14,16,25,28, 29,30,38,39,42,43,51 52,53,56,57,66,75 78,79,95,96 58,59,62,63,68,69,72,73 8,9,12,13,18,19,22,23 74,24 4,11,20,27,54,61,70,77 5,10,21,26,55,60,71,76 December 1998 Rev. 2.0 KM718V887 256Kx18 Synchronous SRAM FUNCTION DESCRIPTION The KM718V887 is a synchronous SRAM designed to support the burst address accessing sequence of the Pentium and Power PC based microprocessor. All inputs(with the exception of OE, LBO and ZZ) are sampled on rising clock edges. The start and duration of the burst access is controlled by ADSP, ADSC, ADV and Chip Select pins. When ZZ is pulled HIGH, the SRAM will enter a Power Down State. At this time, internal state of the SRAM is preserved. When ZZ returns to low, the SRAM normally operates after 2cycles of wake up time. ZZ pin is pulled down internally. Read cycles are initiated with ADSP(or ADSC) using the new external address clocked into the on-chip address register when both GW and BW are high or when BW is low and both WEa and WEb are high, When ADSP is sampled low, the chip selects are sampled active, and the output buffer is enabled with OE, the data of cell array accessed by the current address are projected to the output pins. Write cycles are also initiated with ADSP(or ADSC)and are differentiated into two kinds of operations; All byte write operation and individual byte write operation. All byte write occurs by enabling GW(in dependent of BW and WEx.), and individual byte write is performed only when GW is High and BW is Low. WEa controls DQa0 ~ DQa7 and DQPa, WEb controls DQb0 ~ DQb7 and DQPb. CS1 is used to enable the device and conditions internal use of ADSP and is sampled only when a new external address is loaded. ADV is ignored at the clock edge when ADSP is asserted, but can be sampled on the subsequent clock edges. The address increases internally for the next access of the burst when ADV is sampled low. Addresses are generated for the burst access as shown below, The starting point of the burst sequence is provided by the external address. The burst address counter wraps around to its initial state upon completion. The burst sequence is determined by the state of the LBO pin. When this pin is low, linear burst sequence is selected. And when this pin is High, Interleaved burst sequence is selected. BURST SEQUENCE TABLE LBO PIN (Interleaved Burst) Case 1 HIGH A1 0 0 1 1 First Address Fourth Address Case 2 A0 0 1 0 1 A1 0 0 1 1 Case 3 A0 1 0 1 0 A1 1 1 0 0 Case 4 A0 0 1 0 1 A1 1 1 0 0 SEQUENCE TABLE LBO PIN A0 1 0 1 0 (Linear Burst) Case 1 LOW A1 0 0 1 1 First Address Fourth Address Case 2 A0 0 1 0 1 A1 0 1 1 0 Case 3 A0 1 0 1 0 A1 1 1 0 0 Case 4 A0 0 1 0 1 A1 1 0 0 1 A0 1 0 1 0 Note : 1. LBO pin must be tied to High or Low, and Floating State must not be allowed. TRUTH TABLES ASYNCHRONOUS TRUTH TABLE (See Notes 1 and 2): OPERATION ZZ OE I/O STATUS Sleep Mode H X High-Z L L DQ Read L H High-Z Write L X Din, High-Z Deselected L X High-Z Notes 1. X means "Don′t Care". 2. ZZ pin is pulled down internally 3. For write cycles that following read cycles, the output buffers must be disabled with OE, otherwise data bus contention will occur. 4. Sleep Mode means power down state of which stand-by current does not depend on cycle time. 5. Deselected means power down state of which stand-by current depends on cycle time. -4- December 1998 Rev. 2.0 KM718V887 256Kx18 Synchronous SRAM SYNCHRONOUS TRUTH TABLE CS1 CS2 CS2 H X X ADSP ADSC X ADV WRITE CLK ADDRESS ACCESSED OPERATION X X ↑ None Not Selected None Not Selected L L L X L X X X ↑ L X H L X X X ↑ None Not Selected L L X X L X X ↑ None Not Selected L X H X L X X ↑ None Not Selected L H L L X X X ↑ External Address Begin Burst Read Cycle L H L H L X L ↑ External Address Begin Burst Write Cycle L H L H L X H ↑ External Address Begin Burst Read Cycle X X X H H L H ↑ Next Address Continue Burst Read Cycle H X X X H L H ↑ Next Address Continue Burst Read Cycle X X X H H L L ↑ Next Address Continue Burst Write Cycle H X X X H L L ↑ Next Address Continue Burst Write Cycle X X X H H H H ↑ Current Address Suspend Burst Read Cycle H X X X H H H ↑ Current Address Suspend Burst Read Cycle X X X H H H L ↑ Current Address Suspend Burst Write Cycle H X X X H H L ↑ Current Address Suspend Burst Write Cycle Notes : 1. X means "Don′t Care". 2. The rising edge of clock is symbolized by ↑. 3. WRITE = L means Write operation in WRITE TRUTH TABLE. WRITE = H means Read operation in WRITE TRUTH TABLE. 4. Operation finally depends on status of asynchronous input pins(ZZ and OE). WRITE TRUTH TABLE GW BW WEa WEb OPERATION H H X X READ H L H H READ H L L H WRITE BYTE a H L H L WRITE BYTE b H L L L WRITE ALL BYTEs L X X X WRITE ALL BYTEs Notes : 1. X means "Don′t Care". 2. All inputs in this table must meet setup and hold time around the rising edge of CLK(↑). -5- December 1998 Rev. 2.0 KM718V887 256Kx18 Synchronous SRAM ABSOLUTE MAXIMUM RATINGS* PARAMETER SYMBOL RATING UNIT Voltage on VDD Supply Relative to VSS VDD -0.3 to 4.6 V Voltage on VDDQ Supply Relative to VSS VDDQ VDD V Voltage on Input Pin Relative to VSS VIN -0.3 to 6.0 V Voltage on I/O Pin Relative to VSS VIO -0.3 to VDDQ+0.5 V Power Dissipation PD 1.2 W Storage Temperature TSTG -65 to 150 °C Operating Temperature TOPR 0 to 70 °C Storage Temperature Range Under Bias TBIAS -10 to 85 °C *Note : Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. OPERATING CONDITIONS at 3.3V I/O (0°C≤ TA≤70°C) PARAMETER Supply Voltage Ground SYMBOL MIN Typ. MAX UNIT VDD 3.135 3.3 3.6 V VDDQ 3.135 3.3 3.6 V VSS 0 0 0 V Typ. MAX OPERATING CONDITIONS at 2.5V I/O(0°C ≤ TA ≤ 70°C) PARAMETER Supply Voltage Ground SYMBOL MIN UNIT VDD 3.135 3.3 3.6 V VDDQ 2.375 2.5 2.9 V VSS 0 0 0 V TEST CONDI- MIN MAX UNIT CIN VIN=0V - 5 pF COUT VOUT=0V - 8 pF CAPACITANCE*(TA=25°C, f=1MHz) PARAMETER Input Capacitance Output Capacitance SYMBOL *Note : Sampled not 100% tested. -6- December 1998 Rev. 2.0 KM718V887 256Kx18 Synchronous SRAM DC ELECTRICAL CHARACTERISTICS(TA=0 to 70°C, VDD=3.3V+0.3V/-0.165V) PARAMETER SYMBOL TEST CONDITIONS MIN MAX UNIT Input Leakage Current(except ZZ) IIL VDD=Max ; VIN=VSS to VDD -2 2 µA Output Leakage Current IOL Output Disabled, VOUT=VSS to VDDQ -2 2 µA Operating Current ICC Device Selected, IOUT=0mA, ZZ≤VIL, All Inputs=VIL or VIH Cycle Time ≥ tCYC Min ISB Device deselected, IOUT=0mA, ZZ≤VIL, f=Max, All Inputs≤0.2V or ≥ VDD-0.2V -7 - 350 -8 - 325 -9 - 300 -7 - 100 -8 - 90 -9 - 80 ISB1 Device deselected, IOUT=0mA, ZZ≤0.2V, f=0, All Inputs=fixed (VDD-0.2V or 0.2V) ISB2 Device deselected, IOUT=0mA, ZZ≥VDD-0.2V, f=Max, All Inputs≤VIL or ≥VIH Output Low Voltage(3.3V I/O) VOL IOL = 8.0mA Output High Voltage(3.3V I/O) VOH IOH = -4.0mA Output Low Voltage(2.5V I/O) VOL IOL = 1.0mA Output High Voltage(2.5V I/O) VOH IOH = -1.0mA Standby Current - mA mA 30 mA 30 mA - 0.4 V 2.4 - V - 0.4 V 2.0 - V - Input Low Voltage(3.3V I/O) VIL -0.5* 0.8 V Input High Voltage(3.3V I/O) VIH 2.0 VDD+0.5** V Input Low Voltage(2.5V I/O) VIL -0.3* 0.7 V Input High Voltage(2.5V I/O) VIH 1.7 VDD+0.5** V * VIL(Min)=-2.0(Pulse Width ≤ tCYC/2) ** VIH(Max)=4.6(Pulse Width ≤ tCYC/2) ** In Case of I/O Pins, the Max. VIH=VDDQ+0.5V TEST CONDITIONS (VDD=3.3V+0.3V/-0.165V,VDDQ=3.3V+0.3/-0.165V or VDD=3.3V+0.3V/-0.165V,VDDQ=2.5V+0.4V/-0.125V, TA=0 to 70°C) PARAMETER VALUE Input Pulse Level(for 3.3V I/O) 0 to 3V Input Pulse Level(for 2.5V I/O) 0 to 2.5V Input Rise and Fall Time(Measured at 0.3V and 2.7V for 3.3V I/O) 2ns Input Rise and Fall Time(Measured at 0.3V and 2.1V for 2.5V I/O) 2ns Input and Output Timing Reference Levels for 3.3V I/O 1.5V Input and Output Timing Reference Levels for 2.5V I/O VDDQ/2 Output Load See Fig. 1 -7- December 1998 Rev. 2.0 KM718V887 256Kx18 Synchronous SRAM Output Load(A) Dout Output Load(B) (for tLZC, tLZOE, tHZOE & tHZC) +3.3V for 3.3V I/O /+2.5V for 2.5V I/O RL=50Ω Z0=50Ω VL=1.5V for 3.3V I/O VDDQ/2 for 2.5V I/O 30pF* 319Ω / 1667Ω Dout 353Ω / 1538Ω 5pF* * Including Scope and Jig Capacitance * Capacitive Load consists of all components of the test environment. Fig. 1 AC TIMING CHARACTERISTICS(TA=0 to 70°C, VDD=3.3V+0.3V/-0.165V) PARAMETER SYMBOL KM718V887-7 KM718V887-8 KM718V887-9 MIN MAX MIN MAX MIN MAX UNIT Cycle Time tCYC 8.5 - 10 - 12 - ns Clock Access Time tCD - 7.5 - 8 - 9 ns Output Enable to Data Valid tOE - 3.5 - 3.5 - 3.5 ns Clock High to Output Low-Z tLZC 0 - 0 - 0 - ns Output Hold from Clock High tOH 2 - 2 - 2 - ns Output Enable Low to Output Low-Z tLZOE 0 - 0 - 0 - ns Output Enable High to Output High-Z tHZOE - 3.5 - 3.5 - 3.5 ns Clock High to Output High-Z tHZC 2 3.5 2 3.5 2 3.5 ns Clock High Pulse Width tCH 3 - 4 - 4.5 - ns Clock Low Pulse Width tCL 3 - 4 - 4.5 - ns Address Setup to Clock High tAS 2.0 - 2.0 - 2.0 - ns Address Status Setup to Clock High tSS 2.0 - 2.0 - 2.0 - ns Data Setup to Clock High tDS 2.0 - 2.0 - 2.0 - ns Write Setup to Clock High(GW, BW, WEx) tWS 2.0 - 2.0 - 2.0 - ns Address Advance Setup to Clock High tADVS 2.0 - 2.0 - 2.0 - ns Chip Select Setup to Clock High tCSS 2.0 - 2.0 - 2.0 - ns Address Hold from Clock High tAH 0.5 - 0.5 - 0.5 - ns Address Status Hold from Clock High tSH 0.5 - 0.5 - 0.5 - ns Data Hold from Clock High tDH 0.5 - 0.5 - 0.5 - ns Write Hold from Clock High(GW, BW, WEx) tWH 0.5 - 0.5 - 0.5 - ns Address Advance Hold from Clock High tADVH 0.5 - 0.5 - 0.5 - ns Chip Select Hold from Clock High tCSH 0.5 - 0.5 - 0.5 - ns ZZ High to Power Down tPDS 2 - 2 - 2 - cycle ZZ Low to Power Up tPUS 2 - 2 - 2 - cycle Notes : 1. All address inputs must meet the specified setup and hold times for all rising clock edges whenever ADSC and/or ADSP is sampled low and CS is sampled low. All other synchronous inputs must meet the specified setup and hold times whenever this device is chip selected. 2. Both chip selects must be active whenever ADSC or ADSP is sampled low in order for the this device to remain enabled. 3. ADSC or ADSP must not be asserted for at least 2 Clock after leaving ZZ state. 4. At any given voltage and temperature, tHZC is less than tLZC. -8- December 1998 Rev. 2.0 -9- Data Out OE ADV CS WRITE ADDRESS ADSC ADSP CLOCK tCSS tAS tSS tOE Q1-1 tHZOE tADVH tWH tSS A2 tSH Q2-1 tCD tOH Q2-2 Q2-3 A3 Q2-4 (ADV INSERTS WAIT STATE) BURST CONTINUED WITH NEW BASE ADDRESS tCYC tCL NOTES : WRITE = L means GW = L, or GW = H, BW = L, WEx.= L CS = L means CS1 = L, CS2 = H and CS2 = L CS = H means CS1 = H, or CS1 = L and CS2 = H, or CS1 = L, and CS2 = L tADVS tCSH tWS tLZOE A1 tAH tSH tCH TIMING WAVEFORM OF READ CYCLE Q3-1 Q3-2 Q3-3 Undefined Don′t Care Q3-4 tHZC KM718V887 256Kx18 Synchronous SRAM December 1998 Rev. 2.0 - 10 Data Out Data In OE ADV CS WRITE ADDRESS ADSC ADSP CLOCK Q0-3 tCSS tAS tSS Q0-4 A1 tLZOE tCSH tAH tSH D1-1 tCH tCYC tCL A2 D2-1 D2-2 (ADV SUSPENDS BURST) D2-2 D2-3 (ADSC EXTENDED BURST) TIMING WAVEFORM OF WRTE CYCLE D2-4 D3-1 A3 tDS tADVS tWS tSS D3-2 tDH tADVH tWH tSH D3-3 Undefined Don′t Care D3-4 KM718V887 256Kx18 Synchronous SRAM December 1998 Rev. 2.0 - 11 Data Out Data In OE ADV CS WRITE ADDRESS ADSP CLOCK tHZC tSS A1 tLZC tCD tSH Q1-1 tHZOE tAS A2 tCL tCYC tDS tADVS tWS tAH tCH D2-1 tDH tADVH tWH A3 tLZOE tOE Q3-1 Q3-2 Q3-3 tOH Q3-4 TIMING WAVEFORM OF COMBINATION READ/WRTE CYCLE(ADSP CONTROLLED, ADSC=HIGH) Undefined Don′t Care KM718V887 256Kx18 Synchronous SRAM December 1998 Rev. 2.0 - 12 Data In Data Out OE ADV CS WRITE ADDRESS ADSC CLOCK tCSS tSS A1 tLZOE tOE tCSH tSH Q1-1 A2 Q2-1 A3 Q3-1 A4 Q4-1 tHZOE D5-1 A5 tDS tWS D6-1 A6 tDH tWH D7-1 A7 tWS tCD A8 A9 Q8-1 tCL tCYC tWH tCH TIMING WAVEFORM OF SINGLE READ/WRITE CYCLE(ADSC CONTROLLED, ADSP=HIGH) December 1998 Rev. 2.0 Undefined Don′t Care Q9-1 tOH KM718V887 256Kx18 Synchronous SRAM - 13 Data In Data Out OE ADV CS WRITE ADDRESS ADSP CLOCK tCSS tSS tOE tCSH tLZOE A1 tSH Q1-1 A2 Q2-1 A3 tAS Q3-1 A4 tAH tCYC tCH A5 Q4-1 tCL tHZOE D5-1 A6 tDS D6-1 tDH A7 D7-1 tCD A8 Q8-1 A9 TIMING WAVEFORM OF SINGLE READ/WRITE CYCLE(ADSP CONTROLLED, ADSC=HIGH) Q9-1 tOH Undefined Don′t Care KM718V887 256Kx18 Synchronous SRAM December 1998 Rev. 2.0 - 14 ZZ Data Out Data In OE ADV CS WRITE ADDRESS ADSC ADSP CLOCK tCSS tAS tSS A1 tLZOE tOE tCSH tAH tSH Q1-1 ZZ Setup Cycle tPDS tHZC Sleep State ZZ Recovery Cycle tPUS tCL tCYC tCH TIMING WAVEFORM OF POWER DOWN CYCLE tWS Normal Operation Mode tHZOE A2 D2-1 tWH Undefined Don′t Care D2-2 KM718V887 256Kx18 Synchronous SRAM December 1998 Rev. 2.0 KM718V887 256Kx18 Synchronous SRAM APPLICATION INFORMATION DEPTH EXPANSION The Samsung 256Kx18 Synchronous Burst SRAM has two additional chip selects for simple depth expansion. This permits easy secondary cache upgrades from 256K depth to 512K depth without extra logic. I/O[0:71] Data Address A[0:18] A[18] A[18] A[0:17] Address CLK Microprocessor CS2 CS2 CS2 ADSC CLK Address Data CS2 CLK Address CLK 256Kx18 SB SRAM ADSC OE (Bank 0) OE 256Kx18 SB SRAM (Bank 1) CS1 CS1 ADV Data WEx WEx Cache Controller A[0:17] ADV ADSP ADSP ADS INTERLEAVE READ TIMING (Refer to non-interleave write timing for interleave write timing) (ADSP CONTROLLED , ADSC=HIGH) CLOCK tSS tSH ADSP tAS ADDRESS [0:n] A1 tAH A2 tWS tWH WRITE tCSS tCSH CS1 Bank 0 is selected by CS2, and Bank 1 deselected by CS2 An+1 tADVS Bank 0 is deselected by CS2, and Bank 1 selected by CS2 tADVH ADV OE tOE Data Out (Bank 0) Data Out (Bank 1) tLZOE tHZC Q1-1 Q1-2 Q1-3 Q1-4 tCD tLZC Q2-1 Q2-2 *Notes : n = 14 32K depth, 15 64K depth, 16 128K depth, 17 256K depth - 15 Q2-3 Q2-4 Don′t Care Undefined December 1998 Rev. 2.0 KM718V887 256Kx18 Synchronous SRAM PACKAGE DIMENSIONS 100-TQFP-1420A Units:millimeters/inches 0~8° 22.00 ±0.30 0.127 +- 0.10 0.05 20.00 ±0.20 16.00 ±0.30 14.00 ±0.20 0.10 MAX (0.83) 0.50 ±0.10 #1 0.65 (0.58) 0.30 ±0.10 0.10 MAX 1.40 ±0.10 1.60 MAX 0.50 ±0.10 - 16 0.05 MIN December 1998 Rev. 2.0