KM732V789 128Kx32 Synchronous SRAM Document Title 128Kx32-Bit Synchronous Pipelined Burst SRAM Revision History Rev. No. History Draft Date Remark 1.0 Initial draft May . 19. 1998 Final 2.0 change tCYC from 8.5ns to 10.0ns. Modify Rev No. from 0.0 to 1.0. June . 02. 1998 Final 3.0 Modify DC characteristics( Input Leakage Current test Conditions) form VDD=VSS to VDD to Max. June. 08. 1998 Final 4.0 Add VDDQ Supply voltage( 2.5V ) Dec. 02. 1998 Final 5.0 Remove 119BGA(7x17 Ball Grid Array Package) . Feb. 10. 1999 Final The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any questions, please contact the SAMSUNG branch office near your office, call or contact Headquarters. -1- February 1999 Rev 5.0 KM732V789 128Kx32 Synchronous SRAM 128Kx32-Bit Synchronous Pipelined Burst SRAM FEATURES GENERAL DESCRIPTION • Synchronous Operation. • 2 Stage Pipelined operation with 4 Burst. • On-Chip Address Counter. • Self-Timed Write Cycle. • On-Chip Address and Control Registers. • VDD= 3.3V+0.3V/-0.165V Power Supply. • VDDQ Supply Voltage 3.3V+0.3V/-0.165V for 3.3V I/O The KM732V789 is a 4,194,304-bit Synchronous Static Random Access Memory designed for high performance second level cache of Pentium and Power PC based System. It is organized as 128K words of 32bits and integrates address and control registers, a 2-bit burst address counter and added some new functions for high performance cache RAM applications; GW, BW, LBO, ZZ. Write cycles are internally self-timed and synchronous. Full bus-width write is done by GW, and each byte write is performed by the combination of WEx and BW when GW is high. And with CS1 high, ADSP is blocked to control signals. Burst cycle can be initiated with either the address status processor(ADSP) or address status cache controller(ADSC) inputs. Subsequent burst addresses are generated internally in the system′s burst sequence and are controlled by the burst address advance(ADV) input. LBO pin is DC operated and determines burst sequence(linear or interleaved). ZZ pin controls Power Down State and reduces Stand-by current regardless of CLK. The KM732V789 is fabricated using SAMSUNG′s high performance CMOS technology and is available in a 100pin TQFP package. Multiple power and ground pins are utilized to minimize ground bounce. or 2.5V+0.4V/-0.125V for 2.5V I/O. • 5V Tolerant Inputs Except I/O Pins. • Byte Writable Function. • Global Write Enable Controls a full bus-width write. • Power Down State via ZZ Signal. • LBO Pin allows a choice of either a interleaved burst or a linear burst. • Three Chip Enables for simple depth expansion with No Data Contention ; 2cycle Enable, 1cycle Disable. • Asynchronous Output Enable Control. • ADSP, ADSC, ADV Burst Control Pins. • TTL-Level Three-State Output. • 100-TQFP-1420A FAST ACCESS TIMES PARAMETER Symbol 60 67 72 10 Unit Cycle Time tCYC 6.0 6.7 7.2 10 ns Clock Access Time tCD 3.5 3.8 4.0 4.5 ns Output Enable Access Time tOE 3.5 3.8 4.0 4.5 ns LOGIC BLOCK DIAGRAM CLK LBO BURST CONTROL LOGIC CONTROL REGISTER ADV ADSC 128Kx32 MEMORY ARRAY A′0~A′1 A0~A1 A0~A16 ADSP ADDRESS REGISTER A2~A16 DATA-IN REGISTER CONTROL REGISTER CS1 CS2 CS2 GW BW WEa WEb WEc WEd OE ZZ BURST ADDRESS COUNTER OUTPUT REGISTER CONTROL LOGIC BUFFER DQa0 ~ DQd7 -2- February 1999 Rev 5.0 KM732V789 128Kx32 Synchronous SRAM A6 A7 CS1 CS2 WEd WEc WEb WEa CS2 VDD VSS CLK GW BW OE ADSC ADSP ADV A8 A9 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 100 Pin TQFP 46 A12 50 45 A11 A16 44 A10 49 43 N.C. A15 42 N.C. 48 41 VDD A14 40 VSS 47 39 N.C. A13 38 N.C. 35 A2 37 34 A3 A0 33 A4 36 32 A1 31 (20mm x 14mm) A5 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 LBO N.C. DQc0 DQc1 VDDQ VSSQ DQc2 DQc3 DQc4 DQc5 VSSQ VDDQ DQc6 DQc7 N.C. VDD N.C. VSS DQd0 DQd1 VDDQ VSSQ DQd2 DQd3 DQd4 DQd5 VSSQ VDDQ DQd6 DQd7 N.C. 100 PIN CONFIGURATION(TOP VIEW) 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 N.C. DQb7 DQb6 VDDQ VSSQ DQb5 DQb4 DQb3 DQb2 VSSQ VDDQ DQb1 DQb0 VSS N.C. VDD ZZ DQa7 DQa6 VDDQ VSSQ DQa5 DQa4 DQa3 DQa2 VSSQ VDDQ DQa1 DQa0 N.C. PIN NAME SYMBOL A0 - A16 PIN NAME Address Inputs TQFP PIN NO. SYMBOL 32,33,34,35,36,37, 44,45,46,47,48,49, 50,81,82,99,100 ADV Burst Address Advance 83 ADSP Address Status Processor 84 ADSC Address Status Controller 85 CLK Clock 89 CS1 Chip Select 98 CS2 Chip Select 97 CS2 Chip Select 92 WEx(x=a,b,c,d) Byte Write Inputs 93,94,95,96 OE Output Enable 86 GW Global Write Enable 88 BW Byte Write Enable 87 ZZ Power Down Input 64 LBO Burst Mode Control 31 PIN NAME VDD VSS N.C. Power Supply(+3.3V) Ground No Connect DQa0~a7 DQb0~b7 DQc0~c7 DQd0~d7 Data Inputs/Outputs VDDQ Output Power Supply (2.5V or 3.3V) Output Ground VSSQ -3- TQFP PIN NO. 15,41,65,91 17,40,67,90 1,14,16,30,38,39,42,43 51,66,80 52,53,56,57,58,59,62,63 68,69,72,73,74,75,78,79 2,3,6,7,8,9,12,13 18,19,22,23,24,25,28,29 4,11,20,27,54,61,70,77 5,10,21,26,55,60,71,76 February 1999 Rev 5.0 KM732V789 128Kx32 Synchronous SRAM FUNCTION DESCRIPTION The KM732V789 is a synchronous SRAM designed to support the burst address accessing sequence of the P6 and Power PC based microprocessor. All inputs (with the exception of OE, LBO and ZZ) are sampled on rising clock edges. The start and duration of the burst access is controlled by ADSC, ADSP and ADV and chip select pins. The accesses are enabled with the chip select signals and output enabled signals. Wait states are inserted into the access with ADV. When ZZ is pulled high, the SRAM will enter a Power Down State. At this time, internal state of the SRAM is preserved. When ZZ returns to low, the SRAM normally operates after 2cycles of wake up time. ZZ pin is pulled down internally. Read cycles are initiated with ADSP(regardless of WEx and ADSC)using the new external address clocked into the on-chip address register whenever ADSP is sampled low, the chip selects are sampled active, and the output buffer is enabled with OE. In read operation the data of cell array accessed by the current address, registered in the Data-out registers by the positive edge of CLK, are carried to the Data-out buffer by the next positive edge of CLK. The data, registered in the Data-out buffer, are projected to the output pins. ADV is ignored on the clock edge that samples ADSP asserted, but is sampled on the subsequent clock edges. The address increases internally for the next access of the burst when WEx are sampled High and ADV is sampled low. And ADSP is blocked to control signals by disabling CS1. All byte write is done by GW(regaedless of BW and WEx.), and each byte write is performed by the combination of BW and WEx when GW is high. Write cycles are performed by disabling the output buffers with OE and asserting WEx. WEx are ignored on the clock edge that samples ADSP low, but are sampled on the subsequent clock edges. The output buffers are disabled when WEx are sampled Low(regaedless of OE). Data is clocked into the data input register when WEx sampled Low. The address increases internally to the next address of burst, if both WEx and ADV are sampled Low. Individual byte write cycles are performed by any one or more byte write enable signals(WEa, WEb, WEc or WEd) sampled low. The WEa control DQa0 ~ DQa7 , WEb controls DQb0 ~ DQb7 , WEc controls DQc0 ~ DQc7 , and WEd control DQd0 ~ DQd7 . Read or write cycle may also be initiated with ADSC, instead of ADSP. The differences between cycles initiated with ADSC and ADSP as are follows; ADSP must be sampled high when ADSC is sampled low to initiate a cycle with ADSC. WEx are sampled on the same clock edge that sampled ADSC low(and ADSP high). Addresses are generated for the burst access as shown below, The starting point of the burst sequence is provided by the external address. The burst address counter wraps around to its initial state upon completion. The burst sequence is determined by the state of the LBO pin. When this pin is Low, linear burst sequence is selected. When this pin is High, Interleaved burst sequence is selected. BURST SEQUENCE TABLE LBO PIN HIGH First Address Fourth Address (Interleaved Burst) Case 1 A1 0 0 1 1 Case 2 A0 0 1 0 1 A1 0 0 1 1 Case 3 A0 1 0 1 0 A1 1 1 0 0 Case 4 A0 0 1 0 1 A1 1 1 0 0 A0 1 0 1 0 BQ TABLE LBO PIN (Linear Burst) LOW First Address Fourth Address Case 1 A1 0 0 1 1 Case 2 A0 0 1 0 1 A1 0 1 1 0 Case 3 A0 1 0 1 0 A1 1 1 0 0 Case 4 A0 0 1 0 1 A1 1 0 0 1 A0 1 0 1 0 Note : 1. LBO pin must be tied to High or Low, and Floating State must not be allowed. -4- February 1999 Rev 5.0 KM732V789 128Kx32 Synchronous SRAM TRUTH TABLES SYNCHRONOUS TRUTH TABLE CS1 CS2 CS2 ADV WRITE CLK ADDRESS ACCESSED OPERATION H X X ADSP ADSC X L X X ↑ N/A Not Selected L L X L X X X ↑ N/A Not Selected L X H L X X X ↑ N/A Not Selected L L X X L X X ↑ N/A Not Selected L X H X L X X ↑ N/A Not Selected L H L L X X X ↑ External Address Begin Burst Read Cycle L H L H L X L ↑ External Address Begin Burst Write Cycle L H L H L X H ↑ External Address Begin Burst Read Cycle X X X H H L H ↑ Next Address Continue Burst Read Cycle H X X X H L H ↑ Next Address Continue Burst Read Cycle X X X H H L L ↑ Next Address Continue Burst Write Cycle H X X X H L L ↑ Next Address Continue Burst Write Cycle X X X H H H H ↑ Current Address Suspend Burst Read Cycle H X X X H H H ↑ Current Address Suspend Burst Read Cycle X X X H H H L ↑ Current Address Suspend Burst Write Cycle H X X X H H L ↑ Current Address Suspend Burst Write Cycle 2. The rising edge of clock is symbolized by ↑. Notes : 1. X means "Don′t Care". 3. WRITE = L means Write operation in WRITE TRUTH TABLE. WRITE = H means Read operation in WRITE TRUTH TABLE. 4. Operation finally depends on status of asynchronous input pins(ZZ and OE). WRITE TRUTH TABLE GW BW WEa WEb H H X X H L H H H L L H H L H L H L H H L L L X X WEc WEd OPERATION X X READ H H READ H H WRITE BYTE a H H WRITE BYTE b H L L WRITE BYTE c and d L L L WRITE ALL BYTEs X X X WRITE ALL BYTEs Notes : 1. X means "Don′t Care". 2. All inputs in this table must meet setup and hold time around the rising edge of CLK(↑). ASYNCHRONOUS TRUTH TABLE (See Notes 1 and 2): OPERATION ZZ OE I/O STATUS Sleep Mode H X High-Z L L DQ L H High-Z Write L X Din, High-Z Deselected L X High-Z Read Notes 1. X means "Don′t Care". 2. ZZ pin is pulled down internally 3. For write cycles that following read cycles, the output buffers must be disabled with OE, otherwise data bus contention will occur. 4. Sleep Mode means power down state of which stand-by current does not depend on cycle time. 5. Deselected means power down state of which stand-by current depends on cycle time. -5- February 1999 Rev 5.0 KM732V789 128Kx32 Synchronous SRAM PASS-THROUGH TRUTH TABLE PREVIOUS CYCLE OPERATION PRESENT CYCLE WRITE OPERATION NEXT CYCLE CS1 WRITE OE Write Cycle, All bytes Address=An-1, Data=Dn-1 All L Initiate Read Cycle Address=An Data=Qn-1 for all bytes L H L Read Cycle Data=Qn Write Cycle, All bytes Address=An-1, Data=Dn-1 All L No new cycle Data=Qn-1 for all bytes H H L No carryover from previous cycle Write Cycle, All bytes Address=An-1, Data=Dn-1 All L No new cycle Data=High-Z H H H No carryover from previous cycle Write Cycle, One byte Address=An-1, Data=Dn-1 One L Initiate Read Cycle Address=An Data=Qn-1 for one byte L H L Read Cycle Data=Qn Write Cycle, One byte Address=An-1, Data=Dn-1 One L No new cycle Data=Qn-1 for one byte H H L No carryover from previous cycle Note : 1. This operation makes written data immediately available at output during a read cycle preceded by a write cycle. ABSOLUTE MAXIMUM RATINGS* PARAMETER SYMBOL RATING UNIT Voltage on VDD Supply Relative to VSS VDD -0.3 to 4.6 V Voltage on VDDQ Supply Relative to VSS VDDQ VDD V Voltage on Input Pin Relative to VSS VIN -0.3 to 6.0 V Voltage on I/O Pin Relative to VSS VIO -0.3 to VDDQ+0.5 V Power Dissipation Storage Temperature PD 1.6 W TSTG -65 to 150 °C Operating Temperature TOPR 0 to 70 °C Storage Temperature Range Under Bias TBIAS -10 to 85 °C *Note : Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. OPERATING CONDITIONS at 3.3V I/O (0°C≤ TA≤70°C) PARAMETER Supply Voltage Ground SYMBOL MIN Typ. MAX UNIT VDD 3.135 3.3 3.6 V VDDQ 3.135 3.3 3.6 V VSS 0 0 0 V MAX UNIT OPERATING CONDITIONS at 2.5V I/O(0°C ≤ TA ≤ 70°C) PARAMETER Supply Voltage Ground SYMBOL MIN Typ. VDD 3.135 3.3 3.6 V VDDQ 2.375 2.5 2.9 V VSS 0 0 0 V CAPACITANCE*(TA=25°C, f=1MHz) PARAMETER Input Capacitance Output Capacitance SYMBOL TEST CONDITION MIN MAX UNIT CIN VIN=0V - 5 pF COUT VOUT=0V - 7 pF *Note : Sampled not 100% tested. -6- February 1999 Rev 5.0 KM732V789 128Kx32 Synchronous SRAM DC ELECTRICAL CHARACTERISTICS(TA=0 to 70°C, VDD=3.3V+0.3V/-0.165V) PARAMETER SYMBOL TEST CONDITIONS MIN MAX UNIT Input Leakage Current(except ZZ) IIL VDD = Max ; VIN=VSS to VDD -2 +2 µA Output Leakage Current IOL Output Disabled, VOUT=VSS to VDDQ -2 +2 µA ICC Device Selected, IOUT=0mA, ZZ≤VIL, All Inputs=VIL or VIH Cycle Time ≥ tCYC Min Operating Current ISB Standby Current Device deselected, IOUT=0mA, ZZ≤VIL, f=Max, All Inputs≤0.2V or ≥ VDD-0.2V -60 - 425 -67 - 400 -72 - 375 -10 - 300 -60 - 130 -67 - 120 -72 - 110 -10 - 90 mA mA ISB1 Device deselected, IOUT=0mA, ZZ≤0.2V, f = 0, All Inputs=fixed (VDD-0.2V or 0.2V) - 30 mA ISB2 Device deselected, IOUT=0mA, ZZ≥VDD-0.2V, f=Max, All Inputs≤VIL or ≥VIH - 30 mA Output Low Voltage(3.3V I/O) VOL IOL = 8.0mA - 0.4 V Output High Voltage(3.3V I/O) VOH IOH = -4.0mA 2.4 - V Output Low Voltage(2.5V I/O) VOL IOL = 1.0mA - 0.4 V Output High Voltage(2.5V I/O) VOH IOH = -1.0mA 2.0 - V Input Low Voltage(3.3V I/O) VIL -0.5* 0.8 V Input High Voltage(3.3V I/O) VIH 2.0 VDD+0.5** V Input Low Voltage(2.5V I/O) VIL -0.3* 0.7 V Input High Voltage(2.5V I/O) VIH 1.7 VDD+0.5** V * VIL(Min)=-2.0(Pulse Width ≤ tCYC/2) ** VIH(Max)=4.6(Pulse Width ≤ tCYC/2) ** In Case of I/O Pins, the Max. VIH=VDDQ+0.5V TEST CONDITIONS (VDD=3.3V+0.3V/-0.165V,VDDQ=3.3V+0.3/-0.165V or VDD=3.3V+0.3V/-0.165V,VDDQ=2.5V+0.4V/-0.125V, TA=0 to 70°C) PARAMETER VALUE Input Pulse Level(for 3.3V I/O) 0 to 3V Input Pulse Level(for 2.5V I/O) 0 to 2.5V Input Rise and Fall Time(Measured at 0.3V and 2.7V for 3.3V I/O) 2ns Input Rise and Fall Time(Measured at 0.3V and 2.1V for 2.5V I/O) 2ns Input and Output Timing Reference Levels for 3.3V I/O 1.5V Input and Output Timing Reference Levels for 2.5V I/O VDDQ/2 Output Load See Fig. 1 -7- February 1999 Rev 5.0 KM732V789 128Kx32 Synchronous SRAM Output Load(B) (for tLZC, tLZOE, tHZOE & tHZC) Output Load(A) Dout +3.3V for 3.3V I/O /+2.5V for 2.5V I/O RL=50Ω Z0=50Ω 30pF* VL=1.5V for 3.3V I/O VDDQ/2 for 2.5V I/O 319Ω / 1667Ω Dout 353Ω / 1538Ω * Capacitive Load consists of all components of the test environment. 5pF* * Including Scope and Jig Capacitance Fig. 1 AC TIMING CHARACTERISTICS(TA=0 to 70°C, VDD=3.3V+0.3V/-0.165V) PARAMETER SYMBOL -60 MIN -67 MAX MIN -72 MAX MIN -10 MAX MIN MAX UNIT Cycle Time tCYC 6.0 - 6.7 - 7.2 - 10.0 - ns Clock Access Time tCD - 3.5 - 3.8 - 4.0 - 4.5 ns Output Enable to Data Valid tOE - 3.5 - 3.8 - 4.0 - 4.5 ns Clock High to Output Low-Z tLZC 0 - 0 - 0 - 0 - ns Output Hold from Clock High tOH 1.5 - 1.5 - 1.5 - 1.5 - ns Output Enable Low to Output Low-Z tLZOE 0 - 0 - 0 - 0 - ns Output Enable High to Output High-Z tHZOE - 3.5 - 3.5 - 3.8 - 4.0 ns Clock High to Output High-Z tHZC 1.5 6.0 1.5 6.7 1.5 7.2 1.5 9.0 ns Clock High Pulse Width tCH 2.4 - 2.6 - 2.8 - 3.4 - ns Clock Low Pulse Width tCL 2.4 - 2.6 - 2.8 - 3.4 - ns Address Setup to Clock High tAS 1.5 - 1.5 - 1.5 - 1.5 - ns Address Status Setup to Clock High tSS 1.5 - 1.5 - 1.5 - 1.5 - ns Data Setup to Clock High tDS 1.5 - 1.5 - 1.5 - 1.5 - ns tWS 1.5 - 1.5 - 1.5 - 1.5 - ns Address Advance Setup to Clock High tADVS 1.5 - 1.5 - 1.5 - 1.5 - ns Chip Select Setup to Clock High tCSS 1.5 - 1.5 - 1.5 - 1.5 - ns Address Hold from Clock High tAH 0.5 - 0.5 - 0.5 - 0.5 - ns Write Setup to Clock High (GW, BW, WEX) Address Status Hold from Clock High tSH 0.5 - 0.5 - 0.5 - 0.5 - ns Data Hold from Clock High tDH 0.5 - 0.5 - 0.5 - 0.5 - ns Write Hold from Clock High (GW, BW, WEX) tWH 0.5 - 0.5 - 0.5 - 0.5 - ns Address Advance Hold from Clock High tADVH 0.5 - 0.5 - 0.5 - 0.5 - ns Chip Select Hold from Clock High tCSH 0.5 - 0.5 - 0.5 - 0.5 - ns ZZ High to Power Down tPDS 2 - 2 - 2 - 2 - cycle ZZ Low to Power Up tPUS 2 - 2 - 2 - 2 - cycle Notes : 1. All address inputs must meet the specified setup and hold times for all rising clock edges whenever ADSC and/or ADSP is sampled low and CS is sampled low. All other synchronous inputs must meet the specified setup and hold times whenever this device is chip selected. 2. Both chip selects must be active whenever ADSC or ADSP is sampled low in order for the this device to remain enabled. 3. ADSC or ADSP must not be asserted for at least 2 Clock after leaving ZZ state. -8- February 1999 Rev 5.0 -9- Data Out OE ADV CS WRITE ADDRESS ADSC ADSP CLOCK tCSS tAS tSS A1 tADVS tCSH tWS tAH tSH Q1-1 A2 tHZOE tSH Q2-1 tCD tOH Q2-2 A3 Q2-3 (ADV INSERTS WAIT STATE) BURST CONTINUED WITH NEW BASE ADDRESS NOTES : WRITE = L means GW = L, or GW = H, BW = L, WEx = L CS = L means CS1 = L, CS2 = H and CS2 = L CS = H means CS1 = H, or CS1 = L and CS2 = H, or CS1 = L, and CS2 = L tLZOE tOE tADVH tWH tSS tCL tCYC tCH TIMING WAVEFORM OF READ CYCLE Q2-4 Q3-1 Q3-2 Q3-3 Undefined Don′t Care Q3-4 tHZC KM732V789 128Kx32 Synchronous SRAM February 1999 Rev 5.0 - 10 - Data Out Data In OE ADV CS WRITE ADDRESS ADSC ADSP CLOCK Q0-3 tCSS tAS tSS Q0-4 A1 tHZOE tCSH tAH tSH D1-1 tCL tCYC tCH A2 D2-1 D2-2 (ADV SUSPENDS BURST) D2-2 D2-3 (ADSC EXTENDED BURST) TIMING WAVEFORM OF WRTE CYCLE D2-4 D3-1 A3 tDS tADVS tWS tSS D3-2 tDH tADVH tWH tSH D3-3 Undefined Don′t Care D3-4 KM732V789 128Kx32 Synchronous SRAM February 1999 Rev 5.0 - 11 - Data Out Data In OE ADV CS WRITE ADDRESS ADSP CLOCK tHZC tSS A1 tSH tLZC tCD tAS Q1-1 A2 tCL tHZOE tDS tADVS tWS tAH tCYC tCH D2-1 tDH tADVH tWH A3 tLZOE tOE Q2-1 Q3-1 Q3-2 tOH Q3-3 TIMING WAVEFORM OF COMBINATION READ/WRTE CYCLE(ADSP CONTROLLED , ADSC=HIGH) Undefined Don′t Care Q3-4 KM732V789 128Kx32 Synchronous SRAM February 1999 Rev 5.0 - 12 - Data In Data Out OE ADV CS WRITE ADDRESS ADSC CLOCK tCSS tSS A1 tCSH tSH tOE tLZOE A2 Q1-1 A3 Q2-1 A4 Q3-1 Q4-1 tHZOE D5-1 A5 tDS tWS D6-1 A6 tDH tWH D7-1 A7 tCL A8 tCD tWS tCYC tCH tWH Q7-1 A9 Q8-1 TIMING WAVEFORM OF SINGLE READ/WRITE CYCLE(ADSC CONTROLLED , ADSP=HIGH) Undefined Don′t Care Q9-1 tOH KM732V789 128Kx32 Synchronous SRAM February 1999 Rev 5.0 - 13 - ZZ Data Out Data In OE ADV CS WRITE ADDRESS ADSC ADSP CLOCK tCSS tAS tSS A1 tCSH tAH tSH tLZOE tOE Q1-1 ZZ Setup Cycle tPDS tHZC Sleep State ZZ Recovery Cycle tPUS tCL tCYC tCH TIMING WAVEFORM OF POWER DOWN CYCLE tWS Normal Operation Mode tHZOE A2 D2-1 tWH Undefined Don′t Care D2-2 KM732V789 128Kx32 Synchronous SRAM February 1999 Rev 5.0 KM732V789 128Kx32 Synchronous SRAM APPLICATION INFORMATION DEPTH EXPANSION The Samsung 128Kx32 Synchronous Pipelined Burst SRAM has two additional chip selects for simple depth expansion. This permits easy secondary cache upgrades from 128K depth to 256K depth without extra logic. I/O[0:63] Data Address A[0:17] A[17] A[0:16] A[17] Address Data Address Data CLK 64-Bits Microprocessor CS2 CS2 CS2 CS2 128Kx32 SPB SRAM CLK Address ADSC CLK 128Kx32 SPB SRAM CLK ADSC WEx WEx (Bank 0) OE Cache Controller A[0:16] (Bank 1) OE CS1 CS1 ADV ADV ADSP ADSP ADS INTERLEAVE READ TIMING (Refer to non-interleave write timing for interleave write timing) (ADSP CONTROLLED , ADSC=HIGH) Clock tSS tSH ADSP tAS ADDRESS [0:n] A1 tAH A2 tWS tWH WRITE tCSS tCSH CS1 Bank 0 is selected by CS2, and Bank 1 deselected by CS2 An+1 tADVS tADVH Bank 0 is deselected by CS2, and Bank 1 selected by CS2 ADV OE tOE tHZC tLZOE Data Out (Bank 0) Q1-1 Q1-2 Q1-3 Q1-4 tCD tLZC Data Out (Bank 1) Q2-1 *Notes : n = 14 15 16 17 32K depth 64K depth 128K depth 256K depth Q2-2 Q2-3 Don′t Care - 14 - Q2-4 Undefined February 1999 Rev 5.0 KM732V789 128Kx32 Synchronous SRAM PACKAGE DIMENSIONS 100-TQFP-1420A Units ; millimeters/Inches 0~8° 22.00 ±0.30 0.10 0.127 +- 0.05 20.00 ±0.20 16.00 ±0.30 14.00 ±0.20 0.10 MAX (0.83) 0.50 ±0.10 #1 0.65 (0.58) 0.30 ±0.10 0.10 MAX 1.40 ±0.10 1.60 MAX 0.50 ±0.10 - 15 - 0.05 MIN February 1999 Rev 5.0