KMM5364003CK/CKG KMM5364103CK/CKG DRAM MODULE 4Byte 4Mx36 SIMM (4Mx4 & 16M Quad CAS base) Revision 0.1 Nov. 1997 DRAM MODULE KMM5364003CK/CKG KMM5364103CK/CKG Revision History Version 0.1 (Nov. 1997) • Changed the mode of parity check component from EDO to FP, refer to PACKAGE DIMENSIONS and GENERAL DISCRIPTION. KMM5364003CK/CKG KMM5364103CK/CKG DRAM MODULE KMM5364003CK/CKG & KMM5364103CK/CKG with Fast Page Mode 4M x 36 DRAM SIMM using 4Mx4 and 16M Quad CAS, 4K/2K Refresh, 5V GENERAL DESCRIPTION FEATURES The Samsung KMM53640(1)03CK is a 4Mx36bits Dynamic RAM high density memory module. The Samsung KMM53640(1)03CK consists of eight CMOS 4Mx4bits DRAMs in 24-pin SOJ package and one CMOS 4Mx4 bit Quad CAS DRAM in 28-pin SOJ package mounted on a 72-pin glassepoxy substrate. A 0.1 or 0.22uF decoupling capacitor is mounted on the printed circuit board for each DRAM. The KMM53640(1)03CK is a Single In-line Memory Module with edge connections and is intended for mounting into 72 pin edge connector sockets. • Part Identification - KMM5364003CK(4096 cycles/64ms Ref, SOJ, Solder) - KMM5364003CKG(4096 cycles/64ms Ref, SOJ, Gold) - KMM5364103CK(2048 cycles/32ms Ref, SOJ, Solder) - KMM5364103CKG(2048 cycles/32ms Ref, SOJ, Gold) • Fast Page Mode Operation • CAS-before-RAS refresh capability • RAS-only and Hidden refresh capability • TTL compatible inputs and outputs • Single +5V ±10% power supply PERFORMANCE RANGE Speed tRAC tCAC tRC -5 50ns 13ns 90ns -6 60ns 15ns 110ns PIN CONFIGURATIONS • JEDEC standard PDPin & pinout • PCB : Height(1000mil), single sided component PIN NAMES Pin Symbol Pin Symbol 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 VSS DQ0 DQ18 DQ1 DQ19 DQ2 DQ20 DQ3 DQ21 Vcc NC A0 A1 A2 A3 A4 A5 A6 A10 DQ4 DQ22 DQ5 DQ23 DQ6 DQ24 DQ7 DQ25 A7 A11 Vcc A8 A9 Res(RAS1) RAS0 DQ26 DQ8 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 DQ17 DQ35 Vss CAS0 CAS2 CAS3 CAS1 RAS0 Res(RAS1) NC W NC DQ9 DQ27 DQ10 DQ28 DQ11 DQ29 DQ12 DQ30 DQ13 DQ31 Vcc DQ32 DQ14 DQ33 DQ15 DQ34 DQ16 NC PD1 PD2 PD3 PD4 NC Vss Pin Name Function A0 - A11 Address Inputs(4K Ref) A0 - A10 Address Inputs(2K Ref) DQ0 - DQ35 Data In/Out W Read/Write Enable RAS0 Row Address Strobe CAS0 - CAS3 Column Address Strobe PD1 -PD4 Presence Detect Vcc Power(+5V) Vss Ground NC No Connection PRESENCE DETECT PINS (Optional) Pin 50NS 60NS PD1 PD2 PD3 PD4 Vss NC Vss Vss Vss NC NC NC * Pin connection changing available SAMSUNG ELECTRONICS CO., LTD. reserves the right to change products and specifications without notice. * NOTE : A11 is used for only KMM5364003CK/CKG (4K ref.) KMM5364003CK/CKG KMM5364103CK/CKG DRAM MODULE FUNCTIONAL BLOCK DIAGRAM CAS0 RAS0 CAS RAS OE CAS RAS OE CAS1 CAS RAS OE CAS RAS OE CAS2 CAS RAS OE CAS RAS OE CAS3 CAS RAS OE CAS RAS OE DQ0 DQ1 DQ2 A0A11(A10) DQ3 DQ0-DQ3 DQ0 DQ1 DQ2 A0A11(A10) DQ3 DQ4-DQ7 DQ0 DQ1 DQ2 A0A11(A10) DQ3 DQ9-DQ12 DQ0 DQ1 DQ2 A0A11(A10) DQ3 DQ13-DQ16 DQ0 DQ1 DQ2 A0A11(A10) DQ3 DQ18-DQ21 DQ0 DQ1 DQ2 A0A11(A10) DQ3 DQ22-DQ25 DQ0 DQ1 DQ2 A0A11(A10) DQ3 DQ27-DQ30 DQ0 DQ1 DQ2 A0A11(A10) DQ3 DQ31-DQ34 U0 W U1 W U2 W U3 W U4 W U5 W U6 W U7 W CAS0 CAS1 CAS2 CAS3 RAS OE W U8 DQ0 DQ1 DQ2 DQ3 DQ8 DQ17 DQ26 DQ35 A0A11(A10) W A0-A11(A10) Vcc .1 or .22uF Capacitor for each DRAM Vss To all DRAMs KMM5364003CK/CKG KMM5364103CK/CKG DRAM MODULE ABSOLUTE MAXIMUM RATINGS * Item Voltage on any pin relative to V SS Voltage on V CC supply relative to V SS Storage Temperature Power Dissipation Short Circuit Output Current Symbol Rating Unit VIN , VOUT VCC Tstg Pd IOS -1 to +7.0 -1 to +7.0 -55 to +150 9 50 V V °C W mA * Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for in tended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS (Voltage referenced to V SS, TA = 0 to 70°C) Item Supply Voltage Ground Input High Voltage Input Low Voltage Symbol Min Typ Max Unit VCC VSS VIH VIL 4.5 0 2.4 5.0 0 - 5.5 0 V V V V -1.0 *2 VCC +1 *1 0.8 *1 : V CC +2.0V/20ns, Pulse width is measured at VCC . *2 : -2.0V/ 20ns, Pulse width is measured at VSS . DC AND OPERATING CHARACTERISTICS (Recommended operating conditions unless otherwise noted) ICC1 ICC2 ICC3 ICC4 ICC5 ICC6 II(L) IO(L) VOH VOL Symbol Speed ICC1 KMM5364003CK/CKG KMM5364103CK/CKG Unit Min Max Min Max -5 -6 - 810 720 - 990 900 mA mA ICC2 Don′t care - 18 - 18 mA ICC3 -5 -6 - 810 720 - 990 900 mA mA ICC4 -5 -6 - 720 630 - 810 720 mA mA ICC5 Don′t care - 9 - 9 mA ICC6 -5 -6 - 810 720 - 990 900 mA mA II(L) IO(L) Don′t care -45 -5 45 5 -45 -5 45 5 uA uA VOH VOL Don′t care 2.4 - 0.4 2.4 - 0.4 V V : Operating Current * ( RAS, CAS, Address cycling @ tRC =min) : Standby Current ( RAS=CAS=W=VIH ) : RAS Only Refresh Current * ( CAS=V IH, RAS cycling @ tRC =min) : Fast Page Mode Current * ( RAS=VIL, CAS Address cycling : tPC =min) : Standby Current ( RAS=CAS=W=Vcc-0.2V) : CAS-Before-RAS Refresh Current * ( RAS and CAS cycling @ tRC =min) : Input Leakage Current (Any input 0 ≤VIN≤Vcc+0.5V, all other pins not under test=0 V) : Output Leakage Current(Data Out is disabled, 0V ≤VOUT ≤Vcc) : Output High Voltage Level (I OH = -5mA) : Output Low Voltage Level (I OL = 4.2mA) * NOTE : ICC1 , ICC3 , ICC4 and I CC6 are dependent on output loading and cycle rates. Specified values are obtained with the output open. ICC is specified as an average current. In I CC1 and I CC3 , address can be changed maximum once while RAS=VIL. In I CC4 , address can be changed maximum once within one page mode cycle, tPC . KMM5364003CK/CKG KMM5364103CK/CKG DRAM MODULE CAPACITANCE (TA = 25°C, VCC=5V, f = 1MHz) Item Symbol Input capacitance[A0-A11(A10)] Input capacitance[ W] Input capacitance[ RAS0] Input capacitance[ CAS0 - CAS3] Input/Output capacitance[DQ0-35] CIN1 CIN2 CIN3 CIN4 CDQ Min Max Unit - 65 80 80 40 25 pF pF pF pF pF AC CHARACTERISTICS (0°C≤TA≤70°C, VCC=5.0V±10%. See notes 1,2.) Test condition : Vih /Vil=2.4/0.8V, V oh/Vol =2.4/0.4V, Output loading CL=100pF Parameter Random read or write cycle time Access time from RAS Access time from CAS Access time from column address CAS to output in Low-Z Output buffer turn-off delay Transition time(rise and fall) RAS precharge time RAS pulse width RAS hold time CAS hold time CAS pulse width RAS to CAS delay time RAS to column address delay time CAS to RAS precharge time Row address set-up time Row address hold time Column address set-up time Column address hold time Column address to RAS lead time Read command set-up time Read command hold time referenced to CAS Read command hold time referenced to RAS Write command hold time Write command pulse width Write command to RAS lead time Write command to CAS lead time Data-in set-up time Data-in hold time Refresh period (4K Ref) Refresh period (2K Ref) Write command set-up time CAS setup time( CAS-before-RAS refresh) CAS hold time( CAS-before-RAS refresh) RAS precharge to CAS hold time Symbol tRC tRAC tCAC tAA tCLZ tOFF tT tRP tRAS tRSH tCSH tCAS tRCD tRAD tCRP tASR tRAH tASC tCAH tRAL tRCS tRCH tRRH tWCH tWP tRWL tCWL tDS tDH tREF tREF tWCS tCSR tCHR tRPC -5 Min -6 Max 90 Min Max 110 Unit Note ns 50 60 ns 3,4 13 15 ns 3,4,5 25 30 ns 3,10 0 ns 3 0 13 0 0 15 ns 6 3 50 3 50 ns 2 30 50 40 10K 13 60 ns 10K 15 50 ns ns 60 ns 13 10K 15 10K ns 20 37 20 45 ns 4 15 25 15 30 ns 10 5 5 ns 0 0 ns 10 10 ns 0 0 ns 10 10 ns 25 30 ns 0 0 ns 0 0 ns 8 0 0 ns 8 10 10 ns 10 10 ns 13 15 ns 13 15 ns 0 0 ns 9 10 15 ns 9 0 64 64 ms 32 32 ms 0 ns 5 5 ns 10 10 ns 5 5 ns 7 KMM5364003CK/CKG KMM5364103CK/CKG DRAM MODULE AC CHARACTERISTICS (0°C≤TA≤70°C, VCC=5.0V±10%. See notes 1,2.) Test condition : Vih/Vil=2.4/0.8V, V oh /Vol =2.4/0.4V, Output loading CL=100pF Parameter Access time from CAS precharge Fast page mode cycle time CAS precharge time(Fast page cycle) RAS pulse width(Fast page cycle) W to RAS precharge time(C-B-R refresh) W to RAS hold time(C-B-R refresh) Hold time CAS low to CAS high Symbol tCPA tPC tCP tRASP tWRP tWRH tCLCH -5 Min -6 Max Min 30 Max 35 Unit Note ns 3 35 40 ns 10 10 ns 50 200K 60 200K ns 10 10 ns 10 10 ns 5 5 ns 11 NOTES 1. An initial pause of 200us is required after power-up followed by any 8 RAS-only or CAS-before-RAS refresh cycles before proper device operation is achieved. 2. VIH(min) and V IL(max) are reference levels for measuring timing of input signals. Transition times are measured between V IH(min) and V IL(max) and are assumed to be 5ns for all inputs. 3. Measured with a load equivalent to 2 TTL loads and 100pF. 4. Operation within the tRCD (max) limit insures that tRAC (max) can be met. tRCD (max) is specified as a reference point only. If tRCD is greater than the specified tRCD (max) limit, then access time is controlled exclusively by tCAC . 5. Assumes that tRCD ≥tRCD (max). 6. This parameter defines the time at which the output achieves the open circuit condition and is not referenced to V OH or VOL . 7. tWCS is non-restrictive operating parameter. It is included in the data sheet as electrical characteristic s only. If tWCS ≥tWCS (min), the cycle is an early write cycle and the data out pin will remain high impedance for the duration of the cycle. 8. Either tRCH or tRRH must be satisfied for a read cycle. 9. These parameter are referenced to the CAS leading edge in early write cycles. 10. Operation within the tRAD (max) limit insures that tRAC (max) can be met. tRAD (max) is specified as reference point only. If tRAD is greater than the specified tRAD (max) limit, then access time is controlled by tAA . 11. In order to hold the address latched by the first CAS going low, the parameter tCLCH must be met. KMM5364003CK/CKG KMM5364103CK/CKG DRAM MODULE READ CYCLE tRC tRAS RAS tRP VIH VIL - tCSH tCRP CAS tRCD tCRP tRSH tCAS VIH VIL - tRAD tASR A VIH VIL - tRAH tASC ROW ADDRESS tRAL tCAH COLUMN ADDRESS tRCH tRCS W tRRH VIH VIL - tAA tOFF tCAC DQ VOH VOL - tRAC OPEN tCLZ DATA-OUT Don′t care Undefined KMM5364003CK/CKG KMM5364103CK/CKG DRAM MODULE WRITE CYCLE ( EARLY WRITE ) NOTE : D OUT = OPEN tRAS RAS tRC tRP VIH VIL - tCSH tCRP CAS tRCD tRSH tCAS VIH VIL - tRAD tASR A tCRP VIH VIL - tRAH tASC ROW ADDRESS tRAL tCAH COLUMN ADDRESS tCWL tRWL tWCS W tWP VIL - tDS DQ tWCH VIH - VIH VIL - tDH DATA-IN Don′t care Undefined KMM5364003CK/CKG KMM5364103CK/CKG DRAM MODULE FAST PAGE READ CYCLE NOTE : D OUT = OPEN tRP tRASP RAS VIH - tRHCP VIL - ¡ó tCRP CAS tRCD VIH - tRAD tASC VIL - VIH VIL - tCP tCAS tCAS tASR A tPC tCP tRSH tCAS ¡ó tCSH tRAH tCAH ROW ADDR tASC tCAH COLUMN ADDRESS COLUMN ADDRESS tASC ¡ó ¡ó tCAH COLUMN ADDRESS tRRH tRCS W tRCH tRCS VIH - tRCH VIL - tCAC tCAC tAA tOFF tCLZ tAA DQ ¡ó tRCS VOH VOL - tRAC tCLZ VALID DATA-OUT tCAC tAA tOFF tCLZ VALID DATA-OUT tOFF VALID DATA-OUT Don′t care Undefined KMM5364003CK/CKG KMM5364103CK/CKG DRAM MODULE FAST PAGE WRITE CYCLE ( EARLY WRITE ) NOTE : D OUT = OPEN tRP tRASP RAS tRHCP VIH VIL - ¡ó tPC tCRP CAS tRAD tASC VIL - VIL - tCSH tCAH tRAH tASC COLUMN ADDRESS ROW ADDR VIH - tWCH tCAH tASC ¡ó COLUMN ADDRESS tWCS ¡ó tWCH tWP tCAH COLUMN ADDRESS tWCS ¡ó tWCH tWP tWP VIL - tCWL tDS DQ tRSH tCAS ¡ó tWCS W tCP tCAS tCAS tASR A tRCD VIH - VIH - tPC tCP VIH VIL - tDH tCWL tDS tDH tDS tCWL tRWL tDH ¡ó VALID DATA-IN VALID DATA-IN ¡ó VALID DATA-IN Don′t care Undefined KMM5364003CK/CKG KMM5364103CK/CKG DRAM MODULE RAS - ONLY REFRESH CYCLE NOTE : W, OE, DIN = Don ′t care DOUT = OPEN tRAS RAS tRC tRP VIH VIL - tRPC tCRP CAS VIH VIL - tASR A tCRP VIH VIL - tRAH ROW ADDR CAS - BEFORE - RAS REFRESH CYCLE NOTE : OE, A = Don ′t care tRC tRP RAS tRAS tRP VIH VIL - tRPC tCP CAS tRPC tCSR VIH - tWRP W tCHR VIL - tWRH VIH VIL - tOFF DQ VOH VOL - OPEN Don′t care Undefined KMM5364003CK/CKG KMM5364103CK/CKG DRAM MODULE HIDDEN REFRESH CYCLE ( READ ) tRC tRC tRP tRAS RAS tRP VIH VIL - tCRP CAS tRAS tRCD tRSH tCHR VIH VIL - tRAD tASR A VIH VIL - tRAH tASC ROW ADDRESS tCAH COLUMN ADDRESS tWRH tRCS W tRRH tWRP VIH VIL - tAA tRAC DQ VOH VOL - OPEN tOFF tCAC tCLZ DATA-OUT Don′t care Undefined KMM5364003CK/CKG KMM5364103CK/CKG DRAM MODULE HIDDEN REFRESH CYCLE ( WRITE ) NOTE : D OUT = OPEN tRC RAS VIH - tRP tRCD tRSH tCHR VIH VIL - tRAD tASR A tRAS VIL - tCRP CAS tRC tRP tRAS VIH VIL - tRAH tASC ROW ADDRESS tCAH COLUMN ADDRESS tWRH tWRP W VIH - tWCS tWCH tWP VIL - tDS DQ VIH VIL - tDH DATA-IN Don′t care Undefined KMM5364003CK/CKG KMM5364103CK/CKG DRAM MODULE CAS-BEFORE-RAS REFRESH COUNTER TEST CYCLE tRP RAS CAS VIH - tRAS VIL VIH - tCPT tCSR tRSH tCAS tCHR VIL - tRAL tASC A VIH VIL - READ CYCLE W DQ tWRP tWRH tRCS tRRH tAA tRCH tCAC VIH VIL - tOFF tCLZ VOH - DATA-OUT VOL - WRITE CYCLE W tCAH COLUMN ADDRESS tWRP tRWL tWRH tWCS VIH - tCWL tWCH VIL - tWP tDS DQ VIH VIL - OPEN tDH DATA-IN Don′t care Undefined NOTE : This timing diagram is applied to all devices besides 16M DRAM 4th & 64M DRAM. KMM5364003CK/CKG KMM5364103CK/CKG DRAM MODULE CAS - BEFORE - RAS SELF REFRESH CYCLE NOTE : OE, A = Don′t care tRP RAS tRASS tRPS VIH VIL - tRPC tRPC tCP CAS tCHS VIH - tCSR VIL - tOFF DQ VOH - OPEN VOL - tWRP W tWRH VIH VIL - TEST MODE IN CYCLE NOTE : OE, A = Don ′t care tRC tRP RAS tRAS tRP VIH VIL - tRPC tCP CAS tRPC VIH - tCSR tWTS W tCHR VIL - tWTH VIH VIL - tOFF DQ VOH VOL - OPEN Don′t care Undefined KMM5364003CK/CKG KMM5364103CK/CKG DRAM MODULE PACKAGE DIMENSIONS Units : Inches (millimeters) 4.250(107.95) 3.984(101.19) .133(3.38) R.062(1.57) .125 DIA±.002(3.18±.051) .400(10.16) 1.00(25.40) .250(6.35) .080(2.03) .250(6.35) R.062±.004(R1.57±.10) .125(3.17) .250(6.35) MIN 3.750(95.25) ( Front view ) ( Back view ) Gold & Solder Plating Lead .200(5.08) MAX .100(2.54) .010(.25)MAX MIN .050(1.27) .041±.004(1.04±.10) .054(1.37) .047(1.19) Tolerances : ±.005(.13) unless otherwise specified NOTE : The used device are 4Mx4 FP DRAM (SOJ & 300mil) & 4Mx4 Quad CAS with FP DRAM (SOJ & 300mil) DRAM Part No. : KMM5364003CK/CKG -- KM44C4000CK (300 mil) & KM44C4003CK (300mil) KMM5364103CK/CKG -- KM44C4100CK (300 mil) & KM44C4103CK (300mil) Revision History Rev 0.1 : Nov. 1997