SAMSUNG KMM5321200C2WG

DRAM MODULE
KMM5321200C2W/C2WG
1Mx32 DRAM SIMM
(1MX16 Base)
Revision 0.0
November 1997
-1-
Rev. 0.0 (Nov. 1997)
DRAM MODULE
KMM5321200C2W/C2WG
Revision History
Version 0.0 (November 1997)
• Changed module PCB from 6-Layer to 4-Layer.
• Changed Module Part No. from KMM5321200CW/CWG to KMM5321200C2W/C2WG caused by PCB revision .
-2-
Rev. 0.0 (Nov. 1997)
DRAM MODULE
KMM5321200C2W/C2WG
KMM5321200C2W/C2WG with Fast Page Mode
1M x 32 DRAM SIMM using 1Mx16, 1K Refresh, 5V
GENERAL DESCRIPTION
FEATURES
The Samsung KMM5321200C2W is a 1Mx32bits Dynamic
RAM high density memory module. The Samsung
KMM5321200C2W consists of two CMOS 1Mx16bits DRAMs
in 42-pin SOJ packages mounted on a 72-pin glass-epoxy
substrate. A 0.1 or 0.22uF decoupling capacitor is mounted
on the printed circuit board for each DRAM. The
KMM5321200C2W is a Single In-line Memory Module with
edge connections and is intended for mounting into 72 pin
edge connector sockets.
• Part Identification
PERFORMANCE RANGE
• JEDEC standard PDPin & pinout
Speed
tRAC
tCAC
tRC
-5
50ns
15ns
90ns
-6
60ns
15ns
110ns
- KMM5321200C2W(1024 cycles/16ms Ref, SOJ, Solder)
- KMM5321200C2WG(1024 cycles/16ms Ref, SOJ, Gold)
• Fast Page Mode Operation
• CAS-before-RAS refresh capability
• RAS-only refresh capability
• TTL compatible inputs and outputs
• Single +5V±10% power supply
• PCB : Height(750mil), single sided component
PIN CONFIGURATIONS
PIN NAMES
Pin
Symbol
Pin
Symbol
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
VSS
DQ0
DQ16
DQ1
DQ17
DQ2
DQ18
DQ3
DQ19
Vcc
NC
A0
A1
A2
A3
A4
A5
A6
Res(A10)
DQ4
DQ20
DQ5
DQ21
DQ6
DQ22
DQ7
DQ23
A7
Res(A11)
Vcc
A8
A9
Res(RAS1)
RAS0
NC
NC
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
NC
NC
Vss
CAS0
CAS2
CAS3
CAS1
RAS0
Res(RAS1)
NC
W
NC
DQ8
DQ24
DQ9
DQ25
DQ10
DQ26
DQ11
DQ27
DQ12
DQ28
Vcc
DQ29
DQ13
DQ30
DQ14
DQ31
DQ15
NC
PD1
PD2
PD3
PD4
NC
Vss
Pin Name
Function
A0 - A9
Address Inputs
DQ0 - DQ31
Data In/Out
W
Read/Write Enable
RAS0
Row Address Strobe
CAS0 - CAS3
Column Address Strobe
PD1 -PD4
Presence Detect
Vcc
Power(+5V)
Vss
Ground
NC
No Connection
Res
Reserved Pin
PRESENCE DETECT PINS (Optional)
Pin
50NS
60NS
PD1
PD2
PD3
PD4
Vss
Vss
Vss
Vss
Vss
Vss
NC
NC
* Pin connection changing available
SAMSUNG ELECTRONICS CO., LTD. reserves the right to
change products and specifications without notice.
-3-
Rev. 0.0 (Nov. 1997)
DRAM MODULE
KMM5321200C2W/C2WG
FUNCTIONAL BLOCK DIAGRAM
RAS
RAS0
CAS0
LCAS
CAS1
UCAS
U0
OE
W
A0-A9
RAS
CAS2
LCAS
CAS3
UCAS
U1
OE
W
A0-A9
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
W
A0-A9
Vcc
.1 or .22uF Capacitor
for each DRAM
To all DRAMs
Vss
-4-
Rev. 0.0 (Nov. 1997)
DRAM MODULE
KMM5321200C2W/C2WG
ABSOLUTE MAXIMUM RATINGS *
Item
Voltage on any pin relative to V SS
Voltage on V CC supply relative to V SS
Storage Temperature
Power Dissipation
Short Circuit Output Current
Symbol
Rating
Unit
VIN, VOUT
VCC
Tstg
Pd
IOS
-1 to +7.0
-1 to +7.0
-55 to +150
2
50
V
V
°C
W
mA
* Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to
the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for in tended
periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS (Voltage referenced to VSS, TA = 0 to 70°C)
Item
Symbol
Min
Typ
Max
Unit
VCC
VSS
VIH
VIL
4.5
0
2.4
5.0
0
-
5.5
0
V
V
V
V
Supply Voltage
Ground
Input High Voltage
Input Low Voltage
-1.0*2
VCC +1*1
0.8
*1 : VCC +2.0V/20ns, Pulse width is measured at VCC .
*2 : -2.0V/20ns, Pulse width is measured at VSS.
DC AND OPERATING CHARACTERISTICS (Recommended operating conditions unless otherwise noted)
KMM5321200C2W/C2WG
Symbol
Speed
ICC1
-5
-6
ICC2
Don′t care
-
4
mA
ICC3
-5
-6
-
300
280
mA
mA
ICC4
-5
-6
-
180
160
mA
mA
ICC5
Don′t care
-
2
mA
ICC6
-5
-6
-
300
280
mA
mA
II(L)
IO(L)
Don′t care
-10
-5
10
5
uA
uA
VOH
VOL
Don′t care
2.4
-
0.4
V
V
Min
Max
-
300
280
Unit
mA
mA
ICC1 : Operating Current * ( RAS, LCAS or UCAS, Address cycling @ tRC =min)
ICC2 : Standby Current ( RAS=LCAS=UCAS=W=VIH)
ICC3 : RAS Only Refresh Current * ( LCAS=UCAS=VIH , RAS cycling @ tRC =min)
ICC4 : Fast Page Mode Current * ( RAS=VIL, LCAS or UCAS cycling : tPC =min)
ICC5 : Standby Current ( RAS=LCAS=UCAS=W=Vcc-0.2V)
ICC6 : CAS-Before-RAS Refresh Current * ( RAS and CAS cycling @ tRC =min)
II(L) : Input Leakage Current (Any input 0 ≤VIN≤Vcc+0.5V, all other pins not under test=0 V)
IO(L) : Output Leakage Current(Data Out is disabled, 0V ≤VOUT ≤Vcc)
VOH : Output High Voltage Level (I OH = -5mA)
VOL : Output Low Voltage Level (I OL = 4.2mA)
* NOTE : ICC1 , ICC3 , ICC4 and ICC6 are dependent on output loading and cycle rates. Specified values are obtained with the output open.
ICC is specified as an average current. In I CC1 and ICC3 , address can be changed maximum once while RAS=VIL. In ICC4 ,
address can be changed maximum once within one page mode cycle, tPC.
-5-
Rev. 0.0 (Nov. 1997)
DRAM MODULE
KMM5321200C2W/C2WG
CAPACITANCE (TA = 25°C, VCC=5V, f = 1MHz)
Item
Input capacitance[A0-A9]
Input capacitance[ W]
Input capacitance[ RAS0]
Input capacitance[ CAS0 - CAS3]
Input/Output capacitance[DQ0-31]
Symbol
Min
Max
Unit
CIN1
CIN2
CIN3
CIN4
CDQ
-
30
30
25
20
20
pF
pF
pF
pF
pF
AC CHARACTERISTICS (0°C≤TA≤70°C, VCC=5.0V±10%. See notes 1,2.)
Test condition : Vih/Vil=2.4/0.8V, V oh/Vol=2.4/0.4V, output loading CL=100pF
Parameter
Random read or write cycle time
Access time from RAS
Access time from CAS
Access time from column address
CAS to output in Low-Z
Output buffer turn-off delay
Transition time(rise and fall)
RAS precharge time
RAS pulse width
RAS hold time
CAS hold time
CAS pulse width
RAS to CAS delay time
RAS to column address delay time
CAS to RAS precharge time
Row address set-up time
Row address hold time
Column address set-up time
Column address hold time
Column address to RAS lead time
Read command set-up time
Read command hold referenced to CAS
Read command hold referenced to RAS
Write command hold time
Write command pulse width
Write command to RAS lead time
Write command to CAS lead time
Data-in set-up time
Data-in hold time
Refresh period
Write command set-up time
CAS setup time(CAS-before-RAS refresh)
CAS hold time(CAS-before-RAS refresh)
RAS precharge to CAS hold time
Access time from CAS precharge
Symbol
tRC
tRAC
tCAC
tAA
tCLZ
tOFF
tT
tRP
tRAS
tRSH
tCSH
tCAS
tRCD
tRAD
tCRP
tASR
tRAH
tASC
tCAH
tRAL
tRCS
tRCH
tRRH
tWCH
tWP
tRWL
tCWL
tDS
tDH
tREF
tWCS
tCSR
tCHR
tRPC
tCPA
-5
Min
-6
Max
90
Min
Max
110
50
Unit
Note
ns
60
ns
3,4
15
15
ns
3,4,5
25
30
ns
3,10
0
ns
3
0
13
0
0
15
ns
6
3
50
3
50
ns
2
10K
ns
30
50
40
10K
13
60
ns
15
50
ns
60
ns
13
10K
15
10K
ns
20
37
20
45
ns
4
15
25
15
30
ns
10
5
5
ns
ns
0
0
10
10
ns
0
0
ns
10
10
ns
25
30
ns
0
0
ns
0
0
ns
8
0
0
ns
8
10
10
ns
10
10
ns
13
15
ns
13
15
ns
0
0
ns
9
10
10
ns
9
16
16
ms
0
0
ns
5
5
ns
10
10
ns
5
5
ns
30
-6-
35
ns
7
3
Rev. 0.0 (Nov. 1997)
DRAM MODULE
KMM5321200C2W/C2WG
AC CHARACTERISTICS (0°C≤TA≤70°C, VCC=5.0V±10%. See notes 1,2.)
Test condition : Vih/Vil=2.4/0.8V, V oh/Vol=2.4/0.4V, output loading CL=100pF
Parameter
Fast page mode cycle time
CAS precharge time(Fast page cycle)
RAS pulse width(Fast page cycle)
W to RAS precharge time(C-B-R refresh)
W to RAS hold time(C-B-R refresh)
-5
Symbol
Min
tPC
tCP
tRASP
tWRP
tWRH
-6
Max
Min
Max
Unit
35
40
ns
10
10
ns
50
200K
60
200K
Note
ns
10
10
ns
10
10
ns
NOTES
1. An initial pause of 200us is required after power-up followed
by any 8 RAS-only or CAS-before-RAS refresh cycles before
proper device operation is achieved.
7. tWCS is non-restrictive operating parameter. It is included in
the data sheet as electrical characteristic s only. If
tWCS ≥tWCS (min), the cycle is an early write cycle and the
data out pin will remain high impedance for the duration of
the cycle.
2. VIH(min) and V IL(max) are reference levels for measuring
timing of input signals. Transition times are measured
between V IH(min) and V IL(max) and are assumed to be 5ns
for all inputs.
8. Either tRCH or tRRH must be satisfied for a read cycle.
9. These parameter are referenced to the CAS leading edge in
early write cycles.
3. Measured with a load equivalent to 2 TTL loads and 100pF.
4. Operation within the tRCD (max) limit insures that tRAC (max)
can be met. tRCD (max) is specified as a reference point only.
If tRCD is greater than the specified tRCD (max) limit, then
access time is controlled exclusively by tCAC .
10. Operation within the tRAD (max) limit insures that tRAC (max)
can be met. tRAD (max) is specified as reference point only. If
tRAD is greater than the specified tRAD (max) limit, then
access time is controlled by tAA .
5. Assumes that tRCD ≥tRCD (max).
6. This parameter defines the time at which the output achieves
the open circuit condition and is not referenced to V OH or
VOL .
-7-
Rev. 0.0 (Nov. 1997)
DRAM MODULE
KMM5321200C2W/C2WG
READ CYCLE
tRC
tRAS
RAS
tRP
VIH VIL -
tCSH
tCRP
CAS
tRCD
tCRP
tRSH
tCAS
VIH VIL -
tRAD
tASR
A
VIH VIL -
tRAH
tASC
ROW
ADDRESS
tRAL
tCAH
COLUMN
ADDRESS
tRCH
tRCS
W
tRRH
VIH VIL -
tAA
tOFF
tCAC
DQ
VOH VOL -
tRAC
tCLZ
OPEN
DATA-OUT
Don′t care
Undefined
-8-
Rev. 0.0 (Nov. 1997)
DRAM MODULE
KMM5321200C2W/C2WG
WRITE CYCLE ( EARLY WRITE )
NOTE : DOUT = OPEN
tRAS
RAS
tRC
tRP
VIH VIL -
tCSH
tCRP
CAS
tRCD
tRSH
tCAS
VIH VIL -
tRAD
tASR
A
tCRP
VIH VIL -
tRAH
tASC
ROW
ADDRESS
tRAL
tCAH
COLUMN
ADDRESS
tCWL
tRWL
tWCS
W
tWP
VIL -
tDS
DQ
tWCH
VIH -
VIH VIL -
tDH
DATA-IN
Don′t care
Undefined
-9-
Rev. 0.0 (Nov. 1997)
DRAM MODULE
KMM5321200C2W/C2WG
FAST PAGE READ CYCLE
NOTE : DOUT = OPEN
tRP
tRASP
RAS
VIH -
tRHCP
VIL -
¡ó
tCRP
CAS
tRCD
VIH -
tRAD
tASC
VIL -
VIH VIL -
tCP
tCAS
tCAS
tASR
A
tPC
tCP
tRSH
tCAS
¡ó
tCSH
tRAH
tCAH
ROW
ADDR
tASC
tCAH
COLUMN
ADDRESS
COLUMN
ADDRESS
tASC
¡ó
¡ó
tCAH
COLUMN
ADDRESS
tRRH
tRCS
W
tRCH
tRCS
VIH -
tRCH
VIL -
tCAC
tCAC
tAA
tOFF
tCLZ
tAA
DQ
¡ó
tRCS
VOH VOL -
tRAC
tCLZ
VALID
DATA-OUT
tCAC
tAA
tOFF
tCLZ
VALID
DATA-OUT
tOFF
VALID
DATA-OUT
Don′t care
Undefined
- 10 -
Rev. 0.0 (Nov. 1997)
DRAM MODULE
KMM5321200C2W/C2WG
FAST PAGE WRITE CYCLE ( EARLY WRITE )
NOTE : DOUT = OPEN
tRP
tRASP
RAS
tRHCP
VIH VIL -
¡ó
tPC
tCRP
CAS
tRAD
tASC
VIL -
VIL -
tCSH
tCAH
tRAH
tASC
COLUMN
ADDRESS
ROW
ADDR
VIH -
tWCH
tCAH
tASC
¡ó
COLUMN
ADDRESS
tWCS
¡ó
tWCH
tWP
tCAH
COLUMN
ADDRESS
tWCS
¡ó
tWCH
tWP
tWP
VIL -
tCWL
tDS
DQ
tRSH
tCAS
¡ó
tWCS
W
tCP
tCAS
tCAS
tASR
A
tRCD
VIH -
VIH -
tPC
tCP
VIH VIL -
tDH
tCWL
tDS
tDH
tDS
tCWL
tRWL
tDH
¡ó
VALID
DATA-IN
VALID
DATA-IN
¡ó
VALID
DATA-IN
Don′t care
Undefined
- 11 -
Rev. 0.0 (Nov. 1997)
DRAM MODULE
KMM5321200C2W/C2WG
RAS - ONLY REFRESH CYCLE
NOTE : W, OE, DIN = Don't care
DOUT = OPEN
tRAS
RAS
tRC
tRP
VIH VIL -
tRPC
tCRP
CAS
VIH VIL -
tASR
A
tCRP
VIH VIL -
tRAH
ROW
ADDR
CAS - BEFORE - RAS REFRESH CYCLE
NOTE : OE, A = Don't care
tRC
tRP
RAS
tRAS
tRP
VIH VIL -
tRPC
tCP
CAS
tRPC
tCSR
VIH -
tWRP
W
tCHR
VIL -
tWRH
VIH VIL -
tOFF
DQ
VOH -
OPEN
VOL -
Don′t care
Undefined
- 12 -
Rev. 0.0 (Nov. 1997)
DRAM MODULE
KMM5321200C2W/C2WG
HIDDEN REFRESH CYCLE ( READ )
tRC
tRC
tRP
tRAS
RAS
tRP
VIH VIL -
tCRP
CAS
tRAS
tRCD
tRSH
tCHR
VIH VIL -
tRAD
tASR
A
VIH VIL -
tRAH
tASC
ROW
ADDRESS
tCAH
COLUMN
ADDRESS
tWRH
tRCS
W
tRRH
tWRP
VIH VIL -
tAA
tRAC
DQ
VOH VOL -
tOFF
tCAC
tCLZ
OPEN
DATA-OUT
Don′t care
Undefined
- 13 -
Rev. 0.0 (Nov. 1997)
DRAM MODULE
KMM5321200C2W/C2WG
HIDDEN REFRESH CYCLE ( WRITE )
NOTE : DOUT = OPEN
tRC
RAS
VIH -
tRP
tRCD
tRSH
tCHR
VIH VIL -
tRAD
tASR
A
tRAS
VIL -
tCRP
CAS
tRC
tRP
tRAS
VIH VIL -
tRAH
tASC
ROW
ADDRESS
tCAH
COLUMN
ADDRESS
tWRH
tWRP
W
VIH -
tWCS
tWCH
tWP
VIL -
tDS
DQ
VIH VIL -
tDH
DATA-IN
Don′t care
Undefined
- 14 -
Rev. 0.0 (Nov. 1997)
DRAM MODULE
KMM5321200C2W/C2WG
CAS-BEFORE-RAS REFRESH COUNTER TEST CYCLE
tRP
RAS
CAS
VIH -
tRAS
VIL VIH -
tCPT
tCSR
tRSH
tCAS
tCHR
VIL -
tRAL
tASC
A
VIH VIL -
READ CYCLE
W
DQ
tWRP
tWRH
tRCS
tRRH
tAA
tRCH
tCAC
VIH VIL -
tOFF
tCLZ
VOH -
DATA-OUT
VOL -
WRITE CYCLE
W
tCAH
COLUMN
ADDRESS
tWRP
tRWL
tWRH
tWCS
VIH VIL -
tCWL
tWCH
tWP
tDS
DQ
VIH VIL -
OPEN
tDH
DATA-IN
Don′t care
Undefined
NOTE : This timing diagram is applied to all devices besides 16M DRAM 4th & 64M DRAM.
- 15 -
Rev. 0.0 (Nov. 1997)
DRAM MODULE
KMM5321200C2W/C2WG
CAS - BEFORE - RAS SELF REFRESH CYCLE
NOTE : OE, A = Don′t care
tRP
RAS
tRASS
tRPS
VIH VIL -
tRPC
tRPC
tCP
CAS
tCHS
VIH -
tCSR
VIL -
tOFF
DQ
VOH -
OPEN
VOL -
tWRP
W
tWRH
VIH VIL -
TEST MODE IN CYCLE
NOTE : OE, A = Don′t care
tRC
tRP
RAS
tRAS
tRP
VIH VIL -
tRPC
tCP
CAS
tRPC
VIH -
tCSR
tWTS
W
tCHR
VIL -
tWTH
VIH VIL -
tOFF
DQ
VOH -
OPEN
VOL -
Don′t care
Undefined
- 16 -
Rev. 0.0 (Nov. 1997)
DRAM MODULE
KMM5321200C2W/C2WG
PACKAGE DIMENSIONS
Units : Inches (millimeters)
4.250(107.95)
3.984(101.19)
.133(3.38)
.125 DIA±.002(3.18±.051)
R.062(1.57)
.400(10.16)
.750(19.05)
.250(6.35)
.080(2.03)
R.062±.004(R1.57±.10)
.250(6.35)
.125(3.17)
.250(6.35)
MIN
3.750(95.25)
( Front view )
( Back view )
Gold & Solder Plating Lead
.200(5.08)
MAX
.100(2.54)
.010(.25)MAX
MIN
.050(1.27)
.041±.004(1.04±.10)
.054(1.37)
.047(1.19)
Tolerances : ±.005(.13) unless otherwise specified
NOTE : The used device is 1Mx16 DRAM
DRAM Part No. : KMM5321200C2W/C2WG -- KM416C1200CJ (400 mil)
Revision History
Rev 0.0 : Nov. 1997
- 17 -
Rev. 0.0 (Nov. 1997)