M374F320(8)0DJ1-C DRAM MODULE M374F320(8)0DJ1-C EDO Mode without buffer 32M x 72 DRAM DIMM with ECC Using 16Mx4, 4K & 8K Refresh, 3.3V GENERAL DESCRIPTION FEATURES The Samsung M374F320(8)0DJ1-C is a 32Mx72bits Dynamic RAM high density memory module. The Samsung M374F320(8)0DJ1-C consists of thirty-six CMOS 16Mx4bits DRAMs in SOJ 400mil packages and one 1K/2K EEPROM for SPD in 8-pin SOP package mounted on a 168-pin glassepoxy substrate. A 0.1 or 0.22uF decoupling capacitor is mounted on the printed circuit board for each DRAM. The M374F320(8)0DJ1-C is a Dual In-line Memory Module and is intended for mounting into 168 pin edge connector sockets. • Part Identification • • • • • • • • PERFORMANCE RANGE Speed tRAC tCAC tRC tHPC -C50 50ns 13ns 84ns 20ns -C60 60ns 15ns 104ns 25ns Part number PK Re M374F3200DJ1-C SOJ 4K M374F3280DJ1-C SOJ 8K ROR ref. 4K/64ms 4K/64ms 8K/64ms New JEDEC standard proposal without buffer Serial Presence Detect with EEPROM Extended Data Out Mode Operation CAS-before-RAS Refresh capability RAS-only and Hidden refresh capability LVTTL compatible inputs and outputs Single +3.3V±0.3V power supply PCB : Height(1625mil), double sided component PIN CONFIGURATIONS PIN NAMES Pin Front Pin Front Pin Front Pin Back Pin Back Pin Back 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 VSS DQ0 DQ1 DQ2 DQ3 VCC DQ4 DQ5 DQ6 DQ7 DQ8 VSS DQ9 DQ10 DQ11 DQ12 DQ13 VCC DQ14 DQ15 CB0 CB1 VSS NC NC VCC W0 CAS0 CAS1 RAS0 OE0 VSS A0 A2 A4 A6 A8 A10 A12 VCC VCC DU VSS OE2 RAS2 CAS2 CAS3 W2 VCC NC NC CB2 CB3 VSS DQ16 DQ17 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 VSS DQ32 DQ33 DQ34 DQ35 VCC DQ36 DQ37 DQ38 DQ39 DQ40 VSS DQ41 DQ42 DQ43 DQ44 DQ45 VCC DQ46 DQ47 CB4 CB5 VSS NC NC VCC DU CAS4 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 CAS5 RAS1 DU VSS A1 A3 A5 A7 A9 A11 *A13 VCC DU DU VSS DU RAS3 CAS6 CAS7 DU VCC NC NC CB6 CB7 VSS DQ48 DQ49 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 CBR ref. DQ18 DQ19 VCC DQ20 NC DU NC VSS DQ21 DQ22 DQ23 VSS DQ24 DQ25 DQ26 DQ27 VCC DQ28 DQ29 DQ30 DQ31 VSS NC NC NC SDA SCL VCC DQ50 DQ51 VCC DQ52 NC DU NC VSS DQ53 DQ54 DQ55 VSS DQ56 DQ57 DQ58 DQ59 VCC DQ60 DQ61 DQ62 DQ63 VSS NC NC SA0 SA1 SA2 VCC Pin Name Function A0 - A11 Address Input(4K ref.) A0 - A12 Address Input(8K ref.) DQ0 - DQ63 Data In/Out W0, W2 Read/Write Enable OE0, OE2 Output Enable RAS0 - RAS3 Row Address Strobe CAS0 - CAS7 Column Address Strobe VCC Power(+3.3V) VSS Ground NC No Connection DU Don′t use SDA Serial Address /Data I/O SCL Serial Clock SA0 -SA2 Address in EEPROM CB0 - CB7 Check Bit * These pins are not used in this module. NOTE : A12 is used for only M374F3280DJ1-C (8K ref.) REV. 0.1 Oct. 2000 M374F320(8)0DJ1-C DRAM MODULE FUNCTIONAL BLOCK DIAGRAM RAS0 W0 OE0 A0-A11(A12) CAS0 U0 U1 DQ0 DQ1 DQ2 DQ3 DQ0 DQ1 DQ2 DQ3 U18 U9 DQ0 DQ1 DQ2 DQ3 U10 DQ0 DQ1 DQ2 DQ3 U2 DQ0 DQ1 DQ2 DQ3 U3 DQ0 DQ1 DQ2 DQ3 U4 DQ0 DQ1 DQ2 DQ3 U5 DQ0 DQ1 DQ2 DQ3 U6 DQ0 DQ1 DQ2 DQ3 U7 DQ0 DQ1 DQ2 DQ3 U8 DQ0 DQ1 DQ2 DQ3 DQ0 DQ1 DQ2 DQ3 DQ8~11 DQ12~15 DQ0 DQ1 DQ2 DQ3 DQ0 DQ1 DQ2 DQ3 U19 U20 U21 U11 DQ0 DQ1 DQ2 DQ3 U12 DQ0 DQ1 DQ2 DQ3 U13 DQ0 DQ1 DQ2 DQ3 CAS3 DQ0 DQ1 DQ2 DQ3 DQ16~19 DQ20~23 DQ0 DQ1 DQ2 DQ3 DQ0 DQ1 DQ2 DQ3 U22 U14 DQ0 DQ1 DQ2 DQ3 U23 U15 DQ0 DQ1 DQ2 DQ3 U24 U16 DQ0 DQ1 DQ2 DQ3 U17 DQ0 DQ1 DQ2 DQ3 DQ24~27 DQ0 DQ1 DQ2 DQ3 DQ28~31 DQ0 DQ1 DQ2 DQ3 U25 U26 NOTE : A12 is used for only M374F3280DJ1 (8K ref.) VCC DQ0 DQ1 DQ2 DQ3 U28 DQ40~43 DQ44~45 CAS5 DQ0 DQ1 DQ2 DQ3 U29 DQ0 DQ1 DQ2 DQ3 U30 DQ0 DQ1 DQ2 DQ3 U31 DQ46~51 DQ52~55 DQ56~59 DQ60~63 CAS6 DQ0 DQ1 DQ2 DQ3 U32 DQ0 DQ1 DQ2 DQ3 U33 CAS7 DQ0 DQ1 DQ2 DQ3 U34 DQ0 DQ1 DQ2 DQ3 U35 Serial PD SCL 0.1 or 0.22uF Capacitor under each DRAM Vss U27 CB4~7 CB0~3 CAS2 DQ0 DQ1 DQ2 DQ3 DQ36~39 DQ4~7 CAS1 CAS4 DQ32~35 DQ0~3 DQ0 DQ1 DQ2 DQ3 RAS3 W2 OE2 RAS2 RAS1 A0 A1 A2 SDA To all DRAMs SA0 SA1 SA2 REV. 0.1 Oct. 2000 M374F320(8)0DJ1-C DRAM MODULE ABSOLUTE MAXIMUM RATINGS * Item Voltage on any pin relative VSS Voltage on VCC supply relative to VSS Storage Temperature Power Dissipation Short Circuit Output Current Symbol Rating Unit VIN, VOUT VCC Tstg Pd IOS -0.5 to +4.6 -0.5 to +4.6 -55 to +150 36 50 V V °C W mA * Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for intended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS (Voltage referenced to VSS, TA = 0 to 70°C) Item Supply Voltage Ground Input High Voltage Input Low Voltage Symbol Min VCC VSS VIH VIL 3.0 0 2.0 -0.3*2 Typ Max Unit 3.3 0 - 3.6 0 V V V V VCC+0.3*1 0.8 *1 : VCC+1.3V at pulse width≤15ns which is measured at VCC. *2 : -1.3V at pulse width≤15ns which is measured at VSS. DC AND OPERATING CHARACTERISTICS (Recommended operating conditions unless otherwise noted) Symbol Speed ICC1 M374F3280DJ1 M374F3200DJ1 Unit Min Max Min Max -50 -60 - 1458 1278 - 1998 1818 mA mA ICC2 Don′t care - 36 - 36 mA ICC3 -50 -60 - 1458 1278 - 1998 1818 mA mA ICC4 -50 -60 - 1638 1458 - 1638 1458 mA mA ICC5 Don′t care - 18 - 18 mA ICC6 -50 -60 - 1998 1818 - 1998 1818 mA mA II(L) IO(L) Don′t care -10 -10 10 10 -10 -10 10 10 uA uA VOH VOL Don′t care 2.4 - 0.4 2.4 - 0.4 V V ICC1 : Operating Current * (RAS, CAS, Address cycling @ tRC=min) ICC2 : Standby Current (RAS=CAS=W=V IH) ICC3 : RAS Only Refresh Current * (CAS=VIH, RAS cycling @tRC=min) ICC4 : Extended Data Out Mode Current * (RAS=VIL, CAS cycling : tHPC=min) ICC5 : Standby Current (RAS=CAS=W=V CC-0.2V) ICC6 : CAS-Before-RAS Refresh Current * (RAS and CAS cycling @tRC=min) I(IL) : Input Leakage Current (Any input 0≤VIN≤VCC+0.3V, all other pins not under test=0 V) I(OL) : Output Leakage Current(Data Out is disabled, 0V≤VOUT≤VCC) VOH : Output High Voltage Level (IOH = -2mA) VOL : Output Low Voltage Level (IOL = 2mA) * NOTE : ICC1, ICC3, ICC4 and ICC6 are dependent on output loading and cycle rates. Specified values are obtained with the output open. ICC is specified as an average current. In ICC1 and ICC3, address can be changed maximum once while RAS=VIL. In I CC4, address can be changed maximum once within one EDO mode cycle time, tHPC. REV. 0.1 Oct. 2000 M374F320(8)0DJ1-C DRAM MODULE CAPACITANCE (TA = 25°C, VCC=3.3V, f = 1MHz) Item Symbol Input capacitance[A0-A12] Input capacitance[W0, W2, OE0, OE2] Input capacitance[RAS0 - RAS3] Input capacitance[CAS0 - CAS7] Input/Output capacitance[DQ0-DQ63, CB0-CB7] CIN1 CIN2 CIN3 CIN4 CDQ Min - Max Unit 190 136 73 52 27 pF pF pF pF pF AC CHARACTERISTICS (0°C≤TA≤70°C, VCC=3.3V±0.3V. See notes 1,2.) Test condition : Vih/Vil=2.2/0.7V, Voh/Vol=2.0/0.8V, output loading CL=100pF Parameter Random read or write cycle time Read-modify-write cycle time Access time from RAS Access time from CAS Access time from column address CAS to output in Low-Z OE to output in Low-Z Output buffer turn-off delay from CAS Transition time(rise and fall) RAS precharge time RAS pulse width RAS hold time CAS hold time CAS pulse width RAS to CAS delay time RAS to column address delay time CAS to RAS precharge time Row address set-up time Row address hold time Column address set-up time Column address hold time Column address to RAS lead time Read command set-up time Read command hold referenced to CAS Read command hold referenced to RAS Write command hold time Write command pulse width Write command to RAS lead time Write command to CAS lead time Data set-up time Data hold time Refresh period (4K & 8K Ref.) Write command set-up time CAS to W delay time RAS to W delay time Symbol tRC tRWC tRAC tCAC tAA tCLZ tOLZ tCEZ tT tRP tRAS tRSH tCSH tCAS tRCD tRAD tCRP tASR tRAH tASC tCAH tRAL tRCS tRCH tRRH tWCH tWP tRWL tCWL tDS tDH tREF tWCS tCWD tRWD -50 Min -60 Max 84 Min Max 104 128 Unit Note ns 153 ns 50 60 ns 3,4,9 13 15 ns 3,4,5 30 ns 3,9 3 25 3 ns 3 3 3 ns 3 3 13 3 13 ns 6,10 1 50 1 50 ns 2 30 50 40 10K 8 60 ns 10K 10 38 ns ns 40 ns 8 10K 10 10K ns 17 37 20 45 ns 4 12 25 15 30 ns 9 5 5 ns 0 0 ns 7 10 ns 0 0 ns 7 10 ns 25 30 ns 0 0 ns 0 0 ns 8 0 0 ns 8 7 10 ns 7 10 ns 8 10 ns 7 10 ns 0 0 ns 7 10 ns 64 64 ms 0 0 ns 7 33 38 ns 7 70 84 ns 7 REV. 0.1 Oct. 2000 M374F320(8)0DJ1-C DRAM MODULE AC CHARACTERISTICS (0°C≤TA≤70°C, VCC=3.3V±0.3V. See notes 1,2.) Test condition : Vih/Vil=2.2/0.7V, Voh/Vol=2.0/0.8V, output loading CL=100pF Parameter Column address to W delay time CAS precharge to W delay time CAS setup time (CAS-before-RAS refresh) CAS hold time (CAS-before-RAS refresh) RAS to CAS precharge time Access time from CAS precharge Hyper page mode cycle time Hyper page mode read-modify write cycle time CAS precharge time (Hyper page cycle) RAS pulse width (Hyper page cycle) RAS hold time from CAS precharge OE access time OE to data delay Output buffer turn off delay time from OE OE command hold time Output data hold time Output buffer turn off delay from RAS Output buffer turn off delay from W W to data delay OE to CAS hold time CAS hold time to OE OE precharge time W pulse width (Hyper page cycle) Symbol tAWD tCPWD tCSR tCHR tRPC tCPA tHPC tHPRWC tCP tRASP tRHCP tOEA tOED tOEZ tOEH tDOH tREZ tWEZ tWED tOCH tCHO tOEP tWPE -50 Min -60 Max Min Max Unit Note 7 45 53 ns 47 58 ns 5 5 ns 10 10 ns 5 5 ns 28 35 ns 3 20 25 ns 11 67 73 ns 11 7 50 10 200K 30 60 35 13 10 3 ns 200K ns 15 ns 13 ns 13 13 3 5 5 5 5 3 13 3 13 ns ns 6 ns ns 3 13 ns 6,10 3 13 ns 6 15 15 ns 5 5 ns 5 5 ns 5 5 ns 5 5 ns REV. 0.1 Oct. 2000 M374F320(8)0DJ1-C DRAM MODULE NOTES 1. An initial pause of 200us is required after power-up followed by any 8 RAS-only or CAS-before-RAS refresh cycles before proper device operation is achieved. 2. Input voltage levels are Vih/Vil. VIH(min) and VIL(max) are reference levels for measuring timing of input signals. Transition times are measured between VIH(min) and V IL(max) and are assumed to be 5ns for all inputs. 3. Measured with a load equivalent to 1 TTL loads and 100pF. 4. Operation within the tRCD(max) limit insures that tRAC(max) can be met. tRCD(max) is specified as a reference point only. If tRCD is greater than the specified tRCD(max) limit, then access time is controlled exclusively by tCAC. 8. Either tRCH or tRRH must be satisfied for a read cycle. 9. Operation within the tRAD(max) limit insures that tRAC (max) can be met. tRAD(max) is specified as a reference point only. If tRAD is greater than the specified tRAD(max) limit, then access time is controlled exclusively by tAA. 10. If RAS goes to high before CAS high going, the open circuit condtion of the output is achieved by CAS high going. If CAS goes to high before RAS high going, the open circuit condtion of the output is achieved by RAS high going. 11. tASC≥6ns. 5. Assumes that tRCD ≥tRCD(max). 6. This parameter defines the time at which the output achieves the open circuit condition and is not referenced to VOH or VOL. 7. tWCS, tRWD, tCWD and tAWD are non-restrictive operating parameter. They are inclueded in the data sheet as electrical characteristics only. If tWCS≥tWCS(min), the cycle is an early write cycle and the data out pin will remain high impedance for the duration of the cycle. If tCWD≥tCWD(min), tRWD≥tRWD(min) and tAWD≥tAWD(min), then the cycle is a read-write cycle and the data output will contain the data read from the selected address. If neither of the above contitions are satisfied, The condition of the data out is indeternimated. REV. 0.1 Oct. 2000 M374F320(8)0DJ1-C DRAM MODULE READ CYCLE tRC tRAS RAS VIL - tCSH tCRP CAS tRP VIH - tRCD tCRP tRSH VIH - tCAS VIL - tRAD tASR A VIH VIL - tRAH tRAL tASC tCAH ROW ADDRESS COLUMN ADDRESS tRCH tRCS W tRRH VIH VIL - tWEZ tCEZ tAA OE VIH - tOEZ tOEA VIL - tOLZ tCAC DQ VOH VOL - tRAC OPEN tCLZ tREZ DATA-OUT Don′t care Undefined REV. 0.1 Oct. 2000 M374F320(8)0DJ1-C DRAM MODULE WRITE CYCLE ( EARLY WRITE ) NOTE : DOUT = OPEN tRC tRAS RAS tRP VIH VIL - tCSH tCRP CAS tRSH VIH - VIH VIL - tCRP tCAS VIL - tRAD tASR A tRCD tRAH tASC tRAL tCAH COLUMN ADDRESS ROW ADDRESS tCWL tRWL tWCS W OE VIH VIL - VIH VIL - tDS DQ tWCH tWP VIH VIL - tDH DATA-IN Don′t care Undefined REV. 0.1 Oct. 2000 M374F320(8)0DJ1-C DRAM MODULE WRITE CYCLE ( OE CONTROLLED WRITE ) NOTE : DOUT = OPEN tRC tRAS RAS VIL - tCSH tCRP CAS tRP VIH - tRCD tRSH tCAS VIH - tCRP VIL - tRAD tRAL tASR A VIH VIL - tRAH tASC tCAH ROW ADDRESS COLUMN ADDRESS tCWL tRWL W OE tWP VIH VIL - VIH VIL - tOED tDS DQ VIH - tOEH tDH DATA-IN VIL - Don′t care Undefined REV. 0.1 Oct. 2000 M374F320(8)0DJ1-C DRAM MODULE READ - MODIFY - WRITE CYCLE tRAS RAS tRWC VIL - tCRP tRCD tRSH VIH - CAS tRP VIH - tCAS VIL - tRAD tASR tRAH tASC tCAH tCSH A VIH VIL - ROW ADDR COLUMN ADDRESS tAWD tRWL tCWD W tCWL VIH - tWP VIL - tRWD OE tOEA VIH VIL - tOLZ tCLZ tCAC tAA DQ VI/OH VI/OL - tOED tOEZ tRAC VALID DATA-OUT tDS tDH VALID DATA-IN Don′t care Undefined REV. 0.1 Oct. 2000 M374F320(8)0DJ1-C DRAM MODULE HYPER PAGE READ CYCLE tRP tRASP RAS VIH VIL - ¡ó tCSH tCRP CAS VIL - tHPC tCP tCAS VIH - tHPC tCP tCAS tCP tCAS tCAS tRAD tASR A tRCD VIL - VIH - tRHCP tHPC tRAH tASC ROW ADDR tCAH tASC tCAH COLUMN ADDRESS COLUMN ADDRESS tASC tCAH COLUMN ADDR tASC tCAH tREZ COLUMN ADDRESS tRRH tRCS W tRCH VIH - tCPA VIL - tCAC tAA tCPA tCAC tAA OE VIH - tAA tCPA tOCH tOEA tAA tCHO tOEP tOEA VIL - tOEP tCAC tDOH tRAC DQ tCAC tCAC VOH VOL - VALID DATA-OUT tOLZ tCLZ tOEZ tOEA tOEZ tOEZ VALID DATA-OUT VALID DATA-OUT VALID DATA-OUT Don′t care Undefined REV. 0.1 Oct. 2000 M374F320(8)0DJ1-C DRAM MODULE HYPER PAGE WRITE CYCLE ( EARLY WRITE ) NOTE : DOUT = OPEN tRP tRASP RAS VIH - tRHCP VIL - ¡ó tHPC tCRP CAS tRCD tHPC tCP VIH - tCAS VIL - tRSH tCP tCAS tCAS tRAD ¡ó tCSH tASR A VIH VIL - tRAH ROW ADDR. tASC tCAH COLUMN ADDRESS tWCS W VIH - tASC tWCH COLUMN ADDRESS tWCS tWP ¡ó tCAH COLUMN ADDRESS tWCS ¡ó tWCH tWP VIL - tCWL tCWL tRWL VIH - ¡ó VIL - ¡ó tDS DQ tASC ¡ó tWCH tWP tCWL OE tCAH VIH VIL - tDH tDS tDH tDS tDH ¡ó VALID DATA-IN VALID DATA-IN ¡ó VALID DATA-IN Don′t care Undefined REV. 0.1 Oct. 2000 M374F320(8)0DJ1-C DRAM MODULE HYPER PAGE READ-MODIFY-WRITE CYCLE RAS tCSH tHPRWC tRCD tCAS VIL - VIH VIL - tCAS tRAD tRAH ROW ADDR tCAH tASC tCAH tASC COL. ADDR tRWL tCWL tCWL VIH - tWP VIL - tWP tCWD tCWD tAWD tRWD OE tRAL COL. ADDR tRCS W tCRP tCP VIH - tASR A tRSH VIL - tCRP CAS tRP tRASP VIH - VIH - tAWD tCPWD tOEA tOEA VIL - tOED tOED tCAC tAA tDH tOEZ tCAC tAA tDS tDH tOEZ tDS tRAC DQ VI/OH VI/OL - tCLZ tCLZ tOLZ VALID DATA-OUT VALID DATA-IN tOLZ VALID DATA-OUT VALID DATA-IN Don′t care Undefined REV. 0.1 Oct. 2000 M374F320(8)0DJ1-C DRAM MODULE HYPER PAGE READ AND WRITE MIXED CYCLE tRP tRASP RAS VIH - READ(tCAC) READ(tCPA ) tHPC tHPC tCP tCP CAS VIH VIL - VIH VIL - tCAS tRAD tASR A tRAH tASC ROW ADDR tCAH COLUMN ADDRESS tRCS W READ(tAA) WRITE VIL - tCAS tRCS tCAH tASC COLUMN ADDRESS tRCH tCAS tCAS tCAH tASC tHPC tCP COL. ADDR tRCH tASC tCAH COL. ADDR tWCH tRCH tWCS VIH VIL - tWPE tCLZ tWED tCPA OE VIH VIL - tOEA tCAC tAA DQ VI/OH VI/OL - tWEZ tDH tWEZ tDS VALID VALID DATA-IN tREZ tAA tRAC VALID DATA-OUT DATA-OUT VALID DATA-OUT Don′t care Undefined REV. 0.1 Oct. 2000 M374F320(8)0DJ1-C DRAM MODULE RAS - ONLY REFRESH CYCLE* NOTE : W, OE, DIN = Don′t care DOUT = OPEN tRC RAS VIH - tRP tRAS VIL - tRPC tCRP CAS VIH VIL - tASR A tCRP VIH VIL - tRAH ROW ADDR CAS - BEFORE - RAS REFRESH CYCLE NOTE : OE , A = Don′t care tRC tRP RAS VIH VIL - tRPC tCP CAS tRAS VIH - tRPC tCSR tCHR VIL - tWRP W tRP tWRH VIH VIL - tCEZ DQ VOH VOL - OPEN Don′t care Undefined * In RAS-only refresh cycle of 64Mb A-die & B-die, when CAS signal transits from Low to High, the valid data may be cut off. REV. 0.1 Oct. 2000 M374F320(8)0DJ1-C DRAM MODULE HIDDEN REFRESH CYCLE ( READ ) tRC RAS tRAS VIH - tRP tRAS VIL - tCRP CAS tRC tRP tRCD tRSH tCHR VIH VIL - tRAD tASR A VIH VIL - tRAH tASC tCAH COLUMN ADDRESS ROW ADDRESS tRCS W tRRH tWRH tWRP VIH VIL - tAA OE VIH - tOEA VIL - tCEZ tOLZ tCAC tCLZ tRAC DQ VOH VOL - OPEN tREZ tWEZ tOEZ DATA-OUT Don′t care Undefined REV. 0.1 Oct. 2000 M374F320(8)0DJ1-C DRAM MODULE HIDDEN REFRESH CYCLE ( WRITE ) NOTE : DOUT = OPEN tRC RAS tRAS VIH - tRP tRAS VIL - tCRP CAS tRC tRP tRCD tRSH tCHR VIH VIL - tRAD tASR A VIH VIL - tRAH tASC ROW ADDRESS tCAH COLUMN ADDRESS tWRP tWCS W OE VIH - tWCH tWP VIL - VIH VIL - tDS DQ tWRH VIH VIL - tDH DATA-IN Don′t care Undefined REV. 0.1 Oct. 2000 M374F320(8)0DJ1-C DRAM MODULE CAS-BEFORE-RAS REFRESH COUNTER TEST CYCLE tRP RAS CAS VIH - tRAS VIL VIH - tCPT tCSR tRSH tCAS tCHR VIL - tRAL tASC A VIH - W OE COLUMN ADDRESS VIL - READ CYCLE tWRP tWRH tRRH tAA tRCS tRCH tCAC VIH VIL VIH VIL - tOEA tCLZ VOH - DQ tCAH tOEZ W tWEZ DATA-OUT VOL - WRITE CYCLE tCEZ tREZ tWRP tRWL tWRH VIH - tCWL tWCS tWCH VIL - tWP OE VIH VIL - tDS DQ tDH VIH DATA-IN VIL - READ-MODIFY-WRITE tWRP W tWRH tAWD tRCS tCWL tCWD VIH - tRWL tWP tCAC VIL - tAA tOEA OE VIH - tOED VIL - tCLZ DQ tOEZ tDH tDS VI/OH VI/OL VALID DATA-OUT VALID DATA-IN NOTE : This timing diagram is applied to all devices besides 64M DRAM based modules. Don′t care Undefined REV. 0.1 Oct. 2000 M374F320(8)0DJ1-C DRAM MODULE CAS - BEFORE - RAS SELF REFRESH CYCLE NOTE : OE, A = Don′t care tRP RAS VIL - tRPS tRPC tRPC tCP CAS tRASS VIH - VIH - tCHS tCSR VIL - tCEZ DQ W VOH - OPEN VOL - VIH VIL - tWRP tWRH TEST MODE IN CYCLE NOTE : OE , A = Don′t care tRC tRP RAS tRP tRAS VIH VIL - tRPC tRPC tCP CAS tCSR VIH - tWTS W tCHR VIL - tWTH VIH VIL - tCEZ DQ VOH VOL - OPEN Don′t care Undefined REV. 0.1 Oct. 2000 M374F320(8)0DJ1-C DRAM MODULE PACKAGE DIMENSIONS 0.95 (24.13) 0.118 (3.000) 5.014 (127.350) 0.054 (1.372) R 0.079 (R 2.000) 0.700 B A 0.250 (6.350) 0.350 (8.890) .450 (11.430) C 0.100Min (2.540Min) .118DIA±.004 (3.000DIA±.100) 0.250 (6.350) 1.450 (36.830) (17.780) 0.157±0.004 (4.000±0.100) R 0.055(1.40) 0.118 0.118 (3.000) (3.000) 1.625 (41.28) 0.95 (24.13) Units : Inches (millimeters) 6.000 (152.400) 5.250 (133.350) 2.150 (54.61) 4.550 (115.57) ( Front view ) 0.350Max (8.89Max) 0.050±0.0039 (1.270±0.10) 0.100 Min 0.250 (6.350) 0.250 (6.350) 0.1230±.0050 (3.125±.125) 0.039 ±.002 (1.000±.050) 0.1230±.0050 (3.125±.125) 0.079±.0040 (2.000±.100) Detail A (2.540 Min) ( Back view ) 0.079±.0040 (2.000±.100) Detail B 0.008±.0.006 (0.200±.0.150) 0.050 (1.270) Detail C Tolerances : ±.005(.13) unless otherwise specified The used device is 16Mx4 DRAM with EDO mode, SOJ DRAM Part No. : M374F3280DJ1-K4E660412D-J M374F3200DJ1-K4E640412D-J REV. 0.1 Oct. 2000