1 CHIP CLP SUBSYSTEM IC S1T8527C INTRODUCTION 48−QFP−1010E S1T8527C is a monolithic circuit which can be used in high performance 60MHz MCA type CLP System. The S1T8527C is a subsystem IC for FM / FSK receiving systems and a complete one chip FM / FSK receiver IC for 60MHz system. It’s feature includes receiving functions for FM / FSK systems, a compander to remove external noise, and PLL ( Phase Lock Loop ) of channel selection which blocks surrounding frequency interference. The S1T8527C can be used with a wide range of FM / FSK VHF bandwidth systems, including cordless phone, and the narrow band voice and data sending / receiving systems. To make applications easily and simply, peripheral parts are minimized. FEATURES • Operating voltage range: 2.0V — 5.5V • Typical supply current: 13.5mA at 3.6V • Built−in low battery detection function ( selectable 3.45V, 3.3V, 3.0V, 2.2V, 2.1V ) • Built−in speaker amplifier • Built−in splatter filter • Built−in dual conversion receiver, compander and universal PLL • FM Receiver — Complete dual conversion circuit — Excellent input sensitivity (0.7µVrms at 12dB SINAD) • Compader — Easy gain control to use external component — Included ALC (Automatic Level Control) circuit — Included Mute logic • Universal PLL — RX (TX) divided counter range: 1/16 — 1/16383 — Reference frequency divided counter range: 1/16 — 1/4095 — Lock detector signal output — Serial interface with MCU for controlling each block ORDERING INFORMATION Device Package Operating Temperature S1T8527C01-Q0R0 48−QFP−1010E −20°C — + 70°C 1 S1T8527C 1 CHIP CLP SUBSYSTEM IC 2LOI 2LOI 2MO VCC(RX) LI LD GND(RX) QCI RAO DSCI DSCO MDO BLOCK DIAGRAM 36 35 34 33 32 31 30 29 28 27 26 25 X-tal OSC FSK COMP Limiting IF AMP Regulator (1V) 24 VREF (COMP) VREF 2MI 37 2nd MIX IF AMP (455KHz) 1MO 38 1LOI 39 1LOI 40 RX VCO PRI Meter Driver Quad Detector + Rectifier Carrier Detector RX 1st MIX IF AMP (10.7MHz) SUM AMP Low Battery Detector 1MI 42 1MI 43 GND (PLL) Gain Cell SPK AMP Buffer Limiter + SUM AMP PRI Programmable Counter ( RX ) - 47 Programmable Counter ( REF ) 2 Rectifier Splatter Filter TX Phase Detector Compandor mute 1 2 3 4 5 6 7 8 9 10 11 12 CLK DATA EN LBD AGIC CRC CONTROL GND(PLL) fMCU CDO/LDT RX Phase Detector 4_25 CNT SFO TIF 48 SFI (PLL) ALC CO VCC 46 Programmable Counter ( TX ) PDT (PLL) 19 SAI 17 SAO2 16 VCC (COMP) 15 GND (COMP) 14 CPI+ Gain Cell VREF EPI 18 SAO1 44 PDR 45 22 20 EO SPK AMP Regulator ( 2.15 V ) ALC 21 ERC AMP VCO 41 23 13 CPI - 1 CHIP CLP SUBSYSTEM IC S1T8527C 2LOI 2LOI 2MO VCC(RX) LI LD GND(RX) QCI RAO DSCI DSCO MDO PIN CONFIGURATION 36 35 34 33 32 31 30 29 28 27 26 25 2MI 37 24 VREF(COMP) 1MO 38 23 ALC 1LOI 39 22 EPI 1LOI 40 21 ERC VCORX 41 20 EO 1MI 42 19 SAI S1T8527C KB8527B 1MI 43 18 SAO1 GND(PLL) 44 17 SAO2 PDR 45 16 VCC(COMP) VREF(PLL) 46 15 GND (COMP) 1 2 3 4 5 6 7 8 9 10 11 12 SFO CDO/LDT GND(PLL) CLK DATA EN LBD AGIC CRC 13 CPI - SFI TIF 48 CO 14 CPI+ PDT VCC(PLL) 47 3 S1T8527C 1 CHIP CLP SUBSYSTEM IC PIN DESCRIPTION Pin No Symbol Description 1 PDT3 2 CO Compressor output terminal of compander; connected to the splatter filter amp input terminal. 3 SFI Input terminal of Splatter filter amp. 4 SFO3 5 LDT/CDO Phase detector output terminal of the transmitter at PLL. If fTX > fREF or fTX is leading → the output is negative pulse If fTX < fREF or fTX is lagging → the output is positive Pulse if fTX = fREF and the same phase → the output is High Impedance Output terminal of Splatter filter amp. LDT: Output terminal of transmitter lock detector in PLL block. The output is low if PLL is in lock state and the output is high if PLL is in unlock state. CDO: As an output terminal of the carrier detector buffer, connected to (RSSI ) terminal of MCU. This pin outputs the contents of Meter Driver buffer which is turned on / off, according to the signal level detected by Meter Driver. 4 6 GNDPLL Ground. Ground of logic section at PLL. 7 8 9 CLK DATA EN These pins are serial interface terminals for programming reference counter, auxiliary reference counter, TX channel counter, RX channel counter and control block that controls internal each block with test mode and power saving mode. 10 LBD Low Battery Detecting output. ( Selectable 3.45V, 3.3V, 3.0V, 2.2V, 2.0V ). During the normal operation, output level is low, but it is high at low battery detection. As this pin is an open collector type, it requires a pull - up resistor. 11 AGIC This pin bypasses AC elements at the feedback loop which come from the SUM amp block of COMPRESSOR. A capacitor should be connected between this terminal and GND. ( C = 2.2uF ) 12 CRC Converts waveform from the full wave rectifier to DC element at the rectifier block of Compressor. ( RC = 33msec ) 13 CPI - Pre-amp inverting input terminal of Compressor. Adjusts the negative feedback loop gain. ( in application, gain is 5 ) 14 CPI + Pre-amp non-inverting input terminal of Compressor. Used as an input terminal for voice signals. 15 GND(COMP) Ground of Compander block. 16 Vcc(COMP) Supply voltage. Power supply terminal of Compander. 17 SAO 2 Output terminal of speaker amp 2. This signal is the same as SAO1 output, but phase difference is180° for SAO1. DC voltage level is ( Vcc — 0.7V ) / 2. 1 CHIP CLP SUBSYSTEM IC S1T8527C PIN DESCRIPTION (Continued) Pin No Symbol 18 SAO 1 19 SAI Speaker Amp 1 input terminal. Between this terminal and Expander output terminal, uses a AC coupled. 20 EO Output terminal of Expander, from which a regenerated voice signals are emitted. 21 ERC Converts waveform from the full wave rectifier to DC element at the rectifier block of Expander. ( RC = 33 msec ) 22 EPI − Pre-amp inverting input terminal of Expander. Adjusts the negative feedback loop gain. ( in application, gain is 5 ). 23 ALC Reference current input terminal of Automatic Level Control ( ALC); Adjusts THD of compressor output voltage to less than 3% or limits the frequency deviation of TX if the input is higher than a certain level. The ALC circuit may be turned off depending on the ALC reference current or the magnitude of output voltage may be limited if it is higher than a certain level. 24 Description Output terminal of Speaker amp 1. DC voltage level is ( Vcc — 0.7V ) / 2. VREF(COMP) Reference voltage ( VREF= 1V ). Supplies a regulator voltage to the Compressor and Expander of COMPANDER. 25 MDO Output terminal of the Meter Driver. Amplitude of RF input signal for useful frequency is detected by Meter Driver circuit. The Meter Driver circuit has perfect linear characteristic of 60dB range for input signal level. ( 0.1µA / dB ). 26 DSCO Output terminal of Data Slicing comparator. Separates Frequency Shift Keying ( FSK ) serial data and executes data shaping and limiting. 27 DSCI Input terminal of Data slicing comparator. Non-inverting type with the negative input terminal biased to 1/2 Vcc. 28 RAO Recovered Audio Output terminal. Voice signals detected by the Quadrature Detector are amplified and then output through this terminal. 29 QCI3 Quadrature coil input terminal. The 455kHz oscillator circuit is an Lp = 680uH, Cp = 180pF valued LC tank circuit. Voice signals are detected by mixture of 455kHz ( by phase difference ) which is converted from mixer 2. 30 GNDRX 31 32 LD LI Ground . Ground for Receiver. Limiter input and decoupling terminal. Removes amplitude modulation elements caused by fading or FM signal noise. Limiting IF amplifies and limits the second intermediate frequency, 455kHz.The input impedance of the limiting IF amplifier is set to 1.5kΩ. While FM waves are transmitted with constant magnitude, their magnitudes are slightly modulated due to reflection from obstacles, fading phenomenon, noise wave, and mixing with AM wave elements before entering the receiver’s antenna.The limiter makes amplitude uniform by removing these AM wave elements. 5 S1T8527C 1 CHIP CLP SUBSYSTEM IC PIN DESCRIPTION (Continued) Pin No Symbol 33 VCC(RX) 34 2MO3 Output terminal of Mixer 2. Second intermediate frequency ( 455kHz ), generated by mixing first intermediate frequency ( 10.7MHz ) and Second Local Oscillator is output. 35 36 2LOI 2LOI Input terminal of second local oscillator. Generates second local oscillator frequency to convert output from mixer 1 ( 10.7MHz ) into second intermediate frequency. It is an oscillator with crystal of 10.24MHz and 10.245MHz. 37 2MI Input terminal of mixer 2. Output from mixer 1 is entered to mixer 2 input terminal via 10.7MHz ceramic filter. Second mixer converts frequency to second intermediate frequency ( 455kHz: AM IF ). 38 1MO3 Output terminal of mixer 1. The signal from mixer 1 and the frequency of the first local oscillator are mixed to produce the first intermediate frequency, which is the output through this terminal. The output terminal is an emitter follower with an output impedance of 330Ω to match the 330Ω input/output impedance of the 10.7MHz ceramic filter. 39 40 1LOI 1LOI Input terminal of the first local oscillator. The local oscillator is a voltage controlled oscillator. local oscillation frequency and received frequency are mixed at mixer 1 and then converted to the first intermediate frequency of 10.7MHz or 10.695MHz. 41 VCORX 42 43 1MI 1MI 44 GND (PLL) 45 PDR 46 VREF(PLL) PLL voltage reference output pin. An internal voltage regulator provides a stable power supply voltage for the RX and TX PLLs. 47 VCC(PLL) Power supply terminal of PLL. 48 TIF 6 Description Supply voltage. Supplies power to the Receiver. The terminal which variable capacitor is included in the chip. Used as an input terminal where 1st local oscillation frequency is changed by varying the capacitor connected between 1st local oscillator terminals.The internal variable capacitor has the value of 18.73 ~ 15.86pF depending on the applied voltage. ( 1.0 ~ 2.0 V ). Input terminal of Mixer 1. This mixer is made of double balanced multiplier. The received signal amplified at RF AMP is input to this terminal. Ground. Ground for analog at PLL Phase detector output terminal of the receiver at PLL. If fRX > fREF or fRX is Leading → The output is negative pulse If fRX < fREF or fRX is Lagging → The output is positive pulse If fRX = fREF and the same phase → The output is high impedance Input terminal of TX channel counter. AC coupling with TX VCO. Minimum input level is 300mVp-p ( at 60MHz ). 1 CHIP CLP SUBSYSTEM IC S1T8527C ABSOLUTE MAXIMUM RATINGS Characteristic Symbol Value Unit Maximum Supply Voltage VCC 5.5 V Power Dissipation PD 600 mW Operating Temperature TOPR −20 — + 70 °C Storage Temperature TSTG − 55 — + 150 °C CURRENT CONSUMPTION AT EACH MODE ( VCC = 3.6V ) MODES Min. Typ. Max. Inactive mode − 350uA 600uA RX mode − 6.6mA − Communication mode ( Active mode ) − 13.5mA CURRENT CONSUMPTION IN EACH BLOCK ( VCC = 3.6V ) MODES Min. Typ. Max. Receiver part − 5.0mA 7.5mA Expander part − 1.4mA 2.1mA Speaker part − 1.7mA 2.5mA compressor part − 3.0mA 4.5mA RX part − 1.6mA 2.4mA TX part − 0.8mA 1.2mA PLL 7 S1T8527C 1 CHIP CLP SUBSYSTEM IC ELECTRICAL CHARACTERISTICS Characteristic Operating Voltage Symbol Test Conditions Min. Typ. Max. Unit Vcc − 2.0 − 5.5 V RECEIVER ( VCC = 3.6V, fC = 49.7MHz, fDEV = ± 3kHz, fMOD = 1kHz,Ta = 25°C, unless otherwise specified ) Input for −3dB Sensitivity VLIM −3dB Point − 0.7 2.0 µVrms Input for 20dB Sensitivity VI(SEN) Modulation Input − 0.7 2.0 µVrms Modulation Input No Modulation Input 48 55 − dB VO(RA) RFin = 1mVrms 145 185 225 mVrms VNO RFin = No Input − 130 205 mVrms Recovered Audio Output Voltage Drop VO(RAD) Vcc = 5V → 2V RFin = 1mVrms −8 −3.3 − dB Detect Output Voltage VO(DET) RFin = 1mVrms 1.0 1.5 2.0 V Carrier Detector Threshold VTH(DET) RFin = No Input 0.49 0.60 0.73 V S/N Ratio Recovered Audio Output Noise Output Level S/N Comparator Threshold Voltage Difference ∆VTH VCOMP = 150mVp-p R L = 180kΩ 70 110 150 mV Comparator Output Voltage 1 VOH VCOMP = 150mVp-p RL = 180kΩ 2.7 3.0 − V Comparator Output Voltage 2 VOL VCOMP = 150mVp-p R L = 180kΩ − 0.25 0.5 V First Mixer Conversion Voltage Gain ∆GV(1M) VI(43) = 1mVrms R L(38) = 330Ω 14 18 22 dB Second Mixer Conversion Voltage Gain ∆GV(2M) VI(37) = 1mVrms R L(34) = 1.5kΩ 17 21 25 dB Detector Output Distortion THDDET RFin = 1mVrms − 1.5 2.5 % Detector Output Resistance RO(DET) RFin = 1mVrms − 1.2 − kΩ Detector Output DC Voltage Change Ratio ∆VO(DET) RFin = 1mVrms − 0.15 0.23 V/kHz 70 100 135 nA/dB Meter Drive Slope MDS First Mixer Input Resistance RI(1M) fc = 50MHz 500 690 − Ω First Mixer Input Capacitance CI(1M) fc = 50MHz − 7.2 10 pF Limiter Input Sensitivity VI(LIM) fc = 455kHz, 20dB SINAD − 100 250 µVrms Second Mixer Input Sensitivity SV(2M) fc = 10.7MHz, 20dB SINAD − 10 25 µVrms 8 1 CHIP CLP SUBSYSTEM IC S1T8527C ELECTRICAL CHARACTERISTICS (Continued) Characteristic Symbol Test Conditions Min. Typ. Max. Unit First Mixer 3rd Order Sensitivity 3RD − − -22 − dBm Low Battery Detector LBD3 LBD0— LBD3 = 0 ( Default ) −0.15 Only LBD2 = 0 Only LBD1 = 0 3.45 3.3 3.0 0.1 V −0.1 2.2 2.1 0.075 25 25 − dB No Signal 0.9 1.0 1.1 V Vinc = 13mVrms ( 0dB ), Ralc = GND 255 300 345 mVrms ∆GV1(COM) Vinc=1.3mVrms (−20dB), ∆Gv1 (COM) = 20 × log (Voc1/Voc) + 10K −1.0 −0.5 − dB ∆GV2(COM) Vinc = 0.13mVrms (−40dB) ∆Gv2 (COM) = 20 × log (Voc2/Voc) + 20K −2.0 −1.0 − dB Only LBD3 = 0 LBD0 — LBD3 = 1 AM Rejection Ratio AMRR RFin = 1mVrms — 10mVrms AM MOD = 30% Compressor ( Vcc = 3.6V, fc = 1kHz, Ta = 25°C, unless otherwise specified ) Reference Voltage Standard Output Voltage Compressor Gain Difference VREF Vo(com) Compressor Output Distortion THDCOM Vinc = 0dB − 0.5 1.0 % Mute Attenuation Ratio ATTMUTE Vinc = 0dB 60 80 − dB Compressor Limiting Voltaget VLIM(COM) Vinc = Variable 1.41 1.65 1.83 Vp-p IALC = 8uA ( RALC = 120kΩ ) 280 330 380 mVrms VINC = 13mVrms = 0dB 255 300 345 mVrms 104 130 156 mVrms ALC Splatter filter VALC Vo(SF) Expander (Vcc = 3.6V, fc = 1kHz, Ta = 25°C, unless otherwise specified) Standard Output Voltage VO(EXP) Vine=30mVrms ( 0dB ) 9 S1T8527C 1 CHIP CLP SUBSYSTEM IC ELECTRICAL CHARACTERISTICS (Continued) Characteristic Symbol Test Conditions Min. Typ. Max. Unit ∆GV1(EXP) Vine = 9.5mVrms (−10dB) ∆Gv1(EXP) = 20 × log (Voe1/ Voe) + 20 0 0.5 1.0 dB ∆GV2(EXP) Vine = 3mVrms (−20dB) ∆Gv2 (EXP) = 20 × log (Voe2/Voe) + 40T 0 1.0 2.0 dB ∆GV3(EXP) Vine = 0.95mVrms (−30dB) ∆Gv3 (EXP) = 20 × log (Voe3/Voe) + 60K 0 1.5 3.0 dB THDEXP VinE = 0dB − 0.5 1.0 % Mute Attenuation Ratio ATTMUTE VinE = 0dB 60 80 − dB Expander Maximum Output Voltage VOEXP(MAX) VinE = Variable THD = 10%l 500 600 − mVrms Expander Gain Difference Expander Output Distortion Speaker amp output 1 Vo( SA1) VINE = 30mVrms = 0 dB 104 130 156 mVrms Speaker amp output 2 Vo( SA1) VINE = 30mVrms = 0 dB 104 130 156 mVrms Vcc = 3.6V − 2.0 3.5 mA IIH Vin = Vcc − − 5 µA IIL Vin = 0V −5 − − µA PLL ( Vcc = 3.6V, Ta = 25°C, unless otherwise specified ) Operating Current Input Current Input Voltage Output Current Output Voltage PLL regulator voltage 10 ICCPLL VIH − Vcc-0.3 − − V VIL − − − 0.3 V IOH Vout = Vcc 0.3 − − mA IOL Vout = 0V 0.3 − − mA VOH1 PDT, PDR: Io = −0.3mA ( Sourcing ) Vcc-0.4 − − V VOL1 PDT, PDR: Io = 0.3mA ( Sinking ) − − 0.4 V VOH2 LD, fMCU: Io = −0.1mA ( Sourcing ) Vcc-0.5 − − V VOL2 LD, fMCU: Io = 0.1mA ( Sinking ) − − 0.5 V 1.95 2.15 2.25 V VPLLREG 1 CHIP CLP SUBSYSTEM IC S1T8527C PLL PROGRAM SUMMARY MCU ( MICOM ) SERIAL INTERFACE ( MSB : 1ST INPUT ) Use CLK (Pin 7 ), DATA (Pin 8 ) , EN (Pin 9 ) terminals for program. DATA and CLK terminals are used for loading data to internal Shift - Register. When EN terminal is ‘Low’ It is possible to program TX-Channel Counter, RX Channel Counter and various control functions of PLL. When EN terminal is ‘High’ Program 1st Local Oscillator Capacitor Selection in receiver for U.S.A - 25 CH function. — TX - Register, RX-Register, Control Register MSB DATA PMC0 LSB PMC1 14 Bit DATA EN CLK — Reference - Register MSB DATA PMC0 LSB PMC1 UK_S1 UK_S0 12 Bit DATA EN CLK — RECEIVER -1st local oscillator internal capacitor selection register & low battery detector voltage register [ CLO_LBD-Register ] MSB DATA PMC LSB LBD3 LBD2 LBD1 LBD0 CLO5 CLO4 CLO3 CLO2 CLO1 CLO0 <1> EN CLK 11 S1T8527C • 1 CHIP CLP SUBSYSTEM IC Programmable Counter — RX - counter: Setting frequency for RX.VCO ( 14 Bits --> 1/16 — 1/16383 ) [ Default_CH. = USA_#21 ( REMOTE ): 36.075MHz ( Div._NO = 7215 )]c < RX. Register (16bits) > Bit Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Name PMC0 PMC1 D13 D12 D11 D10 D9 D8 0 1 1 1 0 0 Default value 7215 * Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Name D7 D6 D5 D4 D3 D2 D1 D0 Default value 7215 0 0 1 0 1 1 1 1 — TX - counter: Setting frequency for TX.VCO ( 14 Bits --> 1/16 — 1/16383 ) [ Default_CH. = USA_#21 ( REMOTE ): 49.830MHz ( Div._NO = 9966 )]' < TX. Register (16 bits) > Bit Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Name PMC0 PMC1 D13 D12 D11 D10 D9 D8 0 1 1 1 0 0 Default value 9966 * Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Name D7 D6 D5 D4 D3 D2 D1 D0 Default value 9966 1 1 1 0 1 1 1 0 * Program mode control 12 PMC0 PMC1 Program mode PMC0 PMC1 Program mode 0 0 Control Block 0 1 UPLL_RX. Block 1 0 UPLL_Ref. Block 1 1 UPLL_TX. Block 1 CHIP CLP SUBSYSTEM IC S1T8527C — Ref - counter: Setting reference frequency for phase detector ( 12 Bits --> 1/16 ~ 1/4095 ) [ Default_Divider = 2048, X-tal_OSC = 10.240 MHz --> Fref = 5kHz ] < Ref. Register (16bits) > Bit Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Name PMC0 PMC1 UK_S1 UK_S0 D11 D10 D9 D8 1 0 0 0 Default value 2048 * Ref.freq. selection for United KingdomD Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Name D7 D6 D5 D4 D3 D2 D1 D0 Default value 2048 0 0 0 0 0 0 0 0 — UK_Selection UK_S0 UK_S1 FR1 FR2 FrefTX FrefRX 0 0 fREF (A) − fREF (A) fREF (A) 1 0 fREF (A) fREF/4 (B) fREF/4 (B) fREF/4 (B) 0 1 fREF/4 (B) fREF/25 (C) fREF/4 (B) fREF/25 (C) 1 1 fREF/4 (B) fREF/25 (C) fREF/25 (C) fREF/4 (B) fREF (A) 12 Bits Reference program divider. ÷4 ÷ 25 LD FR1 fREF ÷ 4 (B) FR2 PD_TX fREF ÷ 25 (C) PDT PDR PD_RX Figure 1. < Reference frequency selection > 13 S1T8527C • 1 CHIP CLP SUBSYSTEM IC Control program — Control register (16 Bits) Bit Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Name PMC0 PMC0 - PLLTX-BS CO_M CO_BS CO_BS EX_BS PLL_Tx Battery Save Compress or Mute Selection Compress or Battery Save Expander Mute Selection Expander Battery Save 0:Normal (PLL_TX-On) 1:PLL_TX Power-Off 0:Normal 0:Normal 0: CO-On 1: Normal ( CO-part 1:Mute Power-Off ) Description Program Mode Control_0 Function Bit 7 LDT_ CDO Description LDT or CDO Select Function Don’t Care * Don’t Program Latch Assign Care Bit Name Program Mode Control_1 LDT or CDO Select Bit 6 Bit 5 LBD-BS Rx-Bs Low Battery Detector Battery Save RX Battery Save 0:Normal (LBD-ON) 1:LBD-Part Power-Off 0:Normal (RX-ON) 1:RX-Part Power-Offf 1:Mute Bit 4 Bit 3 Bit 2 − − − Don’t care Don’t care Don’t care − Bit 1 0: EX-On 1: Normal ( EX-part Power-Off ) Bit 0 TEST2 TEST1 TEST Mode 2 TEST Mode 1 * * * Function Test On each block of UPLL *** TEST Mode & LDT-CDO Mode LDT/CDO TEST1 TEST2 LDT / CDO Remark 0 0 0 Rx block CDO Default 1 0 Rx block CDO 0 1 4_25cnt block FR2 1 1 4_25cnt block FR2 0 0 PLL block LDT 1 0 PLL block LDT 0 1 PLL block LDT 1 1 Test PLL_TX 1 14 1 CHIP CLP SUBSYSTEM IC • S1T8527C Operating internal circuit blocks in each mode Mode ( state ) • Operating circuit blocks Active state ( Communication mode ) PLL regulator/MICOM I/F ( Data, CLK, EN ) / 2nd local oscillator / Receiver / 1st local oscillator / RX PLL / Carrier detector / FSK comparator / Low battery detector / TX PLL / Expander & speaker amp / Compressor / Splatter filter amp Receiving mode PLL regulator / MICOM I/F ( Data, CLK, EN )/ 2nd local oscillator / Receiver / 1st local oscillator / RX PLL / Carrier detector / FSK comparator / Low battery detector. Inactive state PLL regulator / MICOM I/F( Data, CLK, EN ) CLO_LBD - Register Program [ Rx - 1’st local oscillation internal cap. for U.S.A - 25CH & Alarm sensor detect voltage ] — CLO register ( 6 bits ) : Receiver 1’st local oscillator internal capacitor selection Bit Bit10 (MSB) Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Name PMC CLO5 CLO4 CLO3 CLO2 CLO1 CLO0 Default 0 0 0 0 0 0 Value 0 1 ***** Function − 0:Normal 1:Internal Cap. for USA 25 Channel = 3.6pF 0:Normal 1:Internal Cap. for USA 25 Channel = 2.4pF 0:Normal 1:Internal Cap. for USA 25 Channel = 1.2pF 0:Normal 1:Internal Cap. for USA 25 Channel = 0.6pF 0:Normal 1:Internal Cap. for USA 25 Channel = 4.4pF 0:Normal 1:Internal Cap. for USA 25 Channel = 1.0pF *****PMC ( Program Mode Control ) PMC = ‘HIGH’ & EN = ‘HIGH’ ---> CLO_LBD Register Program Modeap — Rx - Low Battery Detect Voltage Bit Bit 10(MSB) Bit 9 Bit 8 Bit 7 Bit 6 Low Battery Detector Voltagef Remark Name PMC LBD3 LBD2 LBD1 LBD0 Default Value 1* * * * * 0 0 0 0 − Default Function 1 0 0 0 0 3.45V − 1 0 1 1 3.3V − 1 1 0 1 3.0V − 0 1 1 1 2.2V − 1 1 1 1 2.1V − 15 S1T8527C 1 CHIP CLP SUBSYSTEM IC ***** PMC ( Program Mode Control ) PMC = ‘HIGH’ & EN = ‘HIGH’ ---> CLO - LBD Register Program Mode • Example 1 > Low battery detector voltage : 2.1V U.S.A _CH-#1 ( REMOTE ) ---> 1st local osc. varicap value = 15.86pF, Internal cap = 7.0pF ( Ext_L = 0.45uH, EXT_C = 30pF ) — 12 bit data format MSB Dummy PMC bit 1 1( 0 ) DATA LSB LBD3 LBD2 1 LBD1 LBD0 CLO5 CLO4 CLO3 CLO2 CLO1 CLO0 1 1 1 0 1 1 1 0 0 EN CLK In case the 12 bits programming, insert 1 don’t care bit ( Dummy bit ) between PMC and LBD3. — In case of setting 16 bit data format MSB PMC DATA 1 Dummy bit 1( 0 ) 1( 0 ) 1( 0 ) 1( 0 ) 1( 0 ) LSB LBD3 LBD2 1 1 LBD1 LBD0 CLO5 CLO4 CLO3 CLO2 CLO1 CLO0 1 1 0 1 1 EN CLK In case of 16 bits programming, insert 5 don’t care bits between the PMC and LBD3 16 1 0 0 1 CHIP CLP SUBSYSTEM IC S1T8527C EXAMPLE DATA FOR U.S.A 25_CHANNEL SELECTION 1’st Local Osc. Internal Capacitor Select Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 (CLO5) (CLO4 (CLO3) (CLO2) (CLO1) (CLO0) 0 • 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 1 Base Hand Channels Channels 1— 25CH. 1— 25CH. 16 — 25CH. Varicap Value External C External L Internal C 1.0V— 2.0V 27pF ( 30pF ) 0.45uH pF TYP 1.5Vo 18.73 27pF 0.45uH - 30pF 0.45uH 0.6 27pF 0.45uH 1.6 — 15.86pF 16 — 25CH. 18.73 — 15.86pF 18.73 01 — 04CH. — 15.86pF 0 0 0 0 1 0 05 — 10CH. 18.73 — 15.86pF 27pF 0.45uH 1.2 0 0 0 0 0 1 11 — 15CH 18.73 — 15.86pF 27pF 0.45uH 0.6 0 1 1 1 0 0 01 — 06CH. 18.73 — 15.86pF 30pF 0.45uH 7.0 0 1 1 0 1 0 07 — 15CH. 18.73 — 15.86pF 30pF 0.45uH 5.8 Phase detector / Lock Detector Output Waveforms fREF (A) 12 Bits Reference program divider. ÷4 2LOI ÷ 25 fREF ÷ 4 (B) fREF ÷ 25 (C) LD FR1 REF.Freq FR2 PD_TX TIF ÷ N PDT 14 Bits TX. program divider. TIF 17 S1T8527C 1 CHIP CLP SUBSYSTEM IC REF.Freq. TIF ÷ N PDT LD Figure 2. ( Phase Detector / Lock Detector Output Waveform ) 18 R37 100 RX TX DUPLEX ANT L1 1.8uH FET1 25K544 C51 10N C48 10N 10 R41 C52 0.47uF T3 (AY) C57 10K 47N C58 10N T2 (AY) 56K R40 TX VCO 3.9K C53 10uF C56 10N R39 C50 2P 100N T4 C49 (AW) R36 C47 30P 2LOI CO 2 PDT 1 2LDI 48 TIF R10 R11 10K 10K 47 VCC(PLL) 46 VREF(PLL) 45 PDR 44 GND (PLL) 43 1MI 42 1MI C17 12N 4 R44 10K 3 2MO SFI 41 VCO RX 40 1LOI 39 1LOI VCC (RX) SFO 38 1MO C43 S1T8527C LI 5 CDO/LDT C46 10N LD 6 GND (PLL) R35 22 33N 7 8 R32 470K R31 27K SAO2 17 SAO1 18 SAI 19 EO 20 ERC 21 EPI 22 ALC 23 C24 2.2uF C25 3.3uF 68K R19 C29 10N to MICOM (MCU) L5 22uH R14 560 10 R22 R2 50K DATA FROM MICOM (MCU) C26 1.0uF 100N C28 R25 51K C30 1.0N C33 R24 33K 100N C32 to MICOM (MCU) CPI- 13 CPI+ 14 GND (COMP) 15 C34 C35 4.7uF C37 10N C38 220uF 3.3uF 100N R26 120K 10K C39 10N 10K R30 27K VREF (COMP) 24 R28 VR1 50K R29 VCC(COMP) 16 10 11 12 RAO EN 9 DSCI LBD 36 35 34 33 32 31 30 29 28 27 26 25 GND (RX) CLK ANT R33 C40 22K 10N R34 51K C41 QCI DATA 37 2MI C42 68N T5 DSCO AGIC FET2 10.7MHz 33P C44 455kHz 10N Y1 C45 10.24MHz 20P FLT3 CDO CRC CVI 20P COMPRESSOR INPUT MAIN POWER RX OUT RX DATA OUT 1 CHIP CLP SUBSYSTEM IC S1T8527C APPLICATION CIRCUIT (BASE SET) 19 RX R37 100 C21 6P TX DUPLEX ANT L1 1.8uH FET1 25K544 C51 10N C48 10N 10 R41 C52 1.0uF T3 (AY) R35 22 C47 1.0K C57 47N C58 10N T2 (AY) 120K R40 TX VCO 4.3K C53 10uF C56 10N R39 C50 2P 100N T4 47P C49 (AW) R36 C46 10N 2LOI CO 2 PDT 1 2LDI 48 TIF R10 R11 22K 10K 47 VCC(PLL) 46 VREF(PLL) 45 PDR 44 GND (PLL) 43 1MI 42 1MI VCC (RX) C17 12N 4 SFO R44 10K 3 2MO SFI 41 VCO RX 40 1LOI 39 1LOI C43 S1T8527C LI 5 CDO/LDT ANT LD 6 GND (PLL) 38 1MO R33 C40 22K 10N R34 51K C41 33N R32 470K R31 27K 7 8 SAO2 17 SAO1 18 SAI 19 EO 20 ERC 21 EPI 22 ALC 23 (COMP) 24 VREF C24 2.2uF C25 3.3uF C32 20K R19 C29 10N 100N C28 1 2 SPK R2 50K to MICOM (MCU) DATA FROM MICOM (MCU) C26 1N C31 10P R25 51K C30 1.0N C33 R24 33K 100N to MICOM (MCU) CPI- 13 CPI+ 14 C34 C35 4.7uF C37 10N C38 220uF 3.3uF 100N R26 120K 10K C39 10N 10K R30 27K C36 68N R28 GND (COMP) 15 10 11 12 RAO EN 9 DSCI LBD VR1 50K R29 VCC(COMP) 16 CDO 36 35 34 33 32 31 30 29 28 27 26 25 GND (RX) CLK 37 2MI C42 68N T5 QCI DATA FET2 10.7MHz 33P C44 455kHz 10N Y1 C45 10.24MHz 20P FLT3 DSCO AGIC 20 CRC CVI 20P 10 R22 L5 22uH COMPRESSOR INPUT MAIN POWER RX DATA OUT S1T8527C 1 CHIP CLP SUBSYSTEM IC APPLICATION CIRCUIT (HAND SET)