KB8527B 1 CHIP CLP SUBSYSTEM IC INTRODUCTION 48 -QFP- 1010E KB8527B is a monolithic circuit which can be used in high performance 60MHz MCA type CLP System. The KB8527B is a subsystem IC for FM / FSK receiving systems and a complete one chip FM / FSK receiver IC for 60MHz system. It`s feature includes receiving functions for FM / FSK systems, a compandor to remove external noise, and PLL ( Phase Lock Loop ) of channel selection which blocks surrounding frequency interference. The KB8527B can be used with a wide range of FM / FSK VHF bandwidth systems, including cordless phone, and the narrow band voice and data sending / receiving systems. To make applications easily and simply, pheripheral parts are minimized. ORDERING INFORMATION Device + KB8527BQ Package 48 - QFP - 1010E + : New product FEATURES ¡ Ü ¡ Ü ¡ Ü ¡ Ü Operating voltage range : 2.0V ~ 5.5V Typical supply current : 13.5mA at 3.6V Built - in low battery detection function ( selectable 3.45V, 3.3V, 3.0V, 2.2V, 2.1V ) Built - in speaker amplifier • Built - in splatter filter • Built - in dual conversion receiver, compandor and universal PLL ¡ Ü FM Receiver - Complete dual coversion circuit - Excellent input sensitivity (0.7µVrms at 20dB SINAD) ¡ Ü Compandor - Easy gain control to use external component - Included ALC (Automatic Level Control) circuit - Included Mute logic ¡ Ü Universal PLL - RX (TX) divided counter range : 1/16 ~ 1/16383 - Reference frequency divided counter range : 1/16 ~ 1/4095 - Lock detector signal output - Serial interface with MICOM for controlling each block Operating Temperature -20oC ~ + 70oC KB8527B 1 CHIP CLP SUBSYSTEM IC 2LOI 2LOI 2MO VCC(RX) LI LD GND(RX) QCI RAO DSCI DSCO MDO BLOCK DIAGRAM 36 35 34 33 32 31 30 29 28 27 26 25 X-tal OSC FSK COMP Limiting IF AMP Regulator (1V) 24 VREF (COMP) VREF 2MI 37 1MO 2`nd MIX IF AMP (455KHz) 38 1LOI 39 1LOI 40 RX VCO PRI Meter Driver Quad Detector + Rectifier Carrier Detector RX 1`st MIX IF AMP (10.7MHz) SUM AMP 1MI 42 1MI 43 GND (PLL) Gain Cell Low Battery Detector SPK AMP Buffer Limiter + SUM AMP Programmable Counter ( RX ) PRI - ALC 47 Rectifier Splatter Filter TX Phase Detector Compandor mute 1 2 3 4 5 6 7 8 9 10 11 12 CLK DATA EN LBD AGIC CRC CONTROL GND(PLL) fMCU CDO/LDT RX Phase Detector 4_25 CNT SFO TIF 48 Programmable Counter ( REF ) SFI (PLL) Programmable Counter ( TX ) CO VCC 46 PDT (PLL) 19 SAI 17 SAO2 16 VCC (COMP) 15 GND (COMP) 14 CPI+ Gain Cell VREF EPI 18 SAO1 44 PDR 45 22 20 EO SPK AMP Regulator ( 2.15 V ) ALC 21 ERC AMP VCO 41 23 13 CPI - KB8527B 1 CHIP CLP SUBSYSTEM IC 2LOI 2LOI 2MO VCC(RX) LI LD GND(RX) QCI RAO DSCI DSCO MDO PIN CONFIGURATION 36 35 34 33 32 31 30 29 28 27 26 25 2MI 37 24 VREF(COMP) 1MO 38 23 ALC 1LOI 39 22 EPI 1LOI 40 21 ERC VCORX 41 20 EO KB8527B 1MI 42 19 SAI 1MI 43 18 SAO1 GND(PLL) 44 17 SAO2 PDR 45 16 VCC(COMP) VREF(PLL) 46 15 GND (COMP) 1 2 3 4 5 6 7 8 9 10 11 12 SFO CDO/LDT GND(PLL) CLK DATA EN LBD AGIC CRC 13 CPI - SFI TIF 48 CO 14 CPI+ PDT VCC(PLL) 47 KB8527B 1 CHIP CLP SUBSYSTEM IC PIN DESCRIPTION Pin No Symbol Description Phase detector output terminal of the transmitter at PLL. 1 PDT If fTX > fREF or fTX is leading the output is negative pulse If fTX < fREF or fTX is lagging the output is positive Pulse if fTX = fREF and the same phase 2 3 4 CO SFI SFO the output is High Impedance Compressor output terminal of compandor ; connected to the splatter filter amp input terminal. Input terminal of Splatter filter amp. Output terminal of Splatter filter amp. LDT : Output terminal of transmitter lock detector in PLL block. Output is low if PLL is in lock state and is high if PLL is in unlock state. 5 LDT/ CDO CDO : As an output terminal of the carrier detector buffer, connected to (RSSI ) terminal of MICOM. This pin outputs the contents of Meter Driver buffer which is turned on / off, according to the signal level detected by Meter Driver. 6 GNDPLL 7 CLK 8 DATA 9 EN 10 LBD Ground. Ground of logic section at PLL. These pins are serial interface terminals for programming reference counter, auxiliary reference counter, TX channel counter, RX channel counter and control block that controls internal each block with test mode and power saving mode. Low Battery Detecting output. ( Selectable 3.45V, 3.3V, 3.0V, 2.2V, 2.0V ). During the normal operation, output level is low, but it is high at low battery detection. As this pin is an open collector type, it requires a pull - up resister. This pin bypasses AC elements at the feedback loop which come from the SUM 11 AGIC amp block of COMPRESSOR. A capacitor should be connected between this terminal and GND. ( C = 2.2 uF ) KB8527B 1 CHIP CLP SUBSYSTEM IC Pin No Symbol 12 CRC Description Converts waveform from the full wave rectifier to DC element at the rectifier block of Compressor. ( RC = 33 msec ) 13 CPI - Pre - amp inverting input terminal of Compressor. Adjusts the negative feedback loop gain. ( in application, gain is 5 ) 14 CPI + Pre - amp non - inverting input terminal of Compressor. Used as an input terminal for voice signals. 15 16 GND Ground. (COMP) Ground of Compandor. Vcc (COMP) Supply voltage. Power supply terminal of Compandor. Output terminal of speaker amp 2. 17 SAO 2 This signal is the same as SAO1 output, but phase difference is 180o for SAO1. DC voltage level is ( Vcc - 0.7V ) / 2. 18 SAO 1 19 SAI Output terminal of Speaker amp 1. DC voltage level is ( Vcc - 0.7V ) / 2. Speaker Amp 1 input terminal. Between this terminal and Expander output terminal, uses a AC coupled. 20 EO 21 ERC 22 EPI - Output terminal of Expander, from which a regenerated voice signals are emitted. Converts waveform from the full wave rectifier to DC element at the rectifier block 23 ALC of Expander. ( RC = 33 msec ) Pre - amp inverting input terminal of Expander. Adjusts the negative feedback loop gain. ( in application, gain is 5 ) Reference current input terminal of Automatic Level Control ( ALC) ; Adjusts THD of compressor output voltage to less than 3 % or limites the frequency deviation of TX if the input is higher than a certain level. The ALC circuit may be turned off depending on the ALC reference current or the magnitude of output voltage may be limited if it is higher than a certain level. ( Iref = 8uA, Ralc = 120KΩ) KB8527B Pin No 24 1 CHIP CLP SUBSYSTEM IC Symbol VREF(COMP) Description Reference voltage ( VREF= 1V ). Supplies a regulator voltage to the Compressor and Expander of COMPANDER. Output terminal of the Meter Driver. 25 MDO Amplitude of RF input signal for useful frequency is detected by Meter Driver circuit. The Meter Driver circuit has perfect linear characteristic of 60 dB range for input signal level. ( 0.1µV / dB ) Output terminal of Data Slicing comparator. 26 DSCO Seperates Frequency Shift Keying ( FSK ) serial data and executes data shapping and limiting. 27 DSCI Input terminal of Data slicing comparator. Non - inverting type with the negative input terminal biased to 1/2 Vcc. Recovered Audio Output terminal. Voice signals detected by the Quadrature 28 RAO Detector are amplified and then output through this terminal. Quadrature coil input terminal. 29 QCI The 455 KHz oscillator circuit is an Lp=680uH, Cp=180pF valued LC tank circuit. Voice signals are detected by mixture of 455 KHz ( by phase difference ) which is converted from mixer 2. 30 GNDRX Ground . Ground for Receiver. Limiter input and decoupling terminal. Removes amplitude modulation elements caused by fading or FM signal noise. 31 LD Limiting IF amplifies and limits the second intermediate frequency, 455 KHz. The input impedance of the limiting IF amplifier is set to 1.5 KΩ. 32 LI While FM waves are transmitted with constant magnitude, their magnitudes are slightly modulated due to reflection from obstacles, fading phenomenon, noise wave, and mixing with AM wave elements before entering the receiver`s antenna. The limiter makes amplitude uniform by removing these AM wave elements. KB8527B 1 CHIP CLP SUBSYSTEM IC Pin No Symbol 33 VCC(RX) 34 2MO 35 2LOI 36 2LOI 37 2MI Description Supply voltage. Supplies power to the Receiver. Output terminal of Mixer 2. Second intermediate frequency ( 455 KHz ), generated by mixing first intermediate frequency ( 10.7 MHz ) and Second Local Oscillator is output. Input terminal of second local oscillator. Generates second local oscillator frequency to convert output from mixer 1 ( 10.7 MHz ) into second intermediate frequency. It is an oscillator with crystal of 10.24 MHz and 10.245 MHz. Input terminal of mixer 2. Output from mixer 1 is entered to mixer 2 input terminal via 10.7 MHz ceramic filter. Second mixer converts frequency to second intermediate frequency ( 455 KHz : AM IF ). Output terminal of mixer 1. The signal from mixer 1 and the frequency of the first local oscillator are mixed 38 1MO to produce the first intermediate frequency, which is the output through this terminal. The output terminal is an emitter follower with an output impedance of 330Ω to match the 330Ω input / output impedance of the 10.7 MHz ceramic filter. Input terminal of the first local oscillator. 39 1LOI The local oscillator is a voltage controlled oscillator. local oscillation frequency 40 1LOI and received frequency are mixed at mixer 1 and then conerted to the first intermediate frequency of 10.7 MHz or 10.695 MHz. The terminal which variable capacitor is included in the chip. Used as an input terminal where 1`st local oscillation frequency is changed by varying the capacitor 41 VCORX connected between 1`st local oscillator terminals. The internal variable capacitor has the value of 18.73 ~ 15.86 pF depending on the applied voltage. ( 1.0 ~ 2.0 V ) 42 1MI Input terminal of Mixer 1. This mixer is made of double balanced multiplier. 43 1MI The received signal amplied at RF AMP is input to this teminal. 44 GND Ground. (PLL) Ground for analog at PLL. KB8527B Pin No 1 CHIP CLP SUBSYSTEM IC Symbol Description Phase detector output terminal of the receiver at PLL. 45 PDR If fRX > fREF or fRX is Leading The output is negative pulse If fRX < fREF or fRX is Lagging The output is positive pulse If fRX = fREF and the same phase The output is high impedance PLL voltage reference output pin. 46 VREF(PLL) An internal voltage regulator provides a stable power supply voltage for the RX and TX PLLs. 47 VCC(PLL) Power supply terminal of PLL. Input terminal of TX channel counter. 48 TIF AC coupling with TX VCO. Minimum input level is 300 mVp-p ( at 60MHz ). KB8527B 1 CHIP CLP SUBSYSTEM IC ABSOLUTE MAXIMUM RATINGS Characteristic Symbol Maximum Supply Voltage VCC 5.5 V PD 600 mW Power Dissipation Value Unit Operating Temperature TOPR -20 ~ + 70 oC Storage Temperature TSTG - 55 ~ + 150 oC CURRENT CONSUMPTION AT EACH MODE Modes Min. Inactive mode ( Vcc = 3.6V ) Typ. Max. - 350uA 600uA RX mode - 6.6mA - Communication mode ( Active mode ) - 13.5mA - CURRENT CONSUMPTION IN EACH BLOCK ( Vcc = 3.6V ) Modes Min. Typ. Receiver part - 5.0mA 7.5mA Expander part - 1.4mA 2.1mA Speaker part - 1.7mA 2.5mA compressor part - 3.0mA 4.5mA RX part - 1.6mA 2.4mA TX part - 0.8mA 1.2mA PLL Max. KB8527B 1 CHIP CLP SUBSYSTEM IC ELECTRICAL CHARACTERISTICS Characteristic Operating Voltage Symbol Test Conditions Vcc Min Typ Max Unit 2.0 - 5.5 V RECEIVER ( VCC = 3.6V, fC = 49.7MHz, fDEV =+ 3KHz, fMOD = 1KHz,Ta = 25oC, unless otherwise specified ) Characteristic Symbol Test Conditions Typ Max Unit - 0.7 2.0 µVrms - 0.7 2.0 µVrms Input for -3dB Sensitivity VLIM Input for 20dB Sensitivity VI(SEN) S/N Ratio S/N Modulation Input No Modulation Input 48 55 - dB VO(RA) RFin = 1mVrms 145 185 225 mVrms VNO RFin = No Input - 130 205 mVrms Recovered Audio Output Voltage Drop VO(RAD) Vcc = 5V 2V RFin = 1mVrms -8 -3.3 - dB Detect Output Voltage VO(DET) RFin = 1mVrms 1.0 1.5 2.0 V Carrier Detector Threshold VTH(DET) RFin = No Input 0.49 0.60 0.73 V Comparator Threshold Voltage Difference ∆ VTH VCOMP = 150mVp-p RL = 180KΩ 70 110 150 mV Comparator Output Voltage 1 VOH VCOMP = 150mVp-p RL = 180KΩ 2.7 3.0 - V Comparator Output Voltage 2 VOL VCOMP = 150mVp-p RL = 180KΩ - 0.25 0.5 V Recovered Audio Output Noise Output Level -3dB Point Min Modulation Input First Mixer Conversion Voltage Gain ∆ GV(1M) VI(43) = 1mVrms RL(38) = 330Ω 14 18 22 dB Second Mixer Conversion Voltage Gain ∆ GV(2M) VI(37) = 1mVrms RL(34) = 1.5KΩ 17 21 25 dB KB8527B 1 CHIP CLP SUBSYSTEM IC ELECTRICAL CHARACTERISTICS (Continued) Characteristic Symbol Test Conditions Min Typ Max Unit Detector Output Distortion THDDET RFin = 1mVrms - 1.5 2.5 Detector Output Resistance RO(DET) RFin = 1mVrms - 1.2 - KΩ ∆ VO(DET) RFin = 1mVrms - 0.15 0.23 V/KHz 70 100 135 nA/dB Detector Output DC Voltage Change Ratio Meter Drive Slope MDS % First Mixer Input Resistance RI(1M) fc = 50MHz 500 690 - Ω First Mixer Input Capacitance CI(1M) fc = 50MHz - 7.2 10 pF VI(LIM) fc = 455KHz, 20dB SINAD - 100 250 µV rms Second Mixer Input Sensitivity SV(2M) fc = 10.7MHz, 20dB SINAD - 10 25 µV rms First Mixer 3rd Order Sensitivity 3RD - -22 - dBm Low Battery Detector LBD Limiter Input Sensitivity AM Rejection Ratio AMRR LBD0 ~ LBD3 Only LBD2 Only LBD1 Only LBD3 LBD0 ~ LBD3 = 0 ( Default ) = 0 = 0 = 0 =1 RFin = 1mVrms ~ 10mVrms AM MOD = 30% -0.15 - 0.1 3.45 3.3 3.0 2.2 2.1 0.1 V 0.075 25 35 - dB Min Typ Max Unit 0.9 1.0 1.1 V 255 300 345 mVrms Compressor ( Vcc = 3.6V, fc = 1KHz, Ta = 25oC, unless otherwise specified ) Characteristic Reference Voltage Standard Output Voltage Symbol VREF Test Conditions No Signal Vo(com) Vinc = 13mVrms 0dB Compressor Gain ∆ GV1(COM) Vinc = -20dB -1.0 -0.5 0 dB Difference ∆ GV2(COM) Vinc = -40dB -2.0 -1.0 0 dB KB8527B 1 CHIP CLP SUBSYSTEM IC ELECTRICAL CHARACTERISTICS (Continued) Characteristic Symbol Test Conditions Min Typ Max Unit 1.0 % Compressor Output Distortion THDCOM Vinc = 0dB - 0.5 Mute Attenuation Ratio ATTMUTE Vinc = 0dB 60 80 Compressor Limiting Voltage VLIM(COM) Vinc = Variable 1.41 1.65 1.83 Vp-p 280 330 380 mVrms 255 300 345 mVrms Min Typ Max 104 130 156 mVrms ALC Splatter filter VALC Vo(SF) IALC = 8uA ( RALC = 120KΩ ) VINC = 13mVrms = 0 dB dB Expander (Vcc = 3.6V, fc = 1KHz, Ta = 25oC, unless otherwise specified) Characteristic Standard Output Voltage Expander Gain Difference Symbol V O(EXP) Mute Attenuation Ratio Expander Maximum Output Voltage VinE = 30mVrms 0dB Unit ∆ GV1(EXP) VinE = -10dB 0 0.5 1.0 dB ∆ GV2(EXP) VinE = -20dB 0 1.0 2.0 dB VinE = -30dB 0 1.5 3.0 dB VinE = 0dB - 0.5 1.0 % VinE = 0dB 60 80 - dB VinE = Variable THD = 10% 500 600 - mVrms ∆ GV3(EXP) Expander Output Distortion Test Conditions THDEXP ATTMUTE VOEXP(MAX) Speaker amp output 1 Vo( SA1) VINE = 30mVrms = 0 dB 104 130 156 mVrms Speaker amp output 2 Vo( SA1) VINE = 30mVrms = 0 dB 104 130 156 mVrms KB8527B 1 CHIP CLP SUBSYSTEM IC PLL ( Vcc = 3.6V, Ta = 25oC, unless otherwise specified ) Characteristic Operating Current Symbol Min Typ Max Unit Vcc = 3.6V - 2.0 3.5 mA IIH Vin = Vcc - - 5 µA IIL Vin = 0V -5 - - µA Vcc0.3 - - V - - 0.3 V ICCPLL Test Conditions Input Current VIH Input Voltage VIL IOH Vout = Vcc 0.3 - - mA IOL Vout = 0V 0.3 - - mA Vcc0.4 - - V - 0.4 V - - V - - 0.5 V 1.95 2.15 2.25 V Output Current VOH1 PDT,PDR : Io = -0.3mA ( Sourcing ) VOL1 PDT,PDR : Io = 0.3mA ( Sinking ) VOH2 LD,fMCU : Io = -0.1mA ( Sourcing ) VOL2 LD,fMCU : Io = 0.1mA ( Sinking ) - Output Voltage PLL regulator voltage VPLLREG - Vcc0.5 KB8527B 1 CHIP CLP SUBSYSTEM IC PLL Program summary • MCU ( MICOM ) Serial Interface ( MSB : 1’st INPUT ) Use CLK (Pin 7 ), DATA (Pin 8 ) , EN (Pin 9 ) terminals for program. DATA and CLK terminals are used for loading data to internal Shift - Register. When EN terminal is ` Low `, It is possible to program TX-Channel Counter, RX - Channel Counter and various control functions of PLL. When EN terminal is ` High` , Program 1`st Local Oscillator Capacitor Selection in receiver for U.S.A - 25 CH function. - TX - Register, RX-Register, Control Register MSB DATA PMC0 LSB PMC1 14 Bit DATA EN CLK - Reference - Register MSB DATA PMC0 LSB PMC1 UK_S1 UK_S0 12 Bit DATA EN CLK - RECEIVER -1`st local oscillator internal capacitor selection register & low battery detector voltage register [ CLO _ LBD - Register ] MSB DATA PMC <1> EN CLK LSB LBD3 LBD2 LBD1 LBD0 CLO5 CLO4 CLO3 CLO2 CLO1 CLO0 KB8527B 1 CHIP CLP SUBSYSTEM IC • Programmable Counter - RX - counter : Setting frequency for RX.VCO ( 14 Bits --> 1/16 ~ 1/16383 ) [ Default_CH. = USA_#21 ( REMOTE ) : 36.075MHz ( Div._NO = 7215 )] < RX. Register (16bits) > Bit Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Name PMC0 PMC1 D13 D12 D11 D10 D9 D8 0 1 1 1 0 0 Default value 7215 * Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Name D7 D6 D5 D4 D3 D2 D1 D0 Default value 7215 0 0 1 0 1 1 1 1 - TX - counter : Setting frequency for TX.VCO ( 14 Bits --> 1/16 ~ 1/16383 ) [ Default_CH. = USA_#21 ( REMOTE ) : 49.830MHz ( Div._NO = 9966 )] < TX. Register (16 bits) > Bit Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Name PMC0 PMC1 D13 D12 D11 D10 D9 D8 1 0 0 1 1 0 Default value 9966 * Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Name D7 D6 D5 D4 D3 D2 D1 D0 Default value 9966 1 1 1 0 1 1 1 0 * Program mode control PMC0 PMC1 0 0 1 0 Program mode Program mode PMC0 PMC1 Control Block 0 1 UPLL_RX. Block UPLL_Ref. Block 1 1 UPLL_TX. Block KB8527B 1 CHIP CLP SUBSYSTEM IC - Ref - counter : Setting reference frequency for phase detector ( 12 Bits --> 1/16 ~ 1/4095 ) [ Default_Divider = 2048, X-tal_OSC = 10.240 MHz -->Fref = 5KHz ] < Ref. Register (16bits) > Bit Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Name PMC0 PMC1 UK_S1 UK_S0 D11 D10 D9 D8 1 0 0 0 Default value 2048 Ref.freq. selection for United Kingdom * Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Name D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 0 0 0 Default value 2048 -UK_Selection UK_S0 UK_S1 FR1 FR2 FrefTX FrefRX 0 0 fREF (A) - fREF (A) fREF (A) 1 fREF (A) fREF/4 (B) fREF/4 (B) fREF/4 (B) 0 0 1 fREF/4 (B) fREF/25 (C) fREF/4 (B) fREF/25 (C) 1 1 fREF/4 (B) fREF/25 (C) fREF/25 (C) fREF/4 (B) fREF 12 Bits Reference program divider. .. 4 .. 25 fREF LD FR1 (A) .. 4 (B) FR2 PD_TX . fREF . 25 (C) PDT PDR PD_RX < Reference frequency selection > KB8527B 1 CHIP CLP SUBSYSTEM IC • Control program Control register (16 Bits) Bit Bit 15 Name PMC0 Program Mode Control_0 Description Function Bit Bit 14 Bit 13 Bit 12 PMC1 - PLLTX-BS Program Mode Control_1 Don`t Care * Program Latch Assign Don`t Care Bit 7 Name LDT_CDO LBD-BS Low Battery Detector Battery Save LDT or CDO Select Description Function Bit 6 0:Normal (CDO) 1:LDT 0:Normal (LBD-ON) 1:LBD-Part Power-Off PLL_Tx Battery Save 0:Normal (PLL_TX-On) 1:PLL_TX Power-Off Bit 11 CO_M Compressor Mute Selection 0:Normal 1:Mute Bit 10 Bit 9 CO_BS EX_M EX_BS Compressor Battery Save Expander Mute Selection Expander Battery Save 0: CO-On 1: Normal ( CO-part Power-Off ) Bit 5 Bit 4 Bit 3 Bit 2 Rx-BS - - - Don`t care Don`t care Don`t care RX Battery Save 0:Normal (RX-ON) 1:RX-Part Power-Off 0 1 TEST1 TEST2 LDT / CDO 0 0 Rx block CDO 1 0 Rx block CDO 0 1 4_25cnt block FR2 1 1 4_25cnt block FR2 0 0 PLL block LDT 1 0 PLL block LDT 0 1 Test PLL_RX 1 1 Test PLL_TX 1:Mute Bit 1 TEST2 TEST Mode 2 0: EX-On 1: Normal ( EX-part Power-Off ) Bit 0 TEST1 TEST Mode 1 * * * Function Test On each block of UPLL - *** TEST Mode & LDT-CDO Mode LDT/CDO 0:Normal Bit 8 Remark Default KB8527B 1 CHIP CLP SUBSYSTEM IC • Operating internal circuit blocks in each mode Mode ( state ) Operating circuit blocks Active state ( Communication mode ) Receiving mode PLL regulator / MICOM I/F ( Data, CLK, EN ) / 2`nd local oscillator / Receiver / 1`st local oscillator / RX PLL / Carrier detector / FSK comparator / Low battery detector / TX PLL / Expander & speaker amp / Compressor / Splatter filter amp PLL regulator / MICOM I/F ( Data, CLK, EN ) / 2`nd local oscillator / Receiver / 1`st local oscillator / RX PLL / Carrier detector / FSK comparator / Low battery detector. PLL regulator / MICOM I/F ( Data, CLK, EN ) Inactive state • CLO_LBD - Register Program [ Rx - 1`st local oscillation internal cap. for U.S.A - 25CH & Low battery detect voltage ] - CLO register ( 6 bits ) : Receiver 1`st local oscillator internal capacitor selection Bit Bit10 (MSB) Name PMC Default Value 0 1 ***** Function - Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 CLO5 CLO4 CLO3 CLO2 CLO1 CLO0 0 0 0 0 0 0 0:Normal 1:Internal Cap. for USA 25 Channel =4.4pF 0:Normal 1:Internal Cap. for USA 25 Channel =1.0pF 0:Normal 1:Internal Cap. for USA 25 Channel =3.6pF 0:Normal 1:Internal Cap. for USA 25 Channel =2.4pF 0:Normal 1:Internal Cap. for USA 25 Channel =1.2pF 0:Normal 1:Internal Cap. for USA 25 Channel =0.6pF ***** PMC ( Program Mode Control ) PMC = `HIGH` & EN = `HIGH` ---> CLO_LBD Register Program Mode Bit 0 KB8527B 1 CHIP CLP SUBSYSTEM IC - Rx - Low Battery Detect Voltage Bit Bit 10 (MSB) Bit 9 Bit 8 Bit 7 Bit 6 Name PMC LBD3 LBD2 LBD1 LBD0 0 0 0 0 - Default Default Value 1 ***** Function 1 Low Battery Detector Voltage Remark 0 0 0 0 3.45V - 1 0 1 1 3.3V - 1 1 0 1 3.0V - 0 1 1 1 2.2V - 1 1 1 1 2.1V - ***** PMC ( Program Mode Control ) PMC = `HIGH` & EN = `HIGH` ---> CLO - LBD Register Program Mode * Example 1 > Low battery detector voltage : 2.1V U.S.A _CH-#1 ( REMOTE ) ---> 1`st local osc. varicap value =15.86pF, Internal cap = 7.0pF ( Ext_L = 0.45uH, EXT_C = 30pF ) - 12 bit data format MSB Dummy DATA PMC bit 1 1( 0 ) LSB LBD3 LBD2 1 1 LBD1 LBD0 CLO5 CLO4 CLO3 CLO2 CLO1 CLO0 1 1 0 1 1 1 0 0 EN CLK In case the 12 bits programming, insert 1 don`t care bit ( Dummy bit ) between PMC and LBD3. KB8527B 1 CHIP CLP SUBSYSTEM IC - In case of setting 16 bit data format MSB PMC DATA 1 LSB Dummy bit 1(0) 1(0) 1(0) 1(0) 1(0) LBD3 LBD2 1 1 LBD1 LBD0 CLO5 CLO4 CLO3 CLO2 CLO1 CLO0 1 1 0 1 1 1 0 0 EN CLK In case of 16 bits programming, insert 5 don`t care bits between the PMC and LBD3 * EXAMPLE DATA FOR U.S.A 25_CHANNEL SELECTION Base Channels Hand Channels Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 1 ~ 25CH. (CLO5) (CLO4) (CLO3) (CLO2) (CLO1) (CLO0) 1 ~ 25CH. 1`st Local Osc. Internal Capacitor Select 0 0 0 0 0 0 16 ~ 25CH. - 0 0 0 0 0 1 - 16 ~ 25CH. 0 1 0 0 0 1 01 ~ 04CH. - 0 0 0 0 1 0 05 ~ 10CH. - 0 0 0 0 0 1 11 ~ 15CH - 0 1 1 1 0 0 - 01 ~ 06CH. 0 1 1 0 1 0 - 07 ~ 15CH. Varicap Value 1.0V ~ 2.0V TYP 1.5V 18.73 ~ 15.86pF 18.73 ~ 15.86pF 18.73 ~ 15.86pF 18.73 ~ 15.86pF 18.73 ~ 15.86pF 18.73 ~ 15.86pF 18.73 ~ 15.86pF External C External L 27pF ( 30pF ) 0.45uH Internal C pF 27pF 0.45uH - 30pF 0.45uH 0.6 27pF 0.45uH 1.6 27pF 0.45uH 1.2 27pF 0.45uH 0.6 30pF 0.45uH 7.0 30pF 0.45uH 5.8 KB8527B 1 CHIP CLP SUBSYSTEM IC • Phase detector / Lock Detector Output Waveforms fREF 12 Bits Reference program divider. 2LOI .. . 4 .. 25 LD FR1 (A) fREF . 4 (B) . fREF . 25 REF.Freq FR2 TIF .. N PD_TX (C) 14 Bits TX. program divider. TIF REF.Freq. TIF .. N PDT LD ( Phase Detector / Lock Detector Output Waveform ) PDT