SAMSUNG S6B0715A01-B0CY

S6B0715
33 COM / 100 SEG DRIVER & CONTROLLER FOR STN LCD
January.2000
Ver. 4.0
Prepared by:
Jae-Su, Ko
[email protected]
Contents in this document are subject to change without notice. No part of this document may be reproduced or
transmitted in any form or by any means, electronic or mechanical, for any purpose, without the express written
permission of LCD Driver IC Team.
33 COM / 100 SEG DRIVER & CONTROLLER FOR STN LCD
S6B0715
S6B0715 Specification Revision History
Version
1.0
2.0
3.0
Content
CAP3P → C3+, CAP2P → C2+, CAP1P → C1+
CAP3M → C3-, CAP2M → C2-, CAP1M → C1Oscillator frequency
FOSC (kHz) = → 19 (Min.): 22.5 (Typ.): 26 (Max.)
FCL (kHz) = → 2.37 (Min.): 2.81 (Typ.): 3.25 (Max.)
Temperature coefficient
TEMPS = L: -0.0%/°C → -0.05%/°C
Absolute maximum ratings
VLCD: +0.3 to +15.0 → -0.3 to +17.0
Dynamic current consumption
IDD1: 40µA (Max.)
IDD2: 75µA (Typ.), 100µA (Max.)
Oscillator frequency (internal)
19: 22.5: 26 → 17: 22.5: 27
Oscillator frequency (external)
2.13: 2.81: 3.25 → 2.13: 2.81: 3.37
3.1
4.0
2
Date
Apr.1999
Change VDD Range : 2.4V to 5.5V → 2.4V to 3.6V
Jan.2000
S6B0715
33 COM / 100 SEG DRIVER & CONTROLLER FOR STN LCD
CONTENTS
INTRODUCTION.................................................................................................................................................. 1
FEATURES ......................................................................................................................................................... 1
BLOCK DIAGRAM .............................................................................................................................................. 3
PAD CONFIGURATION....................................................................................................................................... 4
PAD CENTER COORDINATES ........................................................................................................................... 5
PIN DESCRIPTION.............................................................................................................................................. 7
POWER SUPPLY ......................................................................................................................................... 7
LCD DRIVER SUPPLY ................................................................................................................................. 7
SYSTEM CONTROL .................................................................................................................................... 8
MICROPROCESSOR INTERFACE .............................................................................................................. 9
LCD DRIVER OUTPUTS .............................................................................................................................11
TEST PINS..................................................................................................................................................11
FUNCTIONAL DESCRIPTION............................................................................................................................12
MICROPROCESSOR INTERFACE .............................................................................................................12
DISPLAY DATA RAM (DDRAM) ..................................................................................................................16
LCD DISPLAY CIRCUITS............................................................................................................................19
LCD DRIVER CIRCUIT................................................................................................................................21
POWER SUPPLY CIRCUITS.......................................................................................................................22
REFERECE CIRCUIT EXAMPLES ..............................................................................................................28
RESET CIRCUIT .........................................................................................................................................29
INSTRUCTION DESCRIPTION...........................................................................................................................30
SPECIFICATIONS ..............................................................................................................................................43
ABSOLUTE MAXIMUM RATINGS ...............................................................................................................43
DC CHARACTERISTICS .............................................................................................................................44
REFERENCE DATA ....................................................................................................................................47
AC CHARACTERISTICS .............................................................................................................................49
REFERENCE APPLICATIONS...........................................................................................................................53
MICROPROCESSOR INTERFACE .............................................................................................................53
CONNECTIONS BETWEEN S6B0715 AND LCD PANEL ............................................................................54
TCP PIN LAYOUT (SAMPLE)......................................................................................................................57
3
S6B0715
33 COM / 100 SEG DRIVER & CONTROLLER FOR STN LCD
INTRODUCTION
The S6B0715 is a driver & controller LSI for graphic dot-matrix liquid crystal display systems. It contains 33 common
and 100 segment driver circuits. This chip is connected directly to a microprocessor, accepts serial or 8-bit parallel
display data and stores in an on-chip display data RAM of 65 x 132 bits. It provides a highly-flexible display section
due to 1-to-1 correspondence between on-chip display data RAM bits and LCD panel pixels. And it performs display
data RAM read/write operation with no external operating clock to minimize power consumption. In addition,
because it contains power supply circuits necessary to drive liquid crystal, it is possible to make a display system
with the fewest components.
FEATURES
Driver Output Circuits
−
33 common outputs / 100 segment outputs
On-chip Display Data RAM
−
−
−
Capacity: 65 x 132 = 8,580 bits
Bit data "1": a dot of display is illuminated.
Bit data "0": a dot of display is not illuminated.
Multi-chip Operation (Master, Slave) Available
Applicable Duty Ratios
Duty ratio
Applicable LCD bias
Maximum display area
1/33
1/5 or 1/6
33 × 100
Microprocessor Interface
−
−
8-bit parallel bi-directional interface with 6800-series or 8080-series
Serial interface (only write operation) available
Various Instruction Setting
On-chip Low Power Analog Circuit
−
−
−
−
−
On-chip oscillator circuit
Voltage converter (x2, x3 and x4)
Voltage regulator (temperature coefficient: -0.05%/°C, -0.2%/°C)
On-chip electronic contrast control function (32 steps)
Voltage follower (LCD bias: 1/5 or 1/6)
Operating Voltage Range
−
−
Supply voltage (VDD): 2.4 to 3.6 V
LCD driving voltage (VLCD = V0 - VSS): 4.0 to 15.0 V
Low Power Consumption
−
−
100 µΑ Typ. (VDD = 3V, x4 boosting, V0 = 8V, internal power supply ON and display OFF)
10 µΑ Max. (during power save [standby] mode)
Wide Operating Temperature Range
−
Ta = -40°C to +85°C
Package Type
−
Gold bumped chip or TCP
1
33 COM / 100 SEG DRIVER & CONTROLLER FOR STN LCD
S6B0715
Series Specifications
Product code
TEMPS pin
Temp. coefficient
S6B0715A01-B0CZ
0
(VSS connected)
-0.05%/°C
S6B0715A01-B0CY
Package
670 µm
470 µm
COG
S6B0715A11-B0CZ
S6B0715A11-B0CY
S6B0715A01-xxX0
S6B0715A01-xxX0
1
(VDD connected)
-0.2%/°C
0
(VSS connected)
-0.05%/°C
S6B0715A11-xxX0
* xx: TCP ordering number
2
1
(VDD connected)
-0.2%/°C
670 µm
470 µm
670 µm
TCP
S6B0715A11-xxX0
Chip thickness
470 µm
670 µm
470 µm
S6B0715
33 COM / 100 SEG DRIVER & CONTROLLER FOR STN LCD
BLOCK DIAGRAM
COMS
COM31
:
:
100 SEGMENT
DRIVER CIRCUITS
COM0
COMS
SEG99
:
SEG98
:
SEG66
SEG65
SEG64
SEG1
SEG0
VDD
V0
V1
V2
V3
V4
VSS
34 COMMON
DRIVER CIRCUITS
SEGMENT CONTROLLER
COMMON CONTROLLER
V/F
CIRCUIT
PAGE
I/O
ADDRESS
BUFFER
CIRCUIT
V0
DISPLAY DATA RAM
65 X 132 = 8,580 Bits
LINE
ADDRESS
CIRCUIT
VR
TEMPS
V/R
CIRCUIT
V/C
CIRCUIT
MS
CL
M
FRS
DISP
OSCILLATOR
TESTL2
COLUMN ADDRESS
CIRCUIT
VOUT
C1C1+
C2C2+
C3C3+
DISPLAY
TIMING
GENERATOR
CIRCUIT
TESTL1
STATUS REGISTER
INSTRUCTION REGISTER
BUS HOLDER
INSTRUCTION DECODER
MPU INTERFACE (PARALLEL & SERIAL)
DB0
DB1
DB2
DB3
DB4
DB5
DB6(SCLK)
DB7(SID)
MI
RESETB
PS
RW_WR
E_RD
RS
CS2
CS1B
Figure 1. Block Diagram
3
33 COM / 100 SEG DRIVER & CONTROLLER FOR STN LCD
S6B0715
PAD CONFIGURATION
108
209
ððð ððððððððððððððððððð - - - - - - - - - - ððððððððððððððððððð ððð
Y
S6B0715
(TOP VIEW)
(0,0)
X
ðððððððððððððððððððððð - - - - - - - - - - ððððððððððððððððððððððð
1
ðððð - - - -ðððð
234
ðððð - - - -ðððð
210
107
83
82
Figure 2. S6B0715 Chip Configuration
Table 1. S6B0715 Pad Dimensions
Item
Chip size
Pad pitch
Bumped pad size
Bumped pad height
-
7980
2700
83 to 234
70
1 to 82
56
114
83 to 107
108
50
108 to 209
50
108
210 to 234
108
50
All pad
µm
17 (Typ.)
ILB Align Key Coordinate
42µm
108µm
42µm
(+3870, +1230)
42µm
108µm
108µm
30µm
(+3832, -1070)
108µm
42µm
(-3870, +1230)
60µm
4
Y
90
30µm 30µm 30µm
30µm 30µm 30µm
(-3832, -1055)
Unit
X
1 to 82
COG Align Key Coordinate
30µm 30µm 30µm
Size
Pad No.
S6B0715
33 COM / 100 SEG DRIVER & CONTROLLER FOR STN LCD
PAD CENTER COORDINATES
Table 2. Pad Center Coordinates
[Unit: µm]
No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
Name
DUMMY
TESTL1
VDD
FRS
M
CL
DISP
VDD
MS
VSS
RESETB
VDD
PS
VSS
CS1B
CS2
VDD
MI
VSS
VDD
RS
VSS
RW_WR
E_RD
VDD
VDD
VDD
VDD
VDD
VDD
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
VSS
VSS
VSS
VSS
VSS
VSS
VOUT
VOUT
C3+
C3+
C3C3-
X
Y
No.
-3645
-3555
-3465
-3375
-3285
-3195
-3105
-3015
-2925
-2835
-2745
-2655
-2565
-2475
-2385
-2295
-2205
-2115
-2025
-1935
-1845
-1755
-1665
-1575
-1485
-1395
-1305
-1215
-1125
-1035
-945
-855
-765
-675
-585
-495
-405
-315
-225
-135
-45
45
135
225
315
405
495
585
675
765
-1226
-1226
-1226
-1226
-1226
-1226
-1226
-1226
-1226
-1226
-1226
-1226
-1226
-1226
-1226
-1226
-1226
-1226
-1226
-1226
-1226
-1226
-1226
-1226
-1226
-1226
-1226
-1226
-1226
-1226
-1226
-1226
-1226
-1226
-1226
-1226
-1226
-1226
-1226
-1226
-1226
-1226
-1226
-1226
-1226
-1226
-1226
-1226
-1226
-1226
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
Name
C1+
C1+
C1C1C2+
C2+
C2C2VSS
VSS
VR
VR
V0
V0
V0
V0
V0
V0
V1
V1
V2
V2
V3
V3
V4
V4
VSS
VSS
TEMPS
VDD
TESTL2
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
COM15
COM14
COM13
COM12
COM11
COM10
COM9
COM8
COM7
COM6
COM5
COM4
COM3
COM2
X
855
945
1035
1125
1215
1305
1395
1485
1575
1665
1755
1845
1935
2025
2115
2205
2295
2385
2475
2565
2655
2745
2835
2925
3015
3105
3195
3285
3375
3465
3555
3645
3830
3830
3830
3830
3830
3830
3830
3830
3830
3830
3830
3830
3830
3830
3830
3830
3830
3830
Y
No.
-1226
-1226
-1226
-1226
-1226
-1226
-1226
-1226
-1226
-1226
-1226
-1226
-1226
-1226
-1226
-1226
-1226
-1226
-1226
-1226
-1226
-1226
-1226
-1226
-1226
-1226
-1226
-1226
-1226
-1226
-1226
-1226
-840
-770
-700
-630
-560
-490
-420
-350
-280
-210
-140
-70
0
70
140
210
280
350
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
Name
COM1
COM0
COMS
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
SEG0
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
SEG7
SEG8
SEG9
SEG10
SEG11
SEG12
SEG13
SEG14
SEG15
SEG16
SEG17
SEG18
SEG19
SEG20
SEG21
SEG22
SEG23
SEG24
SEG25
SEG26
SEG27
SEG28
SEG29
SEG30
SEG31
SEG32
SEG33
SEG34
SEG35
SEG36
SEG37
SEG38
SEG39
SEG40
SEG41
X
3830
3830
3830
3830
3830
3830
3830
3535
3465
3395
3325
3255
3185
3115
3045
2975
2905
2835
2765
2695
2625
2555
2485
2415
2345
2275
2205
2135
2065
1995
1925
1855
1785
1715
1645
1575
1505
1435
1365
1295
1225
1155
1085
1015
945
875
805
735
665
595
Y
420
490
560
630
700
770
840
1190
1190
1190
1190
1190
1190
1190
1190
1190
1190
1190
1190
1190
1190
1190
1190
1190
1190
1190
1190
1190
1190
1190
1190
1190
1190
1190
1190
1190
1190
1190
1190
1190
1190
1190
1190
1190
1190
1190
1190
1190
1190
1190
5
33 COM / 100 SEG DRIVER & CONTROLLER FOR STN LCD
S6B0715
Table 2. Pad Center Coordinates (Continued)
[Unit: µm]
No.
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
6
Name
SEG42
SEG43
SEG44
SEG45
SEG46
SEG47
SEG48
SEG49
SEG50
SEG51
SEG52
SEG53
SEG54
SEG55
SEG56
SEG57
SEG58
SEG59
SEG60
SEG61
SEG62
SEG63
SEG64
SEG65
SEG66
SEG67
SEG68
SEG69
SEG70
SEG71
SEG72
SEG73
SEG74
SEG75
SEG76
SEG77
SEG78
SEG79
SEG80
SEG81
SEG82
SEG83
SEG84
SEG85
SEG86
SEG87
SEG88
SEG89
SEG90
SEG91
X
525
455
385
315
245
175
105
35
-35
-105
-175
-245
-315
-385
-455
-525
-595
-665
-735
-805
-875
-945
-1015
-1085
-1155
-1225
-1295
-1365
-1435
-1505
-1575
-1645
-1715
-1785
-1855
-1925
-1995
-2065
-2135
-2205
-2275
-2345
-2415
-2485
-2555
-2625
-2695
-2765
-2835
-2905
Y
1190
1190
1190
1190
1190
1190
1190
1190
1190
1190
1190
1190
1190
1190
1190
1190
1190
1190
1190
1190
1190
1190
1190
1190
1190
1190
1190
1190
1190
1190
1190
1190
1190
1190
1190
1190
1190
1190
1190
1190
1190
1190
1190
1190
1190
1190
1190
1190
1190
1190
No.
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
Name
SEG92
SEG93
SEG94
SEG95
SEG96
SEG97
SEG98
SEG99
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
COM16
COM17
COM18
COM19
COM20
COM21
COM22
COM23
COM24
COM25
COM26
COM27
COM28
COM29
COM30
COM31
COMS
DUMMY
DUMMY
DUMMY
DUMMY
X
-2975
-3045
-3115
-3185
-3255
-3325
-3395
-3465
-3535
-3830
-3830
-3830
-3830
-3830
-3830
-3830
-3830
-3830
-3830
-3830
-3830
-3830
-3830
-3830
-3830
-3830
-3830
-3830
-3830
-3830
-3830
-3830
-3830
-3830
Y
1190
1190
1190
1190
1190
1190
1190
1190
1190
840
770
700
630
560
490
420
350
280
210
140
70
0
-70
-140
-210
-280
-350
-420
-490
-560
-630
-700
-770
-840
No.
Name
X
Y
S6B0715
33 COM / 100 SEG DRIVER & CONTROLLER FOR STN LCD
PIN DESCRIPTION
POWER SUPPLY
Table 3. Power Supply Pin Description
Name
I/O
VDD
Supply
Power supply
VSS
Supply
Ground
V0
V1
V2
I/O
V3
V4
Description
LCD driver supply voltages
The voltage determined by LCD pixel is impedance-converted by an operational amplifier
for application.
Voltages should have the following relationship;
V0 ≥ V1 ≥ V2 ≥ V3 ≥ V4 ≥ VSS
When the internal power circuit is active, these voltages are generated as following table
according to the state of LCD Bias.
LCD bias
V1
V2
V3
V4
1/6 bias
(5/6) x V0
(4/6) x V0
(2/6) x V0
(1/6) x V0
1/5 bias
(4/5) x V0
(3/5) x V0
(2/5) x V0
(1/5) x V0
LCD DRIVER SUPPLY
Table 4. LCD Driver Supply Pin Description
Name
I/O
Description
C1-
O
Capacitor 1 negative connection pin for voltage converter
C1+
O
Capacitor 1 positive connection pin for voltage converter
C2-
O
Capacitor 2 negative connection pin for voltage converter
C2+
O
Capacitor 2 positive connection pin for voltage converter
C3-
O
Capacitor 3 negative connection pin for voltage converter
C3+
O
Capacitor 3 positive connection pin for voltage converter
VOUT
I/O
Voltage converter input / output pin
VR
I
V0 voltage adjustment pin
7
33 COM / 100 SEG DRIVER & CONTROLLER FOR STN LCD
S6B0715
SYSTEM CONTROL
Table 5. System Control Pin Description
Name
I/O
Description
Master / Slave operation select pin
− MS = "H": master operation
− MS = "L": slave operation
The following table depends on the MS status.
MS
MS
OSC
circuit
Power
supply
circuit
CL
M
FRS
DISP
H
Enabled
Input
Output
Output
Output
Output
L
Disabled
Disabled
Input
Input
Output
Input
I/O
Display clock input / output pin
When the S6B0715 is used in master/slave mode (multi-chip), the CL pins must be
connected each other for sync.
M
I/O
LCD AC signal input / output pin
When the S6B0715 is used in master/slave mode (multi-chip), the M pins must be
connected each other.
− MS = “ H” : output
− MS = “ L” : input
FRS
O
Static driver segment output pin
This pin is used together with the M pin.
CL
8
I
DISP
I/O
TEMPS
I
LCD display blanking control input/output.
When S6B0715 is used in master/slave mode
(multi-chip), the DISP pins must be connected each other.
− MS = “ H” : output
− MS = “ L” : input
Selects temperature coefficient of the reference voltage
− TEMPS = "L": -0.05%/°C
− TEMPS = "H": -0.2%/°C
S6B0715
33 COM / 100 SEG DRIVER & CONTROLLER FOR STN LCD
MICROPROCESSOR INTERFACE
Table 6. Microprocessor Interface Pin Description
Name
I/O
RESETB
I
Description
Reset input pin
When RESETB is “L”, initialization is executed.
Parallel / serial data input select input
PS
I
PS
Interface
mode
Chip
select
Data /
instruction
Data
Read / write
Serial clock
H
Parallel
CS1B,
CS2
RS
DB0 to DB7
E_RD
RW_WR
-
L
Serial
CS1B,
CS2
RS
SID (DB7)
Write only
SCLK (DB6)
*NOTE: When PS is “L”, DB0 to DB5 a re high impedance and E_RD and RW_WR
should be fixed to either “H” or “L”.
MI
CS1B
CS2
RS
I
Microprocessor interface select input pin
− MI = "H": 6800-series MPU interface
− MI = "L": 8080-series MPU interface
I
Chip select input pins
Data / instruction I/O is enabled only when CS1B is “L” and CS2 is “H”.
When chip select is non-active, DB0 to DB7 may be high impedance.
I
Register select input pin
− RS = "H": DB0 to DB7 are display data.
− RS = "L": DB0 to DB7 are control data.
Read / Write execution control pin
RW_WR
MI
MPU type
RW_WR
H
6800-series
RW
Read/Write control input pin
− RW = “H”: read
− RW = “L”: write
L
8080-series
/WR
Write enable clock input pin
The data on DB0 to DB7 are latched at the rising
edge of the /WR signal.
I
Description
9
33 COM / 100 SEG DRIVER & CONTROLLER FOR STN LCD
S6B0715
Table 6. Microprocessor Interface Pin Description (Continued)
Name
I/O
Description
Read / Write execution control pin
MI
E_RD
DB0
to
DB7
10
I
I/O
MPU Type
E_RD
Description
H
6800-series
E
Read / Write control input pin
− RW = “H”: When E is “ H”, DB0 to DB7 are in an
output status.
− RW = “L”: The data on DB0 to DB7 are latched at
the falling edge of the E signal.
L
8080-series
/RD
Read enable clock input pin
When /RD is “L”, DB0 to DB7 are in an output status.
8-bit bi-directional data bus that is connected to the standard 8-bit microprocessor data
bus. When the serial interface selected (PS = "L");
− DB0 to DB5: high impedance
− DB6: serial input clock (SCLK)
− DB7: serial input data (SID)
When chip select is not active, DB0 to DB7 may be high impedance.
S6B0715
33 COM / 100 SEG DRIVER & CONTROLLER FOR STN LCD
LCD DRIVER OUTPUTS
Table 8. LCD Driver Outputs Pin Description
Name
I/O
Description
LCD segment driver outputs
The display data and the M signal control the output voltage of segment driver.
SEG0
to
SEG99
O
Display data
M
H
Segment driver output voltage
Normal display
Reverse display
H
V0
V2
H
L
VSS
V3
L
H
V2
V0
L
L
V3
VSS
VSS
VSS
Power save mode
LCD common driver outputs
The internal scanning data and M signal control the output voltage of common driver.
COM0
to
COM31
O
Scan data
M
Common driver output voltage
H
H
VSS
H
L
V0
L
H
V1
L
L
V4
Power save mode
COMS
O
VSS
Common output for the icons
The output signals of two pins are same. When not used, these pins should be left open. In
multi-chip (master/slave) mode, all COMS pins on both master and slave units are the
same signal.
TEST PINS
Table 8. Test Pin Description
Name
I/O
TESTL1
TESTL2
I
Description
IC test pins with pull-up
These pins must be open.
NOTE: DUMMY – These pins should be opened (floated).
11
33 COM / 100 SEG DRIVER & CONTROLLER FOR STN LCD
S6B0715
FUNCTIONAL DESCRIPTION
MICROPROCESSOR INTERFACE
Chip Select Input
There are CS1B and CS2 pins for Chip Selection. The S6B0715 can interface with an MPU only when CS1B is “L”
and CS2 is “H”. When these pins are set to any other combination, RS, E_RD, and RW_WR inputs are disabled and
DB0 to DB7 are to be high impedance. And, in case of serial interface, the internal shift register and the counter are
reset.
Parallel / Serial Interface
S6B0715 has three types of interface with an MPU, which are one serial and two parallel interface. This parallel or
serial interface is determined by PS pin as shown in table 9.
Table 9. Parallel / Serial Interface Mode
PS
Type
CS1B
CS2
H
Parallel
CS1B
CS2
L
Serial
CS1B
CS2
MI
Interface mode
H
6800-series MPU mode
L
8080-series MPU mode
*×
Serial-mode
*×: Don't care
Parallel Interface (PS = "H")
The 8-bit bi-directional data bus is used in parallel interface and the type of MPU is selected by MI as shown in table
10. The type of data transfer is determined by signals at RS, E_RD and RW_WR as shown in table 11.
Table 10. Microprocessor Selection for Parallel Interface
MI
CS1B
CS2
RS
E_RD
RW_WR
DB0 to DB7
MPU bus
H
CS1B
CS2
RS
E
RW
DB0 to DB7
6800-series
L
CS1B
CS2
RS
/RD
/WR
DB0 to DB7
8080-series
Table 11. Parallel Data Transfer
Common
12
6800-series
8080-series
E_RD
(E)
RW_WR
(RW)
E_RD
(/RD)
RW_WR
(/WR)
Description
RS
H
H
H
L
H
Display data read out
H
H
L
H
L
Display data write
L
H
H
L
H
Register status read
L
H
L
H
L
Writes to internal register (instruction)
S6B0715
33 COM / 100 SEG DRIVER & CONTROLLER FOR STN LCD
Serial interface (PS = "L")
When the S6B0715 is active, serial data (DB7) and serial clock (DB6) inputs are enabled. And not active, the internal
8-bit shift register and the 3-bit counter are reset. Serial data can be read on the rising edge of serial clock going into
DB6 and processed as 8-bit parallel data on the eighth serial clock. Serial data input is display data when RS is high
and control data when RS is low. Since the clock signal (DB6) is easy to be affected by the external noise caused by
the line length, the operation check on the actual machine is recommended.
CS1B
CS2
SID
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
DB7
DB6
SCLK
RS
Figure 3. Serial Interface Timing
Busy Flag
The Busy Flag indicates whether the S6B0715 is operating or not. When DB7 is “H” in read status operation, this
device is in busy status and will accept only read status instruction. If the cycle time is correct, the microprocessor
needs not to check this flag before each instruction, which improves the MPU performance.
13
33 COM / 100 SEG DRIVER & CONTROLLER FOR STN LCD
S6B0715
Data Transfer
The S6B0715 uses bus holder and internal data bus for Data Transfer with the MPU. When writing data from the
MPU to on-chip RAM, data is automatically transferred from the bus holder to the RAM as shown in figure 4. And
when reading data from on-chip RAM to the MPU, the data for the initial read cycle is stored in the bus holder
(dummy read) and the MPU reads this stored data from bus holder for the next data read cycle as shown in figure 5.
This means that a dummy read cycle must be inserted between each pair of address sets when a sequence of
address sets is executed. Therefore, the data of the specified address cannot be output with the read display data
instruction right after the address sets, but can be output at the second read of data.
MPU signals
RS
/WR
DB0 to DB7
N
D(N)
D(N+1)
D(N+2)
D(N+3)
N
D(N)
D(N+1)
D(N+2)
D(N+3)
Internal signals
/WR
BUS HOLDER
COLUMN ADDRESS
N
N+1
Figure 4. Write Timing
14
N+2
N+3
S6B0715
33 COM / 100 SEG DRIVER & CONTROLLER FOR STN LCD
MPU signals
RS
/WR
/RD
DB0 to DB7
Dummy
N
D(N)
D(N+1)
Internal signals
/WR
/RD
BUS HOLDER
COLUMN ADDRESS
N
D(N)
N
N+1
D(N+1)
D(N+2)
N+2
N+3
Figure 5. Read Timing
15
33 COM / 100 SEG DRIVER & CONTROLLER FOR STN LCD
S6B0715
DISPLAY DATA RAM (DDRAM)
The Display Data RAM stores pixel data for the LCD. It is 65-row by 132-column addressable array. Each pixel can
be selected when the page and column addresses are specified. The 65 rows are divided into 8 pages of 8 lines and
the 9th page with a single line (DB0 only). Data is read from or written to the 8 lines of each page directly through
DB0 to DB7. The display data of DB0 to DB7 from the microprocessor correspond to the LCD common lines as
shown in figure 6. The microprocessor can read from and write to RAM through the I/O buffer. Since the LCD
controller operates independently, data can be written into RAM at the same time as data is being displayed without
causing the LCD flicker.
DB0
0
0
1
--
0
COM0
--
DB1
1
0
0
--
1
COM1
--
DB2
0
1
1
--
0
COM2
--
DB3
1
0
1
--
0
COM3
--
DB4
0
0
0
--
1
COM4
--
Display Data RAM
LCD Display
Figure 6. RAM-to-LCD Data Transfer
Page Address Circuit
This circuit is for providing a page address to Display Data RAM shown in figure 8. It incorporates 4-bit Page
Address register changed by only the “Set Page” instruction. Page Address 8 (DB3 is “H”, but DB2, DB1 and DB0
are “L”) is a special RAM area for the icons and display da ta DB0 is only valid. When Page Address is above 8, it is
impossible to access to on-chip RAM.
Line Address Circuit
This circuit assigns DDRAM a Line Address corresponding to the first line (COM0) of the display. Therefore, by
setting Line Address repeatedly, it is possible to realize the screen scrolling and page switching without changing
the contents of on-chip RAM as shown in figure 8. It incorporates 6-bit line address register changed by only the
initial display line instruction and 6-bit counter circuit. At the beginning of each LCD frame, the contents of register
are copied to the line counter which is increased by CL signal and generates the Line Address for transferring the
132-bit RAM data to the 100 display data latch circuit. However, display data of icons are not scrolled because the
MPU can not access Line Address of icons.
16
S6B0715
33 COM / 100 SEG DRIVER & CONTROLLER FOR STN LCD
Column Address Circuit
Column Address circuit has an 8-bit preset counter that provides column address to the Display Data RAM as shown
in figure 8. When set Column Address MSB / LSB instruction is issued, 8-bit [Y7:Y0] is updated. And, since this
address is increased by 1 each a read or write Data instruction, microprocessor can access the display data
continuously. However, the counter is not increased and locked if a non-existing address above 84H. It is unlocked
if a column address is set again by set Column Address MSB / LSB instruction. And the column address counter is
independent of page address register.
ADC select instruction makes it possible to invert the relationship between the column address and the segment
outputs. It is necessary to rewrite the display data on built-in RAM after issuing ADC select instruction. Refer to the
following figure 7.
SEG output
-
SEG
0
SEG
1
SEG
2
... ...
SEG
97
SEG
98
SEG
99
-
Column address [Y7:Y0]
00H~
0FH
10H
01H
02H
... ...
71H
72H
73H
74H~
83H
Display data
×
1
0
0
0
1
1
0
LCD panel display
Not
outputted
... ...
Not
outputted
Not
outputted
... ...
Not
outputted
( ADC = 0 )
LCD panel display
( ADC = 1 )
Figure 7. The Relationship between the Column Address and the Segment Outputs
Segment Control Circuit
This circuit controls the display data by the display ON / OFF, reverse display ON / OFF and entire display ON / OFF
instructions without changing the data in the display data RAM.
17
33 COM / 100 SEG DRIVER & CONTROLLER FOR STN LCD
Page Address
DB3
DB2
DB1
DB0
0
0
0
0
0
0
0
1
0
0
1
0
0
0
1
1
0
1
0
0
0
1
0
1
0
1
1
0
0
1
1
1
1
0
0
0
Column
Address
Data
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
DB0
ADC=0
ADC=1
Page0
Page1
Page2
Page3
Page4
Page5
Page6
Page7
Page8
-----
SEG99
-
71 72 73 74
12 11 10 1F
SEG98
-
---------
SEG97
-
0F 10 11 12
74 73 72 71
SEG2
-
SEG1
00
83
SEG0
LCD Output
S6B0715
-
-
83
00
-
-
Figure 8. Display Data RAM Map
18
Line
Address
COM
Output
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
0AH
0BH
0CH
0DH
0EH
0FH
10H
11H
12H
13H
14H
15H
16H
17H
18H
19H
1AH
1BH
1CH
1DH
1EH
1FH
20H
21H
22H
23H
24H
25H
26H
27H
28H
29H
2AH
2BH
2CH
2DH
2EH
2FH
30H
31H
32H
33H
34H
35H
36H
37H
38H
39H
3AH
3BH
3CH
3DH
3EH
3FH
COM0
COM1
COM2
COM3
COM4
COM5
COM6
COM7
COM8
COM9
COM10
COM11
COM12
COM13
COM14
COM15
COM16
COM17
COM18
COM19
COM20
COM21
COM22
COM23
COM24
COM25
COM26
COM27
COM28
COM29
COM30
COM31
COMS
Start
Initial start line address = 1CH
S6B0715
33 COM / 100 SEG DRIVER & CONTROLLER FOR STN LCD
LCD DISPLAY CIRCUITS
Oscillator
This is completely on-chip Oscillator and its frequency is nearly independent of VDD. This oscillator signal is used in
the voltage converter and display timing generation circuit.
* Test Condition: Temperature: 25°C & 85°C, TEMPS = ” L” , No Load
VDD vs. fosc
4.00
3.50
3.00
2.50
fosc
2.00
[kHz]
1.50
1/33 Duty (25°C )
1/33 Duty (85°C )
1.00
0.50
0.00
2.4
2.7
3.0
3.3
3.6
4.0
4.5
5.0
5.5
VDD [V]
Figure 9. VDD vs. fOSC
Display Timing Generator Circuit
This circuit generates some signals to be used for displaying LCD. The display clock, CL, generated by oscillation
clock, generates the clock for the line counter and the signal for the display data latch. The line address of on-chip
RAM is generated in synchronization with the display clock (CL) and the 100-bit display data is latched by the
display data latch circuit in synchronization with the display clock. The display data, which is read to the LCD driver,
is completely independent of the access to the display data RAM from the microprocessor. The display clock
generates an LCD AC signal (M) which enables the LCD driver to make a AC drive waveform, and also generates an
internal common timing signal and start signal to the common driver. Driving 2-frame AC driver waveform and
internal timing signal are shown in figure 10.
In a multiple-chip configuration, the slave chip requires the M, CL and DISP signals from the master. Table 12 shows
the M, CL, and DISP status.
Table 12. Master and Slave Timing Signal Status
Operation mode
Master
Slave
Oscillator
M
CL
DISP
ON (internal clock used)
Output
Output
Output
OFF (external clock used)
Output
Input
Output
-
Input
Input
Input
19
33 COM / 100 SEG DRIVER & CONTROLLER FOR STN LCD
32
33
1
2
3
4
5
6
7
8
9
10
11
12
S6B0715
26
27
28
29
30
31
32
33
1
2
3
4
5
6
CL
M
COM0
V0
V1
V2
V3
V4
VSS
COM1
V0
V1
V2
V3
V4
VSS
SEGn
V0
V1
V2
V3
V4
VSS
Figure 9. 2-frame AC Driving Waveform
Common Output Control Circuit
This circuit controls the relationship between the number of common output and specified duty ratio. SHL Select
Instruction specifies the scanning direction of the common output pins.
Table 13. The Relationship between Duty Ratio and Common Output
Duty
SHL
Common output pins
COM0 to COM31
0
COM0 to COM31
1
COM31 to COM0
COMS
1/33
20
COMS
S6B0715
33 COM / 100 SEG DRIVER & CONTROLLER FOR STN LCD
LCD DRIVER CIRCUIT
This driver circuit is configured by 34-channel (including 2 COMS channel) common driver and 100-channel
segment driver. This LCD panel driver voltage depends on the combination of display data and M signal.
VDD
COM0
M
COM1
VSS
COM2
V0
V1
V2
COM0
COM3
COM4
V3
V4
VSS
V0
V1
V2
COM5
COM1
COM6
COM7
V3
V4
VSS
V0
V1
V2
COM8
COM2
COM9
V3
V4
VSS
V0
V1
V2
COM10
SEG0
COM11
COM12
V3
V4
VSS
V0
V1
V2
COM13
SEG1
COM14
COM15
S
E
G
0
S
E
G
1
S
E
G
2
S
E
G
3
S
E
G
4
V3
V4
VSS
V0
V1
V2
SEG2
V3
V4
VSS
Figure 10. Segment and Common Timing
21
33 COM / 100 SEG DRIVER & CONTROLLER FOR STN LCD
S6B0715
POWER SUPPLY CIRCUITS
The Power Supply circuits generate the voltage levels necessary to drive liquid crystal driver circuits with low-power
consumption and the fewest components. There are voltage converter circuits, voltage regulator circuits, and
voltage follower circuits. They are valid only in master operation and controlled by power control instruction. For
details, refers to "Instruction Description". Table 14 shows the referenced combinations in using Power Supply
circuits.
Table 14. Recommended Power Supply Combinations
User setup
Power
control
(VC VR VF)
V/C
circuits
V/R
circuits
V/F
circuits
VOUT
V0
V1 to V4
Only the internal power
supply circuits are used
111
ON
ON
ON
Open
Open
Open
Only the voltage
regulator circuits and
voltage follower circuits
are used
011
OFF
ON
ON
External
input
Open
Open
Only the voltage follower
circuits are used
001
OFF
OFF
ON
Open
External
input
Open
Only the external power
supply circuits are used
000
OFF
OFF
OFF
Open
External
input
External
input
22
S6B0715
33 COM / 100 SEG DRIVER & CONTROLLER FOR STN LCD
Voltage Converter Circuits
These circuits boost up the electric potential between VDD and VSS to 2, 3, or 4 times toward positive side and
boosted voltage is outputted from VOUT pin.
[C1 = 1.0 to 4.7 µF]
V DD
V DD
-
V DD
VOUT
C3+
C3 C2+
C2 C1+
C1 -
+
+
-
V DD
C1
VOUT = 2 × V DD
C1
V DD
V SS
V SS
VOUT
C3+
C3 C2+
C2 C1+
C1 -
V SS
GND
+
C1
VOUT = 3 × V DD
+
C1
+
C1
V DD
V SS
GND
Figure 11. Two Times Boosting Circuit
Figure 12. Three Times Boosting Circuit
V DD
V DD
VOUT
C3+
C3 C2+
C2 C1+
C1 -
V SS
+
+
C1
C1
+
C1
+
C1
-
VOUT = 4 × V DD
V DD
V SS
GND
Figure 13. Four Times Boosting Circuit
23
33 COM / 100 SEG DRIVER & CONTROLLER FOR STN LCD
S6B0715
Voltage Regulator Circuits
The function of the internal Voltage Regulator circuits is to determine liquid crystal operating voltage, V0, by
adjusting resistors, Ra and Rb, within the range of |V0| < |VOUT|. Because VOUT is the operating voltage of
operational-amplifier circuits shown in figure 14, it is necessary to be applied internally or externally.
For the Eq. 1, we determine V0 by Ra, Rb and VEV. The Ra and Rb are connected internally or externally by INTRS
pin. And VEV called the voltage of electronic volume is determined by Eq. 2, where the parameter α is the value
selected by instruction, "Set Reference Voltage Register", within the range 0 to 31. VREF voltage at Ta = 25°C is
shown in table 15-1.
Rb
V0 = ( 1 +  ) x VEV [V] ------ (Eq. 1)
Ra
(31 - α)
VEV = ( 1 -  ) x VREF [V] ------ (Eq. 2)
150
Table 15-1. VREF Voltage at Ta = 25°C
TEMPS
Temp. coefficient
VREF [V]
L
-0.05% / °C
1.9
H
-0.2% / °C
2.1
Table 15-2. Reference Voltage Parameter (α)
24
SV4
SV3
SV2
SV1
SV0
Reference voltage parameter (α)
0
0
0
0
0
0
0
0
0
0
1
1
:
:
:
:
:
:
:
:
:
:
:
:
1
1
1
1
0
30
1
1
1
1
1
31
S6B0715
33 COM / 100 SEG DRIVER & CONTROLLER FOR STN LCD
VOUT
+
V EV
V0
Rb
VR
Ra
V SS
GND
Figure 14. Internal Voltage Regulator Circuit
25
33 COM / 100 SEG DRIVER & CONTROLLER FOR STN LCD
S6B0715
In Case of Using External Resistors, Ra and Rb
It is necessary to connect external regulator resistor Ra between VR and VSS, and Rb between V0 and VR.
Example: For the following requirements
1. LCD driver voltage, V0 = 8V
2. 5-bit reference voltage register = (1, 1, 1, 1, 1)
3. Maximum current flowing Ra, Rb = 1 uA
From Eq. 1
Rb
8 = ( 1 +  ) x VEV [V] ------ (Eq. 3)
Ra
From Eq. 2
(31 - 31)
VEV = ( 1 -  ) x 1.9 = 1.9 [V] ------ (Eq. 4)
150
From requirement 3.
8
 = 1 [uA] ------ (Eq. 5)
Ra + Rb
From equations Eq. 3, 4 and 5
Ra = 1.9 [MΩ]
Rb = 6.1 [MΩ]
The following table shows the range of V0 depending on the above requirements.
Table 16. V0 depending on Electronic Volume Level
Electronic volume level
V0
26
0
.......
16
.......
31
6.33
.......
7.19
.......
8
S6B0715
33 COM / 100 SEG DRIVER & CONTROLLER FOR STN LCD
Voltage Follower Circuits
VLCD voltage (V0) is resistively divided into four voltage levels (V1, V2, V3 and V4) and those output impedance are
converted by the Voltage Follower for increasing drive capability. Table 17 shows the relationship between V1 to V4
level and bias.
Table 17. The Relationship between V1 to V4 Level and Bias
Duty ratio
1/33
LCD bias
V1
V2
V3
V4
1/6
(5/6) x V0
(4/6) x V0
(2/6) x V0
(1/6) x V0
1/5
(4/5) x V0
(3/5) x V0
(2/5) x V0
(1/5) x V0
27
33 COM / 100 SEG DRIVER & CONTROLLER FOR STN LCD
S6B0715
REFERECE CIRCUIT EXAMPLES
VDD
VDD
External
Power
Supply
VOUT
C3+
C3C2+
C2C1+
C1-
C1
C1
C1
Ra
C2
C2
C2
C2
C2
MS
MS
C1
-
Ra
VR
Rb
+
+
+
+
+
VOUT
C3+
C3C2+
C2C1+
C1-
C2
C2
C2
C2
C2
V0
V1
V2
V3
V4
-
VR
+
+
+
+
+
Rb
V0
V1
V2
V3
V4
V SS
V SS
Figure 15. When Using all LCD Power Circuits
(4-time V/C: ON, V/R: ON, V/F: ON)
V DD
Figure 16. When not Using V/C Circuit
V DD
MS
MS
External
Power
Supply
VOUT
C3+
C3C2+
C2C1+
C1-
Value of external Capacitance
Item
Value
C1
1.0 to 4.7
C2
0.47 to 1.0
Unit
µF
VR
C2
C2
C2
C2
C2
-
+
+
+
+
+
Figure 17. When Using some LCD Power Circuits
(V/C: OFF, V/R: OFF, V/F: ON)
28
VR
V0
V1
V2
V3
V4
V SS
VOUT
C3+
C3C2+
C2C1+
C1-
External
Power
Supply
V0
V1
V2
V3
V4
V SS
Figure 18. When not Using Internal
LCD Power Supply Circuit
S6B0715
33 COM / 100 SEG DRIVER & CONTROLLER FOR STN LCD
RESET CIRCUIT
Setting RESETB to “L” or Reset instruction can initialize internal function.
When RESETB becomes “L”, following procedure is occurred.
Display ON / OFF: OFF
Entire display ON / OFF: OFF (normal)
ADC select: OFF (normal)
Reverse display ON / OFF: OFF (normal)
Power control register (VC, VR, VF) = (0, 0, 0)
LCD bias ratio: 1/6
Read-modify-write: OFF
SHL select: OFF (normal)
Static indicator mode: OFF
Display start line: 0 (first)
Column address: 0
Page address: 0
Reference voltage set: off
Reference voltage control register: (SV4, SV3, SV2, SV1, SV0) = (0, 0, 0, 0, 0)
When RESET instruction is issued, following procedure is occurred.
Read-modify-write: OFF
Static indicator mode: OFF
SHL select: 0
Display start line: 0 (first)
Column address: 0
Page address: 0
Reference voltage set: OFF
Reference voltage control register: (SV4, SV3, SV2, SV1, SV0) = (0, 0, 0, 0, 0)
While RESETB is “L” or reset instruction is executed, no instruction except read status could be accepted. Reset
status appears at DB4. After DB4 becomes ”L”, any instruction can be accepted. RESETB must be connected to the
reset pin of the MPU, and initialize the MPU and this LSI at the same time. The initialization by RESETB is essential
before used.
29
33 COM / 100 SEG DRIVER & CONTROLLER FOR STN LCD
S6B0715
INSTRUCTION DESCRIPTION
Table 18. Instruction Table
Instruction
RS
RW
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
× : Don’t care
Description
Read display data
1
1
Read data
Read data from DDRAM
Write display data
1
0
Write data
Write data into DDRAM
Read status
0
1
BUSY
ADC
ON/OFF
RESETB
0
0
0
0
Read the internal status
Display ON / OFF
0
0
1
0
1
0
1
1
1
DON
Turn ON / OFF LCD panel
When DON = 0: display OFF
When DON = 1: display ON
Initial display line
0
0
0
1
ST5
ST4
ST3
ST2
ST1
ST0
Specify DDRAM line for COM0
0
0
1
0
0
0
0
0
0
1
0
0
1
0
0
SV4
SV3
SV2
SV1
SV0
0
0
1
0
1
1
P3
P2
P1
P0
Set page address
Set reference voltage
mode
Set reference voltage
register
Set page address
Set reference voltage mode
Set reference voltage register
Set column address MSB
0
0
0
0
0
1
0
Y6
Y5
Y4
Set column address MSB
Set column address LSB
0
0
0
0
0
0
Y3
Y2
Y1
Y0
Set column address LSB
ADC select
0
0
1
0
1
0
0
0
0
ADC
Reverse display ON / OFF
0
0
1
0
1
0
0
1
1
REV
Entire display ON / OFF
0
0
1
0
1
0
0
1
0
EON
LCD bias select
0
0
1
0
1
0
0
0
1
BIAS
Select LCD bias
Set modify-read
0
0
1
1
1
0
0
0
0
0
Set modify-read mode
Reset modify-read
0
0
1
1
1
0
1
1
1
0
release modify-read mode
Reset
0
0
1
1
1
0
0
0
1
0
Initialize the internal functions
Select COM output direction
When SHL = 0: normal direction
(COM0→COM31)
When SHL = 1: reverse direction
(COM31→COM0)
SHL select
0
0
1
1
0
0
SHL
×
×
×
Power control
0
0
0
0
1
0
1
VC
VR
VF
Set static indicator register
0
0
1
0
1
0
1
1
0
SI
Power save
-
-
-
-
-
-
-
-
-
-
Test instruction
0
0
1
1
1
1
×
×
×
×
30
Select SEG output direction
When ADC = 0: normal direction
(SEG0→SEG99)
When ADC = 1: reverse direction
(SEG99→SEG0)
Select normal / reverse display
When REV = 0: normal display
When REV = 1: reverse display
Select normal/ entire display ON
When EON = 0: normal display.
When EON = 1: entire display
ON
Control power circuit operation
Set static indicator register
SI = 0 (OFF), SI = 1 (ON)
Compound instruction of display
OFF and entire display ON
Don't use this instruction.
S6B0715
33 COM / 100 SEG DRIVER & CONTROLLER FOR STN LCD
Read Display Data
8-bit data from Display Data RAM specified by the column address and page address could be read by this
instruction. As the column address is increased by 1 automatically after each this instruction, the
microprocessor can continuously read data from the addressed page. A dummy read is required after loading
an address into the column address register. Display data cannot be read through the serial interface.
RS
RW
1
1
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
Read data
Write Display Data
8-bit data of display data from the microprocessor can be written to the RAM location specified by the column
address and page address. The column address is increased by 1 automatically so that the microprocessor can
continuously write data to the addressed page.
RS
RW
1
0
DB7
DB6
DB5
DB4
DB3
DB2
DB0
Write data
Set Page Address
Set Page Address
Set Column Address
Set Column Address
Data Write
Dummy Data Read
Column = Column + 1
Column = Column + 1
Data Write Continue ?
DB1
YES
NO
Optional Status
Data Read
Column = Column + 1
Data Read Continue ?
YES
NO
Optional Status
Figure 19. Sequence for Writing Display Data
Figure 20. Sequence for Reading Display Data
31
33 COM / 100 SEG DRIVER & CONTROLLER FOR STN LCD
S6B0715
Read Status
Indicates the internal status of the S6B0715
RS
RW
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
1
BUSY
ADC
ON / OFF
RESETB
0
0
0
0
Flag
Description
The device is busy when internal operation or reset
Any instruction is rejected until BUSY goes Low.
0: chip is active, 1: chip is being busy.
BUSY
Indicates the relationship between RAM column address and segment driver.
0: reverse direction (SEG99 → SEG0), 1: normal direction (SEG0 → SEG99)
ADC
ON / OFF
Indicates display ON / OFF status
0: display ON, 1: display OFF
RESETB
Indicates the initialization is in progress by RESETB signal
0: chip is active, 1: chip is being reset
Display ON / OFF
Turns the display ON or OFF
RS
RW
0
0
DON = 1: display ON
DON = 0: display OFF
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
1
0
1
0
1
1
1
DON
Initial Display Line
Sets the line address of display RAM to determine the Initial Display Line. The RAM display data is displayed at
the top row (COM0 when SHL = L, COM31 when SHL = H) of LCD panel.
32
RS
RW
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
0
1
ST5
ST4
ST3
ST2
ST1
ST0
ST5
ST4
ST3
ST2
ST1
ST0
Line address
0
0
0
0
0
0
0
0
0
0
0
0
1
1
:
:
:
:
:
:
:
1
1
1
1
1
0
62
1
1
1
1
1
1
63
S6B0715
33 COM / 100 SEG DRIVER & CONTROLLER FOR STN LCD
Reference Voltage Select
Consists of 2-byte Instruction
The 1st instruction sets reference voltage mode, the 2nd one updates the contents of reference voltage
register. After second instruction, reference voltage mode is released.
The 1st Instruction: Set Reference Voltage Select Mode
RS
RW
DB7
DB6
DB5
DB4
0
0
1
0
0
The 2nd Instruction: Set Reference Voltage Register
RS
RW
DB7
DB6
DB5
DB3
DB2
DB1
DB0
0
0
0
0
1
DB4
DB3
DB2
DB1
DB0
SV4
SV3
SV2
SV1
SV0
0
0
1
0
0
SV4
SV3
SV2
SV1
SV0
Reference voltage parameter (α)
0
0
0
0
0
0
0
0
0
0
1
1
:
:
:
:
:
:
:
:
:
:
:
:
1
1
1
1
0
30
1
1
1
1
1
31
Setting Reference Voltage Start
1st Instruction for Mode Setting
2nd Instruction for Register Setting
Setting Reference Voltage End
Figure 21. Sequence for Setting the Reference Voltage
33
33 COM / 100 SEG DRIVER & CONTROLLER FOR STN LCD
S6B0715
Set Page Address
Sets the Page Address of display data RAM from the microprocessor into the Page Address register. Any RAM
data bit can be accessed when its Page Address and column address are specified. Along with the column
address, the Page Address defines the address of the display RAM to write or read display data. Changing the
Page Address doesn't effect to the display status.
RS
RW
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
1
0
1
1
P3
P2
P1
P0
P3
P2
P1
P0
Page
0
0
0
0
0
0
0
0
1
1
:
:
:
:
:
0
1
1
1
7
1
0
0
0
8
Set Column Address
Sets the Column Address of display RAM from the microprocessor into the column address register. Along with
the Column Address, the Column Address defines the address of the display RAM to write or read display data.
When the microprocessor reads or writes display data to or from display RAM, Column Addresses are
automatically increased.
Set Column Address MSB
RS
RW
DB7
0
0
0
Set Column Address LSB
RS
RW
DB7
34
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
1
0
Y6
Y5
Y4
DB6
DB5
DB4
DB3
DB2
DB1
DB0
Y2
Y1
Y0
0
0
0
0
0
0
Y3
Y6
Y5
Y4
Y3
Y2
Y1
Y0
Column address
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
:
:
:
:
:
:
:
:
1
1
0
0
0
1
0
98
1
1
0
0
0
1
1
99
S6B0715
33 COM / 100 SEG DRIVER & CONTROLLER FOR STN LCD
ADC Select
Changes the relationship between RAM column address and segment driver. The direction of segment driver
output pins could be reversed by software. This makes IC layout flexible in LCD module assembly.
RS
RW
DB7
DB6
0
0
1
0
ADC = 0: normal direction (SEG0 → SEG99)
ADC = 1: reverse direction (SEG99 → SEG0)
DB5
DB4
DB3
DB2
DB1
DB0
1
0
0
0
0
ADC
Reverse Display ON / OFF
Reverses the display status on LCD panel without rewriting the contents of the display data RAM.
RS
RW
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
1
0
1
0
0
1
1
REV
REV
RAM bit data = “1”
RAM bit data = “0”
0 (normal)
LCD pixel is illuminated
LCD pixel is not illuminated
1 (reverse)
LCD pixel is not illuminated
LCD pixel is illuminated
Reverse Display ON / OFF
Forces the whole LCD points to be turned on regardless of the contents of the display data RAM. At this time,
the contents of the display data RAM are held. This instruction has priority over the reverse display ON / OFF
instruction.
RS
RW
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
1
0
0
1
0
EON
0
0
1
EON = 0: normal display
EON = 1: entire display ON
Select LCD Bias
Selects LCD bias ratio of the voltage required for driving the LCD.
RS
RW
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
1
0
1
0
0
0
1
Bias
LCD bias
Duty
ratio
Bias = 0
Bias = 1
1/33
1/6
1/5
35
33 COM / 100 SEG DRIVER & CONTROLLER FOR STN LCD
S6B0715
Set Modify-read
This instruction stops the automatic increment of the column address by the read display data instruction, but
the column address is still increased by the write display data instruction. And it reduces the load of
microprocessor when the data of a specific area is repeatedly changed during cursor blinking or others. This
mode is canceled by the reset Modify-read instruction.
RS
RW
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
1
1
1
0
0
0
0
0
Reset Modify-read
This instruction cancels the Modify-read mode, and makes the column address return to its initial value just
before the set Modify-read instruction is started.
RS
RW
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
1
1
1
0
1
1
1
0
Set Page Address
Set Column Address (N)
Set Modify-Read
Dummy Read
Data Read
Data Process
Data Write
NO
Change Complete ?
YES
Reset Modify-Read
Return Column Address (N)
Figure 22. Sequence for Cursor Display
36
S6B0715
33 COM / 100 SEG DRIVER & CONTROLLER FOR STN LCD
Reset
This instruction Resets initial display line, column address, page address, and common output status select to
their initial status, but dose not affect the contents of display data RAM. This instruction cannot initialize the LCD
power supply, which is initialized by the RESETB pin.
RS
RW
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
1
1
1
0
0
0
1
0
SHL Select
COM output scanning direction is selected by this instruction which determines the LCD driver output status.
RS
RW
DB7
DB6
DB5
DB4
DB3
DB2
DB1
0
0
1
1
0
0
SHL
×
×
SHL = 0: normal direction (COM0 → COM31)
SHL = 1: reverse direction (COM31 → COM0)
DB0
×
× : Don’ t care
Power Control
Selects one of eight power circuit functions by using 3-bit register. An external power supply and part of internal
power supply functions can be used simultaneously.
RS
RW
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
0
0
1
0
1
VC
VR
VF
VC
VR
VF
Status of internal power supply circuits
0
1
Internal voltage converter circuit is OFF
Internal voltage converter circuit is ON
0
1
Internal voltage regulator circuit is OFF
Internal voltage regulator circuit is ON
0
1
Internal voltage follower circuit is OFF
Internal voltage follower circuit is ON
Set Static Indicator State
This instruction sets the Static Indicator ON / OFF. When it is on, the static indicator operates and blinks at an
interval of approximately 1second.
Set Static Indicator Register
RS
RW
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
1
0
1
0
1
1
0
SI
SI
Status of static indicator output
0
OFF
1
ON (about 1 second blinking)
37
33 COM / 100 SEG DRIVER & CONTROLLER FOR STN LCD
S6B0715
Power Save (Compound Instruction)
If the entire display ON / OFF instruction is issued during the display OFF state, S6B0715 enters the Power
Save status to reduce the power consumption to the static power consumption value. According to the status of
static indicator mode, Power Save is entered to one of two modes (sleep and standby mode). When static
indicator mode is ON, standby mode is issued, when OFF, sleep mode is issued. Power Save mode is released
by the display ON & entire display OFF instruction.
Static Indicator OFF
Static Indicator ON
Power Save (Compound Instruction)
[Display OFF]
[Entire Display ON]
Sleep Mode
[Oscillator Circuit: OFF]
[LCD Power Supply Circuit: OFF]
[All COM / SEG Outputs: VSS]
[Consumption Current: < 2µA]
Standby Mode
[Oscillator Circuit: ON]
[LCD Power Supply Circuit: OFF]
[All COM / SEG Outputs: VSS]
[Consumption Current: < 10µA]
Power Save OFF (Compound Instruction)
[Entire Display OFF]
[Static Indicator ON]
[Display ON]
Power Save OFF (Compound Instruction)
[Entire Display OFF]
[Display ON]
Release Sleep Mode
Release Standby Mode
Figure 23. Power Save Routine
38
S6B0715
33 COM / 100 SEG DRIVER & CONTROLLER FOR STN LCD
Referential Instruction Setup Flow (1)
User System Setup by External Pins
Start of Initialization
Power ON (VDD - VSS) Keeping the RESETB Pin = “L”
Waiting for Stabilizing the Power
RESETB Pin = “H”
User Application Setup by Internal Instructions
[ADC Select]
[SHL Select]
[LCD Bias Select]
User LCD Power Setup by Internal Instructions
[Reference Voltage Register Set]
User LCD Power Setup by Internal Instructions
[Voltage Converter ON]
Waiting for ≥ 1ms
User LCD Power Setup by Internal Instructions
[Voltage Regulator ON]
Waiting for ≥ 1ms
User LCD Power Setup by Internal Instructions
[Voltage Follower ON]
Waiting for Stabilizing the LCD Power Levels
End of Initialization
Figure 24. Initializing with the Built-in Power Supply Circuits
39
33 COM / 100 SEG DRIVER & CONTROLLER FOR STN LCD
Referential Instruction Setup Flow (2)
User System Setup by External Pins
Start of Initialization
Power ON (VDD - VSS) Keeping the RESETB Pin = “L”
Waiting for Stabilizing the Power
RESETB Pin = “H”
Set Power Save
User Application Setup by Internal Instructions
[ADC Select]
[SHL Select]
[LCD Bias Select]
User LCD Power Setup by Internal Instructions
[Reference Voltage Register Set]
Release Power Save
Waiting for Stabilizing the LCD Power Levels
End of Initialization
Figure 25. Initializing without the Built-in Power Supply Circuits
40
S6B0715
S6B0715
33 COM / 100 SEG DRIVER & CONTROLLER FOR STN LCD
Referential Instruction Setup Flow (3)
End of Initialization
Display Data RAM Addressing by Instruction
[Initial Display Line]
[Set Page Address]
[Set Column Address]
Write Display ON / OFF by Instruction
[Display ON / OFF]
Turn Display ON / OFF by Instruction
[Display ON / OFF]
End of Data Display
Figure 26. Data Displaying
41
33 COM / 100 SEG DRIVER & CONTROLLER FOR STN LCD
S6B0715
Referential Instruction Setup Flow (4)
Optional Status
Turn Display ON / OFF by Instruction
[Display OFF]
User LCD Power Setup by Internal Instructions
[Voltage Regulator OFF]
Waiting for ≥ 50ms
User LCD Power Setup by Internal Instructions
[Voltage Follower OFF]
Waiting for ≥ 1ms
User LCD Power Setup by Internal Instructions
[Voltage Converter OFF]
Waiting for ≥ 1ms
Power OFF (VDD-VSS)
Figure 27. Power OFF
42
S6B0715
33 COM / 100 SEG DRIVER & CONTROLLER FOR STN LCD
SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS
Table 19. Absolute Maximum Ratings
Parameter
Symbol
Rating
Unit
VDD
- 0.3 to +7.0
V
VLCD
- 0.3 to +17.0
V
Input voltage range
VIN
- 0.3 to VDD +0.3
V
Operating temperature range
TOPR
- 40 to +85
°C
Storage temperature range
TSTR
- 55 to +125
°C
Supply voltage range
NOTES:
1. VDD and VLCD are based on VSS = 0V.
2. Voltages V0 ≥ V1 ≥ V2 ≥ V3 ≥ V4 ≥ VSS must always be satisfied. (VLCD = V0 – VSS)
3. If supply voltage exceeds its absolute maximum range, this LSI may be damaged permanently.
It is desirable to use this LSI under electrical characteristic conditions during general operation.
Otherwise, this LSI may malfunction or reduced LSI reliability may result.
43
33 COM / 100 SEG DRIVER & CONTROLLER FOR STN LCD
S6B0715
DC CHARACTERISTICS
Table 20. DC Characteristics
( VSS = 0V, VDD = 2.4 to 3.6V, Ta = -40 to 85°C )
Item
Symbol
Operating voltage (1)
Min.
Typ.
Max.
Unit
Pin used
VDD
2.4
-
3.6
V
VDD *1
Operating voltage (2)
V0
4.0
-
15.0
V
V0 *2
High
VIH
0.8VDD
-
VDD
V
*3
Low
VIL
VSS
-
0.2VDD
High
VOH
IOH = -0.5mA
0.8VDD
-
VDD
V
*4
Low
VOL
IOL = 0.5mA
VSS
-
0.2VDD
Input leakage current
IIL
VIN = VDD or VSS
- 1.0
-
+ 1.0
µA
*5
Output leakage current
IOZ
VIN = VDD or VSS
- 3.0
-
+ 3.0
µA
*6
LCD driver ON
resistance
RON
Ta = 25°C, V0 = 8V
-
2.0
3.0
kΩ
SEGn
COMn *7
17
22.5
27
2.13
2.81
3.37
kHz
CL *8
×2
2.4
-
3.6
×3
2.4
-
3.6
V
VDD
×4
2.4
-
3.6
×2 / ×3 / ×4
voltage conversion
(no-load )
95
99
-
%
VOUT
Input voltage
Output
voltage
Oscillator
frequency (1)
Internal
f OSC
External
f CL
Voltage converter
input voltage
Ta = 25°C
Voltage converter
output voltage
VOUT
Voltage regulator
operating voltage
VOUT
4.0
-
15.0
V
VOUT
Voltage follower
operating voltage
V0
4.0
-
15.0
V
V0 *9
-0.05%/°C
1.84
1.9
1.96
V
*10
-0.2%/°C
2.04
2.1
2.16
V
*10
Reference voltage
44
VDD
Condition
VREF0
VREF1
Ta = 25°C
S6B0715
33 COM / 100 SEG DRIVER & CONTROLLER FOR STN LCD
Dynamic Current Consumption (1): when the Built-in Power Circuit is OFF (At Operate Mode)
Item
Symbol
Condition
Min.
Typ.
Max.
Dynamic current
consumption (1)
IDD1
VDD = 3.0V
V0 – VSS = 8.0V
Display OFF, checker pattern
-
5
20
(Ta = 25°C)
Unit Pin used
µΑ
*11
Dynamic Current Consumption (2): when the built-in power circuit is ON (At operate mode)
Item
Dynamic current
consumption (2)
Symbol
Condition
Min.
Typ.
Max.
-
47
70
IDD2
VDD = 3.0V,
quad boosting,
V0 – VSS = 8.0V,
1/65 duty ratio,
Display OFF, checker pattern
Normal power mode
VDD = 3.0V,
quad boosting,
V0 – VSS = 8.0V,
Display ON, checker pattern
Normal power mode
-
(Ta = 25°C)
Unit Pin used
µΑ
75
*12
100
Current Consumption during Power Save mode
(Ta = 25°C)
Item
Symbol
Condition
Min.
Typ.
Max.
Unit
Sleep mode
IDDS1
During sleep
-
-
2.0
µA
Standby mode
IDDS2
During standby
-
-
10.0
µA
Pin used
45
33 COM / 100 SEG DRIVER & CONTROLLER FOR STN LCD
S6B0715
Table 21. The relationship between oscillation frequency and frame frequency
Duty ratio
Item
fCL
On-chip oscillator circuit is
used
fOSC
fOSC


8
16 × 33
On-chip oscillator circuit is
not used
External input (fCL)

1/33
fM
fOSC
2 × 33
(fOSC: oscillation frequency, fCL: display clock frequency, fM: LCD AC signal frequency)
[* Remark Solves]
*1. Though the wide range of operating voltages is guaranteed, a spike voltage change may affect the voltage
assurance during access from the MPU.
*2. In case of external power supply is applied.
*3. CS1B, CS2, RS, DB0 to DB7, E_RD, RW_WR, RESETB, MS, MI, PS, TEMPS, CL, M, DISP pins.
*4. DB0 to DB7, M, FRS, DISP, CL pins.
*5. CS1B, CS2, RS, DB[7:0], E_RD, RW_WR, RESETB, MS, MI, PS, TEMPS, CL, M, DISP pins.
*6. Applies when the DB[7:0], M, DISP, and CL pins are in high impedance.
*7. Resistance value when ± 0.1[mA] is applied during the ON status of the output pin SEGn or COMn.
RON= ∆V / 0.1 [kΩ] (∆V: voltage change when ± 0.1[mA] is applied in the ON status.)
*8. See table 21 for the relationship between oscillation frequency and frame frequency.
*9. The voltage regulator circuit adjusts V0 within the voltage follower operating voltage range.
*10. On-chip reference voltage source of the voltage regulator circuit to adjust V0.
*11,12. Applies to the case where the on-chip oscillation circuit is used and no access is made from the MPU.
The current consumption, when the built-in power supply circuit is ON or OFF.
The current flowing through voltage regulation resistors (Ra and Rb) is not included.
It does not include the current of the LCD panel capacity, wiring capacity, etc.
46
S6B0715
33 COM / 100 SEG DRIVER & CONTROLLER FOR STN LCD
REFERENCE DATA
IDD1 vs. VDD
l
Test Condition: Temperature (25°C & 85°C), V0 = 8V (External), TEMPS = 'L', 1/33 Duty, Ra = 1 [MΩ],
Rb = 3 [MΩ], Normal Power Mode
VDD vs. IDD1(Pattern OFF)
12.00
10.00
8.00
IDD1
6.00
[uA]
4.00
8.0V, 1/33 Duty (25°C)
8.0V, 1/33 Duty (85°C)
2.00
0.00
2.7
3.0
3.3
3.6
4.0
4.5
5.0
5.5
VDD [V]
Figure 28. Display Pattern is OFF
47
33 COM / 100 SEG DRIVER & CONTROLLER FOR STN LCD
S6B0715
IDD2 vs. VDD
l
Test Condition: Temperature (25°C & 85°C), Quad boosting, RR = 6, EV = 32, TEMPS = 'L', 1/33 duty,
Ra = 1 [MΩ], Rb = 3 [MΩ], Normal Power Mode
VDD vs. IDD2 (Pattern OFF)
50.00
45.00
40.00
35.00
30.00
IDD2
25.00
[uA]
20.00
15.00
10.00
5.00
0.00
1/33 Duty (25°C)
1/33 Duty (85°C)
2.7
3.0
3.3
3.6
4.0
4.5
5.0
5.5
VDD [V]
Figure 29. Display Pattern is OFF
VDD vs. IDD2 (Checker Pattern)
250.00
200.00
IDD2
[uA]
150.00
1/33 Duty (25°C )
1/33 Duty (85°C )
100.00
50.00
0.00
2.7
3.0
3.3
3.6
4.0
4.5
5.0
5.5
VDD [V]
Figure 30. Display Pattern is Checker
48
S6B0715
33 COM / 100 SEG DRIVER & CONTROLLER FOR STN LCD
AC CHARACTERISTICS
Read / Write Characteristics (8080-series MPU)
RS
tAS80
tAH80
CS1B
(CS2 = 1)
tCY80
tPW80(R),
RD, WR
0.9V DD
tPW80(W)
0.1VDD
tDS80
tDH80
DB0 to DB7
(Write)
tACC80
tOD80
DB6 to DB7
(Read)
Figure 31. Read / Write Characteristics (8080-series MPU)
Item
Address setup time
Address hold time
System cycle time
Pulse width (WR)
Pulse width (RD)
Data setup time
Data hold time
Read access time
Output disable time
Signal
RS
RS
RW_WR
E_RD
DB7
to
DB0
Symbol
tAS80
tAH80
tCY80
tPW80(W)
tPW80(R)
tDS80
tDH80
tACC80
tOD80
Min.
13
17
400
55
125
35
13
10
Typ.
(VDD = 2.4 to 3.6V, Ta = -40 to +85°C)
Max.
Unit
Remark
-
-
ns
-
-
ns
ns
ns
-
-
ns
-
125
90
ns
CL = 100 pF
49
33 COM / 100 SEG DRIVER & CONTROLLER FOR STN LCD
S6B0715
Read / Write Characteristics (6800-series Microprocessor)
RS
tAS68
tAH68
CS1B
(CS2 = 1)
tCY68
tPW68(R), tPW68(W)
E
0.1VDD
0.9VDD
tDS68
tDH68
DB0 to DB7
(Write)
tACC68
tOD68
DB0 to DB7
(Read)
Figure 32. Read / Write Characteristics (6800-series Microprocessor)
Item
Address setup time
Address hold time
Signal
System cycle time
RS
Data setup time
Data hold time
Access time
Output disable time
Read
Enable pulse width
Write
50
RS
DB7
to
DB0
E_RD
Symbol
tAS68
tAH68
Min.
13
17
tCY68
400
tDS68
tDH68
tACC68
tOD68
tPW68(R)
tPW68(W)
35
13
10
125
55
(VDD = 2.4 to 3.6V, Ta = -40 to +85°C)
Typ.
Max.
Unit
Remark
-
-
ns
-
-
ns
-
-
ns
-
125
90
ns
-
-
-
CL = 100 pF
S6B0715
33 COM / 100 SEG DRIVER & CONTROLLER FOR STN LCD
Serial Interface Characteristics
tCSS
CS1B
(CS2 = 1)
tCHS
tASS
tAHS
RS
tCYS
DB6
(SCLK)
0.9VDD
0.1VDD
tWLS
tWHS
tDSS
tDHS
DB7
(SID)
Figure 33. Serial Interface Characteristics
Item
Signal
Serial clock cycle
SCLK high pulse width
SCLK low pulse width
(VDD = 2.4 to 3.6V, Ta = -40 to +85°C )
Max
Unit
Remark
Min
Typ
DB6
(SCLK)
Symbol
tCYS
tWHS
tWLS
450
180
135
-
-
ns
Address setup time
Address hold time
RS
tASS
tAHS
90
360
-
-
ns
Data setup time
Data hold time
DB7
(SID)
tDSS
tDHS
90
90
-
-
ns
CS1B setup time
CS1B hold time
CS1B
tCSS
tCHS
55
180
-
-
ns
51
33 COM / 100 SEG DRIVER & CONTROLLER FOR STN LCD
S6B0715
Reset Input Timing
tRW
RESETB
Figure 34. Reset Input Timing
Item
Signal
Symbol
Min.
Reset low pulse width
RESETB
tRW
900
(VDD = 2.4 to 3.6V, Ta = -40 to +85°C)
Typ.
Remark
Max.
Unit
-
-
ns
Display Control Output Timing
tDM
CL
M
Figure 35. Display Control Output Timing
52
Item
Signal
Symbol
Min.
Typ.
M delay time
M
tDM
-
13
(VDD = 2.4 to 3.6V, Ta = -40 to +85°C)
Remark
Max.
Unit
70
ns
S6B0715
33 COM / 100 SEG DRIVER & CONTROLLER FOR STN LCD
REFERENCE APPLICATIONS
MICROPROCESSOR INTERFACE
IN CASE OF INTERFACING WITH 6800-SERIES (PS = “H”, MI = “H”)
CS1B
CS2
RS
6800-series
CS2
RS
E
RW
DB0 to DB7
MPU
CS1B
RESETB
E_RD
KS0715
RW_WR
DB0 to DB7
RESETB
VDD
MI
VDD
PS
Figure 36. Interfacing with 6800-series (PS = “H”, MI = “H”)
In Case of Interfacing with 8080-series (PS = “H”, MI = “L”)
8080-series
MPU
CS1B
CS2
RS
/R D
/W R
DB0 to DB7
RESETB
VSS
VDD
CS1B
CS2
RS
S6B0715
E_RD
RW_WR
DB0 to DB7
RESETB
MI
PS
Figure 37. Interfacing with 8080-series (PS = “H”, MI = “L”)
In Case of Serial Interface (PS = “L”, MI = “H/L”)
CS1B
CS2
RS
SID
MPU
SCLK
RESETB
OPEN
V DD or VSS
VSS
CS1B
CS2
RS
DB7(SID)
S6B0715
DB6(SCLK)
RESETB
DB0 to DB5
MI
PS
Figure 38. Serial Interface (PS = “L”, MI = “H/L”)
53
33 COM / 100 SEG DRIVER & CONTROLLER FOR STN LCD
S6B0715
CONNECTIONS BETWEEN S6B0715 AND LCD PANEL
Single Chip Configuration (1/33 Duty Configurations)
COMS
COM31
:
COM16
COM15
:
COM0
COMS
S6B0715
(Bottom View)
SEG99
...........
♣
♦
♥
♠
SEG0
Ξ
COM15
:
COM0
COMS
SEG0
♦
♥
♠
♣
Ξ
♦
♥
♠

Ξ
♣
SEG0
COMS
COM0
:
COM15
♦
♥
♠
Ξ
...........
S6B0715
(Bottom View)
♣

♠
Ξ

♦
♥
♠
Ξ

♦
♥
♠
Ξ

32 × 100 pixels
♣

SEG99
COM16
:
COM31
COMS
Figure 41. SHL = 1, ADC = 0
54
♥
Figure 40. SHL = 0, ADC = 0
32 × 100 pixels
♣
♦
SEG99
32 × 100 pixels
Figure 39. SHL = 0, ADC = 1
♣
............

32 × 100 pixels
♣
COMS
COM31
:
COM16
S6B0715
(Top View)
SEG99
COM16
:
COM31
COMS
♦
♥
♠
Ξ
...........
S6B0715
(Top View)

SEG0
COMS
COM0
:
COM15
Figure 42. SHL = 1, ADC = 1
S6B0715
33 COM / 100 SEG DRIVER & CONTROLLER FOR STN LCD
Multiple Chip Configuration
-
33COM (32COM + 1COMS) × 200SEG (100SEG × 2)
COMS
COM31
:
COM16
SEG99
...................
COMS
COM31
:
COM16
COM15
:
COM0
COMS
S6B0715
( Bottom View )
( Master )
SEG0
SEG99
♣
♦
♥
♠
Ξ
S6B0715
( Bottom View )
( Slave )
...................
COM15
:
COM0
COMS
SEG0

32 × 200 pixels
♣
♦
♥
♠
Ξ

Figure 43. SHL = 0, ADC = 1
♦ Connect the following pins of two chips each other
- Display clock pins: CL, M
- Display control pin: DISP
- LCD power pins: V0, V1, V2, V3, V4
♣
♦
♥
♠
Ξ

32 × 200 pixels
♣
SEG0
COMS
COM0
:
COM15
...............
S6B0715
( Bottom View )
( Master )
♦
SEG99
COM16
:
COM31
COMS
♥
♠
Ξ

SEG0
COMS
COM0
:
COM15
...............
S6B0715
( Bottom View )
( Slave )
SEG99
COM16
:
COM31
COMS
Figure 44. SHL = 1, ADC = 0
♦ Connect the following pins of two chips each other
- Display clock pins: CL, M
- Display control pin: DISP
- LCD power pins: V0, V1, V2, V3, V4
55
33 COM / 100 SEG DRIVER & CONTROLLER FOR STN LCD
-
S6B0715
66COM (64COM + 2COMS) × 100SEG
COM15
:
COM0
COMS
COMS
COM31
:
COM16
S6B0715
( Top View )
( Master )
SEG0
...................
♣
♦
♥
♠
Ξ
SEG99

64 × 100 pixels
♣
SEG99
COM16
:
COM31
COMS
♦
♥
♠
Ξ
...................

SEG0
S6B0715
( Top View )
( Slave )
COMS
COM0
:
COM15
Figure 45. 66COM (64COM + 2COMS) × 100SEG
♦ Connect the following pins of two chips each other
- Display clock pins: CL, M
- Display control pin: DISP
- LCD power pins: V0, V1, V2, V3, V4
♦ Common / Segment output direction select
- Master chip: SHL = 0, ADC = 0
- Slave chip: SHL = 1, ADC = 1
56
S6B0715
33 COM / 100 SEG DRIVER & CONTROLLER FOR STN LCD
TCP PIN LAYOUT (SAMPLE)
S6B0715
(TOP VIEW)
FRS
M
CL
DISP
MS
RESETB
PS
CS1B
CS2
MI
RS
RW_WR
E_RD
VDD
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
VSS
VOUT
C3+
C3C1+
C1C2+
C2VSS
VR
V0
V1
V2
V3
V4
VSS
TEMPS
COMS
COM31
COM30
:
:
:
COM26
COM25
COM24
:
:
:
COM19
COM18
COM17
COM16
SEG99
SEG98
SEG97
SEG96
:
:
:
:
SEG66
SEG65
SEG64
SEG63
:
:
:
:
SEG3
SEG2
SEG1
SEG0
COMS
COM0
COM1
:
:
:
COM7
COM8
COM9
:
:
:
COM13
COM14
COM15
COMS
Figure 46. TCP Pin Layout
57