Revised August 2000 74AC273 • 74ACT273 Octal D-Type Flip-Flop General Description Features The AC273 and ACT273 have eight edge-triggered D-type flip-flops with individual D-type inputs and Q outputs. The common buffered Clock (CP) and Master Reset (MR) input load and reset (clear) all flip-flops simultaneously. ■ Ideal buffer for microprocessor or memory The register is fully edge-triggered. The state of each Dtype input, one setup time before the LOW-to-HIGH clock transition, is transferred to the corresponding flip-flop’s Q output. All outputs will be forced LOW independently of Clock or Data inputs by a LOW voltage level on the MR input. The device is useful for applications where the true output only is required and the Clock and Master Reset are common to all storage elements. ■ Eight edge-triggered D-type flip-flops ■ Buffered common clock ■ Buffered, asynchronous master reset ■ See 377 for clock enable version ■ See 373 for transparent latch version ■ See 374 for 3-STATE version ■ Outputs source/sink 24 mA ■ 74ACT273 has TTL-compatible inputs Ordering Code: Order Number 74AC273SC 74AC273SJ 74AC273MTC Package Number Package Description M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide MTC20 74AC273PC 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide 74ACT273SC M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide 74ACT273SJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74ACT273MTC MTC20 74ACT273PC N20A 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Logic Symbols Connection Diagram IEEE/IEC FACT is a trademark of Fairchild Semiconductor Corporation. © 2000 Fairchild Semiconductor Corporation DS009954 www.fairchildsemi.com 74AC273 • 74ACT273 Octal D-Type Flip-Flop November 1988 74AC273 • 74ACT273 Pin Descriptions Pin Names Mode Select-Function Table Description Inputs Outputs Operating Mode D0–D7 Data Inputs MR CP Dn MR Master Reset Reset (Clear) L X X L CP Clock Pulse Input Load ‘1' H H H Q0–Q7 Data Outputs Load ‘0' H L L H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial = LOW-to-HIGH Transition Logic Diagram Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. www.fairchildsemi.com 2 Qn Supply Voltage (VCC) Recommended Operating Conditions −0.5V to +7.0V DC Input Diode Current (IIK) VI = −0.5V −20 mA VI = VCC + 0.5V +20 mA DC Input Voltage (VI) Supply Voltage (VCC) −0.5V to VCC + 0.5V VO = VCC + 0.5V +20 mA 0V to VCC −40°C to +85°C Minimum Input Edge Rate (∆V/∆t) AC Devices DC Output Source VIN from 30% to 70% of VCC ± 50 mA VCC @ 3.3V, 4.5V, 5.5V for AC 125 mV/ns Minimum Input Edge Rate (∆V/∆t) DC VCC or Ground Current ± 50 mA per Output Pin (ICC or IGND) Storage Temperature (TSTG) 0V to VCC Operating Temperature (TA) −0.5V to VCC + 0.5V or Sink Current (IO) 4.5V to 5.5V Output Voltage (VO) −20 mA DC Output Voltage (VO) 2.0V to 6.0V ACT Input Voltage (VI) DC Output Diode Current (IOK) VO = −0.5V AC ACT Devices −65°C to +150°C VIN from 0.8V to 2.0V Junction Temperature (TJ) VCC @ 4.5V, 5.5V for ACT 140°C (PDIP) 125 mV/ns Note 1: Absolute maximum ratings are those values beyond which damage to the device may occur. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. Fairchild does not recommend operation of FACT circuits outside databook specifications. DC Electrical Characteristics for AC Symbol VIH VIL VOH Parameter TA = +25°C VCC TA = −40°C to +85°C (V) Typ Guaranteed Limits Minimum HIGH Level 3.0 1.5 Input Voltage 4.5 2.25 3.15 3.15 5.5 2.75 3.85 3.85 2.1 Units Maximum LOW Level 3.0 1.5 0.9 0.9 Input Voltage 4.5 2.25 1.35 1.35 5.5 2.75 1.65 1.65 Minimum HIGH Level 3.0 2.99 2.9 2.9 Output Voltage 4.5 4.49 4.4 4.4 5.5 5.49 5.4 5.4 3.0 2.56 2.46 4.5 3.86 3.76 5.5 4.86 4.76 Conditions VOUT = 0.1V 2.1 V or VCC − 0.1V VOUT = 0.1V V or VCC − 0.1V V IOUT = −50 µA VIN = VIL or VIH VOL Maximum LOW Level 3.0 0.002 0.1 0.1 Output Voltage 4.5 0.001 0.1 0.1 5.5 0.001 0.1 0.1 3.0 0.36 0.44 4.5 0.36 0.44 5.5 0.36 0.44 5.5 ±0.1 IOH = −12 mA V IOH = −24 mA IOH = −24 mA (Note 2) V IOUT = 50 µA VIN = VIL or VIH IOL = 12 mA V IOL = 24 mA IOL = 24 mA (Note 2) IIN Maximum Input (Note 4) Leakage Current ±1.0 µA VI = VCC, GND IOLD Minimum Dynamic 5.5 75 mA VOLD = 1.65V Max IOHD Output Current (Note 3) 5.5 −75 mA ICC Maximum Quiescent (Note 4) Supply Current 5.5 4.0 40.0 µA VOHD = 3.85V Min VIN = VCC or GND Note 2: All outputs loaded; thresholds on input associated with output under test. Note 3: Maximum test duration 2.0 ms, one output loaded at a time. Note 4: IIN and ICC @ 3.0V are guaranteed to be less than or equal to the respective limit @ 5.5V VCC. 3 www.fairchildsemi.com 74AC273 • 74ACT273 Absolute Maximum Ratings(Note 1) 74AC273 • 74ACT273 AC Electrical Characteristics for AC Symbol Parameter VCC TA = +25°C (V) CL = 50 pF (Note 5) fMAX tPLH tPHL tPHL Min Typ TA = −40°C to +85°C CL = 50 pF Max Min Units Max Maximum Clock 3.3 90 125 75 Frequency 5.0 140 175 125 Propagation Delay 3.3 4.0 7.0 12.5 3.0 14.0 Clock to Output 5.0 3.0 5.5 9.0 2.5 10.0 Propagation Delay 3.3 4.0 7.0 13.0 3.5 14.5 Clock to Output 5.0 3.0 5.0 10.0 2.5 11.0 Propagation Delay 3.3 4.0 7.0 13.0 3.5 14.0 MR to Output 5.0 3.0 5.0 10.0 2.5 10.5 MHz ns ns ns Note 5: Voltage Range 3.3 is 3.3V ± 0.3V Voltage Range 5.0 is 5.0V ± 0.5V AC Operating Requirements for AC TA = +25°C VCC Symbol tS tH tW tW trec Parameter TA = −40°C to +85°C CL = 50 pF (V) CL = 50 pF (Note 6) Typ Setup Time, HIGH or LOW 3.3 3.5 5.5 6.0 Data to CP 5.0 2.5 4.0 4.5 Units Guaranteed Minimum ns Hold Time, HIGH or LOW 3.3 −2.0 0 0 Data to CP 5.0 −1.0 1.0 1.0 Clock Pulse Width 3.3 3.5 5.5 6.0 HIGH or LOW 5.0 2.5 4.0 4.5 ns ns MR Pulse Width 3.3 2.0 5.5 6.0 HIGH or LOW 5.0 1.5 4.0 4.5 Recovery Time 3.3 1.5 3.5 4.5 MR to CP 5.0 1.0 2.0 3.0 ns ns Note 6: Voltage Range 3.3 is 3.3V ± 0.3V Voltage Range 5.0 is 5.0V ± 0.5V www.fairchildsemi.com 4 Symbol VIH VIL VOH Parameter Minimum HIGH Level TA = +25°C VCC (V) Typ 4.5 1.5 TA = −40°C to +85°C Guaranteed Limits 2.0 2.0 Input Voltage 5.5 1.5 2.0 2.0 Maximum LOW Level 4.5 1.5 0.8 0.8 Input Voltage 5.5 1.5 0.8 0.8 Minimum HIGH Level 4.5 4.49 4.4 4.4 Output Voltage 5.5 5.49 5.4 5.4 3.86 3.76 Units V V Conditions VOUT = 0.1V or VCC − 0.1V VOUT = 0.1V or VCC − 0.1V V IOUT = −50 µA V IOH = −24 mA VIN = VIL or VIH 4.5 5.5 VOL 4.86 4.76 Maximum LOW Level 4.5 0.001 0.1 0.1 Output Voltage 5.5 0.001 0.1 0.1 4.5 0.36 0.44 5.5 0.36 0.44 5.5 ±0.1 ±1.0 IOH = −24 mA (Note 7) V IOUT = 50 µA V IOL = 24 mA VIN = VIL or VIH IIN Maximum Input Leakage Current ICCT Maximum IOL = 24 mA (Note 7) µA VI = VCC, GND 1.5 mA VI = VCC − 2.1V IOLD Minimum Dynamic 5.5 75 mA VOLD = 1.65V Max IOHD Output Current (Note 8) 5.5 −75 mA ICC Maximum Quiescent 5.5 ICC/Input Supply Current 0.6 5.5 4.0 µA 40.0 VOHD = 3.85V Min VIN = VCC or GND Note 7: All outputs loaded; thresholds on input associated with output under test. Note 8: Maximum test duration 2.0 ms, one output loaded at a time. AC Electrical Characteristics for ACT Symbol Parameter fMAX Maximum Clock Frequency tPLH Propagation Delay tPHL CP to Qn tPHL Propagation Delay MR to Qn VCC TA = +25°C (V) CL = 50 pF TA = −40°C to +85°C CL = 50 pF Max Min Units (Note 9) Min Typ Max 2.0 125 189 5.0 1.5 6.5 8.5 1.5 9.0 ns 5.0 1.5 7.0 9.0 1.5 8.5 ns 110 MHz Note 9: Voltage Range 5.0 is 5.0V ± 0.5V 5 www.fairchildsemi.com 74AC273 • 74ACT273 DC Electrical Characteristics for ACT 74AC273 • 74ACT273 AC Operating Requirements for ACT Symbol Parameter VCC TA = +25°C (V) CL = 50 pF TA = −40°C to +85°C CL = 50 pF Units (Note 10) Typ Guaranteed Minimum 5.0 1.0 3.5 3.5 ns 5.0 −0.5 1.5 1.5 ns 5.0 2.0 4.0 4.0 ns 5.0 1.5 4.0 4.0 ns 5.0 0.5 3.0 3.0 ns Setup Time, HIGH or LOW tS Dn to CP tH Hold Time, HIGH or LOW Dn to CP tW Clock Pulse Width HIGH or LOW tW MR Pulse Width HIGH or LOW tW Recovery Time MR to CP Note 10: Voltage Range 5.0 is 5.0V ± 0.5V Capacitance Symbol CIN CPD Typ Units Conditions Input Capacitance Parameter 4.5 pF VCC = OPEN Power Dissipation Capacitance for AC 50.0 Power Dissipation Capacitance for ACT 40.0 pF VCC = 5.0V www.fairchildsemi.com 6 74AC273 • 74ACT273 Physical Dimensions inches (millimeters) unless otherwise noted 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide Package Number M20B 7 www.fairchildsemi.com 74AC273 • 74ACT273 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M20D www.fairchildsemi.com 8 74AC273 • 74ACT273 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC20 9 www.fairchildsemi.com 74AC273 • 74ACT273 Octal D-Type Flip-Flop Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Package Number N20A Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com www.fairchildsemi.com 10