Ordering number : EN5804A CMOS IC LC3564B, BS, BM, BT-70/10 64K (8192-word × 8-bit) SRAM with OE, CE1, and CE2 Control Pins Overview The LC3564B, LC3564BS, LC3564BM, and LC3564BT are 8192-word × 8-bit asynchronous silicon gate CMOS SRAMs. These are full CMOS type SRAMs that adopt a six-transistor memory cell and feature fast access times, low operating power dissipation, and an ultralow standby current. These SRAMs provide three control signal inputs: an OE input for high-speed memory access, and two chip enable lines, CE1 and CE2, for low power mode and device selection. These means that these SRAMs area ideal for systems that require low power and battery backup, and that they support easy memory expansion. The ultralow standby current that is a feature of these SRAMs allows them to be used with capacitor backup as well. Since these SRAMs support 3-V operation, they are also appropriate for use in portable battery operated systems. • • • • Three control inputs: OE, CE1, and CE2 Shared input and output pins, three-state outputs No clock required Packages 28-pin DIP (600 mil) plastic package: LC3564B 28-pin DIP (300 mil) plastic package: LC3564BS 28-pin SOP (450 mil) plastic package: LC3564BM 28-pin TSOP (8 × 13.4 mm) plastic package: LC3564BT Package Dimensions unit: mm 3012A-DIP28 (600 mil) [LC3564B] Features • Supply voltage range: 2.7 to 5.5 V — In 5-V operation mode: 5.0 V ±10% — In 3-V operation mode: 3.0 V ±10% • Address access time (tAA) — In 5-V operation mode: LC3564B, BS, BM, and BT-70: 70 ns (max) LC3564B, BS, BM, and BT-10: 100 ns (max) — In 3-V operation mode: LC3564B, BS, BM, and BT-70: 200 ns (max) LC3564B, BS, BM, and BT-10: 500 ns (max) • Ultralow standby current — In 5-V operation mode: 1.0 µA (Ta ≤ 70°C), 3.0 µA (Ta ≤ 85°C) — In 3-V operation mode: 0.8 µA (Ta ≤ 70°C), 2.5 µA (Ta ≤ 85°C) • Operating temperature range — In 5-V operation mode: –40 to 85°C — In 3-V operation mode: –40 to 85°C • Data retention supply voltage: 2.0 to 5.5 V • All input and output levels: — In 5-V operation mode: TTL compatible levels — In 3-V operation mode: VCC –0.2 V/0.2 V SANYO: DIP28 (600 mil) unit: mm 3133-DIP28 (300 mil) [LC3564BS] SANYO: DIP28 (300 mil) SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN 53098HA (OT) No. 5804-1/9 LC3564B, BS, BM, BT-70/10 unit: mm unit: mm 3187-SOP28 3221-TSOP28 (type I) [LC3564BT] [LC3564BM] SANYO: TSOP28 (type I) SANYO: SOP28 Pin Assignments Pin Functions A0 to A12 Address inputs WE Read/write control input OE Output enable input CE1, CE2 Chip enable inputs Row decoder Memory cell array Input data control circuit Input data buffer Address buffer Block Diagram Column I/O circuit Column decoder Output data Address buffer I/O1 to I/O8 Data I/O VCC, GND Power supply and ground Function Table Mode CE1 CE2 OE WE I/O Read cycle L H L H Data output ICCA Write cycle L H X L Data input ICCA Output disable Not selected Supply current L H H H High impedance ICCA H X X X High impedance ICCS X L X X High impedance ICCS X : H or L No. 5804-2/9 LC3564B, BS, BM, BT-70/10 Specifications Absolute Maximum Ratings at Ta = 25°C Parameter Maximum supply voltage Symbol Conditions Ratings VCC max Unit 7.0 V V Input voltage VIN –0.3* to VCC + 0.3 I/O voltage VI/O –0.3 to VCC + 0.3 V Operating temperature Topr –40 to +85 °C Storage temperature Tstg –55 to +125 °C Note: For pulse widths less than 30 ns: –3.0 V Input and Output Capacitances at Ta = 25°C, f = 1 MHz Parameter Symbol Ratings Conditions min typ Unit max I/O pin capacitance CI/O VI/O = 0 V 6 10 pF Input pin capacitance CIN VIN = 0 V 6 10 pF Note: These parameters are sampled, and are not measured for every unit. [5-V Operation] DC Allowable Operating Ranges at Ta = –40 to +85°C, VCC = 4.5 to 5.5 V Parameter Supply voltage Input voltage Symbol Ratings Conditions min typ Unit max VCC 4.5 5.5 V VIH 2.2 VCC + 0.3 V VIL –0.3* +0.8 V 5.0 Note: For pulse widths less than 30 ns: –3.0 V DC Electrical Characteristics at Ta = –40 to +85°C, VCC = 4.5 to 5.5 V Parameter Input leakage current Symbol Ratings Conditions min typ * Unit max ILI VIN = 0 to VCC –1.0 +1.0 µA I/O leakage current ILO VCE1 = VIH or VCE2 = VIL or VOE = VIH or VWE = VIL, VI/O = 0 to VCC –1.0 +1.0 µA Output high-level voltage VOH IOH = –1.0 mA Output low-level voltage VOL IOL = 2.0 mA ICCA1 VCE1 ≤ 0.2 V, VCE2 ≥ VCC – 0.2 V, II/O = 0 mA, VIN ≤ 0.2 V or VIN ≥ VCC – 0.2 V ICCA4 VCE1 ≤ 0.2 V, min LC3564B,BS, BM, BT-70 VCE2 ≥ VCC – 0.2 V, cycle LC3564B,BS,BM,BT-10 II/O = 0 mA, DUTY = 100% 1 µs cycle ICCA2 VCE1 = VIL, VCE2 = VIH, II/O = 0 mA, VIN = VIH or VIL ICCA3 VCE1 = VIL, VCE2 = VIH, II/O = 0 mA, DUTY = 100% VCC – 0.2 V/0.2 V inputs ICCS1 VCE2 ≤ 0.2 V or VCE1 ≥ VCC – 0.2 V VCE2 ≥ VCC – 0.2 V TTL inputs ICC2 VCC – 0.2 V/0.2 V inputs Operating supply current TTL inputs Standby mode supply current 2.4 min Ta ≤ 70°C V 0.01 Ta ≤ 85°C 0.4 V 1.0 µA 3.0 35 4 mA 7 LC3564B,BS, BM, BT-70 40 cycle LC3564B,BS,BM,BT-10 35 1 µs cycle 7 Ta ≤ 70°C Ta ≤ 85°C VCE2 = VIL or VCE1 = VIH, VIN = 0 to VCC mA 30 0.01 mA mA mA 1.0 µA 3.0 2.0 mA Note *: Reference values at VCC = 5 V, Ta = 25°C No. 5804-3/9 LC3564B, BS, BM, BT-70/10 AC Electrical Characteristics at Ta = –40 to +85°C, VCC = 4.5 to 5.5 V Parameter Conditions [AC Test Conditions] Input pulse voltage VIH = 2.4 V, VIL = 0.6 V Input rise and fall times 5 ns Input and output timing level 1.5 V LC3564B, BS, BM, and BT-70: 30 pF + 1 TTL gate (Including the jig capacitance.) Output load LC3564B, BS, BM, and BT-10: 100 pF + 1 TTL gate (Including the jig capacitance.) Read Cycle LC3564B, BS, BM, BT Parameter Symbol -70 min -10 max min Unit max Read cycle time tRC Address access time tAA 70 100 ns CE1 access time tCA1 70 100 ns CE2 access time tCA2 70 100 ns OE access time tOA 35 50 ns Output hold time tOH 10 10 ns CE1 output enable time tCOE1 10 10 ns CE2 output enable time tCOE2 10 10 ns OE output enable time tOOE 5 5 CE1 output disable time tCOD1 30 35 ns CE2 output disable time tCOD2 30 35 ns OE output disable time tOOD 25 25 ns 70 100 ns ns Write Cycle LC3564B, BS, BM, BT Parameter Symbol -70 min -10 max min Unit max Write cycle time tWC 70 100 Address setup time tAS 0 0 ns Write pulse width tWP 50 55 ns CE1 setup time tCW1 60 65 ns CE2 setup time tCW2 60 65 ns Write recovery time tWR 0 0 ns CE1 write recovery time tWR1 0 0 ns CE2 write recovery time tWR2 0 0 ns tDS 35 40 ns Data hold time tDH 0 0 ns CE1 data hold time tDH1 0 0 ns CE2 data hold time tDH2 0 0 ns WE output enable time tWOE 5 5 WE output disable time tWOD Data setup time 30 ns ns 35 ns No. 5804-4/9 LC3564B, BS, BM, BT-70/10 [3-V Operation] DC Allowable Operating Ranges at Ta = –40 to +85°C, VCC = 2.7 to 3.3 V Parameter Supply voltage Input voltage Symbol Ratings Conditions min typ Unit max VCC 2.7 3.3 V VIH VCC – 0.2 VCC V VIL 0 0.2 V 3.0 DC Electrical Characteristics at Ta = –40 to +85°C, VCC = 2.7 to 3.3 V Parameter Input leakage current Symbol Ratings Conditions min typ * Unit max ILI VIN = 0 to VCC –1.0 +1.0 µA I/O leakage current ILO VCE1 = VIH or VCE2 = VIL or VOE = VIH or VWE = VIL, VI/O = 0 to VCC –1.0 +1.0 µA Output high-level voltage VOH IOH = –0.5 mA Output low-level voltage VOL IOL = 1.0 mA Operation supply current Standby mode supply current VCC – 0.2 V/0.2 V inputs V 0.2 ICCA1 VCE1 ≤ VIL, VCE2 ≥ VIH, II/O = 0 mA, VIN ≤ VIL or VIN ≥ VIH ICCA4 VCE1 ≤ VIL, VCE2 ≥ VIH, II/O = 0 mA, DUTY = 100% ICCS1 VCE2 ≤ 0.2 V or VCE1 ≥ VIH VCE2 ≥ VIH VCC – 0.2 V/0.2 V inputs VCC – 0.2 Ta ≤ 70°C 0.01 0.8 µA Ta ≤ 85°C 2.5 LC3564B,BS, BM, BT-70 20 cycle LC3564B,BS,BM,BT-10 10 min 1 µs cycle 3 Ta ≤ 70°C Ta ≤ 85°C V 0.01 mA mA 0.8 µA 2.5 Note *: Reference values at VCC = 3 V, Ta = 25°C No. 5804-5/9 LC3564B, BS, BM, BT-70/10 AC Electrical Characteristics at Ta = –40 to +85°C, VCC = 2.7 to 3.3 V Parameter Conditions [AC Test Conditions] Input pulse voltage VIH = VCC – 0.2 V, VIL = 0.2 V Input rise and fall times 10 ns Input and output timing level 1.5 V LC3564B, BS, BM, BT-70 : 30pF (Including the jig capacitance.) Output load LC3564B, BS, BM, BT-10 : 100pF (Including the jig capacitance.) Read Cycle LC3564B, BS, BM, BT Parameter Symbol -70 min -10 max min Unit max Read cycle time tRC Address access time tAA 200 500 ns CE1 access time tCA1 200 500 ns CE2 access time tCA2 200 500 ns OE access time tOA 100 250 Output hold time tOH 20 20 ns CE1 output enable time tCOE1 20 20 ns CE2 output enable time tCOE2 20 20 ns OE output enable time tOOE 10 10 CE1 output disable time tCOD1 60 120 ns CE2 output disable time tCOD2 60 120 ns OE output disable time tOOD 50 100 ns 200 500 ns ns ns Write Cycle LC3564B, BS, BM, BT Parameter Symbol -70 min -10 max min Unit max Write cycle time tWC 200 500 Address setup time tAS 0 0 ns Write pulse width tWP 140 200 ns CE1 setup time tCW1 150 250 ns CE2 setup time tCW2 0 250 ns Write recovery time tWR 0 0 ns CE1 write recovery time tWR1 0 0 ns CE2 write recovery time tWR2 130 0 ns ns Data setup time tDS 0 180 ns Data hold time tDH 0 0 ns CE1 data hold time tDH1 0 0 ns CE2 data hold time tDH2 10 0 ns WE output enable time tWOE WE output disable time tWOD 10 60 ns 120 ns No. 5804-6/9 LC3564B, BS, BM, BT-70/10 Timing Charts Read Cycle *1 Write Cycle (1): WE Write *6 No. 5804-7/9 LC3564B, BS, BM, BT-70/10 Write Cycle (2): CE1 Write *6 Write Cycle (3): CE2 Write *6 Notes: 1. Hold WE high during the read cycle. 2. Applications must not apply reverse phase signals to the DOUT pins when those pins are in the output state. 3. The time tWP is the period when CE1 and WE are low and CE2 is high, and is defined as the time from the fall of WE until either CE1 or WE rises, or CE2 falls, whichever occurs first. 4. The times tCW1 and tCW2 are periods when CE1 and WE are low and CE2 is high. They are defined as the times from the fall of CE1 or the rise of CE2 to the rise of CE1 and WE, or the fall of CE2, whichever occurs first. 5. The DOUT pins will be in the high-impedance state if either OE is high, CE1 is high, CE2 is low, or WE is low. 6. OE must be held either at VIH or VIL during the write cycle. 7. The DOUT pins have the same phase as the write cycle write data. No. 5804-8/9 LC3564B, BS, BM, BT-70/10 Data Retention Characteristics at Ta = –40 to +85°C Parameter Symbol Data retention supply voltage VDR Data retention supply current ICCDR Chip enable setup time tCDR Chip enable hold time tR Ratings Conditions min VCE2 ≤ 0.2 V or VCE1 ≥ VCC – 0.2 V, VCE2 ≥ VCC – 0.2 V VCC = 3V, VCE2 ≤ 0.2 V, or VCE1 ≥ VCC – 0.2 V, VCE2 ≥ VCC – 0.2 V typ 2.0 max 5.5 Ta ≤ 70°C 0.8 Ta ≤ 85°C 2.5 Unit µA µA 0 ns tRC* ns Note *: tRC is the read cycle time. Data Retention Waveforms (1): CE1 Control Data retention mode Data Retention Waveforms (2): CE2 Control Data retention mode Note *:In 5-V operation: 4.5 V In 3-V operation: 2.7 V Notes on Circuit Design When actually design a circuit using these devices, take the following points into consideration and design the circuit so that none of the maximum rating items are ever exceeded. • Variations in the supply voltage • Variations in the electrical characteristics of components such as semiconductor devices, resistors, and capacitors. • Ambient temperature • Variations in input and clock signals • Possible application of abnormal pulses Also, these devices must be operated within the ranges stipulated in the allowable operating ranges. If CMOS IC input pins are left open, intermediate potential input voltages may occur leading to incorrect operation due to through currents or other phenomenon. Applications must handle unused input pins appropriately. ■ No products described or contained herein are intended for use in surgical implants, life-support systems, aerospace equipment, nuclear power control systems, vehicles, disaster/crime-prevention equipment and the like, the failure of which may directly or indirectly cause injury, death or property loss. ■ Anyone purchasing any products described or contained herein for an above-mentioned use shall: ➀ Accept full responsibility and indemnify and defend SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors and all their officers and employees, jointly and severally, against any and all claims and litigation and all damages, cost and expenses associated with such use: ➁ Not impose any responsibility for any fault or negligence which may be cited in any such claim or litigation on SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors or any of their officers and employees jointly or severally. ■ Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. This catalog provides information as of May, 1998. Specifications and information herein are subject to change without notice. PS No. 5804-9/9