ETC LC36256ALL-70

Ordering number : EN4327A
Asynchronous Silicon Gate CMOS LSI
LC36256ALL, AMLL-70/85/10/12
256 K (32768 words × 8 bits) SRAM
Overview
Package Dimensions
The LC36256ALL, AMLL are fully asynchronous silicon
gate CMOS static RAMs with a 32768 words × 8 bits
configuration.
unit: mm
3012A-DIP28
This series has CE chip enable pin for device
select/nonselect control and an OE output enable pin for
output control, and features high speed as well as low
power dissipation.
[LC36256ALL]
Current dissipation is notably reduced during stand-by and
data retention. For these reasons, this series is most suited
for use in systems requiring high speed, low power
consumption and long-term battery backup. Simple
memory capacity expansion is also supported.
Features
• Access time
70 ns (max.)
85 ns (max.)
100 ns (max.)
120 ns (max.)
:
:
:
:
LC36256ALL-70, LC36256AMLL-70
LC36256ALL-85, LC36256AMLL-85
LC36256ALL-10, LC36256AMLL-10
LC36256ALL-12, LC36256AMLL-12
• Low current dissipation
During standby
0.5 µA (max.) / Ta = 25°C
1 µA (max.) / Ta = 0 to +40°C
5 µA (max.) / Ta = 0 to +70°C
SANYO: DIP28
unit: mm
3187-SOP28D
[LC36256AMLL]
During data retention
0.3 µA (max.) / Ta = 25°C
0.6 µA (max.) / Ta = 0 to +40°C
3 µA (max.) / Ta = 0 to +70°C
During operation (DC)
10 mA (max.)
•
•
•
•
•
•
Single 5 V power supply: 5 V ±10%
Data retention power supply voltage: 2.0 to 5.5 V
No clock required (Fully static memory)
All input/output levels are TTL compatible
Common input/output pins, with three output states
Packages
DIP 28- pin (600 mil) plastic package : LC36256ALL
SOP 28-pin (450 mil) plastic package : LC36256AMLL
SANYO: SOP28D
SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-0005 JAPAN
32896HA (OT)/21593JN (OT) No. 4327-1/7
LC36256ALL, AMLL-70/85/10/12
Pin Assignment
Block Diagram
Pin Functions
A0 to A14
Address input
WE
Read/write control input
OE
Output enable input
CE
Chip enable input
I/O1 to I/O8
Data input/output
VCC, GND
Power supply pins
Functions
Mode
CE
OE
WE
I/O
Supply current
Read cycle
L
L
H
Data output
ICCA
Write cycle
L
X
L
Data input
ICCA
Output disable
L
H
H
High impedance
ICCA
Nonselect
H
X
X
High impedance
ICCS
X : H or L
No. 4327-2/7
LC36256ALL, AMLL-70/85/10/12
Specifications
Absolute Maximum Ratings at Ta=25°C
Parameter
Symbol
Maximum supply voltage
VCC max
Input pin voltage
Conditions
Ratings
Unit
7.0
V
VIN
–0.5* to VCC+0.5
V
I/O pin voltage
VI/O
–0.5* to VCC+0.5
V
Allowable power dissipation
Pd max
LC36256ALL
1.0
W
LC36256AMLL
0.7
W
Operating temperature range
Topr
0 to +70
°C
Storage temperature range
Tstg
–55 to +150
°C
max
Unit
* –3.0 V when pulse width is less than 50 ns
DC Recommended Operating Ranges at Ta = 0 to +70°C
Parameter
Symbol
min
Power supply voltage
VCC
4.5*
Input high level voltage
VIH
Input low level voltage
VIL
typ
5.0
5.5
V
2.2*
VCC+0.3
V
–0.3*
+0.8
V
* –3.0 V when pulse width is less than 50 ns
DC Electrical Characteristics at Ta = 0 to +70°C, VCC = 5 V ±10%
Parameter
Symbol
Conditions
min
typ*
max
Unit
Input leakage current
ILI
VIN = 0 to VCC
–0.5
+0.5
µA
I/O leakage current
ILO
VCE = VIH or VOE = VIH,
VI/O = 0 to VCC
–0.5
+0.5
µA
Output high level voltage
VOH
IOH = –1.0mA
Output low level voltage
VOL
IOL = 2.1mA
Operating supply
current (DC)
ICCA1
VCE ≤ 0.2V,
VIN ≤ 0.2V or VIN ≥ VCC–0.2V
ICCA2
VCE = VIL, II/O=0mA
2.4
min cycle
Average operating
supply current
Standby supply
current
ICCA3
Duty = 100%
I I/O = 0mA
ICCS1
VCE ≥VCC-0.2V
Access
time
VCE = VIH
0.4
V
1
5
mA
3
10
mA
70ns
30
50
85ns
25
50
100ns
23
50
120ns
20
50
0 to +70°C
5
0 to +40°C
1
25°C
ICCS2
V
0.2
0.5
0.4
2
mA
µA
mA
* Reference values at VCC = 5 V, Ta = 25°C
No. 4327-3/7
LC36256ALL, AMLL-70/85/10/12
Input/Output Capacitance at Ta = 25°C, f = 1 MHz
Parameter
Input/output capacitance
Input capacitance
Note:
Symbol
CI/O
CIN
Conditions
VI/O = 0V
VIN = 0V
min
typ
max
8
6
Unit
pF
pF
These parameters were obtained through sampling, and not full-lot measurement.
AC Electrical Characteristics at Ta = 0 to +70°C, VCC = 5 V ±10%
AC testing conditions
Input pulse voltage level
: 0.8 V, 2.2 V
Input rise and fall time
: 5 ns
Input - output timing level : 1.5 V
Output load
: 1 TTL gate + CL = 100 pF (85 ns/100 ns/120 ns)
1 TTL gate + CL = 30 pF (70 ns)
(including scope and jig capacitance)
Read Cycle
Parameter
Read cycle time
Address access time
CE access time
OE access time
Output hold time
CE output enable time
OE output enable time
OE output disable time
OE output disable time
Symbol
tRC
tAA
tCA
tOA
tOH
tCOE
tOOE
tCOD
tOOD
-70
min
70
max
70
70
35
20
10
5
0
0
30
30
LC36256ALL, AMLL
-85
-10
min
max
min
max
85
100
85
100
85
100
45
50
20
20
10
10
5
5
0
30
0
30
0
30
0
30
-12
min
120
Unit
max
120
120
60
20
10
5
0
0
30
30
ns
ns
ns
ns
ns
ns
ns
ns
ns
Write Cycle
Parameter
Write cycle time
Address valid to end of write
Address setup time
Write pulse width
CE setup time
Write recovery time (WE)
Write recovery time (CE)
Data setup time
Data hold time
WE output enable time
WE output disable time
-70
tWC
tAW
tAS
tWP
tCW
tWR
tWR1
tDS
tDH
tWOE
tWOD
min
70
65
0
50
65
0
0
30
0
10
0
max
25
LC36256ALL, AMLL
-85
-10
min
max
min
max
85
100
75
80
0
0
50
60
75
80
0
0
0
0
30
35
0
0
10
10
0
25
0
25
-12
min
120
100
0
70
100
0
0
40
0
10
0
Unit
max
25
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
No. 4327-4/7
LC36256ALL, AMLL-70/85/10/12
Timing Chart
• Read Cycle (1): CE = OE = VIL, WE = VIH
• Read Cycle (2): WE = VIH
• Write Cycle (1): WE Control Note (6)
No. 4327-5/7
LC36256ALL, AMLL-70/85/10/12
• Write Cycle (2): CE Control Note (6)
Notes
(1) tCOD, tOOD, and tWOD are defined as the time at which the outputs becomes the high impedance state and
are not referred to output voltage levels.
(2) An external antiphase signal must not be applied when DOUT is in the output state.
(3) tWP is the time interval that CE and WE are low-level and is defined as the interval from the falling of WE
to the rising of CE or WE whichever is earlier.
(4) tCW is the time interval that CE and WE are low-level and is defined as the time from the falling of CE to
the rising of CE or WE whichever is earlier.
(5) DOUT goes to the high-impedance state when either OE is high-level, CE is high-level, or WE is low-level.
(6) When OE is high-level during the write cycle, DOUT goes to the high-impedance state.
Data Retention Characteristics at Ta = 0 to +70°C
Parameter
Data retention supply voltage
Symbol
VDR
ICCDR1
Data retention supply current
ICCDR2
CE setup time
tCDR
CE hold time
tR
* Reference values at VCC = 5V, Ta = 25°C
Conditions
min
VCE ≥ VCC–0.2V
VCC = 3.0V,
VCE ≥ 2.8V
typ*
2.0
max
5.5
0 to +70°C
3
0 to +40°C
0.6
25°C
0.1
0.3
0.2
5
Unit
V
µA
VCC = 2.0 to 5.5V,
VCE ≥ VCC–0.2V
µA
0
ns
tRC**
ns
** tRC = Read Cycle time
Data Retention Waveform
No. 4327-6/7
LC36256ALL, AMLL-70/85/10/12
■ No products described or contained herein are intended for use in surgical implants, life-support systems, aerospace
equipment, nuclear power control systems, vehicles, disaster/crime-prevention equipment and the like, the failure of
which may directly or indirectly cause injury, death or property loss.
■ Anyone purchasing any products described or contained herein for an above-mentioned use shall:
➀ Accept full responsibility and indemnify and defend SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and
distributors and all their officers and employees, jointly and severally, against any and all claims and litigation and all
damages, cost and expenses associated with such use:
➁ Not impose any responsibility for any fault or negligence which may be cited in any such claim or litigation on
SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors or any of their officers and employees
jointly or severally.
■ Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for
volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied
regarding its use or any infringements of intellectual property rights or other rights of third parties.
This catalog provides information as of March, 1996. Specifications and information herein are subject to
change without notice.
PS No. 4327-7/7