Ordering number: EN 6157 CMOS IC LC7940YC,7941YC Dot-matrix LCD Drivers Overview The LC7940YC and LC7941YC are segment driver ICs for driving large, dot–matrix LCD displays. They read 4– bit parallel or serial input, display data from a controller into an 80–bit latch, and then generate LCD drive signals corresponding to that data. The LC7940YC and LC7941YC feature mirror–image pin assignments, allowing them to be used together to increase component density. They are designed to be used with the LC7942YC common driver to drive large LCD panels. Features • • • • 80 built–in LCD display drive circuits 1/8 to l/128 display duty cycle Serial or 4–bit parallel data input Chip disable for low power dissipation for large–sized panels • Bias supply voltags can be supplied externally • Operating supply voltage and ambient temperature - 2.7 to 5.5 V logic supply ( VDD) at Ta = –20 to +85°C - 8 to 20V LCD supply (VDD – VEE ) at Ta = –20 to +85 °C • CMOS process Specifications The following electrical characteristics apply when sealed in a Sanyo standard QIC-100 package. Absolute Maximum Ratings at Ta = 25 ± 2°C, VSS = 0 V Parameter Logic supply voltge LCD supply voltage, See Note below. Input voltage Symbol Ratings Unit VDD max –0.3 to +7.0 V VDD – VEE max 0 to 22 V VI max –0.3 to VDD + 03 °C ■ Any and all SANYO products described or contained herein do not have specifications that can handle applications that require extremely high levels of reliability, such as life-support systems, aircraft’s control systems, or other applications whose failure can be reasonably expected to result in serious physical and/or material damage. Consult with your SANYO representative nearest you before using any SANYO products described or contained herein in such applications. ■ SANYO assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO products described or contained herein. SANYO Electric Co., Ltd. Semiconductor Company TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN 63099RM (ID) No. 6157—1/13 LC7940YC, LC7941YC Parameter Symbol Ratings Unit Operating temperature range Topr –20 to +85 °C Storage temperature range Tstg –40 to +125 °C Note VDD ≥ V1 > V3 > V4 > VEE Recommended Operating Condltions at Ta = –20 to + 85°C, VSS = 0V Ratings Parameter Symbol Conditions Unit min Logic supply voltage VDD LCD supply voltage VDD – VEE See Notes 1 and 2. typ max 2.7 – 5.5 V 8 – 20 V HIGH–level input voltage VIH CP, CDl, DI1 to DI3, M, SDl, P/S, DISPOFF and LOAD 0.8VDD – – V LOW–level inpvt voltage VIL CP, CDI, Dl1 to DI3, M, SDl, P/S,DISPOFF and LOAD – – 0.2VDD V CP shift clock frequency fCP – 3.3 CP pulsewidth tWC 100 – – ns LOAD pulsewidth MHz tWL 100 – – ns DIn and SDI to CP setup time tSETUP 80 – – ns DIn and SDI to CP hold time tHOLD 80 – – ns tCL1 0 – – ns CP to LOAD time tCL2 100 – – ns LOAD to CP time tLC 100 – – ns CP rise time tR – – 50 ns CP fall time tF – – 50 ns LOAD rise time tRL – – 50 ns LOAD fall time tFL – – 50 ns Notes 1. VDD ≥ Vl > V3 > V4 > VEE 2. At turn ON, the LCD supply should be energized after or simultaneously with the logic supply. At turn OFF, the logic supply should be cut after or simultaneously with the LCD supply. Electrlcai Characterfstlcs at Ta = 25 ± 2°C,VSS = 0V, VDD = 2.7 to 5.5 V Ratings Parameter Symbol Conditions Unit min typ max HIGH–level input current IIH VIN =VDD; LOAD, CP, CDI, P/S, DI1 to DI3, SDl, M, and DISPOFF – – 1 µA LOW–level input current IIL VIN = VSS; LOAD, CP, CDl, P/S, DI1 to DI3, SDI, M, and DISPOFF – – –1 µA VDD – 0.4 – – V V CDO HIGH–level output voltage VOH CDO LOW–levef output voltage VOL IOL = 400 µA – – 0.4 RON VDD – VEE = 18 V, |VDE – VO|= 0.25 V. See note – 2 4 O1 to O80 driver ON resistance IOH = –400 µA kΩ No. 6157—2/13 LC7940YC, LC7941YC Ratings Parameter Symbol Conditions Unit min typ max IST CDI = VDD, VDD – VEE = 18 V, fCP = 3.3 MHz, no output load ; VSS – – 200 µA ISS VDD – VEE = 18 V, fCP = 3.3 MHz, ILOAD= 5.156 kHz, fM = 52 Hz ;VSS – – 1.0 mA VDD to VEE operating supply current IEE VDD – VEE = 18V, fCP = 3.3 MHz, fLOAD = 5,156 kHz, fM = 52 Hz ; VEE – – 0.1 mA CP input capacitance CI fCP = 3.3 MHz ; CP – 5 – pF VDD to VSS standby supply current VDD to Vss operating supply current Note VDE = V1 or V3, or V4 or VEE, V1 = VDD, V3 = 9/11 × (VDD – VEE), V4 = 2/11 × (VDD – VEE) Switching Characteristics at Ta = 25 ± 2°C,VSS = 0V, VDD = 2.7 to 5.5 V Ratings Parameter Symbol Conditions Unit min CDO output delay time tD CL = 30 pF typ – max – 200 ns Switching Characteristics Waveform tR tWC tF tWC 0.8VDD CP 0.2VDD tSET UP tHOLD SDI DI1 to 3 tCL (1) tRL tCL (2) tFL tLC LOAD tWL tD tD CDO No. 6157—3/13 LC7940YC, LC7941YC P/S DISPOFF CDO VSS VEE V4 V3 VDD O1 O2 O3 O4 O5 O6 O7 O8 O9 O10 O11 O12 O13 O14 O15 O16 O17 O18 O19 O20 O21 O22 O23 O24 O25 O26 O27 O28 O29 O30 V1 CP CDI LOAD SDI DI3 DI2 DI1 M Pad Layout (Top view) M DI1 DI2 DI3 SDI LOAD CDI CP V1 VDD V3 V4 VEE LC7941YC O1 O2 O3 O4 O5 O6 O7 O8 O9 O10 O11 O12 O13 O14 O15 O16 O17 O18 O19 O20 O21 O22 O23 O24 O25 O26 O27 O28 O29 O30 O50 O49 O48 O47 O46 O45 O44 O43 O42 O41 O40 O39 O38 O37 O36 O35 O34 O33 O32 O31 O80 O79 O78 O77 O76 O75 O74 O73 O72 O71 O70 O69 O68 O67 O66 O65 O64 O63 O62 O61 O60 O59 O58 O57 O56 O55 O54 O53 O52 O51 VSS CDO DISPOFF P/S O31 O32 O33 O34 O35 O36 O37 O38 O39 O40 O41 O42 O43 O44 O45 O46 O47 O48 O49 O50 LC7940YC O80 O79 O78 O77 O76 O75 O74 O73 O72 O71 O70 O69 O68 O67 O66 O65 O64 O63 O62 O61 O60 O59 O58 O57 O56 O55 O54 O53 O52 O51 No. 6157—4/13 LC7940YC, LC7941YC LC7940YC Pad Location chip size : 4.830 mm x 3.550 mm Pin_No. Name X Y Pin_No. Name X Y 1 O1 -1600 2240 51 O51 1600 -2240 2 O2 -1600 2072 52 O52 1600 -2072 3 O3 -1600 1906 53 O53 1600 -1906 4 O4 -1600 1742 54 O54 1600 -1742 5 O5 -1600 1580 55 O55 1600 -1580 6 O6 -1600 1420 56 O56 1600 -1420 7 O7 -1600 1262 57 O57 1600 -1262 8 O8 -1600 1106 58 O58 1600 -1106 9 O9 -1600 952 59 O59 1600 -952 10 O10 -1600 800 60 O60 1600 -800 11 O11 -1600 650 61 O61 1600 -650 12 O12 -1600 502 62 O62 1600 -502 13 O13 -1600 356 63 O63 1600 -356 14 O14 -1600 212 64 O64 1600 -212 15 O15 -1600 70 65 O65 1600 -70 16 O16 -1600 -70 66 O66 1600 70 17 O17 -1600 -212 67 O67 1600 212 18 O18 -1600 -356 68 O68 1600 356 19 O19 -1600 -502 69 O69 1600 502 20 O20 -1600 -650 70 O70 1600 650 21 O21 -1600 -800 71 071 1600 800 22 O22 -1600 -952 72 O72 1600 952 23 O23 -1600 -1106 73 O73 1600 1106 24 O24 -1600 -1262 74 O74 1600 1262 25 O25 -1600 -1420 75 O75 1600 1420 26 O26 -1600 -1580 76 O76 1600 1580 27 O27 -1600 -1742 77 O77 1600 1742 28 O28 -1600 -1906 78 O78 1600 1906 29 O29 -1600 -2072 79 O79 1600 2072 30 O30 -1600 -2240 80 O80 1600 2240 31 O31 -1420 -2240 81 --- --- --- 32 O32 -1262 -2240 82 CDO 1415 2240 33 O33 -1106 -2240 83 --- --- --- 34 O34 -952 -2240 84 DISPOFF 1252 2240 35 O35 -800 -2240 85 P/S 1091 2240 36 O36 -650 -2240 86 VSS 825 2179 37 O37 -502 -2240 87 VEE 629 2179 38 O38 -356 -2240 88 V4 464 2179 39 O39 -212 -2240 89 V3 299 2179 40 O40 -70 -2240 90 --- --- --- 41 O41 70 -2240 91 VDD 123 2179 42 O42 212 -2240 92 V1 -42 2179 43 O43 356 -2240 93 M -316 2240 44 O44 502 -2240 94 DI1 -467 2240 45 O45 650 -2240 95 DI2 -620 2240 46 O46 800 -2240 96 DI3 -775 2240 47 O47 952 -2240 97 SDI -932 2240 48 O48 1106 -2240 98 LOAD -1091 2240 49 O49 1262 -2240 99 CDI -1252 2240 50 O50 1420 -2240 100 CP -1415 2240 No. 6157—5/13 LC7940YC, LC7941YC LC7941C Pad Location chip size : 4.830 mm x 3.550 mm Pin No. Name X Y Pin No. Name X Y 1 O80 -1600 2240 51 O30 1600 -2240 2 O79 -1600 2072 52 O29 1600 -2072 3 O78 -1600 1906 53 O28 1600 -1906 4 O77 -1600 1742 54 O27 1600 -1742 5 O76 -1600 1580 55 O26 1600 -1580 6 O75 -1600 1420 56 O25 1600 -1420 7 O74 -1600 1262 57 O24 1600 -1262 8 O73 -1600 1106 58 O23 1600 -1106 9 O72 -1600 952 59 O22 1600 -952 10 O71 -1600 800 60 O21 1600 -800 11 O70 -1600 650 61 O20 1600 -650 12 O69 -1600 502 62 O19 1600 -502 13 O68 -1600 356 63 O18 1600 -356 14 O67 -1600 212 64 O17 1600 -212 15 O66 -1600 70 65 O16 1600 -70 16 O65 -1600 -70 66 O15 1600 70 17 O64 -1600 -212 67 O14 1600 212 18 O63 -1600 -356 68 O13 1600 356 19 O62 -1600 -502 69 O12 1600 502 20 O61 -1600 -650 70 O11 1600 650 21 O60 -1600 -800 71 O10 1600 800 22 O59 -1600 -952 72 O9 1600 952 23 O58 -1600 -1106 73 O8 1600 1106 24 O57 -1600 -1262 74 O7 1600 1262 25 O56 -1600 -1420 75 O6 1600 1420 26 O55 -1600 -1580 76 O5 1600 1580 27 O54 -1600 -1742 77 O4 1600 1742 28 O53 -1600 -1906 78 O3 1600 1906 29 O52 -1600 -2072 79 O2 1600 2072 30 O51 -1600 -2240 80 O1 1600 2240 31 O50 -1420 -2240 81 CP 1415 2240 32 O49 -1262 -2240 82 CDI 1252 2240 33 O48 -1106 -2240 83 LOAD 1091 2240 34 O47 -952 -2240 84 SDI 932 2240 35 O46 -800 -2240 85 DI3 775 2240 36 O45 -650 -2240 86 DI2 620 2240 37 O44 -502 -2240 87 DI1 467 2240 38 O43 -356 -2240 88 M 316 2240 39 O42 -212 -2240 89 V1 42 2179 40 O41 -70 -2240 90 VDD -123 2179 41 O40 70 -2240 91 --- --- --- 42 O39 212 -2240 92 V3 -299 2179 43 O38 356 -2240 93 V4 -464 2179 44 O37 502 -2240 94 VEE -629 2179 45 O36 650 -2240 95 VSS -825 2179 46 O35 800 -2240 96 P/S -1091 2240 47 O34 952 -2240 97 DISPOFF -1252 2240 48 O33 1106 -2240 98 --- --- --- 49 O32 1262 -2240 99 CDO -1415 2240 50 O31 1420 -2240 100 --- --- --- No. 6157—6/13 LC7940YC, LC7941YC Block Diagram 01 02 03 079 080 V1 V3 4 Level LCD Drive Circuit VDD V4 (80 bits) VSS VEE 80 Level Shifter (80 bits) M DISP OFF 80 2nd Latch (80 bits) 80 1st Latch (80 bits) SDI DI3 4 20 4 bits Address Decoder Data Bus DI2 CLK Interface Address Counter (7 bits) DI1 Chip Disable & Latch Control SER/PAR Control P/S CDO CDI CP LOAD Pin Functions Pin No. Symbol I/O Function LC7940YC LC7941YC 91 90 VDD 86 95 VSS 87 94 VEE 92 89 V1 89 92 V3 88 93 V4 l00 81 CP I Display data Input clock (falling–edge trigger). 99 82 CDI I Chip disable. Data is read in when LOW, and not road in when HIGH. 98 83 LOAD I Display data latch clock (falling–edge trigger). On the falling edge, the LCD drive signals set by the display data are output. 97 84 SDI I Serial data input. 96 85 DI3 4–bit parallel data input pins. 95 86 DI2 Data input Supply VDD – VSS is the logic supply. VDD – VEE is the LCD supply. Supply LCD panel drive voltage supplies V1 and VEE are selected levels. V3 and V4 are not–selected levels. I 94 87 D11 LCD driver outputs SDI O4 O8 O80 DI3 O3 O7 O79 DI2 O2 O6 O78 DI1 O1 O5 O77 In serial data input mode, DI1 to DI3 should all be tied HIGH or LOW. No. 6157—7/13 LC7940YC, LC7941YC Pin No. Symbol I/O 88 M I LCD panel drive voltage output alternation control signal. 85 96 P/S I Data input mode select. 4–bit parallel input when HIGH, and serial input when LOW 82 99 CDO O Cascade connection pin for extension segment drivers. Data is read out when HIGH. Goes LOW after data is read out. Connected to the CDI input of the next chip. LC7940YC LC7941YC 93 Function LCD drive outputs. The output drive level is determined by the display data, M signal and DISP OFF input as shown below. M 1 to 80 80 to 1 Ol to O80 O Q DISP OFF Output LOW LOW HIGH V3 LOW HIGH HIGH V1 HIGH LOW HIGH V4 HIGH HIGH HIGH VEE × × LOW V1 Note x = don’t care (tied HIGH or LOW) 84 97 DISPOFF 81 91 NC 83 98 NC 90 100 NC I O1 to O80 output control input pin. When LOW, V1 is output on the O1 to 080 outputs, See the truth table. – No connection. No. 6157—8/13 7R R R R R VEE – + – + – + – + LA5311M –11 to –13V VDD controller 6 V5 V4 V3 V2 V1 ED2 4 V1 V2 V5 VEE CL2 01 DI01 DI064 01 064 CP 4 V1 V2 V5 VEE 036 LC7942YC M 4 CP OD2 DI01 LC7942YC M CL1 M 4 V1 V3 V4 VEE 100 M LC7941YC (LC7941YC) V1 V3 V4 VEE LC7940YC M V1 V4 VEE V1 V3 V4 V3 VEE CDI CDO V1 V4 LC7941YC V1 V3 V4 VEE LC7940YC M VEE V1 V3 V4 (LC7940YC) LC7941YC M M LC7941YC (LC7941YC) V3 VEE V1 V3 V4 VEE LC7940YC LCD panel (640 × 200 pixels) (LC7941YC) 640 1280 (LC7940YC) LC7941YC 639 1279 FLM CDO 482 1122 CDI 481 1121 (LC7940YC) LC7941YC VEE M 480 1120 ED1 V4 V1 V3 479 1119 OD1 M M 322 962 V3 321 961 VEE CDI M CDO V4 VEE V1 V3 V4 V1 (LC7940YC) LC7941YC M M VEE V3 M V1 V3 V4 VEE LOAD CP OD2 ED2 LC7941YC (LC7941YC) LC7940YC 162 802 V1 161 801 V4 160 800 M 320 960 CP SDI LOAD 159 799 CP SDI LOAD 2 642 CP SDI LOAD 319 959 OD1 ED1 CP LOAD 1 641 2 CDI CP SDI LOAD 4 4 CP SDI LOAD LC7940YC, LC7941YC Application Notes LCD Panel 1 No. 6157—9/13 7R R R R R VEE – + – + – + – + LA5311M –11 to –13V VDD CP LOAD M V5 V4 V3 V2 V1 4bit Data controller FLM 4bit Data 6 4 DI01 01 01 4 4 V1 V2 V5 VEE CP 036 LC7942YC-#2 M DI01 CP 064 LC7942YC-#1 M 4 4 V1 V3 V4 VEE 100 100 LC7941YC-#8 LC7941YC-#8 2 2 4 4 4 LC7941YC-#2 2 4 LC7941YC-#2 LCD panel (640 × 200 pixels) 2 2 2 4 4 CDO CDO M V1 V3 V4 VEE 01 01 LC7941YC-#1 080 080 4 2 4 CP LOAD 4 4bit Data CDI CDI 4bit Data V1 V3 V4 VEE CP LOAD LC7941YC-#1 M 2 LC7940YC, LC7941YC LCD Panel 2 No. 6157—10/13 LC7940YC, LC7941YC 100 x 240-pixel LCD Panel Application A 100 × 240–pixel LCD panel requires the following drivers. • 3 x LC7940YC (or LC7941YC) drivers • 2 x LC7942YC drivers An example using l/l00 duty cycle is shown below. (m,n) : pixel address 1,79 Segment line (n) Common line (m) Frame Signal DI01 01 RS/LS 02 LC7942YC 1,1 1,2 2,1 2,2 1,80 1,82 1,81 1,160 --- 63,1 63,2 064 64,1 64,2 DI01 01 RS/LS 02 65,1 65,2 66,1 66,2 ----- 64,80 64,81 65,80 65,81 --- --- 1,240 2,240 --- --- 063 DI064 1,161 --- --- LCD Panel (100 × 240 pixels) CP M #1 1,79 --- 64,160 64,161 --- 65,160 65,161 --- 64,240 65,240 --- LC7942YC 100,1 100,2 01 02 --- 100,79 100,80 100,81 100,82 --- --- --- --- 036 --- #2 CP M 100,160 100,161 --- 100,240 DI064 O37 to O64 are open. 080 LC7940YC #2 CDO (LC7941YC) P/S DI1 DI2 DI3 SDI CP LOAD M M LOAD CDI CP LC7940YC #2 CDO (LC7941YC) SDI 01 DI3 080 DI2 02 DI1 CDI P/S M LOAD CDO CP SDI DI3 DI2 DI1 P/S #1 01 Data Shift clock Serial Data Alternating signal 080 LC7940YC (LC7941YC) CDI Data latch clock 079 1. The LC7942YC chips are cascaded by connecting DIO64 on chip I to DIO1 on chip 2. For a 100–bit shift register, O37 to O64 on chip 2 are left open. 2. The LC7940YC (or LC7941YC) chips are cascaded by connecting CDO on chip I to CDI on chip 2, and CDO on chip 2 to CDI on chip 3. CDI on chip I is tied to GND, and CDO on chip 3 is not used. This configuration allows the input of 240–bit serial data. No. 6157—11/13 LC7940YC, LC7941YC 100 x 240-pixel LCD Panel Timing Diagram M LOAD CP SDI 1,1 1,2 --- 1,79 1,80 1,81 --- 1,160 1,161 --- 1,240 #1 SDO #2 #3 Chip 2 data read Chip 1 data read Chip 3 data read 1 frame (240 bits) M LOAD CP SDI 1,1 1,2 --- 1,239 1,240 1st line data read 2,1 --- 2,240 3,1 --- 100,240 2nd line data read 1frame (100 × 240 bits) M #1 DIO1 #1 2,1 --- 98,1 99,1 100,1 1,1 --- 99,1 100,1 02 1,2 2,2 --- 98,2 99,2 100,2 1,2 --- 99,2 100,2 080 1,80 2,80 --- 98,80 99,80 100,80 1,80 --- 99,80 100,80 01 1,81 2,81 --- 98,81 99,81 100,81 1,81 --- 99,81 100,81 080 1,160 2,160 --- 98,160 99,160 100,160 1,160 --- 99,160 100,160 01 1,161 2,161 --- 98,161 99,161 100,161 1,161 --- 99,161 100,161 1,240 2,240 --- 98,240 99,240 100,240 1,240 --- 99,240 100,240 --- #3 1,1 --- #2 01 LCD driver output data LOAD 080 No. 6157—12/13 LC7940YC, LC7941YC Segment Data Not Multiples of 4 Example. LCD panel (100 × 230 pixels) --- --01 080 01 01 080 LC7940YC #2 LC7940YC #1 070 LC7940YC #3 LOAD SDI m,1 m,2 --- ,228 m,229 m,230 If this timing data is sent, data elements (m, 229), (m, 230), (m+1, 229), (m+1. 230)... will not appear in the output (O69 and O70 on chip 3). This is because the LC7940YC (or LC7941YC) converts serial/parallel data m+1,1 m+1,2 ,228 m+1,229 m+1,230 in 4–bit units, which also decreases power dissipation . For data that is not a multiple of 4, like 230, the following scheme is used. LOAD SDI m,1 m,2 --- ,228 m,229 Valid display data m,230 m,231 m,232 Dummy data Multiple of 4 In this case, (m, 231) is output on O71 on chip 3, and (m, 232) on O72 on chip 3. However, these outputs are not connected to the panel and are, therefore, invalid. ■ Specifications of any and all SANYO products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer’s products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer’s products or equipment. ■ SANYO Electric Co., Ltd. strives to supply high-quality high-reliability products. However, any and all semiconductor products fail with some probability. It is possible that these probabilistic failures could give rise to accidents or events that could endanger human lives, that could give rise to smoke or fire, or that could cause damage to other property. When designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. ■ In the event that any or all SANYO products(including technical data,services) described or contained herein are controlled under any of applicable local export control laws and regulations, such products must not be exported without obtaining the export license from the authorities concerned in accordance with the above law. ■ No part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written permission of SANYO Electric Co. , Ltd. ■ Any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification" for the SANYO product that you intend to use. ■ Information (including circuit diagrams and circuit parameters) herein is for example only ; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. This catalog provides information as of June, 1999. Specifications and information herein are subject to change without notice. No. 6157—13/13