Ordering number : ENN*6789 CMOS IC LC4102C-T2A LCD Dot Matrix Common Driver for STN Displays Preliminary Overview Features The LC4102C-T2A is a common driver for large-scale dot matrix LCD panels. It includes a 160-bit bidirectional shift register and 4-level LCD driver circuits. The number of bits can be further increased by using the provided input and output pins to connect multiple LC4102C-T2A in cascade. The LC4102C-T2A and the LC4104C-T2A LCD dot matrix segment driver IC form a large-screen LCD panel driver chip set. • • • • • • Fabricated in a CMOS (P-sub) high-voltage process. LCD drive voltage: 36 V Logic system power-supply voltage: 2.7 to 5.5 V fcp max: 2.5 MHz Bidirectional shift register The shift register can be split into two 80-bit registers. (Two screens drivable) • DISPOFF function that locks the drive voltages output to the LCD at fixed levels. • Display duty: 1/160 to 1/480 • Package: TCP (Tape Carrier Package) Specifications The electrical characteristics values shown below are for devices packaged in the SANYO standard PGA-208 package. Absolute Maximum Ratings at VSS = 0 Parameter Supply voltage Symbol Ratings Unit VDD –0.3 to +7.0 VEE max VEE –0.3 to +40.0 V VSSH max VSSH –0.3 to +0.3 V –0.3 to VDD + 0.3 V VIN V0, V1 Input voltage Applicable pins VDD max *1 V0, V1 *2 V VEE – 7.0 to VEE + 0.3 V V V4 V4 *2 –0.3 to VSS + 7.0 V5 V5 *2 –0.3 to +0.3 V Operating temperature Topr –20 to +75 °C Storage temperature Tstg –55 to +125 °C Note: 1. LOAD, RS/LS, DISP, DF, DIO1, DIO160, DMIN and MODE 2. The voltages V0, V1, V4, and V5 must obey the relationships VEE ≥ V0 ≥ V1 ≥ VEE – 7 V, and 7 V ≥ V4 ≥ V5 ≥ VSSH. Any and all SANYO products described or contained herein do not have specifications that can handle applications that require extremely high levels of reliability, such as life-support systems, aircraft’s control systems, or other applications whose failure can be reasonably expected to result in serious physical and/or material damage. Consult with your SANYO representative nearest you before using any SANYO products described or contained herein in such applications. SANYO assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO products described or contained herein. SANYO Electric Co.,Ltd. Semiconductor Company TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN 20702TN (OT) No. 6789-1/8 LC4102C-T2A Allowable Operating Ranges at VSS = 0, Ta = –20 to +75°C Parameter Supply voltage Symbol Ratings Applicable pins min typ Unit max VDD VDD 2.7 5.5 V VEE VEE 14 36 V VSSH VSSH 0 V Input high-level voltage VIH *1 0.8 × VDD VDD V Input low-level voltage VIL *1 0 0.2 × VDD V VEE – 7.0 VEE V 0 VSSH + 7.0 V0, V1 Input voltage V0, V1 *2 V4 V4 *2 V5 V5 *2 0 V V Note: 1. LOAD, RS/LS, DISP, DF, DIO1, DIO160, DMIN and MODE 2. The voltages V0, V1, V4, and V5 must obey the relationships VEE ≥ V0 ≥ V1 ≥ VEE – 7 V, and 7 V ≥ V4 ≥ V5 ≥ VSSH. When turning on the power supplies, first turn on the logic system power supply and then turn on the high-voltage system power supply; alternatively, turn both on at the same time. When turning off the power supplies, first turn off the high-voltage system power supply and then turn off the logic system power supply; alternatively, turn both off at the same time. Electrical Characteristics at Ta = –20 to +75°C, VDD = 2.7 to 5.5 V, VSS = 0 V Parameter Symbol Applicable pins Input high-level current IIH VIN = VDD*1 Input low-level current IIL VIN = VSS*1 Output high-level voltage VOH IOH = –0.4 mA, DIO1, DIO160 Output low-level voltage VOL IOL = 0.4 mA, DIO1, DIO160 Output on resistance Ratings min typ Unit max 1 –1 0.8 × VDD VDD VSS 0.2 × VDD RON0 VOUT = V0 – 0.5 V *2, OUT1 to 160 RON1 VOUT = V1 – 0.5 V *2, OUT1 to 160 1000 RON4 VOUT = V4 + 0.5 V *2, OUT1 to 160 1000 VOUT = V5 + 0.5 V *2, OUT1 to 160 1000 RON5 µA V 1000 Current drain 1 IDD VDD*3 200 Current drain 2 IDDH VDD*4 500 Ω µA Note: 1. LOAD, RS/LS, DISP, DF, DIO1, DIO160, DMIN and MODE 2. VOUT is the voltage applied by on-state outputs. V0 = VEE, V1 = 19/20 (VEE – VSSH), V4 = 1/20 (VEE – VSSH), V5 = VSSH, VSSH = VSS 3. VDD = 2.7 to 5.5 V, fCP = 50 kHz 4. fDF = 100 Hz, with no output load, VEE = 36 V, for a single data shift No. 6789-2/8 LC4102C-T2A OUT160 OUT159 OUT158 OUT3 OUT2 OUT1 Block Diagram V0 V1 V0 4 Level LCD Driver Circuit (160 bits) V1 V4 V4 V5 V5 Output Control VEE VEE Level Shifter VSSH VSSH DISP DF DI01 Bidirectional Shift Register (80 bits) Shift Control Bidirectional Shift Registe (80 bits) DIO160 RS/LS VSS DMIN VDD MODE LOAD A13673 No. 6789-3/8 LC4102C-T2A Switching Characteristics at Ta = –20 to +75°C, VDD = 2.7 to 5.5 V, VSS = 0 V Parameter Clock frequency Symbol Conditions Ratings min fload LOAD High-level clock pulse width twl LOAD 100 Input setup time tsu LOAD, DIOn, DMIN 100 Input hold time th LOAD, DIOn, DMIN 30 LOAD rising time tr LOAD LOAD falling time DIO output delay time LOAD-on delay time DF-on delay time tf typ max 2.5 30 LOAD 30 tpld LOAD, DIOn: 30 pF capacitance load 200 tplo LOAD, OUTn: 100 pF capacitance load 1.0 DF, OUTn: 100 pF capacitance load 1.0 tpdfo Unit MHz ns µs Switching Characteristics tr tW1 tf 0.8VDD 0.2VDD LOAD tsu th DIOn DMIN tpld DIO output tplo OUTn tpdfo DF A13674 No. 6789-4/8 LC4102C-T2A Pin Functions Symbol I/O Function LCD drive outputs OUT1 to OUT160 O DF Data DISP OUTn L H H V0 H L H V1 L L H V4 H H H V5 * * L V5 V0 I V0 level drive voltage input V1 I V1 level drive voltage input V4 I V4 level drive voltage input V5 I V5 level drive voltage input VEE – High-voltage block power supply *: don’t care VSSH – High-voltage block ground DISP I LCD off function. All outputs will be held at a fixed V5 level when this pin is low. DF I Alternation input LOAD I Data shift pulse input (falling edge) MODE I Data shift direction specification input RS/LS I DIO1 I/O DMIN I DIO160 I/O MODE RS/LS Shift direction DIO1 DIO160 DMIN L L OUT160 → OUT1 OUT IN * L H OUT1 → OUT160 IN OUT * H L OUT160 → OUT81 OUT80 → OUT1 OUT IN IN H H OUT1 → OUT80 OUT81 → OUT160 IN OUT IN *: don’t care (Must be fixed at low or high.) VDD — Logic system power supply VSS — Logic system ground No. 6789-5/8 LC4102C-T2A Pin Assignment DUMMY OUT160 OUT159 OUT158 VSSH V5 V4 V1 V0 VEE VSSH DIO160 DMIN DIO1 VSS LC4102C-T2A (CHIP TOP VIEW) LOAD VSS DF DISP VDD RSLS MODE VSSH VEE V0 V1 V4 V5 VSSH OUT3 OUT2 OUT1 DUMMY A13675 Note: This figure shows the chip pattern surface as seen from abobe. This figure dose not stipulate the TCP package. No. 6789-6/8 A=0.3±0.05 1.2±0.05(SL) 1.2±0.05(SL) 15.0 3.7(Cut line) 10.3±0.05 1.7±0.3(SR) 8.5±0.3(SR) 6.7±0.05(SL) 4.9±0.05(SL) 1.2±0.05(SL) 2.0±0.05(SL) 0.6 MAX 0.6 MAX 1.7±0.1(SL) 0.6 MAX 0.4±0.05 V1 V0 VEE RSLS VSSH VDD MODE DISP DF VSS DIO1 LOAD DMIN VSS DIO160 V0 VSSH V1 VEE VSSH A V5 V4 V4 V5 19.8±0.1 VSSH 19.8±0.1 24.0±0.055 12.55±0.1(SL) 12.55±0.1(SL) 0.14(P)×(162--1)=22.54±0.055 (W=0.09) 23.6±0.05(SL) ø1.0±0.05 1.7±0.1(SL) 0.4±0.02 0.6±0.02 R0.5±0.05 u) 0.1 ø 2.0 ± (C 1.95(LSI) 1.981±0.03 R0.8±0.3(SR) 2.45 4.75±0.03 18.25 MAX(Sealing area) 16.25±0.05(Device hole) 15.75(LSI) 4.0±0.1(SL) 8.0±0.1(SL) 48.175±0.2 42.177±0.07 32.0±0.1 25.5(Cut line) 24.3±0.3(SR) 23.0±0.05(SL) 22.0±0.05(SL) 0.8(P)×(25--1)=19.2±0.055 (W=0.34) Device hole Sealing area 0.3 MAX Flex hole LSI chip 0.75 MAX 1.35 MAX LC4102C-T2A Package Dimensions unit: mm LC4102C-T2A No. 6789-7/8 4.75(P)×4=19.0±0.05 4.45 MAX(Sealing area) LC4102C-T2A Specifications of any and all SANYO products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer’s products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer’s products or equipment. SANYO Electric Co., Ltd. strives to supply high-quality high-reliability products. However, any and all semiconductor products fail with some probability. It is possible that these probabilistic failures could give rise to accidents or events that could endanger human lives, that could give rise to smoke or fire, or that could cause damage to other property. When designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. In the event that any or all SANYO products (including technical data, services) described or contained herein are controlled under any of applicable local export control laws and regulations, such products must not be exported without obtaining the export license from the authorities concerned in accordance with the above law. No part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written permission of SANYO Electric Co., Ltd. Any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. When designing equipment, refer to the “Delivery Specification” for the SANYO product that you intend to use. Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. This catalog provides information as of February, 2002. Specifications and information herein are subject to change without notice. PS No. 6789-8/8