Ordering number : EN5682 CMOS LSI LC7972VA, 7972VB CMOS Operational Amplifier with Programmable Offset Correction Function Overview The LC7972VA and LC7972VB are dual inverting/noninverting operational amplifier ICs that are fabricated in a CMOS process. These ICs provide a programmable offset correction function and a power saving function for use when the operational amplifier is unused, both of which can be controlled from a microprocessor interface. • The following modes are supported. These are selected via port level settings. Package Dimensions unit: mm 3179A-SSOP20 [LC7972VA, VB] Features • High input impedance provided by fabrication in a CMOS process. • Low power provided by fabrication in a CMOS process. • One of two types of operational amplifier can be selected: inverting (operational amplifier 1) or noninverting (operational amplifier 2) • Operating supply voltage: 4.9 to 5.2 V • Package: SSOP20 • Operating temperature: Ta = –30 to +70°C Port Level L OP1ON OP2ON OFST1 OFST2 CLKC SANYO: SSOP20 Function Operational amplifier 1: Operation stopped (low-power mode) H Operational amplifier 1: Normal operation (OP2ON must be low in this mode.) L Operational amplifier 2: Operation stopped (low-power mode) H Operational amplifier 2: Normal operation (OP1ON must be low in this mode.) L Operational amplifier 1: Offset mode (inverting input = VSS) H Operational amplifier 1: Operating mode (inverting input = normal input) L Operational amplifier 2: Offset mode (noninverting input = VSS) H Operational amplifier 2: Operating mode (noninverting input = normal input) L Operational amplifier power supply clock: Internal clock ■ No products described or contained herein are intended for use in surgical implants, life-support systems, aerospace equipment, nuclear power control systems, vehicles, disaster/crime-prevention equipment and the like, the failure of which may directly or indirectly cause injury, death or property loss. ■ Anyone purchasing any products described or contained herein for an above-mentioned use shall: ➀ Accept full responsibility and indemnify and defend SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors and all their officers and employees, jointly and severally, against any and all claims and litigation and all damages, cost and expenses associated with such use: ➁ Not impose any responsibility for any fault or negligence which may be cited in any such claim or litigation on SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors or any of their officers and employees jointly or severally. ■ Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. This catalog provides information as of July, 1997. Specifications and information herein are subject to change without notice. SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110 JAPAN 73097HA(OT) No. 5682-1/4 LC7972VA, 7972VB Pin Assignment Pin Functions Pin Function No. Symbol 1 DVDD Digital system power supply. Normally connected to +5 V. 2 EXT Must be tied low. Must be tied low. 3 CLKC 4 OP2ON Operational amplifier 2 operation control 5 OFST2 Operational amplifier 2 mode control 6 OP1ON Operational amplifier 1 operation control 7 OFST1 8 TGO Operational amplifier 1 VSS/small voltage output Operational amplifier 1 mode control 9 OP1I Operational amplifier 1 input 10 OP1O Operational amplifier 1 output 11 OP2O Operational amplifier 2 output 12 OP2I Operational amplifier 2 input 13 TGI Small voltage input common to operational amplifiers 1 and 2 14 AVSSM Operational amplifier power supply minus voltage generation 15 AVDD Analog system power supply. Normally connected to +5 V. 16 AVSSP Operational amplifier power supply external Zener diode connection 17 AVSS Analog system ground. Must be connected to 0 V. 18 CUP2 Operational amplifier power supply external capacitor connection 2 19 CUP1 Operational amplifier power supply external capacitor connection 1 20 DVSS Digital system ground. Must be connected to 0 V. No. 5682-2/4 LC7972VA, 7972VB System Block Diagram and Sample Application A circuit that amplifies very small voltages around the VSS level can be constructed by adding the peripheral circuits shown in the figure below. Step-down voltage converter circuit Small-voltage input A/D converter inputs Microcontroller Port outputs No. 5682-3/4 LC7972VA, 7972VB Specifications Absolute Maximum Ratings at Ta = 25°C, VSS = 0 V Parameter Maximum supply voltage Output voltage Input voltage Peak output current Average output current Allowable power dissipation Symbol VDD max Conditions Ratings VDD Unit –0.3 to +7.0 V VO OP1O, OP2O, TGO –0.3 to VDD+0.3 V VI1 OP1ON, OFST1, OP2ON, OFST2, EXT, CLKC, CUP2, CUP1, AVSSP, OP1I, OP2I, TGI –0.3 to VDD+0.3 V VI2 AVSSM IOP OP1O, OP2O, TGO –1 to +1 OP1O, OP2O, TGO : The current per pin –1 to +1 mA 100 mW IOA Pd max –3 to +0.3 SSOP20 : Ta = –30 to +70°C V mA Operating temperature Topr –30 to +70 °C Storage temperature Tstg –55 to +125 °C Allowable Operating Ranges at Ta = –30 to +70°C, VSS = 0 V, VDD = 4.9 to 5.2 V, unless otherwise specified Parameter Symbol Conditions Supply voltage VDD VDD Input high-level voltage VIH OP1ON, OFST1, OP2ON, OFST2 VIL1 VIL2 Input low-level voltage Common-mode input voltage VIC Voltage drop DV Ratings min typ Unit max 4.9 5.2 V 0.7 VDD VDD V OP1ON, OFST1, OP2ON, OFST2, CLKC VSS 0.3 VDD V EXT VSS 0.3 VDD V 0 4.2 V AVSSM: Zener diode = 5.1 V (X rank specified) –0.2 V Electrical Characteristics at Ta = –30 to +70°C, VSS = 0 V, VDD = 4.9 to 5.2 V, unless otherwise specified Parameter Input high-level current Input low-level current Symbol Conditions Unit max OP1ON, OFST1, OP2ON, OFST2 : VIN = VDD 1.0 µA IIH2 TGI: VIN = VDD, with the built-in TG off. 1.0 µA IIL1 OP1ON, OFST1, OP2ON, OFST2, EXT, CLKC : VIN = VSS IIL2 TGI: VIN = VSS, with the built-in TG off. VOH OP1O, OP2O : IOH = –3 µA Output low-level voltage VOL OP1O, OP2O : IOL = 3 µA Operational amplifier 1 gain-related resistance difference typ IIH1 Output high-level voltage Operational amplifier 1 gain-related resistance Ratings min Rtg + 2Rs TGO, TGI –1.0 µA –1.0 µA VDD – 0.5 500 V 700 0.5 V 900 Ω 80 Ω |Rx–Ry| TGO, TGI: Offset mode: Rx = Rtg + 2Rs Operating mode: Ry = Rtg + 2Rs Operating IDDOP VDD; Using the internal clock, with the operational amplifier 1 circuit operating. 700 900 µA Standby IDDST VDD; Both operational amplifiers 1 and 2 stopped. 0.05 10 µA Current drain Operational Amplifier Characteristics at Ta = 25°C ±2°C, VSS = 0 V, VDD = 4.9 to 5.2 V, unless otherwise specified Parameter Input offset voltage Symbol Conditions Ratings min typ Unit max OP1I, OP2I : LC7972VA 5 10.5 mV LC7972VB 5 15 mV VIO Supply voltage rejection ratio PSRR 60 dB Common-mode rejection ratio CMRR 60 dB Open-loop voltage gain AO 80 dB 0-dB bandwidth fT 90 kHz 1 kHz Maximum output voltage VO OP1O, OP2O : RL ≥ 100 kΩ VDD – 0.5 V Current drain ICC For the operational amplifier 1 circuit 100 µA Settling time TSET OP1O, OP2O 900 µs No. 5682-4/4