Ordering number : ENN4212A CMOS IC LC86P6032 8-Bit Single Chip Microcontroller with One-Time PROM Overview The LC86P6032 microcontroller, a new addition to the LC866000 series, is a 8-bit single chip CMOS microcontroller with one-time PROM. This microcontroller has the same function and pin assignment as for the LC866000 series mask ROM version, and a 32K-byte PROM. Features (1) Option switching using PROM data The optional functions of the LC866000 series can be specified using PROM data. The functions of the trial products can be evaluated using a mass production board. (2) Internal one-time PROM capacity : 32768 bytes (3) Internal RAM capacity : 512 bytes Mask ROM version LC866032 LC866028 LC866024 LC866020 LC866016 LC866012 LC866008 PROM capacity RAM capacity 32512 bytes 28672 bytes 24576 bytes 20480 bytes 16384 bytes 12288 bytes 8192 bytes 512 bytes 512 bytes 512 bytes 384 bytes 384 bytes 384 bytes 384 bytes (4) Operating supply voltage : 4.5V to 6.0V (5) Instruction cycle time : 0.98µs to 400µs (6) Operating temperature range : -30°C to +70°C (7) Pin and package compatible with the mask ROM version (8) Applicable mask ROM version : LC866032/LC866028/LC866024/LC866020/LC866016/LC866012 /LC866008 (9) Factory shipment : DIP64S : QFP64E Programming service We offer various services at nominal charges. These include ROM writing, ROM reading, and package stamping and screening. Contact our local representatives for further information. Ver.1.02G 31293 91400 RM (IM) TW No.4212-1/22 LC86P6032 Notice for use When using, please take note of the following. (1) Differences between the LC86P6032 and the LC866000 series Item Port status at reset Operation after releasing reset Output form of segment •S0/T0 to S6/T6 •S7/T7 to S15/T15 •S16 to S23 •S24 to S29 Operating supply voltage range (VDD) Power dissipation LC86P6032 LC866032/28/24/20/16/12/08 Please refer to “Port status at reset” on the next page. The option is specified by degrees within The program located at 00H is executed 3ms after applying a ‘H’ level to the reset immediately after applying a ‘H’ level to pin. the reset pin. The program located at 00H is executed. Pulldown resistor Pulldown resistor : Provided/Not provided Not provided Specified by the option Provided(fixed) Provided(fixed) Provided(fixed) Specified by the option Not provided Specified by the option 4.5V to 6.0V 2.5V to 6.0V Refer to “electrical characteristics” on the semiconductor news. LC86P6032 uses 256 bytes that is addressed on 7F00H to 7FFFH in the program memory as the option configuration data area. This option configuration cannot execute all options which LC866000 series have. Next tables show the options that correspond and not correspond to LC86P6032. • LC86P6032 Options Option Pins, Circuits Option Settings Configuration of input/output ports Port 0 (Can be specified for each bit.) 1. Input : No pull-up MOS transistor Output : N-channel open drain 2. Input : Pull-up MOS transistor Output : CMOS 1. Input : Programmable pull-up MOS transistor Output : N-channel open drain 2. Input : Programmable Pull-up MOS transistor Output : CMOS 1. Pull-up MOS transistor not provided. 2. Pull-up MOS transistor provided. Port 1 (Can be specified for each bit.) Port 7 pull-up MOS transistor Port 7 (Can be specified for each bit.) • A kind of option not corresponding LC86P6032 Option Pull-down resistor of high voltage withstand output terminal Pins, Circuits ·S0/T0 to S6/T6 ·S16 to S23 ·S24 to S29 (specified in a bit) LC86P6032 LC866032/28/24/20/16/12/08 Not provided Provided(fixed) Not provided Specified by the option Specified by the option Specified by the option The port operation related to the option is different at reset. Please refer to the next table. No.4212-2/22 LC86P6032 • Port configuration at reset Pin P0 P1 P7 Option settings LC86P6032 Input : No pull-up MOS transistor Output : N-channel open drain Input : Pull-up MOS transistor Output : CMOS Input : Programmable pull-up MOS transistor Output : N-channel open drain Input : Programmable pull-up MOS transistor Output : CMOS Pull-up MOS transistor not provided Pull-up MOS transistor provided LC866032/28/24/20/16/12/08 (Same as for the mask version) Input mode •The Pull-up MOS transistor is not present during reset or several hundred microseconds after releasing reset. After that, the pull-up MOS transistor is present. (Output is OFF) (Same as for the mask version) Input mode without pull-up MOS transistor (Output is OFF) Input mode with pull-up MOS transistor (Output is OFF) Input mode without pull-up MOS transistor (Output is OFF) (Same as for the mask version) Input mode without pull-up MOS transistor (Output is OFF) (Same as for the mask version) Input mode without pull-up MOS transistor Input mode with pull-up MOS transistor Input mode •The Pull-up MOS transistor is not present during reset or several hundred microseconds after releasing reset. After that, the pull-up MOS transistor is present. (2) Option The option data is created by the option specified program “SU866000.EXE”. The created option data is linked to the program area by the linkage loader “L866000.EXE”. (3) ROM space LC86P6032 and LC866000 series use 256 bytes that is addressed on 07F00H to 07FFFH in the program memory as the option specified data area. These program memory capacity are 32512 bytes that is addressed on 0000H to 7EFFH. Option data 7FFFH 7F00H area 256 bytes 7EFFH Option Data Area Option Data Area Option Data Area Option Data Area Option Data Area Option Data Area 32K 28K 24K 20K 16K 12K 8K LC866032 LC86P6032 LC866028 LC866024 LC866020 LC866016 LC866012 LC866008 6FFFH 5FFFH 4FFFH 3FFFH 2FFFH 1FFFH 0000H (4) Ordering information 1.When ordering identical mask ROM and PROM devices simultaneously. Provide an EPROM containing the target memory contents together with separate order forms for each of the mask ROM and PROM versions. 2. When ordering a PROM device. Provide an EPROM containing the target memory contents together with an order form. No.4212-3/22 LC86P6032 How to use (1) Specification of option LC86P6032 is programmed after specifying option data. The option is specified by the SU866000.EXE. The specified option file and the file created by our macro assembler (M866000.EXE) are linked by our linker (L866000.EXE) which creates HEX file, then the option code is put in the option specified area (07F00H to 07FFFH) of its HEX file. (2) How to program for the EPROM The LC86P6032 can be programmed by an EPROM programmer with attachments W86EP6032D and W86EP6032Q. - Recommended EPROM programmer Supplier EPROM programmer Advantest Andou AVAL Minato electronics R4945, R4944, R4943 AF-9704 PKW-1100, PKW-3000 MODEL 1890A - “27512 (Vpp=12.5V) Intel high-speed programming” mode available. The address must be set to “0000H to 07FFFH” and the jumper (DASEC) must be set ‘OFF’ at programming. (3) How to use the data security function “Data security” is a function to prevent EPROM data from being read. Instructions on using the data security function : 1. Set the jumper of attachment “ON”. 2. Attempt to program the EPROM. The EPROM programmer will display an error. The error indication is a result of normal activity of the data security feature. This is not a problem with the EPROM programmer chip. (Notes) • The data security function is not carried out when the data of all addresses contain “FF” at step 2 above. • Data security cannot be executed when the sequential operation “BLANK=>PROGRAM=>VERIFY” is used at step 2 above. • Set the jumper “OFF” after execution of data security. 1 pin mark of LSI Data security Data security 1 pin Not data security Not data security 1 pin W86EP6032Q W86EP6032D No.4212-4/22 LC86P6032 Pin Assignment P10/SO0 1 64 P07 P11/SI0/SB0 2 63 P06 P12/SCK0 3 62 P05 P13/SO1 4 61 P04 P14/SI1/SB1 5 60 P03 P15/SCK1 6 59 P02 P16/BUZ 7 58 P01 P17/PWM 8 57 P00 TEST1 9 56 S29 RES 10 55 S28 XT1 11 54 S27 XT2 12 53 S26 VSS 13 52 S25 CF1 14 51 S24 CF2 15 50 S23 VDD 16 49 S22 P80/AN0 17 48 S21 P81/AN1 18 47 S20 P82/AN2 19 46 S19 P83/AN3 20 45 S18 P70/INT0 21 44 S17 P71/INT1 22 43 S16 72/INT2/T0IN 23 42 VP 73/INT3/T0IN 24 41 VDDVPP S0/T0 25 40 S15/T15 S1/T1 26 39 S14/T14 S2/T2 27 38 S13/T13 S3/T3 28 37 S12/T12 S4/T4 29 36 S11/T11 S5/T5 30 35 S10/T10 S6/T6 31 34 S9/T9 S7/T7 32 33 S8/T8 Package Dimension (unit : mm) 3071 SANYO : DIP-64S(750mil) No.4212-5/22 LC86P6032 P17/PWM P16/BUZ P15/SCK1 P14/SI1/SB1 P13/SO1 P12/SCK0 P11/SI0/SB0 P10/SO0 P07 P06 P05 P04 P03 P02 P01 P00 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 Pin Assignment TEST1 49 32 S29 RES 50 31 S28 XT1 51 30 S27 XT2 52 29 S26 VSS 53 28 S25 CF1 54 27 S24 CF2 55 26 S23 12 13 14 15 16 S13/T13 S14/T14 S15/T15 VDDVPP S12/T12 17 S11/T11 64 11 73/INT3/T0IN S10/T10 VP 10 18 9 63 S9/T9 S16 72/INT2/T0IN S8/T8 S17 19 8 20 62 7 61 P71/INT1 S7/T7 P70/INT0 S6/T6 S18 6 S19 21 S5/T5 22 60 5 59 P83/AN3 4 P82/AN2 S4/T4 S20 S3/T3 23 3 58 2 S21 P81/AN1 S2/T2 S22 24 S1/T1 25 57 1 56 S0/T0 VDD P80/AN0 Package Dimension (unit : mm) 3159 SANYO : QIP-64E Notes • The QFP packages should be heat-soaked for 24 hours at 125°C immediately prior to mounting (This baking is called pre-baking). • After pre-baking, a controlled environment must be maintained until soldering. The environment must be held at a temperature of 30°C or less and a humidity level of 70% or less. Please solder within 8 hours. No.4212-6/22 LC86P6032 System Block Diagram Interrupt Control IR Stand-by Control RC A15-A0 D7-D0 TA CE OE DASEC VDDVPP PROM Control Clock Generator CF PLA PROM(32KB) X’tal PC Base Timer Bus Interface ACC SIO0 Port 1 B Register SIO1 Port 7 C Register Timer 0 Port 8 ALU Timer 1 ADC PSW INT0 to 3 Noise Rejection Filter RAR Real Time Service RAM XRAM (128 bytes) Stack Pointer Port 0 VFD Controller Watch dog Timer High Voltage Output No.4212-7/22 LC86P6032 Pin Description Pin Description Table Pin name VSS VDD VP I/O Function Description - Power supply pin (-) Power supply pin (+) Power supply pin (-) for the VFD output pull-down resist Power supply pin (+) *6 •8-bit Input / output port •Input for port 0 interrupt •Input/output in nibble units •Input for HOLD release VDDVPP PORT0 P00 to P07 I/O PORT1 P10 to P17 I/O PORT7 P70 I/O P71 to P73 I PORT8 P80 to P83 I S0/T0 to S6/T6 *7 S7/T7 to S15/T15 O O *8 S16 to S23 O *9 S24 to S29 O *10 RES I Option Function in PROM mode Power for programming •Pull-up resistor : Present/Not present •Output form : CMOS/N-channel open drain Output form : CMOS/N-channel open drain •8-bit input/output port •Data direction can be specified for each bit. •Other pin functions P10 : SIO0 data output P11 : SIO0 data input/bus input/output P12 : SIO0 clock input/output P13 : SIO1 : data output P14 : SIO1 : data input/bus input/output P15 : SIO1 clock input/output P16 : Buzzer output P17 : Timer 1 output (PWM output) •4-bit input port •Pull-up resistor : •Other pin functions Present/Not present P70 : INT0 input/HOLD release/N-channel Tr. output for watchdog timer P71 : INT1 input/HOLD release P72 : INT2 input/timer 0 event input P73 : INT3 input with noise filter/timer 0 event input •Interrupt received format, vector address Rising Falling Rising H level L level Vector /falling Enable Enable Disable Enable Enable 03H INT0 INT1 Enable Enable Disable Enable Enable 0BH INT2 Enable Enable Enable Disable Disable 13H INT3 Enable Enable Enable Disable Disable 1BH •4-bit input port •Other pin functions AD input port (4 port pins) Output for VFD display controller segment/timing in common •Output for VFD display controller segment/timing in common •Internal pull-down resistor output Data input/output D0 to D7 •Output for VFD display controller segment •Internal pull-down resistor output •Output for VFD display controller segment Address input A13 to A0 Input of PROM control signal •DASEC (*1) • OE (*2) • CE (*3) •S14/T14 : TA (*4) •S15/T15 : A14 (*5) Reset pin No.4212-8/22 LC86P6032 Pin name I/O TEST1 O XT1 I XT2 O CF1 CF2 I O Function Description Option Function in PROM mode Test pin Should be left open Input pin for 32.768kHz crystal oscillation When not used, connect to VDD Output pin for 32.768kHz crystal oscillation When not used, should be left open Input pin for ceramic resonator oscillation Output pin for ceramic resonator oscillation • All port options can be specified in bit units. *1 *2 *3 *4 *5 *6 Memory select input for data security Output enable input Chip enable input TA ! PROM control signal input A14 ! Address input Connect as shown in the following figure to reduce noise into VDD pin. • Short-circuit the VDD pin to the VDDVPP pin. LSI VDD Power Supply VDDVPP VSS *7 *8 *9 *10 S0/T0 to S6/T6 : not provided the pull-down resistor S7/T7 to S15/T15 : provided the pull-down resistor (fixed) S16 to S23 : provided the pull-down resistor (fixed) S24 to S29 : not provided the pull-down resistor No.4212-9/22 LC86P6032 1. Absolute Maximum Ratings at VSS=0V and Ta=25°C Parameter Symbol Pins Supply voltage Input voltage VDDMAX VI(1) Output voltage VI(2) VO VDD,VDDVPP •Ports 71,72,3,8 • RES VP •S0/T0 to S15/T15 •S16 to S29 •Ports 0, 1 •Port 70 Ports 0, 1 Input/Output voltage High Peak level output output current current Total output current Low level output current Peak output current Total output current Power dissipation (max.) Operating temperature range Storage temperature range VIO IOPH(1) IOPH(2) IOPH(3) ∑IOAH(1) ∑IOAH(2) ∑IOAH(3) IOPL(1) IOPL(2) S0/T0 to S15/T15 S16 to S29 Port 0 Port 1 •S0/T0 to S15/T15 •S16 to S29 Ports 0, 1 Port 70 ∑IOAL(1) ∑IOAL(2) Pdmax(1) Pdmax(2) Topr Tstg Conditions Ratings VDD[V] min. -0.3 -0.3 VDD-4.5 VDD-4. 5 -0.3 •CMOS output •At each pin •At each pin •At each pin Total of all pins Total of all pins Total of all pins typ. max. +7.0 unit V VDD+0.3 VDD+0.3 VDD+0.3 VDD+0.3 -4 mA -30 -15 -10 -10 -130 At each pin At each pin 20 15 Port 0 Ports 1, 70 Total of all pins Total of all pins 40 40 DIP64S QFP64E Ta=-30 to+70°C Ta=-30 to+70°C -30 760 430 +70 -65 +150 mW °C Notes • The QFP packages should be heat-soaked for 24 hours at 125°C immediately prior to mounting (This baking is called pre-baking). • After pre-baking, a controlled environment must be maintained until soldering. The environment must be held at a temperature of 30°C or less and a humidity level of 70% or less. Please solder within 8 hours. No.4212-10/22 LC86P6032 2. Recommended Operating Range at Ta=-30°C to +70°C, VSS=0V Parameter Symbol Pins Conditions Ratings VDD[V] min. typ. max. Operating supply voltage range Hold voltage VDD VDD 0.98µs ≤ tCYC ≤ 400µs 4.5 6.0 VHD VDD RAM and registers retain their pre-HOLD mode values 2.0 6.0 Pull-down voltage Input high voltage VP VP -35 VDD VIH(1) Port 0 (Schmitt) Output disable VIH(2) •Port 1 •Ports 72,73 (Schmitt) •Port 70 port input/interrupt •Port 71 (Schmitt) • RES Port 70 Watchdog timer Port 8 Port 0 (Schmitt) •Port 1 •Ports 72,73 (Schmitt) •Port 70 port input/interrupt •Port 71 (Schmitt) • RES Port 70 Watchdog timer Port 8 Output disable VIH(3) VIH(4) Input low voltage VIH(5) VIL(1) VIL(2) VIL(3) VIL(4) Operation cycle time VIL(5) tCYC 4.5 to 6.0 4.5 to 6.0 0.4VDD +0.9 4.5 to 6.0 0.75VDD VDD Output N-channel Tr. OFF 4.5 to 6.0 0.75VDD VDD Output N-channel Tr. OFF 4.5 to 6.0 0.9VDD VDD 4.5 to 6.0 0.75VDD 4.5 to 6.0 VSS 4.5 to 6.0 VSS VDD 0.2VDD 0.25VDD N-channel Tr. OFF 4.5 to 6.0 VSS 0.25VDD N-channel Tr. OFF 4.5 to 6.0 VSS 4.5 to 6.0 4.5 to 6.0 VSS 0.98 0.8VDD -1.0 0.25VDD 400 Output disable Output disable unit V VDD µs continue No.4212-11/22 LC86P6032 Parameter Symbol Pins Oscillation frequency range (Note 1) FmCF(1) CF1,CF2 FmCF(2) CF1,CF2 FmRC FsXtal Oscillation stable time period (Note 1) XT1,XT2 tmsCF(1) CF1,CF2 tmsCF(2) CF1,CF2 tssXtal (Note 1) XT1,XT2 Conditions Ratings VDD[V] min. typ. max. •12MHz (ceramic resonator oscillation) •Refer to figure 1 •3MHz (ceramic resonator oscillation) •Refer to figure 1 RC oscillation 4.5 to 6.0 11.76 12 12.24 4.5 to 6.0 2.94 3 3.06 4.5 to 6.0 0.4 0.8 2.0 •32.768kHz (crystal resonator oscillation) •Refer to figure 2 •12MHz (ceramic resonator oscillation) •Refer to figure 3 •3MHz (ceramic resonator oscillation) •Refer to figure 3 •32.768kHz (crystal resonator oscillation) •Refer to figure 3 4.5 to 6.0 32.768 4.5 to 6.0 0.02 0.2 4.5 to 6.0 0.1 1 4.5 to 6.0 1 1.5 unit MHz kHz ms s The oscillation constants are shown on Table 1 and Table 2. No.4212-12/22 LC86P6032 3. Electrical Characteristics at Ta=-30°C to +70°C, VSS=0V Parameter Input high current Input low current Symbol Pins Conditions IIH(1) •Port 1 •Port 0 without pull-up MOS Tr. IIH(2) •Port 7 without pull-up MOS Tr. •Port 8 RES •Port 1 •Port 0 without pull-up MOS Tr. •Output disabled •Pull-up MOS Tr. OFF •VIN=VDD (including off-state leak current of output Tr.) VIN=VDD IIH(3) IIL(1) IIL(2) Output high voltage Output low voltage Pull-up MOS Tr. resistance IIL(3) VOH(1) VOH(2) VOH(3) VOH(4) •Port 7 without pull-up MOS Tr. •Port 8 RES Ports 0, 1 at CMOS output S0/T0 to S15/T15 VOH(5) VOH(6) S16 to S29 VOL(1) VOL(2) Ports 0, 1 VOL(3) Rpu Port 70 •Ports 0, 1 •Port 7 VIN=VDD •Output disabled •Pull-up MOS Tr. OFF •VIN=VSS (including off-state leak current of output Tr.) VIN=VSS VIN=VSS IOH=-1.0mA IOH=-0.1mA IOH=-20mA •IOH=-1mA •The current IOH at each pin should be between 0 and -1mA. IOH=-5mA •IOH=-1mA •The current IOH at each pin should be between 0 and -1mA. IOL=10mA •IOL=1.6mA •When the total current of the ports 0, 1 is not over 40mA. IOL=1mA VOH=0.9VDD Ratings VDD[V] min. typ. max. 4.5 to 6.0 1 4.5 to 6.0 1 4.5 to 6.0 4.5 to 6.0 -1 4.5 to 6.0 -1 4.5 to 6.0 4.5 to 6.0 4.5 to 6.0 4.5 to 6.0 4.5 to 6.0 -1 VDD-1 unit µA 1 V VDD-0.5 VDD-1.8 VDD-1 4.5 to 6.0 VDD-1.8 4.5 to 6.0 VDD-1 4.5 to 6.0 4.5 to 6.0 4.5 to 6.0 4.5 to 6.0 1.5 0.4 15 40 0.4 70 KΩ continue No.4212-13/22 LC86P6032 Parameter Symbol Output offleakage current IOFF(1) Pull-down resistor Rpd Hysteresis voltage VHIS Pin capacitance CP IOFF(2) Pins Conditions S0/T0 to S6/T6, •Output P-ch Tr. OFF S24 to S29 without •VOUT=VSS pull-down resistor •Output P-ch Tr. OFF •VOUT=VDD-40V S7/T7 to S15/T15, •Output P-ch Tr. OFF •VOUT=3V S16 to S23 with pull-down resistor •Vp=-30V •Ports 0, 1 Output disable •Port 7 • RES •f=1MHz All pins •Unmeasured input pins are set to VSS level •Ta=25°C Ratings VDD[V] min. 4.5 to 6.0 -1 4.5 to 6.0 -30 5.0 60 typ. max. unit µA 100 200 KΩ 4.5 to 6.0 0.1VDD V 4.5 to 6.0 10 pF Serial output Serial input Symbol Cycle Low-level pulse width High-level pulse width Cycle Low-level pulse width High-level pulse width Data set up time tCKCY(1) tCKL(1) Data hold time tCKI Output delay time (Serial clock is external clock) tCKO(1) Output delay time (Serial clock is internal clock) tCKO(2) Input clock Parameter Output clock Serial clock 4. Serial Input/Output Characteristics at Ta=-30°C to +70°C, VSS=0V Pins SCK0, SCK1 Conditions Refer to figure 5. tCKH(1) tCKCY(2) tCKL(2) SCK0, SCK1 tCKH(2) tICK •SI0,SI1 •SB0,SB1 •SO0,SO1 •SB0,SB1 •Use pull-up resistor (1kΩ) when set to opendrain output. •Refer to figure 5. Ratings VDD[V] min. 4.5 to 6.0 4.5 to 6.0 2 1 4.5 to 6.0 1 4.5 to 6.0 4.5 to 6.0 2 typ. max. unit tCYC 1/2 tCKCY 1/2 tCKCY 4.5 to 6.0 •Data set-up to SCK0,1 •Data hold from SCK0,1 •Refer to figure 5. 4.5 to 6.0 0.1 4.5 to 6.0 0.1 •Use pull-up resistor (1kΩ) when set to opendrain output. •Data hold from SCK0,1 •Refer to figure 5. 4.5 to 6.0 µs 7/12 tCYC +0.2 4.5 to 6.0 1/3 tCYC +0.2 No.4212-14/22 LC86P6032 5. Pulse Input Conditions at Ta=-30°C to +70°C, VSS=0V Parameter Symbol Pins High/low level pulse width tPIH(1) tPIL(1) •INT0, INT1 •INT2/T0IN tPIH(2) tPIL(2) INT3/T0IN (The noise rejection clock selected to 1/1.) INT3/T0IN (The noise rejection clock selected to 1/64.) tPIH(3) tPIL(3) tPIL(4) RES Conditions Ratings VDD[V] min. •Interrupt acceptable •Timer0 pulse countable •Interrupt acceptable •Timer0 pulse countable 4.5 to 6.0 1 4.5 to 6.0 2 •Interrupt acceptable •Timer0 pulse countable 4.5 to 6.0 128 Reset acceptable 4.5 to 6.0 200 VDD[V] min. typ. max. unit tCYC µs 6. AD Converter Characteristics at Ta=-30°C to +70°C, VSS=0V Parameter Resolution Absolute precision Conversion time Analog input voltage range Analog port input current Symbol Pins N ET tCAD VAIN IAINH IAINL Conditions (Note 2) AD conversion time = 16 × tCYC (ADCR2=0) (Note 3) AD conversion time = 32 × tCYC (ADCR2=1) (Note 3) AN0 to AN3 VAIN=VDD VAIN=VSS Ratings 4.5 to 6.0 4.5 to 6.0 4.5 to 6.0 typ. 8 max. unit 15.68 (tCYC= 0.98µs) bit ±1.5 LSB 65.28 µs (tCYC= 4.08µs) 31.36 (tCYC= 0.98µs) 130.56 (tCYC= 4.08µs) 4.5 to 6.0 VSS VDD V 4.5 to 6.0 4.5 to 6.0 1 µA -1 (Note 2) Quantizing error (±1/2 LSB) is ignored. (Note 3) The conversion time is the period from execution of the instruction to start conversion to the completion of shifting the A/D converted value to the register. No.4212-15/22 LC86P6032 7. Current Drain Characteristics at Ta=-30°C to +70°C, VSS=0V Parameter Current drain during basic operation (Note 4) Symbol IDDOP(1) IDDOP(2) IDDOP(3) IDDOP(4) Pins VDD Conditions •FmCF=12MHz for Ceramic resonator oscillation •FsXtal=32.768kHz for crystal oscillator •System clock : CF oscillator •Internal RC oscillator stopped •FmCF=3MHz for Ceramic resonator oscillation •FsXtal=32.768kHz for crystal oscillator •System clock : CF oscillator •Internal RC oscillator stopped •FmCF=0Hz (when oscillator stops) •FsXtal=32.768kHz for crystal oscillator •System clock : RC oscillator •FmCF=0Hz (when oscillator stops) •FsXtal=32.768kHz for crystal oscillator •System clock : crystal oscillator •Internal RC oscillator stopped Ratings VDD[V] min. typ. max. 4.5 to 6.0 13 26 4.5 to 6.0 6.5 14 4.5 to 6.0 4 10 4.5 to 6.0 3.5 9 unit mA Continue. No.4212-16/22 LC86P6032 Parameter Symbol Pins Current drain at IDDHALT(1) VDD HALT mode (Note 4) IDDHALT(2) IDDHALT(3) IDDHALT(4) Current drain at IDDHOLD(1) VDD HOLD mode IDDHOLD(2) (Note 4) Conditions •HALT mode •FmCF=12MHz for Ceramic resonator oscillation •FsXtal=32.768kHz for crystal oscillator •System clock : CF oscillator •Internal RC oscillator stopped •HALT mode •FmCF=3MHz for Ceramic resonator oscillation •FsXtal=32.768kHz for crystal oscillator •System clock : CF oscillator •Internal RC oscillator stopped •HALT mode •FmCF=0Hz (when oscillator stops) •FsXtal=32.768kHz crystal oscillator •System clock : RC oscillator •HALT mode •FmCF=0Hz (when oscillator stops) •FsXtal=32.768kHz for crystal oscillator •System clock : crystal oscillator •Internal RC oscillator stopped HOLD mode Ratings VDD[V] min. typ. max. 4.5 to 6.0 5 10 4.5 to 6.0 1.8 4.6 4.5 to 6.0 400 800 4.5 to 6.0 20 60 4.5 to 6.0 0.05 30 2.5 to 4.5 0.02 20 unit mA µA (Note 4) The currents of output transistors and pull-up MOS transistors are ignored. No.4212-17/22 LC86P6032 Table 1. Ceramic resonator oscillation circuit recommended constants (main-clock) Oscillation type Supplier Oscillator C1 C2 12MHz ceramic resonator oscillation Murata CSA12.0MTZ CSA12.0MT CST12.0MTW KBR-12.0M CSA3.00MG CST3.00MGW KBR-3.0MS 33pF 33pF 33pF 33pF 3MHz ceramic resonator oscillation Kyocera Murata Kyocera on chip 33pF 33pF 33pF 33pF on chip 47pF 47pF * For both C1 and C2, the K rank (±10%) and SL characteristics must be used. Table 2. Crystal oscillation circuit recommended constants (sub-clock) (Notes) Oscillation type Supplier Oscillator C3 C4 32.768kHz crystal oscillation Daishinku Kyocera DT-38(1TA252E00) KF-38G-13P0200 18pF 18pF 18pF 18pF •Since the circuit pattern affects the oscillation frequency, place the oscillation-related parts as close to the oscillation pins as possible with the shortest possible pattern length. •If you use other oscillators herein, we provide no guarantee for the characteristics. CF1 CF2 XT1 X’tal CF C1 Figure 1 XT2 C2 Ceramic resonator oscillation C3 C4 Figure 2 Crystal oscillation No.4212-18/22 LC86P6032 VDD VDD limit Power supply 0V Reset time RES Internal RC resontor oscillation tmsCF CF1, CF2 tssXtal XT1, XT2 Operation mode Unfixed Reset Instruction execution mode < Reset time and oscillation stable time. > Valid HOLD release signal Internal RC resontor oscillation tmsCF CF1, CF2 tssXtal XT1, XT2 Operation mode HOLD Instruction execution mode < Hold release signal and oscillation stable time. > Figure 3 Oscillation stable time VDD RRES (Note) The values of CRES and RRES should be determined such that reset time is at least 200µs, measured from the moment the power exceeds the VDD lower limit. RES CRES Figure 4 Reset circuit No.4212-19/22 LC86P6032 0.5VDD <AC timing point> tCKCY tCKL VDD tCKH SCK0 SCK1 1KΩ tICK tCKI SI0 SI1 tCKO 50pF SO0, SO1 SB0, SB1 <Timing> Figure 5 Serial input/output test conditions tPIL Figure 6 <Test load> tPIH Pulse input timing conditions No.4212-20/22 LC86P6032 Notice for use • The construction of the one-time programmable microcomputer with a blank built-in PROM makes it impossible for SANYO to completely factory-test it before shipping. To probe reliability of the programmed devices, the screening procedure shown in the following figure should always be followed. • It is not possible to perform a writing test on the blank PROM.. 100% yield, therefore, cannot be guaranteed. • Should be stored in dry conditions (QFP type only) The environment must be held at a temperature of 30°C or less and a humidity level of 70% or less. • After opening the packing (QFP type only) The preparation procedures shown in the following figure should always be followed prior to mounting the packages on the substrate. After opening the packing, a controlled environment must be maintained until soldering. The environment must be held at a temperature of 30°C or less and a humidity level of 70% or less. Please solder within 8 hours. a. Shipping with a blank PROM (Data to be programmed by customer) This microcomputer is provided DIP/QFP packages, but the condition before mounting is not same. Refer to the mounting precedure as follows; DIP QFP Programming and verifying Programming and verifying Recommended process of screening Recommended process of screening Heat-soak 150±5°C, 24 +1 -0 Hr Heat-soak 150±5°C, 24 +1 -0 Hr Program reading test Program reading test Baking before mounting 125°C, 24 hours Baking Mounting Mounting No.4212-21/22 LC86P6032 b. Shipping with programmed PROM (Data programmed by Sanyo) DIP QFP Baking before mounting 125°C, 24 hours Baking Mounting Mounting PS No.4212-22/22