Ordering number : ENN*6749 CMOS IC LC86E7248 8-Bit Single Chip Microcontroller with the UVEPROM Preliminary Overview The LC86E7248 is a CMOS 8-bit single chip microcontroller with UVEPROM for the LC867200 series. This microcontroller has the function and the pin description of the LC867200 series mask ROM version, and 48K-byte EPROM. The program data is rewritable. It is suitable to develop the program. Features (1) Option switching by EPROM data The option function of the LC867200 series can be specified by the EPROM data. LC86E7248 can be checked the functions of the trial pieces using the mass production board. (2) Internal EPROM capacity : 49408 bytes (3) Internal RAM capacity : 1152 bytes Used EPROM or RAM capacity are equal ROM or RAM capacity of mask ROM version which applies LC86E7248. Mask ROM version LC867248 LC867240 LC867232 LC867224 EPROM capacity 49152 bytes 40960 bytes 32768 bytes 24576 bytes RAM capacity 1152 bytes 1152 bytes 1152 bytes 1152 bytes (4) Operating supply voltage : 4.5V to 6.0V (5) Instruction cycle time : 1µs to 366µs (6) Operating temperature : +10°C to +40°C (7) The pin compatible with the LC867200 series mask ROM devices (8) Applicable mask ROM version : LC867248/40/32/24 (9) Factory shipment : QFC100S (with window) Ver.1.02 80196 91400 RM (IM) SK No.6749-1/19 LC86E7248 Notice for use At using, take notice of the followings. (1) A point of difference LC86E7248 and LC867200 series LC86E7248 LC867248/40/32/24 Operation after reset releasing Item The option is specified until 3ms after going to a ‘H’ level to the reset terminal by degrees. The program is executed from 00H of the program counter. The program is executed from 00H of the program counter immediately after going to a ‘H’ level to the reset terminal. Operating supply voltage range (VDD) 4.5V to 6.0V 2.5V to 6.0V Operating temperature range (Topr) +10°C to +40°C -30°C to +70°C Power dessipation Refer to ‘electrical characteristics’ on the semiconductor news. LC86E7248 uses 256 bytes that is addressed on 0FF00H to FFFFH in the program memory as the option configuration data area. This option configuration cannot execute all options which LC867200 series have. Next tables show the options that correspond and not correspond to LC86E7248. • A kind of the option corresponding of the LC86E7248 A kind of option Pins, Circuits Contents of the option Input/output form of input/output ports Port 0 1. N-channel open drain output 2. CMOS output *1 1. Pull-up MOS Tr. 2. No Pull-up MOS Tr. *2 *1 1. Input : Programmable pull-up MOS Tr. Output : N-channel open drain 2. Input : Programmable pull-up MOS Tr. Output : CMOS *1 1. Input : No Programmable pull-up MOS Tr. Output : N-channel open drain 2. Input : Programmable pull-up MOS Tr. Output : CMOS *1 1. No Pull-up MOS Tr. 2. Pull-up MOS Tr. Port 1 Port 3 Pull-up MOS Tr. of input port *1) Specified in a bit. *2) Specified in nibble unit. Ports 70, 71, 72, 73 Pull-up MOS Tr. is not provided in N-channel open drain output port. The port operation related the option is different at reset. Refer to the next table. No.6749-2/19 LC86E7248 (1) Option The option data is created by the option specified program “SU86K.EXE”. program area by linkage loader “L86K.EXE”. The created option data is linked to the (2) ROM space LC86E7248 and LC867200 series use 256 bytes that is addressed on 0FF00H to 0FFFFH in the program memory as the option specified data area. These program memory capacity are 49152 bytes that is addressed on 0000H to 0BFFFH. 0FFFFH 0FF00H 0EFFFH 0DFFFH 0CFFFH 0BFFFH 0AFFFH 9FFFH 8FFFH 7FFFH 6FFFH 5FFFH 4FFFH 3FFFH 2FFFH 1FFFH 0FFFH 0000H Option data area 256 bytes Option data area Option data area Option data area Program area 48K bytes Program area 40K bytes Program area 32K bytes Program area 28K bytes LC867248 LC867240 LC867232 LC867224 No.6749-3/19 LC86E7248 How to use (1) Specification of option Programming data for PROM of the LC86E7248 is required. Debugged evaluation file (EVA file) must be converted to an INTEL-HEX formatted file (HEX file) with file converter program, EVA2HEX.EXE. The HEX file is used as the programming data for the LC86P6548. (2) How to program for the EPROM The LC86E7248 can be programmed by EPROM programmer with attachment ; W86EP7248Q • Recommended EPROM programmer Productor EPROM programmer Advantest Andou AVAL Minato electronics R4945, R4944, R4943 AF-9704 PKW-1100, PKW-3000 MODEL1890A • “27512 (Vpp=12.5V) Intel high speed programming” mode available. jumper (DASEC) must be set to ‘OFF’ at programming. The address must be set to “0 to 0FFFFH” and a (3) How to use the data security function “Data security” is the disabled function to read the data of the EPROM. The following is the process in order to execute the data security. 1. Set ‘ON’ the jumper of attachment. 2. Program again. Then EPROM programmer displays the error. The error means normally activity of the data security. It is not a trouble of the EPROM programmer or the LSI. Notes • Data security is not executed when the data of all address have ‘FFH’ at the sequence 2 above. • The programming by a sequential operation “BLANK=>PROGRAM=>VERIFY” cannot be executed data security at the sequence 2 above. • Set to ‘OFF’ the jumper after executing the data security. (4) How to eliminate The programming data can be erased by using the EPROM eraser. (5) Shielding The UVEPROM (ultraviolet erasable programmable ROM) is in it. Put the seal on the window in use. Data security Not data security W86EP7248Q No.6749-4/19 RES 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 XT1/P74 XT2/P75 VSS1 CF1 CF2 VDD1 P80/AN0 P81/AN1 P82/AN2 P83/AN3 P84/AN4 P85/AN5 P86/AN6 P87/AN7 P71/INT1 P72/INT2/T0IN P73/INT3/T0IN S0/PA0 V2/PL5 V1/PL4 COM0/PL0 COM1/PL1 COM2/PL2 COM3/PL3 P30 P31 VSS3 VDD3 P32 P33 P34 P35 P00 P01 P02 P03 P04 P05 P06 P07 P10/SO0 P11/SI0/SB0 P12/SCK0 P13/SO1 P14/SI1/SB1 P15/SCK1 P16/BUZ P17/PWM0 P70/INT0 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 V3/PL6 S47/PF7 S46/PF6 S45/PF5 S44/PF4 S43/PF3 S42/PF2 S41/PF1 S40/PF0 S39/PE7 S38/PE6 S37/PE5 S36/PE4 S35/PE3 S34/PE2 S33/PE1 S32/PE0 S31/PD7 S30/PD6 S29/PD5 S28/PD4 S27/PD3 S26/PD2 VSS2 VDD2 S25/PD1 S24/PD0 S23/PC7 S22/PC6 S21/PC5 LC86E7248 Pin Assignment 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 S20/PC4 S19/PC3 S18/PC2 S17/PC1 S16/PC0 S15/PB7 S14/PB6 S13/PB5 S12/PB4 S11/PB3 S10/PB2 S9/PB1 S8/PB0 S7/PA7 S6/PA6 S5/PA5 S4/PA4 S3/PA3 S2/PA2 S1/PA1 SANYO : QFC100S No.6749-5/19 LC86E7248 System Block Diagram Interrupt Control IR PLA A15-A0 D7-D0 TA CE OE DASEC Stand-by Control CF RC Clock Generator EPROM Control EPROM (48KB) X’tal PC Base Timer Bus Interface ACC SIO0 Port 1 B Register SIO1 Port 7 C Register Timer 0 Port 8 ALU Timer 1 Port 3 Real Time Service ADC RAM 128 bytes INT0-3 Noise Rejection Filter LCD Display Controller PSW RAR RAM SO0 - S7 (PA) S8 - S13 (PB) Stack Pointer S16 - S23 (PC) S24 - S31 (PD) Port 0 S32 - S39 (PE) S40 - S47 (PF) Watchdog Timer COM0-COM3(PL) No.6749-6/19 LC86E7248 Pin Description Pin name I/O VSS1, 2, 3 *1 VDD1, 2, 3 *1 PORT0 I/O P00 - P07 Function description - Power pin (+) - - • 8-bit input/output port Input/output in nibble units • Input for port 0 interrupt • Input for HOLD release • Pull-up resistor : Provided/Not provided (specified in nibble units) • Output form (P00 – P07) : CMOS/N-channel open drain (specified in a bit) • Output form : CMOS/N-channel open drain (specified in a bit) - • Output form : CMOS/N-channel open drain (specified in a bit) Pull-up resistor : Provided/Not provided (specified in a bit) (P70, P71, P72, P73) * P74 , P75 don’t have the pull-up resistor option. - I/O PORT3 P30 - P35 I/O PORT7 • 6-bit input port • Other pin functions I/O P70 : INT0 input/HOLD release input/ N-ch Tr. output for watchdog timer I P71 : INT1 input/HOLD release input P72 : INT2 input/timer 0 event input P73 : INT3 input with noise filter/timer 0 event input • Interrupt received form, vector address rising falling rising high low & level level falling INT0 enable enable disable enable enable INT1 enable enable disable enable enable INT2 enable enable enable disable disable INT3 enable enable enable disable disable I P74 : XT1 terminal for crystal oscillation P75 : XT2 terminal for crystal oscillation I • 8-bit input port • Other function AD input port (8 port pins) P71 - P73 P74 , P75 Port8 P80 – P87 PROM mode - PORT1 P10 - P17 P70 Option Power pin (–) • 8-bit input/output port Input/output can be specified in bit unit • Other pin functions P10 : SIO0 data output P11 : SIO0 data input/bus input/output P12 : SIO0 clock input/output P13 : SIO1 data output P14 : SIO1 data input/bus input/output P15 : SIO1 clock input/output P16 : Buzzer output P17 : Timer1 output (PWM output) • 6-bit input/output port • Input/output can be specified in bit unit Data line D0 to D7 Power for programming PROM control signals DASEC (*2) OE (*3) CE (*4) vector 03H 0BH 13H 1BH - - No.6749-7/19 LC86E7248 Pin name I/O Function description Port A (S0/PA0 – S7/PA7) Port B (S8/PB0 – S15/PB7) Port C (S16/PC0 – S23/PC7) I/O • Segment output terminal for LCD display • Can be used as a general input/output port • Segment output terminal for LCD display • Can be used as a general input/output port • Segment output terminal for LCD display • Can be used as a general input/output port - Address input A0 to A7 - Address input A8 to A13 - Port D (S24/PD0 – S31/PD7) Port E (S32/PE0 – S39/PE7) Port F (S40/PF0 – S47/PF7) Port L (COM0/PL0 – COM3/PL3) V1/PL4 – V3/PL6 RES XT1/ P74 I/O • Segment output terminal for LCD display • Can be used as a general input/output port • Segment output terminal for LCD display • Can be used as a general input/output port • Segment output terminal for LCD display • Can be used as a general input/output port • Common output terminal for LCD display • Can be used as a general input port - PROM control signal input • TA (*5) Address input • A14, A15 - - - - - - - - - - - XT2/P75 O • Bias power terminal for LCD drive • Can be used as a general input port Reset pin • Input pin for 32.768kHz crystal oscillation In case of non use, connect to VDD. • Other function A general input port P74 • Output pin for 32.768kHz crystal oscillation In case of non use, should be left unconnected • Other function A general input port P75 Input pin for ceramic resonator oscillation Output pin for ceramic resonator oscillation - - - - - - I/O I/O I/O I/O I/O I I I (I) CF1 I CF2 O Option PROM mode * All of port options can be specified in a bit unit except the pull-up resistor of port 0. [Notes] • The VDD1, VDD2 and VDD3 terminals must be shorted electrically each other. • The VSS1, VSS2 and VSS3 terminals must be shorted electrically each other. *1 Connect like the following figure to reduce noise into a VDD terminals. *2 Memory select input for data security *3 Output enable input Power *4 Chip enable input *5 TA ! PROM control signal input Supply LSI VDD1 VDD2 VDD3 VSS1 VSS2 VSS3 No.6749-8/19 LC86E7248 1. Absolute Maximum Ratings at Ta=25°C, VSS=VSS1=VSS2=VSS3=0V Parameter Symbol Supply voltage VDDMAX LCD display voltage Input voltage VLCD Input/output voltage VIO High level output current Peak output current IOPH(1) IOPH(2) Total output current ΣIOAH(1) Low level output current Peak output current Total output current Maximum power dissipation Operating temperature range Storage temperature range VI ΣIOAH(2) ΣIOAH(3) ΣIOAH(4) IOPL(1) IOPL(2) IOPL(3) ΣIOAL(1) ΣIOAL(2) ΣIOAL(3) ΣIOAL(4) ΣIOAL(5) Pdmax Pins Conditions VDD[V] min. VDD1, VDD2 VDD3 V1/PL6, V2/PL5 V3/PL4 •Ports 71, 72, 73 •Ports 74 , 75 •Port 8, Port L • RES •Port 0, 1, 3 •Port 70 •Ports A,B,C,D,E,F Ports 0, 1, 3 Ports A,B,C,D,E,F VDD1=VDD2= VDD3 VDD1=VDD2= VDD3 •CMOS output •At each pins -4 -4 Ports 0, 1, 32, 33, 34, 35 Ports 30, 31 Ports S0 to S25 Ports S26 to S47 Ports 0, 1, 3 Ports A,B,C,D,E,F Port 70 Ports 0, 1, 32, 33, 34, 35 Ports 30, 31 Ports S0 to S25 Ports S26 to S47 Port 70 QFC100S Total all pins -38 Total all pins Total all pins Total all pins At each pins At each pins At each pins Total all pins -4 -25 -25 Ratings typ. max. -0.3 +7.0 -0.3 VDD -0.3 VDD+0.3 -0.3 VDD+0.3 unit V mA 20 20 15 50 Total all pins Total all pins Total all pins Total all pins Ta=+10 to+40°C 20 39 33 10 515 mW °C Topr +10 +40 Tstg -55 +125 No.6749-9/19 LC86E7248 2. Recommended Operating Range at Ta=+10°C to +40°C, VSS =0V Parameter Symbol VDD(1) Pins Operating supply voltage range VDD(2) Hold voltage VHD VDD1, VDD2, VDD3 Input high voltage VIH(1) Port 0 VIH(2) •Ports 1, 3 •Ports A,B,C,D,E,F,L •Ports 72, 73 •Port 70 Port input/interrupt •Port 71 • RES Port 70 Watchdog timer •Port 8 VIH(3) VIH(4) VIH(5) Input low voltage VIL(1) VIL(2) VIL(3) VIL(4) VIL(5) Operation cycle time Oscillation frequency range (Note 1) Oscillation stabilizing time period (Note 1) VDD1, VDD2, VDD3 Port 0 •Ports 1, 3 •Ports A,B,C,D,E,F,L •Ports 72, 73 •Port 70 Port input/interrupt •Port 71 • RES Port 70 Watchdog timer •Port 8 Conditions 0.98µs ≤ tCYC ≤ 400µs 3.9µs ≤ tCYC ≤ 400µs RAMs and the registers hold voltage at HOLD mode. Output disable 4.5-6.0 Output disable CF1, CF2 FmCF(2) CF1, CF2 FmRC FsXtal XT1, XT2 tmsCF(1) CF1, CF2 tmsCF(2) CF1, CF2 tssXtal XT1, XT2 min. 4.5 Ratings typ. max. 6.0 2.5 6.0 2.0 6.0 VDD 4.5-6.0 0.4VDD +0.9 0.75VDD Output N-channel Tr. OFF 4.5-6.0 0.75VDD VDD Output N-channel Tr. OFF Output N-channel Tr. OFF Output disable Output disable 4.5-6.0 0.9VDD VDD 4.5-6.0 0.75VDD VDD 4.5-6.0 4.5-6.0 VSS VSS 0.2VDD 0.25VDD Output N-channel Tr. OFF 4.5-6.0 VSS 0.25VDD Output N-channel Tr. OFF Output N-channel Tr. OFF 4.5-6.0 VSS 4.5-6.0 VSS 0.8VDD -1.0 0.25VDD 4.5-6.0 4.5-6.0 4.5-6.0 0.98 3.9 400 400 tCYC FmCF(1) VDD[V] •6MHz (ceramic resonator oscillation) •Refer to figure 1 •3MHz (ceramic resonator oscillation) •Refer to figure 1 RC oscillation •32.768kHz (crystal oscillation) •Refer to figure 2 •6MHz (ceramic resonator oscillation) •Refer to figure 3 •3MHz (ceramic resonator oscillation) •Refer to figure 3 •32.768kHz (crystal oscillation) •Refer to figure 3 4.5-6.0 4.5-6.0 4.5-6.0 V VDD 6 4.5-6.0 unit µs MHz 3 0.4 0.8 32.768 3.0 kHz ms 4.5-6.0 4.5-6.0 s (Note 1) The oscillation constant is shown on table 1 and table 2. No.6749-10/19 LC86E7248 3. Electrical Characteristics at Ta=+10°C to +40°C, VSS=VSS1=VSS2=VSS3=0V Parameter Input high current Symbol IIH(1) •Port 1 •Port 0 without pull-up MOS Tr. IIH(2) •Port 7 without pull-up MOS Tr. •Port 8 Port 3 Ports A,B,C,D,E,F,L RES Ports 74 ,75 IIH(3) IIH(4) IIH(5) IIH(6) Input low current IIL(1) •Port 1 •Port 0 without pull-up MOS Tr. IIL(2) •Port 7 without pull-up MOS Tr. •Port 8 Port 3 Ports A,B,C,D,E,F,L RES Ports 74 ,75 IIL(3) IIL(4) IIL(5) IIL(6) Output high voltage VOH(1) VOH(2) Output low voltage Pins VOL(1) VOL(2) VOL(3) VOL(4) VOL(5) VOL(6) VOL(7) Ports 0,1 of CMOS output •Port 3 of CMOS output •Ports A,B,C,D,E,F of CMOS output Ports 0, 1 Port 70 Port 3 Ports A,B,C,D,E,F of CMOS output Conditions •Output disable •Pull-up MOS Tr. OFF. VIN=VDD (including the offleak current of the output Tr.) VIN=VDD VDD[V] min. Ratings typ. max. 4.5-6.0 1 4.5-6.0 1 VIN=VDD VIN=VDD VIN=VDD Using as port VIN=VDD •Output disable •Pull-up MOS Tr. OFF. VIN=VSS (including the offleak current of the output Tr.) VIN=VSS 4.5-6.0 4.5-6.0 4.5-6.0 4.5-6.0 1 1 1 1 4.5-6.0 -1 4.5-6.0 -1 VIN=VSS VIN=VSS VIN=VSS Using as port VIN=VSS IOH=-1.0mA 4.5-6.0 4.5-6.0 4.5-6.0 4.5-6.0 -1 -1 -1 -1 4.5-6.0 VDD-1 IOH=-1.0mA 4.5-6.0 VDD-1 IOL=10mA IOL=1.6mA IOL=1mA IOL=10mA IOL=1.6mA IOL=8mA IOL=1.6mA 4.5-6.0 4.5-6.0 4.5-6.0 4.5-6.0 4.5-6.0 4.5-6.0 4.5-6.0 unit µA V 1.5 0.4 0.4 1.5 0.4 1.5 0.4 Continue. No.6749-11/19 LC86E7248 Parameter LCD output regulation LCD ladder resistor Symbol Pins VODLS S0 to S47 VODLC COM0 to COM3 Conditions RLCD(1) RLCD(2) Pull-up MOS Tr. resistor Rpu Hysteresis voltage VHIS Pin capacitance CP •Ports 0, 1, 3 •Ports A,B,C,D,E,F •Ports 70, 71, 72, 73 •Port 1 •Ports 70, 71, 72, 73 • RES All pins •Deference voltage to ideal value •VLCD, 2/3VLCD, 1/3VLCD •Deference voltage to ideal value •VLCD, 2/3VLCD, 1/2VLCD, 1/3VLCD Resistance at a ladder resistor •Resistance at a ladder resistor •1/2R mode VOH=0.9VDD VDD[V] 4.5-6.0 min. 0 4.5-6.0 0 Ratings typ. 60 4.5-6.0 30 15 unit V ±0.2 4.5-6.0 4.5-6.0 max. ±0.2 kΩ 40 70 Output disable 4.5-6.0 0.1VDD V •f=1MHz •Unmeasurement terminals for the input are set to VSS level. •Ta=25°C 4.5-6.0 10 pF 4. Serial Input / Output Characteristics at Ta=+10°C to +40°C, VSS=VSS1=VSS2=VSS3=0V Serial output Serial input Symbol tCKCY(1) tCKL(1) Data hold time tCKI Output delay time (Serial clock is external clock) tCKO(1) Output delay time (Serial clock is internal clock) tCKO(2) Input clock Cycle Low Level pulse width High Level pulse width Cycle Low Level pulse width High Level pulse width Data set up time Output clock Serial clock Parameter Pins SCK0, SCK1 Conditions Refer to figure 5. VDD[V] 4.5-6.0 tCKH(1) tCKCY(2) tCKL(2) Ratings typ. max. unit tCYC 1 2 SCK0, SCK1 •Use pull-up resistor (1kΩ) when open drain output. •Refer to figure 5. 4.5-6.0 •SI0,SI1 •SB0,SB1 •Data set-up to SCK0, 1 •Data hold from SCK0, 1 •Refer to figure 5. 4.5-6.0 0.1 4.5-6.0 0.1 tCKH(2) tICK min. 2 1 •SO0, SO1 •SB0, SB1 •Use pull-up resistor (1kΩ) when open drain output. •Data hold from SCK0, 1 •Refer to figure 5. 1/2 tCKCY 1/2 tCKCY µs 4.5-6.0 7/12tCYC +0.2 4.5-6.0 1/3tCYC +0.2 No.6749-12/19 LC86E7248 5. Pulse Input Conditions at Ta=+10°C to +40°C, VSS=VSS1=VSS2=VSS3=0V Parameter High/low level pulse width Symbol tPIH(1) tPIL(1) tPIH(2) tPIL(2) tPIH(3) tPIL(3) tPIH(4) tPIL(4) tPIL(5) Pins •INT0, INT1 •INT2/T0IN INT3/T0IN (The noise rejection clock is selected to 1/1.) INT3/T0IN (The noise rejection clock is selected to 1/16.) INT3/T0IN (The noise rejection clock is selected to 1/64.) RES Conditions VDD[V] 4.5-6.0 min. 1 4.5-6.0 2 •Interrupt acceptable •Timer0-countable 4.5-6.0 32 •Interrupt acceptable •Timer0-countable 4.5-6.0 128 Reset acceptable 4.5-6.0 200 •Interrupt acceptable •Timer0-countable •Interrupt acceptable •Timer0-countable Ratings typ. max. unit tCYC µs 6. AD Converter Characteristics at Ta=+10°C to + 40°C, VSS=VSS1=VSS2=VSS3=0V Parameter Resolution Absolute precision (Note 2) Conversion time Analog input voltage range Analog port input current Symbol Pins Conditions NAD ETAD tCAD VAIN IAINH IAINL AD conversion time = 16 × tCYC (ADCR2=0) (Note 3) AD conversion time = 32 × tCYC (ADCR2=1) (Note 3) AN0 - AN7 VAIN=VDD VAIN=VSS Ratings typ. 8 max. unit VDD[V] 4.5-6.0 4.5-6.0 min. 4.5-6.0 15.68 (tCYC= 0.98µs) 65.28 (tCYC= 4.08µs) 31.36 (tCYC= 0.98µs) 130.56 (tCYC= 4.08µs) 4.5-6.0 VSS VDD V 4.5-6.0 4.5-6.0 1 µA -1 ±1.5 bit LSB µs (Note 2) Absolute precision excepts quantizing error (±1/2 LSB). (Note 3) The conversion time means the time from executing the AD conversion instruction to setting the complete digital conversion value to the register. No.6749-13/19 LC86E7248 7. Current Dissipation Characteristics at Ta=+10°C to +40°C, VSS=VSS1=VSS2=VSS3=0V Parameter Current dissipation during basic operation (Note 4) Symbol IDDOP(1) IDDOP(2) IDDOP(3) IDDOP(4) Pins VDD1= VDD2= VDD3 Conditions •FmCF=6MHz Ceramic resonator oscillation •FsXtal=32.768kHz crystal oscillation •System clock : CF oscillation •Internal RC oscillation stops •1/1 divided •FmCF=3MHz Ceramic resonator oscillation •FsXtal=32.768kHz crystal oscillation •System clock : CF oscillation •Internal RC oscillation stops •1/2 divided •FmCF=0Hz (when oscillation stops) •FsXtal=32.768kHz crystal oscillation •System clock : RC oscillation •1/2 divided •FmCF=0Hz (when oscillation stops) •FsXtal=32.768kHz crystal oscillation •System clock : crystal oscillation •Internal RC oscillation stops •1/2 divided Ratings typ. 15 max. 30 4.5-6.0 6 15 4.5-6.0 4 13 4.5-6.0 4 9 VDD[V] 4.5-6.0 min. unit mA Continue. No.6749-14/19 LC86E7248 Parameter Symbol Current dissipation in HALT mode (Note 4) IDDHALT(1) Pins VDD1= VDD2= VDD3 IDDHALT(2) IDDHALT(3) IDDHALT(4) IDDHALT(5) Current dissipation in HOLD mode (Note 4) IDDHOLD(1) VDD1= VDD2= VDD3 Conditions •HALT mode •FmCF=6MHz Ceramic resonator oscillation •FsXtal=32.768kHz crystal oscillation •System clock : CF oscillation •Internal RC oscillation stops •1/1 divided •HALT mode •FmCF=3MHz Ceramic resonator oscillation •FsXtal=32.768kHz crystal oscillation •System clock : CF oscillation •Internal RC oscillation stops •1/2 divided •HALT mode FmCF=0Hz (when oscillation stops) •FsXtal=32.768kHz crystal oscillation •System clock : RC oscillation •1/2 divided •HALT mode FmCF=0Hz (when oscillation stops) •FsXtal=32.768kHz crystal oscillation •System clock : crystal oscillation •Internal RC oscillation stops •1/2 divided HOLD mode Ratings typ. 6 max. 11 4.5-6.0 2.2 9 4.5-6.0 500 1700 4.5-6.0 25 100 4.5-6.0 0.05 30 VDD[V] 4.5-6.0 min. unit mA µA (Note 4) The currents of the output transistors and the pull-up MOS transistors are ignored. No.6749-15/19 LC86E7248 Table 1. Ceramic resonator oscillation guaranteed constant (main clock) Oscillation type Maker Oscillator C1 C2 6MHz ceramic resonator oscillation 3MHz ceramic resonator oscillation * Both C1 and C2 must use K rank (±10%) and SL characteristics. Table 2. Crystal oscillation recommended constant (sub clock) Oscillation type Maker Oscillator C3 C4 32.768kHz crystal oscillation Rd * Both C3 and C4 must use J rank (±5%) and CH characteristics. (It is about the application which is not in need of high precision. Use K rank (±10%) and SL characteristics.) (Notes) •Since the circuit pattern affects the oscillation frequency, place the oscillation-related parts as close to the oscillation pins as possible with the shortest possible pattern length. •If you use other oscillators herein, we provide no guarantee for the characteristics. CF1 CF2 XT1 XT2 Rd CF C1 Figure 1 C2 Ceramic oscillation circuit C3 Figure 2 X’tal C4 Crystal oscillation circuit No.6749-16/19 LC86E7248 VDD VDD limit 0V Power supply Reset time RES Internal RC resonator oscillation tmsCF CF1, CF2 tssXtal XT1, XT2 Operation mode Unfixed Reset Instruction execution mode OCR6=1 Instruction execution mode < Reset time and oscillation stable time > HOLD release signal Valid Internal RC resonator oscillation tmsCF CF1, CF2 tssXtal XT1, XT2 Operation mode HOLD Instruction execution mode < HOLD release signal and oscillation stable time > Figure 3 Oscillation stable time No.6749-17/19 LC86E7248 VDD RRES (Note) Fix the value of CRES, RRES that is sure to reset until 200µs, after Power supply has been over inferior limit of supply voltage. RES CRES Figure 4 Reset circuit 0.5VDD <AC timing point> tCKCY tCKL VDD tCKH SCK0 SCK1 1kΩ tICK tCKI SI0 SI1 tCKO 50pF SO0, SO1 SB0, SB1 <Timing> Figure 5 tPIL Figure 6 <Test load> Serial input / output test condition tPIH Pulse input timing condition No.6749-18/19 LC86E7248 PS No.6749-19/19