Ordering number : ENN6238 CMOS IC LC895199K 32× CD-ROM Decoder with ATAPI (IDE) Interface Overview The LC895199K is a CD-ROM decoder IC that provides subcode read functions and an ATAPI interface integrated on the same chip. Functions CD-ROM ECC function Subcode read function ATA-PI (IDE) I/F (register block, etc.) CAV audio function Package Dimensions unit: mm 3214-SQFP144 [LC895199K] 0.5 1.25 22.0 20.0 0.145 1.25 73 108 109 1.25 72 22.0 20.0 37 144 1 0.20 36 1.6max • Built-in ATAPI (IDE) I/F • 32× speed supported: Using EDO-DRAM (×16, 50 ns) 16.6 Mbytes/s (with IORDY) Operating frequency: 33.8688 MHz • 32× speed supported: Using EDO-DRAM (×16, 45 ns) 16.6 Mbytes/s (without IORDY) Operating frequency: 33.8688 MHz • 24× speed supported: Using EDO-DRAM (×16, 50 ns) 16.6 Mbytes/s (without IORDY) Operating frequency: 33.8688 MHz • 1 Mbits to 4 Mbits of buffer RAM connectable in case of DRAM • CD main channel, C2 flag, and subcode areas in buffer RAM can be freely set by user 0.5 Features 1.25 • • • • • Built-in batch transfer function (function for sending CD main channel, C2 flag, subcode, etc. at one time) • Built-in multi-block transfer function (function for automatically sending several blocks at one time) • Built-in CAV audio function • Built-in intelligent functions (auto buffering, auto decoding, CD-R support, etc.) • Built-in subcode P to W buffering function (NO-ECC) and CD-TEXT support • Package: SQFP-144 0.5 0.5 0.1 1.4 SANYO: SQFP144 Any and all SANYO products described or contained herein do not have specifications that can handle applications that require extremely high levels of reliability, such as life-support systems, aircraft’s control systems, or other applications whose failure can be reasonably expected to result in serious physical and/or material damage. Consult with your SANYO representative nearest you before using any SANYO products described or contained herein in such applications. SANYO assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO products described or contained herein. SANYO Electric Co.,Ltd. Semiconductor Company TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN 21000TH (OT)/30899TH (OT) No. 6238-1/12 LC895199K Changes from the LC895199 Items changed from the LC895199-MK2 • Revision 4. • The DVD-ROM and DVD-RAM interface functions have been removed. • The buffer circuits for the DRAM pins (RAS, CAS0, CAS1, OE, WE, and A0 to A8) have been changed from 8 mA sink to 4 mA sink. • The buffer circuits for the D/A converter output pins (DSDATA, DLRCK, DBCK) have been changed from 8 mA sink to 4 mA sink. • The amount of external DRAM supported has been changed from 16M to 4M. • The MCK3 output has been changed to a 1/1, 1/2, stop output. • Settings have been added for cases when the PLL circuit is not used. (W register R46 bit 7 (set to 1) and C register R1 (set to 40h)) Specifications Absolute Maximum Ratings at VSS = 0 V Parameter Maximum supply voltage Input/output voltage Allowable power dissipation Symbol Conditions Ratings Unit VDD5 max Ta = 25°C –0.3 to +6.0 VDD3 max Ta = 25°C –0.3 to +4.6 V V VI15, VO5 Ta = 25°C –0.3 to VDD5 + 0.3 V VI13, VO3 Ta = 25°C –0.3 to VDD3 + 0.3 Pd max Ta ≤ 70°C 550 V mW Operating temperature Topr –30 to +70 °C Storage temperature Tstg –55 to +125 °C Soldering temperature (pin part only) Input/output power II, IO 10 s 235 °C * ±20 mA Note: * Per 1 input/output reference cell Allowable Operating Range at Ta = –30 to +70°C, VSS = 0 V IO Cell 5.0 V Supply Voltage Parameter Symbol Conditions Ratings min typ Supply voltage VDD 4.5 Input voltage range VIN 0 5.0 max Unit 5.5 V VDD V Internal Cell 3.3 V Supply Voltage Parameter Symbol Conditions Ratings min typ Supply voltage VDD 3.0 Input voltage range VIN 0 3.3 max Unit 3.6 V VDD V No. 6238-2/12 LC895199K DC Characteristics at Ta = –30 to +70°C, VSS = 0 V, VDD = 4.5 to 5.5 V Parameter Symbol Conditions Input high-level voltage VIH Input low-level voltage VIL Input high-level voltage VIH TTL levels Input low-level voltage VIL with pull-down resistor Input high-level voltage VIH TTL levels Input low-level voltage VIL Schmitt Output high-level voltage VOH IOH1 = –4 mA Output low-level voltage VOL IOL1 = 4 mA Output high-level voltage VOH IOH1 = –8 mA Output low-level voltage VOL IOL1 = 8 mA Output high-level voltage VOH IOH1 = –12 mA Output low-level voltage VOL IOL1 = 12 mA Output high-level voltage VOH IOH1 = –12 mA Output low-level voltage VOL IOL1 = 12 mA Output high-level voltage VOH IOH1 = –4 mA Output low-level voltage VOL IOL1 = 24 mA Output low-level voltage VOL IOL1 = 24 mA Output low-level voltage VOL IOL1 = 8 mA TTL levels IIL VI = VSS, VDD Output leakage current IOZ During high-impedance output Pull-up resistance RUP Pull-up resistance RUP Input leakage current ZDMACK *2 Applicable pins *1 (1) (10) (2), (3), (11) (4) (10), (12) (5) (5) Ratings min typ max Unit 2.2 — — V — — 0.8 V 2.2 — — V — — 0.8 V 2.4 — — V — — 0.8 V VDD – 2.1 — — V V — — 0.4 VDD – 2.1 — — V — — 0.4 V VDD – 2.1 — — V — — 0.4 V VDD – 2.1 — — V — — 0.4 V VDD – 2.1 — — V — — 0.4 V (9) — — 0.4 V (6), (7) — — 0.4 V +10 µA (8), (11) (1), (2), (3), (11) –10 (6), (8), (9), (11) –10 +10 µA (10) 40 80 160 kΩ (7) 20 40 80 kΩ Notes:1. The applicable pin sets are as follows. 2. When ZDMACK is reset, internal pull-up resistor is OFF. When Config-Reg-R46 (PULON)-bit 0 (ZDMACK) = 1, pull-up resistor becomes ON. INPUT (1) ATPINSEL, CSCTRL, SUA0 to SUA6, BCK, C2PO, LRCK, SDATA, SBS0, SCOR, WFCK, TEST0 to TEST1 (2) ZRESET, ZCS, ZRD, ZWR, CSEL (3) DA0 to DA2, ZCS1FX, ZCS3FX, ZDIOR, ZDIOW, ZDMACK, ZHRST OUTPUT (4) RA0 to RA8, ZRAS0, ZCAS0 to ZCAS1, ZUWE, ZLWE, ZOE (5) MCK, MCK3 (6) ZRSTCPU (7) ZINT, ZINT1, ZSWAIT (8) DMARQ, HINTRQ (9) IORDY, ZIOCS16 INOUT (10) D0 to D7, IO0 to IO15, HDB0 to HDB7 (11) DD0 to DD15, ZDASP, ZPDIAG (12) EXCK Note: Pins XTAL and XTALCK are not included in the DC characteristics. No. 6238-3/12 LC895199K Recommended Oscillator Circuit LC895199K XTALCK PN52 XTAL PN53 R1 R2 C1 C2 A12521 R1 = 1 MΩ R2 = 47 Ω C1 = 0 C2 = 47 pF Ceramic oscillator frequency = 33.8688 MHz. The 33.8688 MHz frequency in the recommended circuit is the third harmonic. Since the exact values of these components will vary depending on characteristics of the printed circuit board used and other factors, consult the manufacturer of the oscillator element when designing the oscillator circuit. External Circuits for the On-Chip PLL Version (LC895199) LC895199K PLL PN69 3.3V R3 PN70 PN71 R4 R5 C3 Analog VSS A12522 R3 = 5.1 kΩ, R4 = 200 Ω, R5 = 10 kΩ, C3 = 0.1 µF The analog VDD and VSS must be made completely independent of the logic system power supply. In particular, they must not be affected by fluctuations in the logic system power supply. No. 6238-4/12 LC895199K Block Diagram LC895199K RAM Data bus[0:15] Address bus[0:17] Data bus[0:7] *1 Sub-code I/F 10byte FIFO for Sub Q EXCK Address generator CAV-Audio contorol *10 CD-DSP DAC Address generator *2 CD-DSP I/F & SYNC Detector De-scramble & Buffering Address generator ECC & EDC ZRESET ZRSTCPU Reset Controller Address generator Each Block Bus control signal External HOST *3 *4 *5 ZINT0 ZINT1 *6 *7 Micro controller IDE I/F Based HISIDE Each Block Register R0-R127 decoder ZSWAIT Each Block XTALCK Clock generator & PLL XTAL **1 Bus Arbiter & DRAM controller *8 *9 Buffer DRAM Data output input I/F Address generator Microcontroller RAM access Address generator MCK3 MCK *11 A12523 *1 *2 *3 *4 *5 *6 *7 *8 *9 *10 *11 **1 WFCK, SBSO, SCOR BCK, SDATA, LRCK, C2PO DD0 to DD15, ZDASP, ZPDIAG ZCS1FX, ZCS3FX, DA0 to DA2, ZDIOR, ZDIOW, ZDMACK, CSEL DMARQ, HINTRQ, ZIOCS16, IORDY, ZHRST ZRD, ZWR, SUA0 to SUA6, ZCS, CSCTRL D0 to D7 IO0 to IO15 RA0 to RA8, ZRAS0, ZCAS0, ZCAS1, ZOE, ZUWE, ZLWE DBCK, DLRCK, DSDATA IOP0 to IOP7 HISIDE(WD25C32) is made by WESTERN DIGITAL No. 6238-5/12 LC895199K Pin Functions LC895199K Pin Functions (When pin 103 (ATPINSEL) is low) Type I INPUT B BIDIRECTION O OUTPUT P POWER Pin No. Pin name Type 1 VSS0 P 2 ZRAS0 O Buffer DRAM RAS signal output 3 ZCAS0 O Buffer DRAM CAS signal output 0 (Normally held at 0 (low).) 4 ZCAS1 O Buffer DRAM CAS signal output 1 5 VSS0 P NOT CONNECT Pin functions 6 ZOE O Buffer DRAM output enable 7 ZUWE O Buffer DRAM upper write enable 8 ZLWE O Buffer DRAM lower write enable 9 VSS0 P 10 RA0 O 11 RA1 O 12 RA2 O 13 RA3 O 14 RA4 O 15 RA5 O 16 RA6 O 17 RA7 O 18 VDD0 P 19 VSS0 P 20 RA8 O 21 IO0 B 22 IO1 B 23 IO2 B Data buffer DRAM data input and output 24 IO3 B These pins have built-in pull-up resistors. 25 IO4 B Data buffer DRAM address signal outputs 5.0 V Data buffer DRAM address signal output 26 IO5 B 27 VSS0 P 28 IO6 B 29 IO7 B 30 IO8 B 31 IO9 B Data buffer DRAM data input and output 32 IO10 B These pins have built-in pull-up resistors. 33 IO11 B 34 IO12 B 35 IO13 B 36 VSS0 P 37 VDD1 P 3.3 V 38 IO14 B Data buffer DRAM data input and output 39 IO15 B These pins have built-in pull-up resistors. 40 NC NC 41 VSS0 P 42 IOP0 B 43 IOP1 B 44 IOP2 B 45 IOP3 B 46 IOP4 B 47 IOP5 B 48 IOP6 B 49 IOP7 50 General-purpose input and output ports B NC 51 TEST0 I Test pin. This pin must be connected to VSS in normal operation. 52 XTALCK I Crystal oscillator circuit input Continued on next page. No. 6238-6/12 LC895199K Continued from preceding page. Pin No. Pin I/O 53 XTAL O Crystal oscillator circuit output 54 VDD0 P 5.0 V 55 VSS0 P 56 MCK O XTALCLK 1/1, 1/2, and stop output 57 TEST1 I Test pin. This pin must be connected to VSS in normal operation. 58 DSDATA O 59 DLRCK O 60 DBCK O 61 C2PO I 62 SDATA I 63 BCK I 64 LRCK I 65 EXCK O 66 WFCK I 67 SBSO I 68 SCOR I 69 PLL1 70 PLL2 71 PLL3 Function D/A converter outputs CD DSP interface Subcode input and output PLL circuit connections 72 VSS0 P (This is an analog VSS pin in the LC895199 built-in PLL version.) 73 VDD1 P 3.3 V (This is an analog VDD pin in the LC895199 built-in PLL version.) 74 ZRESET I IC reset 75 MCK3 O XTALCLK 1/1, 1/5, 2/5, 1/512, and stop output 76 CSCTRL I Microcontroller CS pin active low/active high selection 77 ZRD I Microcontroller data read signal input 78 ZWR I Microcontroller data write signal input 79 ZCS I Register chip select input from the microcontroller 80 SUA0 I 81 SUA1 I 82 SUA2 I 83 SUA3 I 84 SUA4 I 85 SUA5 I 86 SUA6 I 87 D0 B 88 D1 B 89 D2 B 90 VDD0 P 91 VSS0 P 92 D3 B 93 D4 B 94 D5 B 95 D6 B 96 D7 B 97 ZINT0 O 98 ZINT1 O Microcontroller register selection signals Microcontroller data signals These pins have built-in pull-up resistors. 5.0 V Microcontroller data signals These pins have built-in pull-up resistors. Interrupt request signal output to the microcontroller 99 ZSWAIT O Wait signal output to the microcontroller 100 ZRSTCPU O CPU reset signal 101 CSEL I 102 ZHRST I 103 ATPINSEL I 104 ZDASP B 105 ZCS3FX I 106 ZCS1FX I 107 DA2 I ATAPI control signals ATAPI pin layout selection. (This pin must be connected to VSS0.) Continued on next page. No. 6238-7/12 LC895199K Continued from preceding page. Pin No. Pin I/O 108 VSS1 P 109 VDD1 P 110 DA0 I 111 ZPDIAG B 112 DA1 I 113 ZIOCS16 O 114 HINTRQ O 115 ZDMACK I 116 VSS1 P 117 IORDY O 118 ZDIOR I 119 ZDIOW I 120 DMARQ O 121 VSS1 P 122 DD15 B 123 DD0 B 124 DD14 B 125 DD1 B 126 VDD0 P 127 VSS1 P 128 DD13 B 129 DD2 B 130 DD12 B 131 DD3 B 132 VSS1 P 133 DD11 B 134 DD4 B 135 DD10 B 136 VSS1 P 137 VDD0 P 138 DD5 B 139 DD9 B 140 DD6 B 141 VSS1 P 142 DD8 B 143 DD7 B 144 VDD1 P Function 3.3 V ATAPI control signals ATAPI control signals ATAPI data bus 5.0 V ATAPI data bus ATAPI data bus 5.0 V ATAPI data bus ATAPI data bus 3.3 V Unused (“NC”) pins must be left open. Pins whose name begin with Z operate with inverted (negative) logic. VSS0 is the logic system ground and VSS1 is the IDE interface driver ground. Applications must supply 5.0 V for VDD0 and 3.3 V for VDD1. No. 6238-8/12 LC895199K Pin Functions LC895199K Pin Functions (When pin 103 (ATPINSEL) is high) Type I INPUT B BIDIRECTION O OUTPUT P POWER Pin No. Pin name Type 1 VSS0 P 2 ZRAS0 O Buffer DRAM RAS signal output 3 ZCAS0 O Buffer DRAM CAS signal output 0 (Normally held fixed at 0 (low).) 4 ZCAS1 O Buffer DRAM CAS signal output 1 5 VSS0 P NOT CONNECT Pin functions 6 ZOE O Buffer DRAM output enable 7 ZUWE O Buffer DRAM upper write enable 8 ZLWE O Buffer DRAM lower write enable 9 VSS0 P 10 RA0 O 11 RA1 O 12 RA2 O 13 RA3 O 14 RA4 O 15 RA5 O 16 RA6 O 17 RA7 O 18 VDD0 P 19 VSS0 P 20 RA8 O 21 IO0 B 22 IO1 B 23 IO2 B Data buffer DRAM data input and output 24 IO3 B These pins have built-in pull-up resistors. 25 IO4 B Data buffer DRAM address signal outputs 5.0 V Data buffer DRAM address signal output 26 IO5 B 27 VSS0 P 28 IO6 B 29 IO7 B 30 IO8 B 31 IO9 B Data buffer DRAM data input and output 32 IO10 B These pins have built-in pull-up resistors. 33 IO11 B 34 IO12 B 35 IO13 B 36 VSS0 P 37 VDD1 P 3.3 V 38 IO14 B Data buffer DRAM data input and output 39 IO15 B These pins have built-in pull-up resistors. 40 NC NC 41 VSS0 P 42 IOP0 B 43 IOP1 B 44 IOP2 B 45 IOP3 B 46 IOP4 B 47 IOP5 B 48 IOP6 B 49 IOP7 50 General-purpose input and output ports B NC 51 TEST0 I Test pin. This pin must be connected to VSS in normal operation. 52 XTALCK I Crystal oscillator circuit input Continued on next page. No. 6238-9/12 LC895199K Continued from preceding page. Pin No. Pin I/O 53 XTAL O Crystal oscillator circuit output 54 VDD P 5.0 V 55 VSS0 P 56 MCK O XTALCLK 1/1, 1/2, and stop output 57 TEST1 I Test pin. This pin must be connected to VSS in normal operation. 58 DSDATA O 59 DLRCK O 60 DBCK O 61 C2PO I 62 SDATA I 63 BCK I 64 LRCK I 65 EXCK O 66 WFCK I 67 SBSO I 68 SCOR I 69 PLL1 70 PLL2 71 PLL3 Function D/A converter outputs CD DSP interface Subcode input and output PLL circuit connections 72 VSS0 P (This is an analog VSS pin in the LC895199 built-in PLL version.) 73 VDD1 P 3.3 V (This is an analog VDD pin in the LC895199 built-in PLL version.) 74 ZRESET I IC reset 75 MCK3 O XTALCLK 1/1, 1/5, 2/5, 1/512, and stop output 76 CSCTRL I Microcontroller CS pin active low/active high selection 77 ZRD I Microcontroller data read signal input 78 ZWR I Microcontroller data write signal input 79 ZCS I Register chip select input from the microcontroller 80 SUA0 I 81 SUA1 I 82 SUA2 I 83 SUA3 I 84 SUA4 I 85 SUA5 I 86 SUA6 I 87 D0 B 88 D1 B 89 D2 B 90 VDD0 P 91 VSS0 P 92 D3 B 93 D4 B Microcontroller data signals 94 D5 B These pins have built-in pull-up resistors. 95 D6 B 96 D7 B 97 ZINT0 O 98 ZINT1 O Microcontroller register selection signals Microcontroller data signals These pins have built-in pull-up resistors. 5.0 V Interrupt request signal output to the microcontroller 99 ZSWAIT O Wait signal output to the microcontroller 100 ZRSTCPU O CPU reset signal 101 CSEL I ATAPI control signal 102 DD7 B ATAPI data bus ATAPI pin layout selection. (This pin must be connected to VDD0.) 103 ATPINSEL I 104 DD8 B 105 DD6 B 106 DD9 B 107 DD5 B ATAPI data bus Continued on next page. No. 6238-10/12 LC895199K Continued from preceding page. Pin No. Pin I/O 108 VSS1 P 109 VDD1 P 110 DD10 B 111 DD4 B 112 DD11 B 113 DD3 B 114 DD12 B 115 DD2 B 116 VSS1 P 117 DD13 B 118 DD1 B 119 DD14 B 120 DD0 B 121 VSS1 P 122 DD15 B 123 DMARQ O 124 ZDIOW I 125 ZDIOR I 126 VDD0 P 127 VSS1 P 128 IORDY O 129 ZDMACK I 130 HINTRQ O 131 ZIOCS16 O 132 VSS1 P 133 DA1 I 134 ZPDIAG B 135 DA0 I 136 VSS1 P 137 VDD0 P 138 DA2 I 139 ZCS1FX I 140 ZCS3FX I 141 VSS1 P 142 ZDASP B 143 ZHRST I 144 VDD1 P Function 3.3 V ATAPI data bus ATAPI data bus ATAPI data bus ATAPI control signal 5.0 V ATAPI control signal ATAPI control signal 5.0 V ATAPI control signal 3.3 V Unused (“NC”) pins must be left open. Pins whose name begin with Z operate with inverted (negative) logic. VSS0 is the logic system ground and VSS1 is the IDE interface driver ground. Applications must supply 5.0 V for VDD0 and 3.3 V for VDD1. No. 6238-11/12 LC895199K Specifications of any and all SANYO products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer’s products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer’s products or equipment. SANYO Electric Co., Ltd. strives to supply high-quality high-reliability products. However, any and all semiconductor products fail with some probability. It is possible that these probabilistic failures could give rise to accidents or events that could endanger human lives, that could give rise to smoke or fire, or that could cause damage to other property. When designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. In the event that any or all SANYO products (including technical data, services) described or contained herein are controlled under any of applicable local export control laws and regulations, such products must not be exported without obtaining the export license from the authorities concerned in accordance with the above law. No part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written permission of SANYO Electric Co., Ltd. Any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. When designing equipment, refer to the “Delivery Specification” for the SANYO product that you intend to use. Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. This catalog provides information as of February, 2000. Specifications and information herein are subject to change without notice. PS No. 6238-12/12