SANYO LC895926

Ordering number : EN5829A
CMOS IC
LC895926
CD-R Encoder/Decoder IC with Built-in SCSI Interface
Overview
The LC895926 is a CD-R IC that provides a wide range of
functions including CD-ROM decoding (including ECC)
and encoding, subcode encoding and decoding, CD
encoding, ATIP decoding and CLV servo, and a SCSI
interface that includes the register block.
• Built-in multiblock transfer function for transferring
multiple blocks in a single operation.
• Automatic sequencing of encoding and decoding
processing for a reduced processing load on the system
microcontroller.
Package Dimensions
Features
unit: mm
• ECC and EDC correction/addition for CD-ROM data
(during decoding and encoding)
• Subcode decoding/encoding complete with error
detection and error correction
• ATIP decoding and CRC checking for both encoding
and decoding
• CLV servo control using ATIP data during encoding
• CIRC code insertion and EFM modulation during
encoding
• Access to buffer RAM from microcontroller via
LC895926
• Built-in SCSI interface
• Speeds of 24× for decoding and 12× for encoding
• Transfers speeds of 10 megabytes/s (synchronous) and 5
megabytes/s (asynchronous) with 16-bit 50-ns EDODRAMs
• Buffer RAM sizes between 1 and 32 megabits (using 16bit EDO-DRAMs)
• User control over sizes of CD main channel, C2 flag,
and subcode areas in buffer RAM
• Built-in batch transfer function for transferring entire
CD main channel, C2 flag, or subcode area in a single
operation.
3153A-QFP160E
[LC895926]
SANYO: QIP160E
SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN
51398HA (OT) No. 5829-1/7
LC895926
Specifications
Absdute Maximum Ratings at Ta = 25°C, VSS = 0 V
Parameter
Maximum power supply voltage
I/O voltage
Symbol
Conditions
Ratings
VDD max
VI, VO
Allowable power dissipation
Pd max
Unit
–0.3 to +7.0
V
–0.3 to VDD+0.3
V
Ta ≤ 70°C
600
mW
Operating temperature
Topr
–30 to +70
Storage temperature
Tstg
–55 to +125
°C
260
°C
Solder resistance (Pins only)
10 seconds
°C
Allowable Operating Ranges at Ta = –30 to +70°C, VSS = 0 V
Parameter
Symbol
3.3V
min
typ
3.3
Power supply voltage
VDD
3.0
Input voltage range
VIN
0
5V
max
min
typ
3.6
4.5
5.0
VDD
0
Unit
max
5.5
V
VDD
V
DC Characteristics at Ta = –30 to +70°C, VSS = 0 V, VDD = 4.5 to 5.5 V
Parameter
Symbol
Conditions
Ratings
min
typ
Unit
max
Input high level voltage
VIH
Input low level voltage
VIL
Input high level voltage
VIH
Input low level voltage
VIL
Input high level voltage
VIH
Input low level voltage
VIL
Output high level voltage
VOH
IOH = –2 mA, for pin (3)
Output low level voltage
VOL
IOL = 2 mA, for pin (3)
Output high level voltage
VOH
IOH = –2 mA, for pins (2), (4), and (6)
Output low level voltage
VOL
IOL = 2 mA, for pins (2), (4), and (6)
Output high level voltage
VOH
IOH = –48 mA, for pin (7)
Output low level voltage
VOL
IOL = 48 mA, for pin (7)
0.4
Output low level voltage
VOL
IOL = 2 mA, for pin (5)
0.4
V
+10
µA
160
kΩ
Input leak current
IIL
Pull-up resistance
RUP
TTL levels, for pins (1) and (6)
TTL levels, for pin (4), with pull-up resistors
TTL levels, for pins (0) and (7), with Schmitt inputs
VI = VSS, VDD, for pins (0), (1), (6), and (7)
For pins (4) and (5)
2.2
V
0.8
2.2
0.8
2.5
V
V
0.6
VDD — 2.1
V
V
0.4
VDD — 2.1
V
V
0.4
VDD — 2.1
V
V
–10
40
V
V
80
V
The pins above refer to the following groups.
Input
(0) BCK, BICLKIN, BIDATAI, C2PO, LOCKIN, LRCK, PLLOUTIN, ROUGH, SBSO, SCOR, SDATA, WFCK, CS,
RD, WR
(1) SUA0 to SUA7, TEST0 to TEST6, RESET
Output
(2) CLV+, CLV–, FSW
(3) EFM, EFMG, EFMGATE0 to EFMGATE3, EXCK, LOCK, MON, RA0 to RA9, SUBSYNC, CAS0 to CAS1, RAS0
to RAS1, LWE, UWE, OE
Input
(4) D0 to D7, IO0 to IO15
(5) INT0 to INT1, SWAIT
(6) ATIPSYNC, Reserve0 to Reserve7
(7) ACK, ATN, BSY, C/D, DB0 to DB7, DBP, I/O, MSG, REQ, RST, SEL
Note: The XTAL0, XTAL1, XTALCK0, and XTALCK1 pins are not included in these DC characteristic specifications.
No. 5829-2/7
LC895926
Block Diagram
Sub-code I/F
de-interleave/interleave
*1
*2
*3
*4
*6
*7
*8
*9
*10
*11
*12
WFCK, SBSO, SCOR
BCK, SDATA, LRCK, C2PO
DB0 to DB7, DBP, BSY, MSG, SEL, RST, REQ, I/O, C/D
ACK, ATN
RD, WR, SUA0 to SUA7, CS
D0 to D7
IO0 to IO15
RA0 to RA9, RAS0, RAS1, CAS0, CAS1, OE, UWE, LWE
PLLOUTIN, ROUGH, LOCKIN, BICLKIN, BIDATAIN
LOCK, CLV+ (MDP), CLV– (MDS), MON, FSW
SUBSYNC, EFM, EFMG, EFMGATE0 to EFMGATE3
No. 5829-3/7
LC895926
Pin Descriptions
Type: I: Input pin, O: Output pin, B: Bidirectional pin, P: Power supply pin, N: No connection pin
Pin Number
Pin Name
Type
1
VSS
P
Description
2
XTALCK0
I
Xtal oscillator circuit input pin (17.2872 MHz)
3
XTAL0
O
Xtal oscillator circuit output pin
4
TEST0
I
Test pin (connect to VSS)
5
RESET
I
Reset pin
6
VDD
P
5V
7
SUBSYNC
O
Subcode synchronization signal output pin
8
EFMG
O
EFM output gate signal output pin
9
EFM
O
EFM signal output pin
10
EFMGATE0
O
11
EFMGATE1
O
12
EFMGATE2
O
13
EFMGATE3
O
14
TEST1
I
15
Reserve0
B
16
Reserve1
B
17
Reserve2
B
18
Reserve3
B
19
Reserve4
B
20
VDD
P
21
VSS
P
22
Reserve5
B
23
Reserve6
B
24
Reserve7
B
25
TEST2
I
Test pin (connect to VSS)
26
LOCKIN
I
CD decoder lock signal input pin
27
LOCK
O
CLV servo lock monitor pin
28
PLLOUTIN
I
Wobble signal carrier clock input pin
29
VSS
P
EFM pulse width detection gate signals
Test pin (connect to VSS)
Reserved for future expansion (connect to VSS if unused.)
3.3V
Reserved for future expansion (connect to VSS if unused.)
30
ROUGH
I
Rough CLV servo wobble signal input pin
31
ATIPSYNC
B
ATIP synchronization signal I/O pin
32
BICLKIN
I
Biphase data transfer clock input pin
33
BIDATAI
I
Biphase data input pin
34
VDD
P
3.3V
35
VSS
P
36
CLV+ (MDP)
O
37
CLV– (MDS)
O
38
MON
O
39
FSW
O
40
VDD
P
41
VSS
P
CLV servo signal output pin
5V
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No. 5829-4/7
LC895926
Continued from preceding page.
Type: I: Input pin, O: Output pin, B: Bidirectional pin, P: Power supply pin, N: No connection pin
Pin Number
Pin Name
Type
42
IO0
B
43
IO1
B
44
IO2
B
45
IO3
B
46
IO4
B
47
IO5
B
48
VDD
P
49
IO6
B
50
IO7
B
51
IO8
B
52
IO9
B
53
VSS
P
54
IO10
B
55
IO11
B
56
IO12
B
57
IO13
B
58
IO14
B
59
IO15
B
60
VDD
P
61
VSS
P
62
RA0
O
63
RA1
O
64
RA2
O
65
RA3
O
66
RA4
O
67
RA5
O
68
RA6
O
69
VSS
P
70
RA7
O
71
RA8
O
72
RA9
O
73
RAS0
O
74
RAS1
O
75
CAS0
O
76
CAS1
O
Description
Data signal pins for ROM encoder/decoder DRAM, with pull-up resistors
5V
Data signal pins for ROM encoder/decoder DRAM, with pull-up resistors
Data signal pins for ROM encoder/decoder DRAM, with pull-up resistors
3.3V
Address signal pins for ROM encoder/decoder DRAM
Address signal pins for ROM encoder/decoder DRAM
RAS signal pins for ROM encoder/decoder DRAM
CAS signal pins for ROM encoder/decoder DRAM
77
OE
O
Output enable signal pin for ROM encoder/decoder DRAM
78
UWE
O
Upper write enable signal pin for ROM encoder/decoder DRAM
79
LWE
O
Lower write enable signal pin for ROM encoder/decoder DRAM
80
VDD
P
5V
81
VSS
P
82
DB0
B
83
DB1
B
84
VDD
P
85
DB2
B
86
DB3
B
87
VSS
P
88
DB4
B
89
DB5
B
SCSI pins
3.3V
SCSI pins
SCSI pins
Continued on next page.
No. 5829-5/7
LC895926
Continued from preceding page.
Type: I: Input pin, O: Output pin, B: Bidirectional pin, P: Power Supply pin, N: No connection pin
Pin Number
Pin Name
Type
90
VDD
P
Description
91
DB6
B
SCSI pin
92
VDD
P
5V
93
VSS
P
94
DB7
B
95
DBP
B
3.3V
SCSI pins
96
VDD
P
97
VSS
P
98
ATN
B
99
BSY
B
SCSI pin
100
VDD
P
5V
5V
SCSI pin
101
VSS
P
102
ACK
B
103
RST
B
104
VDD
P
105
VSS
P
106
MSG
B
107
SEL
B
108
VDD
P
3.3V
109
C/D
B
SCSI pin
110
VDD
P
5V
111
REQ
B
112
I/O
B
113
VSS
P
114
XTALCK1
I
115
XTAL1
O
Xtal oscillator circuit output pin for SCSI interface
116
TEST3
I
Test pin (connect to VSS)
117
TEST4
I
Test pin (connect to VSS)
118
TEST5
I
Test pin (connect to VSS)
119
BCK
I
Serial data input clock input pin
120
VDD
P
5V
121
VSS
P
SCSI pins
5V
SCSI pins
SCSI pins
Xtal oscillator circuit input pin for SCSI interface (20 MHz)
122
SDATA
I
Serial data input pin
123
LRCK
I
44.1 kHz strobe signal input pin
124
C2PO
I
C2 pointer input pin
125
EXCK
O
Subcode data read shift clock output pin
126
WFCK
I
Subcode frame synchronization input pin
127
SBSO
I
Subcode serial data input pin
128
SCOR
I
Subcode block synchronization input pin
129
VSS
P
130
SUA0
I
131
SUA1
I
132
SUA2
I
133
SUA3
I
134
SUA4
I
135
SUA5
I
136
SUA6
I
137
SUA7
I
Commande registor selection address input pins
Continued on next page.
No. 5829-6/7
LC895926
Continued from preceding page.
Type: I: Input pin, O: Output pin, B: Bidirectional pin, P: Power Supply pin, N: No connection pin
Pin Number
Pin Name
Type
138
WR
I
Data write signal from microcontroller
Description
139
RD
I
Data read signal from microcontroller
140
VDD
P
3.3V
141
VSS
P
142
CS
I
143
D0
B
144
D1
B
145
D2
B
146
D3
B
147
D4
B
148
D5
B
149
D6
B
150
D7
B
151
SWAIT
O
Wait signal to microcontroller
152
VDD
P
5V
153
INT0
O
154
INT1
O
Chip select signal from microcontroller
Microcontroller data signal pins, with pull-up resistors
Interrupt request signals to microcontroller. Open drain outputs with built-in pull-up resistors
155
TEST6
I
Test pin (connect to VSS)
156
PD
O
Charge pump output pin
157
VCNT
I
VCO control voltage pin
158
R
I
VCO bias resistor pin
159
VSS
P
160
VDD
P
3.3V
■ No products described or contained herein are intended for use in surgical implants, life-support systems, aerospace
equipment, nuclear power control systems, vehicles, disaster/crime-prevention equipment and the like, the failure of
which may directly or indirectly cause injury, death or property loss.
■ Anyone purchasing any products described or contained herein for an above-mentioned use shall:
➀ Accept full responsibility and indemnify and defend SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and
distributors and all their officers and employees, jointly and severally, against any and all claims and litigation and all
damages, cost and expenses associated with such use:
➁ Not impose any responsibility for any fault or negligence which may be cited in any such claim or litigation on
SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors or any of their officers and employees
jointly or severally.
■ Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for
volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied
regarding its use or any infringements of intellectual property rights or other rights of third parties.
This catalog provides information as of May, 1998. Specifications and information herein are subject to change
without notice.
PS No. 5829-7/7