SEMTECH SC1406ACTS

®
PORTABLE PENTIUM II & III
POWER SUPPLY CONTROLLER
January 28, 2000
SC1406A
TEL:805-498-2111 FAX:805-498-3804 WEB:http://www.semtech.com
DESCRIPTION
FEATURES
The SC1406A is a High Speed, High performance
Hysteretic Mode controller. It is part of a two chip solution, with the SC1405 Smart Driver, providing power
to advanced micro-processors. It uses a Dynamic Set
Point switching technique along with an ultra-fast comparator to provide the control signal to an external
high speed Mosfet driver. A 5-bit DAC sets the output
voltage, thus providing a voltage resolution of 25mV.
•
SC1406A has two on-chip linear regulators which
drive external PNP transistors with output voltage settings of 1.5V and 2.5Vdc. The linear regulator drivers
have a separate soft start. A PWRGD TTL level signal
is asserted when all voltages are within specifications.
The part features Low Battery Detect and Undervoltage Lock-Out for the main Hysteretic controller to assure V-DC is within acceptable limits. An Over-Current
comparator disables the main controller during an
overcurrent condition using an externally programmable threshold.
•
•
•
•
•
•
High Speed Hysteretic controller provides high
efficiency over a wide operating load range
Inherently stable
Complete power solution with two LDO drivers
®
Programmable output voltage for Pentium II & III
Processors
APPLICATIONS
Laptop and Notebook computers
High performance Microprocessor based systems
High efficiency distributed power supplies
ORDERING INFORMATION
DEVICE
PACKAGE
TEMP. (T J)
SC1406ACTS
TSSOP-28
0 - 125°C
BLOCK DIAGRAM
PIN CONFIGURATION
Top View
TSSOP-28
Pentium is a registered trademark of Intel Corporation
© 2000 SEMTECH CORP.
652 MITCHELL ROAD
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NEWBURY PARK CA 91320
®
PORTABLE PENTIUM II & III
POWER SUPPLY CONTROLLER
SC1406A
January 28, 2000
PIN DESCRIPTION
Pin
Pin Name Pin Function
1
HYS
2
CLSET
Current limit setting pin.
3
VCOUT
Voltage clamp output.
4
VCIN
Voltage clamp input.
5
VCBYP
6
VID4
VID most significant bit main controller voltage programming DAC input.
7
VID3
VID input
8
VID2
VID input
9
VID1
VID input
10
VID0
VID least significant bit main controller voltage programming DAC input.
11
BASE25
12
FB25
13
BASE15
14
FB15
15
EN
Enable. SC1406A is enabled when this signal is High. This is capable of accepting 5.0V signal
level. When used with the SC1405 driver, this pin can be connected to the PWRDY pin of the
SC1405 to include UVLO feature on the V_5 (Intel Smart Driver’s VCC).
16
PWRGD
Power Good. When the main converter output approaches and stays within ±12% of the VID
DAC setting, and both soft-start circuits periods for the main core controller and linear regulator
controllers have been terminated, this signal is driven high to VCC level. During UVLO, this
signal is undefined.
17
LBIN
Low battery input. This pin is used to set the minimum voltage to the converter through an
external resistor divider. When the input to this pin is less than 1.225V, typical, Tamky is held in
an Under-Voltage-Lock-Out mode regardless of the status of EN.
18
SSLR
Linear regulators soft start. During power-up with EN high and not in UVLO, the external soft
start capacitor (1200pF, typ) is charged by an internal 1µA current source to set the ramp up
time of the linear regulator outputs, 1.5V and 2.5V. This ramp up time is typically 2ms, 6ms
max. This is discharged through an internal switch when BIASEN is low, EN low or enter UVLO
region. Enabling internal bias and soft start requires the pin voltage to drop below a threshold of
150mV typical (200mV max). Linear regulator soft start current tolerance tracks the core soft
start current within 10%.
19
Core comparator hysteresis settling.
Voltage clamp bypass pin. Needs to have a 1500pF cap from this pin to ground to ensure
proper operation.
2.5V Linear regulator drive.
2.5V Linear regulator output feedback.
1.5V Linear regulator drive.
1.5V Linear regulator output feedback.
SSCORE Main controller CORE output soft start. During power-up with EN high and not in UVLO, the
external soft start capacitor (1800pF, typ) is charged by an internal 1µA current source to set
the ramp up time of the main converter output. This ramp up time is typically 3ms, 6ms max.
This is discharged by an internal switch when BIASEN is low, EN pin is low or in UVLO.
Enabling internal bias and soft start requires the pin voltage to drop below a threshold of
150mV typical (200mV max). Core soft start current tolerance tracks the LDO soft start current
to within 10%.
Pentium is a registered trademark of Intel Corporation
© 2000 SEMTECH CORP.
652 MITCHELL ROAD
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NEWBURY PARK CA 91320
®
PORTABLE PENTIUM II & III
POWER SUPPLY CONTROLLER
SC1406A
January 28, 2000
PIN DESCRIPTION (Cont.)
Pin Pin Name Pin Function
20
CORE
Main CORE converter output feedback.
21
DAC
Main controller digital to analog output.
22
GND
Ground
23
CO
24
VCC
Input power. Supply voltage input. This input is capable of accepting 3.3V or 5.0V supply
voltage.
25
CMP
Core comparator input pin.
26
Comparator output. Main regulator controller output used to drive the input of the SC1405 driver
IC.
CMPREF Core comparator reference input pin.
27
CL
28
CLREF
Current limit input pin.
Current limit reference input pin.
Pentium is a registered trademark of Intel Corporation
© 2000 SEMTECH CORP.
652 MITCHELL ROAD
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NEWBURY PARK CA 91320
®
PORTABLE PENTIUM II & III
POWER SUPPLY CONTROLLER
SC1406A
January 28, 2000
ABSOLUTE MAXIMUM RATINGS
PARAMETER
SYMBOL
MAXIMUM
UNITS
VCC Supply Voltage
VmaxVCC
7
V
LBIN
7
V
VCC + 0.3
GND - 0.3
V
Low Battery Input
Input & Output Pins
Enable
EN
7
V
Operating Junction Temperature
TJ
0 to +125
°C
Lead Temperature (Soldering) 10 seconds
TL
300
°C
TSTG
-65 to 150
°C
Storage Temperature
ELECTRICAL CHARACTERISTICS
Unless specified: 0 < TA < 100°C; VCC = 3.3V (See Note 1)
PARAMETER
SYMBOL
CONDITIONS
SUPPLY, BIAS, UVLO, VDC MONITOR AND POWERGOOD
Supply (VCC, GND)
VCC Supply Voltage
VCCMAX
Range
VCC Quiescent Current
ICCQ
EN is low, 3.0V < VCC < 3.6V
EN is high and in UVLO
VCC Operating Current
ICC
EN is high
MIN
TYP
MAX
UNITS
3.0
3.3
6.0
V
µA
10.0
10
350
15
mA
2.95
V
Under Voltage Lock Out Circuit
Threshold
VHCC
Hysteresis
VLCC
VHYSTCC
Enable Input
Input High
Vih
Input Low
Vil
3.0 < VCC < 5V
2.7
20
mV
0.7*VCC
V
0.8
V
V
µA
Low Battery Monitor
Threshold
Input Bias Current
VTHDC
IBDC
1.175
1.225
1.275
±0.3
VLB_IN < VTHDC
0.6
1.0
10.5
VDAC = 0.9V - 1.675V
1.08*VCC
1.12*VCC
V
0.88*VCC
IPWRGD = 10µa (source) EN is high
0.95*
VCC
IPWRGD = 10µA (sink), EN is high
0.92*VCC
V
V
0.4
V
0.8
V
VLB_IN > VTHDC
VCORE Power Good Generator
Input Threshold
VHCORE
Output Voltage
Note that during the
latency time of any VID
code change, the PWRGD
output signal is not valid
VLCORE
VHPWRGD
(Active Hi)
VLPWRGD
(Active low)
VPWRGD
VOUT
IPWRGD = 10µA (sink), UVLO
During the latency time (50µs) of
any VID code change
Note 1: Specification refers to application circuit (Figure 1.).
© 2000 SEMTECH CORP.
Pentium is a registered trademark of Intel Corporation
652 MITCHELL ROAD
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NEWBURY PARK CA 91320
®
PORTABLE PENTIUM II & III
POWER SUPPLY CONTROLLER
SC1406A
January 28, 2000
ELECTRICAL CHARACTERISTICS (CONT.)
Unless specified: -0 < TA < 100°C; VCC = 3.3V (See test circuit)
PARAMETER
SYMBOL
CONDITIONS
CORE CONVERTER CONTROLLER
MIN
TYP MAX UNITS
Core Converter Soft Start Current
Core Converter Soft Start Current
VSSCORE Soft Start Termination
Threshold
VSSCORE Discharge Threshold
ISSCORE
Charge (Source) current
0.6
1
Discharge (Sink) current
0.30
1
1.53
1.70
1.87
V
150
400
mV
VSSTERM
VSSDIS
1.45
µA
mA
VID DAC
VID Input Threshold
VVID_IH
3.0V < VCC < 3.6V
0.7*VCC
V
VVID_IL
VID Input-Pull-up Current,VID (0-4)
Output Voltage Accuracy
0.8
IVID
VID (0-4) = 00000...11111
6
40
µA
VDAC_ERR
IDAC = 0, VID(0-4) = 00000...11111
-0.85
+0.85
%
35
µs
±2
µA
±3
mV
CDAC = 1000pF
VID is set to change VCORE from
1.30V to 1.45V or 1.45V to 1.30V
CORE Comparator (CMP, CMPREF, HYS, CO)
Settling Time*
Input Bias Current
Input Offset Voltage
tpdVID_DAC
IBCMP
VCMP = VCMPREF = 1.3V
VCPM-
VCMPREF = 1.3V
±1.5
VCPMREF
Hysteresis Setting Current
RHYS = open
ICMPREF
Output Voltage
VHCO
CMP<CMPREF
VLCO
CMP>CMPREF
Propagation Delay Time**
Measured at device pins, from the
trip point to 50% of CO transition.
Output Rise/Fall Times**
Measured between 30% and 70%
points of CO transition
Tpd CMP-CO
TR
TF
+2
RHYS = 17kΩ
±85
+100 +115
RHYS = 170kΩ
±7
+10
Load Impedance = 100k in
parallel with 10pF, VCC = 3.0V
2.5
RCO = 100K
+13
V
Load Impedance = 100k in
parallel with 10pF, VCC = 3.6V
VCMPREF = 1.3V ∆ VCMP = +40mV
step with +20mV, overdrive
TA = 25°C,
TA = full range
VCMPREF = 1.3V ∆ VCMP = 40mV
step with 20mV overdrive,
TA = 25°C,
TA = full range
CCO = 10pF
VCC = 3.0V
0.4
V
20
30
ns
20
30
7
10
ns
7
10
Pentium is a registered trademark of Intel Corporation
© 2000 SEMTECH CORP.
652 MITCHELL ROAD
µA
5
NEWBURY PARK CA 91320
®
PORTABLE PENTIUM II & III
POWER SUPPLY CONTROLLER
SC1406A
January 28, 2000
ELECTRICAL CHARACTERISTICS (CONT.)
Unless specified: -0 < TA < 100°C; VCC = 3.3V (See test circuit)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX UNITS
Current Limit Comparator (CL, CLREF, CLSET)
Input Bias Current
Current Limit Setting Current
+ICL
|+ICLREF|
*The Tamky device is required to
meet the CL setting current
requirements for RCLSET of
“17kΩ and 170kΩ or “42.5kΩ and
20kΩ”. Supplier production testing
will use the 17kΩ /170kΩ
combination or the 42.5kΩ /20kΩ
combination.
VCS = 1.3V
RCLSET = open
RCLSET = 17kΩ∗
RCLSET = 170kΩ∗
RCLSET = 42.5kΩ∗
RCLSET = 20kΩ∗
Input Offset Voltage
Propagation Delay Time**
Measured at the device pins, from
the trip point to 50% of CO
transition
VCL VCLREF
Tpd_CL-CO
5
VCLREF-VCL
= 10mV
VCLRER-VCL
= -10mV
VCLREF-VCL 262.5
= 10mV
VCLREF-VCL 175
= -10mV
VCLREF-VCL 19.5
= 10mV
VCLREF-VCL 13
= -10mV
VCLRER-VCL 100.5
= 10mV
VCLRER-VCL 67
= -10mV
VCLREF-VCL
= 10mV
VCLRER-VCL
= -10mV
VCLREF = 1.3V
7.5
µA
5.0
300
337.5
200
225
30
40.5
20
27
120
139.5
80
93
222
255
288
148
170
192
±4
±6
VCMPREF = 1.3V, ∆ VCMP = +50mV
step with +20mV overdrive,
TA = 25°C,
100
TA = full range
150
VCMPREF = 1.3V, ∆ VCMP =
-50mV step with -20mV overdrive,
TA = 25°C,
100
TA = full range
150
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© 2000 SEMTECH CORP.
652 MITCHELL ROAD
µA
µA
µA
µA
µA
mV
ns
6
NEWBURY PARK CA 91320
®
PORTABLE PENTIUM II & III
POWER SUPPLY CONTROLLER
SC1406A
January 28, 2000
ELECTRICAL CHARACTERISTICS (CONT.)
Unless specified: -0 < TA < 100°C; VCC = 3.3V (See test circuit)
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX UNIT
LINEAR REGULATOR CONTROLLERS
1.5V Linear Regulator Controller
Input Bias Current
ILR15
VFB_15 = 1.5V
IO = 500mA, pnp BJT with BMIN > 50 @ 1.47 1.50
IC = 500mA
Output Voltage
CO_1.5 = 56µF, 20mΩ ESR max
or 150µF, 45mΩ ESR max
Capacitance tolerance = 20%
VO_1.5,
Imin =
0.1mA
Base Drive Output Current
IBASE_1.5
@ 25°C
ILR25
VFB_25 = 2.5V
VO_2.5,
Imin = 0A
IO = Imax, pnp BJT with BMIN > 50 @
IC = 100mA
10
1
mA
1.54
V
120
mA
1
mA
2.55
V
20
mA
2.5V Linear Regulator Controller
Input Bias Current
Output Voltage
CO_2.5 = 1µFceramic
ESR range = 1mΩ − 30mΩ
Capacitance tolerance = 20%
2.45 2.50
Imax=0.1A
Base Drive Output Current
IBASE_2.5
2.5
Linear Regulator Soft Start (LRSS)
Linear Reg Soft-Start Current
ILRSS
Charge Current, VLRSS = 0V
-0.6
-1
µA
Discharge Current, VLRSS = 1.50V,
EN is low or in UVLO
0.3
1
mA
Enable Threshold
VSSLR_EN
150
400
mV
Soft Start Termination Threshold
VTH_LRSS
1.53 1.70
1.87
V
0.93
1.60
V
VS
V
Voltage Clamp (VCIN, VCOUT, VCBYP)
Input Voltage
Output Voltage
Imin = 10µA
VH_VCIN
VH_VCOUT
VL_VCOUT
Progagation Delay**
Tpd
VCIN_VCOUT
RVCOUT = 150Ω
tied to VS = 2.5V
IVCIN = -10µA
VCIN is open 0.8VS
VVCIN = 0.175V
RVCOUT = 150Ω tied to VS = 2.5V
CVCBYP = 1500pF, VCIN steps from
0.175V to 1.50V and back.
Measured from 50% of VCIN step to
50% of VCOUT transient
1.5
0.375
10
ns
* Guaranteed by design.
**Guaranteed by characterization.
Pentium is a registered trademark of Intel Corporation
© 2000 SEMTECH CORP.
652 MITCHELL ROAD
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NEWBURY PARK CA 91320
®
PORTABLE PENTIUM II & III
POWER SUPPLY CONTROLLER
SC1406A
January 28, 2000
VID vs. VDAC VOLTAGE
VID
MIN
TYP
MAX
4
3
2
1
0
1% < VO
VO
1% > VO
0
0
0
0
0
1.658
1.675
1.692
0
0
0
0
1
1.633
1.650
1.666
0
0
0
1
0
1.609
1.625
1.641
0
0
0
1
1
1.584
1.600
1.616
0
0
1
0
0
1.560
1.575
1.591
0
0
1
0
1
1.534
1.550
1.565
0
0
1
1
0
1.510
1.525
1.540
0
0
1
1
1
1.485
1.500
1.515
0
1
0
0
0
1.460
1.475
1.490
0
1
0
0
1
1.435
1.450
1.464
0
1
0
1
0
1.411
1.425
1.439
0
1
0
1
1
1.386
1.400
1.414
0
1
1
0
0
1.361
1.375
1.389
0
1
1
0
1
1.336
1.350
1.363
0
1
1
1
0
1.312
1.325
1.338
0
1
1
1
1
1.287
1.300
1.313
1
0
0
0
0
1.262
1.275
1.288
1
0
0
0
1
1.237
1.250
1.262
1
0
0
1
0
1.213
1.225
1.237
1
0
0
1
1
1.188
1.200
1.212
1
0
1
0
0
1.163
1.175
1.187
1
0
1
0
1
1.138
1.150
1.161
1
0
1
1
0
1.114
1.125
1.136
1
0
1
1
1
1.089
1.100
1.111
1
1
0
0
0
1.064
1.075
1.086
1
1
0
0
1
1.039
1.050
1.060
1
1
0
1
0
1.015
1.025
1.035
1
1
0
1
1
0.99
1.00
1.01
1
1
1
0
0
0.965
0.975
0.984
1
1
1
0
1
0.940
0.950
0.959
1
1
1
1
0
0.916
0.925
0.934
1
1
1
1
1
0.891
0.900
0.909
Pentium is a registered trademark of Intel Corporation
© 2000 SEMTECH CORP.
652 MITCHELL ROAD
8
NEWBURY PARK CA 91320
®
PORTABLE PENTIUM II & III
POWER SUPPLY CONTROLLER
SC1406A
January 28, 2000
FUNCTIONAL DESCRIPTION
SUPPLY
The chip is optimized to operate from a 3.3V + 5% rail
but is also designed to work up to 6V maximum supply
voltage. If VCC is out of the 3.3V + 5% voltage range,
the quiescent current will increase somewhat and
slight degradation of line regulation is expected.
UNDER VOLTAGE LOCK-OUT CIRCUIT
The under voltage lockout circuit consists of two comparators, the low battery and low VCC (low supply voltage) comparators. The output of the comparator
gated with the Enable signal turns on or off the internal bias, enables or disables the CO output, and
initiates or resets the soft start timers.
POWER GOOD GENERATOR
If the chip is enabled but not in UVLO condition, and
the core voltage gets within +10% of the VID programmed value, then a high level Power Good signal
is generated on the PWRGD pin to trigger the CPU
power up sequence. If the chip is either disabled or
enabled in UVLO condition, then PWRGD stays low.
This condition is satisfied by the presence of an internal 200kΩ pull-down resistor connected from PWRGD
to ground.
During soft start, PWRGD stays low independently
from the status of Vcore voltage. During this time,
PWRGD status is “don’t care”.
BAND GAP REFERENCE
A better than +1% precision band gap reference acts
as the internal reference voltage standard of the chip,
which all critical biasing voltages and currents are derived from. All references to VREF in the equations to
follow will assume VREF = 1.7V.
CORE CONVERTER CONTROLLER
Precision VID DAC Reference
The 5-bit digital to analog converter (DAC) serves as
the programmable reference source of the core comparator. Programming is accomplished by CMOS logic
level VID code applied to the DAC inputs. The VID
code vs. the DAC output is shown in the Output Voltage Table. The accuracy of the VID DAC is maintained on the same level as the band gap reference.
There is a 10µA pull-up current on each DAC input
while EN is high.
Core Comparator
This is an ultra-fast hysteretic comparator with a typical propagation delay of approximately 20ns at a
20mV overdrive. Its hysteresis is determined by the
resistance ratio of two external resistors, RHYS and ROH,
and the high accuracy internal reference voltage, VREF.
VHYS =
R OH
• VREF
R HYS
This chip can be used in standard hysteretic mode
controller configuration and in DSPS (Dynamic Set
Point Switching) hysteretic controller scheme.
In standard hysteretic controller configuration, the
core comparator compares the output voltage of the
core converter, VCORE to the VID code programmed
DAC voltage, VDAC.
VCORE(t) = VDAC + VHYST(t)
The core voltage ramps up and down between the two
thresholds determined by the hysteresis of the comparator:
VHCORE = VDAC + VHYST
VLCORE = VDAC - VHYST
In DSPS hysteretic controller configuration, the
core comparator compares the core voltage, VCORE,
not to the DAC voltage, VDAC directly but rather to a
voltage less than the DAC voltage by a DSPS voltage,
VDSPS.
VCORE(t) = VDAC - VDSPS(t) + VHYST(t)
The DSPS voltage is a function of the load current. It
is generated from the current sense voltage, VCS ,
developed across a sense resistor, RCS, which is inserted in series with the main buck inductor and also
used for current sensing for the cycle-by-cycle current
limiting. The sense voltage is scaled up by the DSPS
gain, ADSPS, which is set by the resistance ratio of two
external resistors, RDAC and RCORE.
VDSPS ( t ) = A DSPS • VCS ( t ) = (1 +
R DAC
) • R CS • iCORE ( t )
R CORE
Pentium is a registered trademark of Intel Corporation
© 2000 SEMTECH CORP.
652 MITCHELL ROAD
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NEWBURY PARK CA 91320
®
PORTABLE PENTIUM II & III
POWER SUPPLY CONTROLLER
SC1406A
January 28, 2000
In DSPS hysteretic controller configuration
(Cont’d)
The comparator reference voltage positioning is such
that an increasing current sense voltage, VCS, i,e, an
elevating load current, causes the reference voltage to
decrease, and as a consequence, the core output voltage also droops. At no load current, there is no droop
while a maximum load, the droop is likewise maximum.
In order for the core voltage to be positioned around
the nominal VDAC voltage symmetrically and not just
one way downward from the nominal value, a DSPS
offset voltage, VDSPSOFFS, can be introduced. The offset voltage moves the comparator reference voltage
upward at no load. At optimal offsetting, the reference
voltage is above the nominal level for load currents
less than half of the maximum load, and below the
nominal value for currents higher than that. The maximum amount of core voltage positioning can be determined from the constrain which says the output voltage at no load condition must still remain below the
upper threshold of the core voltage regulation window,
and at maximum load, it must be above the lower
threshold.
The offset voltage can be generated across a resistor,
ROH, which is also used to create the hysteresis voltage by forcing a unipolar DSPS offsetting current
through it. The offsetting current is conveniently provided by a high value resistor, ROFFSET, connected from
the comparator CMP pin to the ground.
V DSPSOFFS = R OH • IDSPS = R OH •
VCS + VCORE
R OH +R OFFSET
VCS << VCORE , VCORE = VDAC ,ROH <<ROFFSET
≈
R OH
R OFFSET
• V DAC
In DSPS hysterestic controller configuration, the comparator thresholds can be calculated from the DAC
voltage, VDAC, the DSPS offsetting voltage, VDSPSOFFS,
the DSPS voltage VDSPS, and the bipolar hysteresis
voltage, VHYST by summing them at the comparator inputs at the appropriate load current levels:
Vcore :=
Core Voltage Offsetting
In order for the core voltage to be positioned around
the nominal VDAC voltage symmetrically and not just
always one direction downward, a core offset voltage,
VOFFS can be introduced. The offset voltage moves the
comparator reference voltage upwards. Using optimal
offsetting, the core comparator reference voltage will
be above the VID programmed nominal DAC voltage
for load currents less than half of the maximum load,
and below that for higher current. The maximum
amount of the core voltage positioning can be determined from the constraint that the output voltage regulation window, and at maximum load, it has to be
above the lower threshold.
The positioning offset voltage can be generated
across the same resistor, ROH also used to create the
hysteresis voltage, by forcing a unipolar offsetting current through it. The offsetting current is conveniently
provided by a high value resistor, ROFFS connected
from the comparator CMP pin to the ground.
Current Limit Comparator
The current limit comparator monitors the core converter output current and turns the high side switch off
when the current exceeds the upper current limit
threshold, VHCL and re-enable only if the load current
drops below the lower current limit threshold, VLCL.
The current is sensed by monitoring the voltage drop
across the current sense resistor, RCS, connected in
series with the core converter main inductor (the same
resistor used for DSPS input signal generation). The
thresholds have the following relationships:
VHCL = 3 •
R CLOH
• V REF
R CLSET
VLCL = 2 •
R CLOH
• V REF
R CLSET
VHYSCL =
R CLOH
• V REF
R CLSET
Vdac • (Roffset + Roh ) • Rcore − Rcs • Icore • Roffset • (Rcore + Rdac )
Rcore • Roffset − Rdac • Roh
∆Vcore := 2 • Vhys •
Rcore • (Roffset + Roh )
•
Rcore • Roffset − Rdac • Roh
Re sr +
Re sr
Rcore • (Roffset + Roh )
Rcore • Roffset − Rdac • Roh
Pentium is a registered trademark of Intel Corporation
© 2000 SEMTECH CORP.
652 MITCHELL ROAD
10
NEWBURY PARK CA 91320
®
PORTABLE PENTIUM II & III
POWER SUPPLY CONTROLLER
SC1406A
January 28, 2000
Core Converter Soft Start Timer
The main purpose of this block is to control the rampup time of the core voltage in order to reduce the initial inrush current on the core input voltage (battery)
rail. The soft start circuit consists of an internal current source, external soft start timing capacitor, internal switch across the capacitor, and a comparator
monitoring the capacitor voltage.
LINEAR REGULATOR CONTROLLER
1.5V Linear Regulator
This block is a linear regulator controller, which drives
an external PNP bipolar transistor as a pass element.
The linear regulator is capable of delivering 500mA
steady state DC current and should support transient
current of 1A, assuming the output filtering capacitor
is properly selected to provide enough charge for the
duration of the load transient.
Linear Regulator Soft Start Timer
A soft start timer circuit of the linear regulators is similar to that of the core converter, and is used to control
the ramp up time of the linear regulator output voltages. For maximum flexibility in controlling the start
up sequence, the soft start function of the linear regulators is separated from that of the core converter.
VOLTAGE CLAMP
The level translator converts an input voltage swing
on the IO rail, into a voltage swing on the CLK or VCC
rail depending on where the open drain output of the
translator is tied to through an external pull-up resistor.
The level translator has to track the input in phase,
and must be able to switch in 5ns (typical) following an
input threshold intercept.
2.5V Linear Regulator
This block is a low drop-out (LDO) linear regulator
controller, which drives an external PNP bipolar transistor as a pass element. The LDO linear regulator is
capable of delivering 100mA steady DC current and
should support transient current of 100mA, assuming
the output filtering capacitor is properly selected to
provide enough charge for the duration of the load
transient.
APPLICATION INFORMATION
Power on/off Sequence
See Application note AN99-12 for further information.
Pentium is a registered trademark of Intel Corporation
© 2000 SEMTECH CORP.
652 MITCHELL ROAD
11
NEWBURY PARK CA 91320
© 2000 SEMTECH CORP.
652 MITCHELL ROAD
R3
150
14
13
12
11
10
9
8
7
6
5
4
3
2
1
C4
150uF,4V(OSCON)
DPAK
Q2
MJD210
C1
0.001
R4(opt)
0
[email protected]
VCIN
[email protected]
SOT-23
Q1
MMBT4403LT1
C3
1uF,10V+/_20%MLCC
"D"
C2
220/6.3(T)
+3.3V
VCOUT
82k CLSET
R2
160k HYS
R1
FB15
BASE15
FB25
BASE25
VID0
VID1
VID2
VID3
VID4
VCBYP
VCIN
VCOUT
CLSET
HYS
U1
SC1406
CO
CO pin#23
EN
PWRGD
LBIN
SSLR
SSCORE
CORE
DAC
GND
CO
VCC
CMP
CMPREF
CL
CLREF
C
0.1
R8
0
C8
1.2n
0.001
R7
OH
R6
2.55k
EN1
R11
1.2k
C5
0.1
240k
OFFSET
C10
20p
CO
DACC6
C7
1.8n
C9
0.001
C
47p
PWRGD
15
16
17
18
19
20
21
22
23
24
25
26
27
28
R5
10
EN2
R
100k
SMOD
R10
10k
7
6
5
4
3
2
1
PRDY
C11
47p
C27
0.1
R9
10k
ovps
R12
3.9k
PRDY
DELAYC
SMOD
CO
GND
EN
OVPS
U2
SC1405
VCC
BG
PGND
DSPSDR
DRN
TG
C12
0.1
8
+5Vcc
9
10
11
12
13
14
CLOH
BST
1.2k
R14
2.55kCORE
R13
MMelf
D2 *
LL42
DSPSDR
C13
1u(C)
+5Vcc
R18
3.9
R17
3.9
R16
2.2
R15
2.2
C28*
1.0
"A"
Q3
Si4822
Q5
Si4822
C14
3.3u/10V(T)
Q6
Si4822
L1
1uH
Q4
Si4822
C21-23
3x1000/2V"SP"
R20
0.008
CS
R19
0.005
C24-26
3x10u(C)
C15-17
3x1u(C)
R22
5.1K
R21
omit
C18-20
3x33/25V"SC"
ovps
BST *
+5Vcc
+3.3Vcc
_
0 to 12A
+
_
+5 to 21V
+
PORTABLE PENTIUM II & III
POWER SUPPLY CONTROLLER
®
SC1406A
January 28, 2000
TYPICAL APPLICATION SCHEMATIC
Refer to application note AN99-12 for further information.
Pentium is a registered trademark of Intel Corporation
12
NEWBURY PARK CA 91320
®
PORTABLE PENTIUM II & III
POWER SUPPLY CONTROLLER
SC1406A
January 28, 2000
Output Ripple Voltage @ VIN = 6.0V
VOUT = 1.6V, IOUT = 2.0A
VOUT = 1.6V, IOUT = 12.0A
Output Ripple Voltage @ VIN = 18V
VOUT = 1.6V, IOUT = 2.0A
VOUT = 1.6V, IOUT = 12.0A
Pentium is a registered trademark of Intel Corporation
© 2000 SEMTECH CORP.
652 MITCHELL ROAD
13
NEWBURY PARK CA 91320
®
PORTABLE PENTIUM II & III
POWER SUPPLY CONTROLLER
SC1406A
January 28, 2000
Load Regulation & Efficiency
Line Regulation & Efficiency
1.05
1.05
1.00
1.00
0.95
0.95
V reg
Effi
% 0.90
0.85
0.85
0.80
0.80
0.75
Vreg
Effi
% 0.90
0.75
0
1
2
3
4
5
6
7
8
9
10 11
12
13
3
6
9
Iout, A
12
15
18
21
24
Vin, V
VIN = 12V, VO = 1.6V
VOUT = 1.6V, IOUT = 8.0A
Efficiency vs Output Voltage
Efficiency vs Input Line
0.95
0.95
0.90
0.90
% 0.85
% 0.85
0.80
0.80
0.75
0.9
1
1.1
1.2
1.3
Vout, V
VIN = 12V, IOUT = 8.0A
1.4
1.5
1.6
1.7
0.75
3
6
9
12
15
18
21
VOUT = 1.3V, IOUT = 8.0A
Pentium is a registered trademark of Intel Corporation
© 2000 SEMTECH CORP.
24
Vin, V
652 MITCHELL ROAD
14
NEWBURY PARK CA 91320
®
PORTABLE PENTIUM II & III
POWER SUPPLY CONTROLLER
SC1406A
January 28, 2000
Supply Current vs VIN, Temperature @ UVLO mode
Supply Current vs VIN. Temperature @ Operating mode
400
8
7
350
100'C
20'C
0'C
250
Current, mA
Current, uA
6
300
5
Operating @100'C
Operating @ 20'C
Operating @ 0'C
4
3
200
2
150
3
4
5
6
1
3
4
Voltage, V
DAC Output vs Temperature
120
1.6
110
Vout @ 1.675V
Vout @ 1.350V
Vout @ 0.900V
1.2
1.0
Vout/Vnom.%
1.4
DAC, V
6
Power Good Threshold vs Temperature
1.8
0.8
100
VhCode
VLCode
90
80
70
0.6
0
20
40
60
80
60
100
0
20
Temperature, 'C
40
60
80
100
Temperature, 'C
Hysteresis Setting Current vs Temperature
Current Limit Threshold vs Temperature
120
300
100
250
200
17k(+10mV)
17k(-10mV)
170k(+10mV)
170k(-10mV)
60
Current, uA
80
Current, uA
5
Voltage, V
40
100
20
50
0
42.5k +10mV
42.5k -10mV
20k +10mV
20k -10mV
150
0
0
20
40
60
Temperature, 'C
80
100
0
20
40
60
80
100
Temperaure, 'C
Pentium is a registered trademark of Intel Corporation
© 2000 SEMTECH CORP.
652 MITCHELL ROAD
15
NEWBURY PARK CA 91320
®
PORTABLE PENTIUM II & III
POWER SUPPLY CONTROLLER
SC1406A
January 28, 2000
LDOs Soft Start Current vs Temperature
2.5
2.5
2
2
1.5
DisCharge, mA
Charge, uA
1
Current
Current
Core Soft Start Current vs Temperature
1.5
DisCharge, mA
Charge, uA
1
0.5
0.5
0
0
0
20
40
60
80
0
100
20
40
60
80
100
Temperature, 'C
Temperature, 'C
Low Battery Monitor Threshold vs Temperature
LDOs Drive Currents vs Temperature
80
2.0
70
60
Current, mA
Voltage, V
1.5
1.0
50
1.5V
2.5V
40
30
20
0.5
10
0
0.0
0
20
40
60
80
0
100
20
40
60
80
100
Temperature 'C
Temperature, 'C
I/O LDO Load Regulation-Normalized for 1A
CLK LDO Load Regulation-Normalized for 100mA
101.0%
103%
102%
101%
Regulation, %
Regulation, %
100.5%
100.0%
99.5%
100%
99%
98%
97%
96%
99.0%
95%
0.0
0.5
1.0
1.5
2.0
0
50
Current, A
100
150
Pentium is a registered trademark of Intel Corporation
© 2000 SEMTECH CORP.
200
Current, mA
652 MITCHELL ROAD
16
NEWBURY PARK CA 91320
®
PORTABLE PENTIUM II & III
POWER SUPPLY CONTROLLER
SC1406A
January 28, 2000
OUTLINE DRAWING - TSSOP-28
ECN 99-755
ECN 00-856
Pentium is a registered trademark of Intel Corporation
© 2000 SEMTECH CORP.
652 MITCHELL ROAD
17
NEWBURY PARK CA 91320