SC453 Portable, VID Programmed Single Phase Power Supply Controller POWER MANAGEMENT Description Features The SC453 IC is a single chip high-performance Hysteretic PWM controller. With its integrated SmartDrive™ it powers advanced graphics and core processors. It provides sleep mode and boot voltage support. Automatic powersave is present to prevent negative current flow in the lowside FET during light loading conditions saving even more power. The high side driver initially turns on with a weak drive to reduce ringing, EMI, and capacitive turn-on of the low side. High Speed Hysteretic Controller Single Phase Operation Selectable Analog or VID Controlled Sleep Setting 6 Bit VID programmable Output Integrated Drivers with SmartDrive™ Programmable Soft-Start Programmable Boot Voltage Programmable Sleep Voltage with Sleep Mode Under-Voltage Lockout on VCCA and V5 Over-voltage Protection on VCORE Current Limit Protection on VCORE Thermal Protection Power Good Flag with Blanking During VCORE Changes Automatic Power Save at Light Load Package Types — TSSOP-28, MLPQ-32 A 6-bit DAC (accurate to 0.85%) sets the output voltage reference and implements the 0.700V to 1.708V range required by the processor. The hysteretic converter uses a comparator without an error amplifier to provide fast transient response while avoiding the stability issues inherent to classical PWM controllers. The DAC is externally slew rate limited to minimize transient currents and audible noise. The SC453 operates from a 5V supply and also features soft-start, an open-drain power good signal with VCORE transition blanking, and an enable input. Programmable current limiting shuts down the SC453 after 32 current limit pulses. Applications Low Power Notebook and Laptop Computers Embedded Applications PowerStep IV™ and Smart Driver™ are trademarks of Semtech Corporation. Typical Application Circuit VIN V5 VCCA VCORE 0.700V – 1.708V Smart Driver + SC453 Single Phase Power Supply PWM Controller VID (5:0) June 22, 2009 VID Logic and DAC 1 www.semtech.com VID0 VID1 VID2 VID3 VID4 VID5 PG_DEL 54.9K R3 1nF C10 PG# SLP EN R5 36.5K R4 33.2K 10 11 12 13 14 VID4 VID3 VID2 VID1 VID0 PG_DEL 9 8 7 6 5 VID5 HYS PG# BOOTV SLPV 4 3 BST SLP 2 1 TG DRN VID0 VID1 VID2 VID3 VID4 VID5 HYS PG# BOOTV SLPV SLP BST TG DRN BG V5 SS PG_DEL CORE DAC GND REFIN VCCA CLRF CMP CL EN PGND BST_L SC453 U1 R2 0 15 16 17 18 19 20 21 22 23 24 25 26 27 28 1uF SS CORE DAC VCCA CLRF CMP CL EN BG 15nF C22 1nF C23 C11 100pF 330pF C22 no_pop R10 1uF C9 10 R1 R13 no_pop 332 R12 150pF C12 150pF C13 R8 R7 R6 +VCORE 681 1K 681 4 1uF C6 5V Q1 Q3 IRF7832 D 4 IRF7821 MBR0530 D1 8 7 6 5 3 2 1 5 1 3 4 0.6uH L1 4 2 6 D 10uF 10uF IRF7832 Q4 R9 0.001 C7 0 R11 330uF 330uF 330uF C17 + +VCORE no_pop C8 330uF C18 + no_pop C16 + 10uF 10uF VIN C15 + C5 C4 MBRS140L D2 CSH 4.7uF C14 4 IRF7821 Q2 C3 C2 8 7 6 5 3 2 1 8 7 6 5 2 3 2 1 8 7 6 5 © 2009 Semtech Corp. 3 2 1 C1 SC453 POWER MANAGEMENT Reference Design www.semtech.com SC453 POWER MANAGEMENT Absolute Maximum Ratings Exceeding the specifications below may result in permanent damage to the device or device malfunction. Operation outside of the parameters specified in the Electrical Characteristics section is not implied. Parameter Symbol Supply Voltages VCCA, V5 Min Max Units -0.3 7 V -0.3 VCCA +0.3 V -0.3 7 V -0.3 36 40 V V -0.3 7 V -2 -5 -7.5 30 34 34 V V V TG to BST -0.3 BST +0.3 V PGND to GND -0.3 0.3 V Input and Output Voltages Conditions VSLPV, VSLP, VVID [0..5], VDAC, VREFIN, VCMP, VHYS, VCORE, VCL, VCLRF, VPG#, VBOOTV, VSS, VBG, VCLSET EN to GND to GND VEN Static Transient < 100ns BST to PGND BST to DRN Static Transient < 100ns Transient < 10ns DRN to PGND TSSOP-28(1) 70 MLPQ-32 26 θJC TSSOP-28 20 °C/W Lead Temperature (Soldering) 10s TLEAD TSSOP-28 300 °C Peak IR Reflow Temperature 10 - 40s TPKG TSSOP-28 260 MLPQ-32 260 Thermal Resistance Junction to Ambient θJA Thermal Resistance Junction to Case °C/W °C NOTES: (1) Calculated from package in still air, mounted to 3 x 4.5(in), 4 layer FR4 PCB. (2) Tested according to JEDEC standard JESD22-A114. Electrical Characteristics Unless otherwise specified: VIN = 15V, VCCA = 5V, and V5 = 5V. Parameter Symbol Conditions Min Typ Max Units 25 V Supply (VIN, VCCA, V5) VIN Supply Voltage Range VIN 3.0 V5 Supply Voltage Range V5 4.3 5.0 6.0 V VCCA 4.5 5.0 6.0 V VCCA Voltage Range © 2009 Semtech Corp. 3 www.semtech.com SC453 POWER MANAGEMENT Electrical Characteristics (Cont.) Parameter Symbol VCCA Quiescent Current ICCQ VCCA Operating Current ICC Conditions Min Typ EN is low EN is high, VCCA or V5 in UVLO Max Units 10 μA 400 μA 5 mA Under-Voltage Lockout Circuits (VCCA, V5) Threshold (VCCA falling) VCCA Hysteresis Threshold (V5 falling) V5 Hysteresis VHCCA 3.47 VHYST CCA 3.70 3.93 190 VHV5 3.85 VHYST V5 4.00 V mV 4.25 210 V mV Fixed Over-Voltage Protection (CORE) Threshold (CORE Rising) VTH CORE Not dependent on DAC setting 1.95 2.00 2.05 V FIXED Enable Input (EN) Input High ViH (EN) Input Low ViL (EN) 2 V 0.8 V VCORE Power Good Generator (PG_DEL, PG#) VDAC = 0.6 - 1.75V Core Input Threshold VTH CORE Note: during UVLO, the output level of this signal is undefined Upper Threshold 1.1× VDAC 1.15× VDAC Lower Threshold 0.86× VDAC 0.9× VDAC Hysteresis PG# Output Voltage VPG# Pulled up with external 680Ω resistor to VPULL-UP PG_DEL Output Voltage VPG_DEL 0.4 Either VCORE < 0.88*VDAC, or, VCORE > 1.12*VDAC 0.95× VPULL-UP VCCA or V5 in UVLO 0.95× VPULL-UP VCORE = VDAC, PG_DEL pulled-up with external 680Ω resistor to VPULL-UP V 0.95× VPULL-UP VCORE < 0.88*VDAC or VCORE > 1.12*VDAC 0.4 VCCA or V5 in UVLO PG_DEL Delay (at start-up) © 2009 Semtech Corp. Measured from PG# assertion 4 % 1 VCORE = VDAC V V 0.8 1007 Clocks www.semtech.com SC453 POWER MANAGEMENT Electrical Characteristics (Cont.) Parameter Symbol Conditions Min Typ Max Discharge (sink) Current 5 10 Soft-Start transition 0 < TA < 85°C, - 40 < TA < 85° C 7.5 10.5 16 Sleep Exit, 0 < TA < 85°C 204 256 310 Sleep Exit, -40 < TA < 85°C 180 240 320 VID Transition, 0 < TA < 85°C 102 128 155 VID Transition, -40 < TA < 85°C 90 120 160 40 100 Units Soft-Start & DAC Slew (SS) Soft-Start/DAC Slew Current Note: SS cap is not discharged until EN goes low or UVLO cuts in. To enable the converter, SS has to drop below VSS_EN. Soft-Start Enable Threshold ISS VSS_EN mA μA mV DAC (VID [5:0]) VID Input Threshold ViH_VID 0.55 V ViL_VID DAC Output Voltage Accuracy VDAC_ERR 0.45 0° < TA < 85°C, VID [5:0] = 000000 111111(1.708V - 0.812V) -25°C < TA < 85°C, VID [5:0] = 000000 111111 (1.708V - 0.700V) -0.85 +0.85 % -2.0 +2.0 % |±3| % Boot Voltage (BOOTV) Input Voltage Offset VBOOTV-VDAC BOOT Delay Time(1) TBOOT BOOTV = 1.2V 10 35 μs Sleep (SLP, SLPV) Input Voltage Offset SLP Logic Threshold VSLPV - VDAC SLPV = 0.8V ViH_SLP |±3| % 2 V ViL_SLP 0.8 CORE Comparator (CMP, REFIN, HYS) Input Bias Current IREFIN Input Voltage Offset VCMP VREFIN © 2009 Semtech Corp. VREFIN = 1.3V |±1.5| 5 |±2| μA |±3| mV www.semtech.com SC453 POWER MANAGEMENT Electrical Characteristics (Cont.) Parameter Symbol Conditions Min Typ Max VCMP < VREFIN -110 -100 -90 VCMP > VREFIN 90 100 110 VCMP < VREFIN -7 -10 -13 VCMP > VREFIN 7 10 13 VCMP < VREFIN -83 -73 -63 VCMP > VREFIN 63 73 83 Units CORE Comparator (CMP, REFIN, HYS) (Cont.) RHYS = 17K Hysteresis Setting Current SLP = low ICMP RHYS = 170K Hysteresis Setting Current SLP = high ISLP_ ICMP RHYS = 17K μA μA Current Limit Comparator (CL, CLRF, HYS) Input Bias Current Input Voltage Offset ICL VCL1, 2 = 1.3V VCL- VCLRF RHYS = 17K Current Limit Setting Current SLP = low ICLRF RHYS = 170K Current Limit Setting Current SLP = high ISLP_CLRF RHYS = 17K |±2| μA |±3| |±5| mV VCL < VCLRF 150 200 250 VCL > VCLRF 250 300 350 VCL < VCLRF 15 20 25 VCL > VCLRF 25 30 35 VCL < VCLRF 120 150 180 VCL > VCLRF 195 230 265 μA μA Zero-Crossing (Powersave) Comparators (CL, CORE) Offset VCL- VCORE |±5| mV High Side Driver (TG) Peak Output Current(1) Output Resistance Ipkh RSRC_TG 1.5 I = 100mA, VBST-VDRN = 5V A VDRN < 1V 4.2 VDRN > 1V 1 4 1.4 Ω RSINK_TG I = 100mA, VBST-VDRN = 5V 0.7 Rise Time(1) trTG CTG = 3nF, VBST-VDRN = 5V 60 ns Fall Time(1) tfTG CTG = 3nF, VBST-VDRN = 5V 36 ns © 2009 Semtech Corp. 6 Ω www.semtech.com SC453 POWER MANAGEMENT Electrical Characteristics (Cont.) Parameter Symbol Conditions Min Typ Max Units High Side Driver (Cont.) Propagation Delay TG Going High(1) tpdhTG CMP crossing REFIN to 10% point of TG, CTG = 3nF, BG = 0V 45 ns Propagation Delay TG Going Low(1) tpdlTG CMP crossing REFIN to 90% point of TG, CTG = 3nF 45 ns Shoot-thru Protection Delay Time(1) tspd 21 30 39 ns Low Side Driver (BG) Peak Output Current(1) Output Resistance Ipkl RSRC_BG 3 A 1.0 2.6 0.5 1.2 I = 100mA, V5 = 5V RSINK_BG Ω Rise Time(1) trBG CBG = 3nF, V5 = 5V 25 ns Fall Time(1) tfBG CTG = 3nF, V = 5V 15 ns Propagation Delay TG Going High(1) tpdhBG CMP crossing REFIN to 10% point of BG, CBG = 3nF, DRN = 0V 35 ns Propagation Delay TG Going Low(1) tpdlBG CMP crossing REFIN to 90% point of TG, CTG = 3nF, DRN = 0V 35 ns Notes: 1) Guaranteed by design. © 2009 Semtech Corp. 7 www.semtech.com SC453 POWER MANAGEMENT Pin Configurations Ordering Information TOP VIEW DRN 1 28 V5 TG 2 27 BG BST 3 26 PGND SLP 4 25 EN SLPV 5 24 CL BOOTV 6 23 CMP PG# 7 22 CLRF HYS 8 21 VCCA VID5 9 20 REFIN VID4 10 19 GND VID3 11 18 DAC VID2 12 17 CORE VID1 13 16 PG_DEL VID0 14 15 SS Device Package SC453TSTRT(1)(2)(3) TSSOP-28 SC453EVB EVALUATION BOARD SC453MLTRT(1)(2)(4) MLPQ-32 Notes: 1. This device is ESD sensitive. Use of standard ESD handling precautions is required. 2. Lead-free package only. Qualified to support maximum IR reflow temperature of 260°C for 30 seconds. 3. Available in tape and reel only. A reel contains 2500 devices. 4. Available in tape and reel only. A reel contains 3000 devices. NC BST TG DRN V5 BG PGND NC TSSOP-28 Package θJA = 70°C/W 32 31 30 29 28 27 26 25 SLP 1 24 NC SLPV 2 23 EN BOOTV 3 22 CL PG# 4 21 CMP HYS 5 20 CLRF VID5 6 19 VCCA TOP VIEW T 9 10 11 12 13 14 15 16 GND NC DAC 17 CORE 8 PG_DEL VID3 SS REFIN VID0 18 VID1 7 VID2 VID4 MLPQ-32 Package θJA = 29°C/W © 2009 Semtech Corp. 8 www.semtech.com SC453 POWER MANAGEMENT Pin Confi guration Descriptions Pin# Pin# TSSOP-28 MLPQ-32 Pin Name Pin Function This pin connects to the junction of the switching and synchronous MOSFETs. 1 29 DRN 2 30 TG 3 31 BST Bootstrap pin. A capacitor is connected between BST and DRN pins to develop the floating bootstrap voltage for the high-side MOSFET gate drive. 4 1 SLP Sleep logic input signal. 5 2 SLPV 6 3 BOOTV 7 4 PG# Start clock indicator open drain output — Active low 8 5 HYS Core Comparator Hysteresis — Connect to ground through an external resistor. Hysteresis current is established by the internal VREF voltage, 1.7V, divided by the total HYS resistance (RHYS). 9 6 VID5 VID input, most significant bit of the voltage programming DAC input 10 7 VID4 VID input 11 8 VID3 VID input 12 9 VID2 VID input 13 10 VID1 VID input 14 11 VID0 VID input, least significant bit of the voltage programming DAC input 15 12 SS 16 13 17 14 CORE 18 15 DAC Main controller digital-to-analog output 19 16 GND Analog ground 20 18 REFIN Core Comparator reference input pin — connect to DAC. 21 19 VCCA 5V supply for precision analog circuitry 22 20 CLRF Current limit reference input 23 21 CMP Core Comparator input 24 22 CL © 2009 Semtech Corp. Gate drive for the switching (high-side) MOSFET. Connect this pin to VCCA to select VID Sleep Mode. Otherwise, SLPV Sleep Mode is selected and the voltage on this pin sets the DAC output during sleep. The voltage on this pin sets the Boot-Up voltage. Soft-start — an external cap defines the soft-start ramp. Delayed Power Good — open drain output. After the VCORE output is within ± 14% of PG_DEL the VID_DAC setting, and the tCPU_PWRGD period has terminated, this internal pulldown MOSFET opens and the pin is pulled high by an external resistor. Feedback input for the VCORE output. A small RC filter should be used to filter out high frequency noise to prevent false or faulty trip conditions. Current limit input 9 www.semtech.com SC453 POWER MANAGEMENT Pin Descriptions (Cont.) Pin# Pin# TSSOP-28 MLPQ-32 Pin Name Pin Function 25 23 EN 26 26 PGND 27 27 BG Gate drive output for the synchronous (low-side) MOSFET 28 28 V5 5V supply input for the gate drive outputs — a 1μF minimum capacitor should be connected from V5 to GND — 17 NC No connection — 24 NC No connection — 25 NC No connection — 32 NC No connection — T T © 2009 Semtech Corp. Enable input — active high Power ground — connect to the low-side MOSFET power ground Thermal pad — No internal connection. Connect to GND. 10 www.semtech.com SC453 POWER MANAGEMENT Block Diagram VCCA V5 VCCA Voltage and Current Ref. GND BST TG DRN BG VSS DAC VID DAC V IN Driver Delay Driver Control VREF VID (0:5) 5V L1 RCS PGND SLPV BOOTV CORE CL CLREF Zero Crossing comparator SLP 1•Hys Bias EN RCLOH 2•Hys SST DAC VID/SLPV Sleep Mode Detect VCCA Vss Term CDAC Bias EN VCCA UVLO Generator REFIN CMP Core Converter Soft-Start Core Comparator RCH CORE SS UVLO Bias & Reference CSS RHYS1 RHYS2 RHYS3 VPULL_UP + +/-1• Hys HYS CORE Enable EN VCCA Power Good Generator DAC Core Hi PG# VPULL_UP Core Low Bias_EN SST PG_DEL Startup Delay Counter © 2009 Semtech Corp. Blanking Counter 11 VID/Sleep Change Detect www.semtech.com SC453 POWER MANAGEMENT Applications Information (Cont.) SUPPLY, BIAS, UVLO, POWER GOOD GENERATOR VID Supply The chip is optimized to operate from a 5V ± 5% rail but also designed to work up to 6V maximum supply voltage. Under-Voltage Lock-Out Circuit The Under-Voltage Lock-Out (UVLO) circuitry monitors both the VCCA and V5 voltage levels. The SC453 is in UVLO mode while either supply has not ramped above the upper threshold or has dropped below the lower threshold. During UVLO, the external FETs are held off. Over-Voltage Protection If the CORE voltage is greater than +14% of the DAC (i.e., out of the power good window), the SC453 will latch off and hold the low-side driver on permanently. Either of the 5V supplies or the EN pin must be cycled to clear the latch. The latch is disabled during soft-start and VID/Sleep transitions. For safety, the latch is enabled if the CORE voltage exceeds 2V even during VID/Sleep transitions. Thermal Shutdown The device will be disabled and latched off when the internal junction temperature reaches approximately 160°C. Either the power or EN must be recycled to clear the latch. Band Gap Reference A ± 0.85% precision band gap reference acts as the internal reference voltage standard of the chip, which all critical biasing voltages and currents are derived from. All references to VREF in the equations to follow will assume VREF = 1.7V. Precision DAC This 6-bit digital-to-analog converter (DAC) serves as the programmable reference source of the core comparator. Programming is accomplished by logic voltage levels applied to the DAC inputs. The VID code vs. the DAC output is shown in the following table. The accuracy of the VID /DAC is maintained on the same level as the band gap reference. © 2009 Semtech Corp. 12 VDAC VID VDAC 5 4 3 2 1 0 V 5 4 3 2 1 0 V 0 0 0 0 0 0 1.708 1 0 0 0 0 0 1.196 0 0 0 0 0 1 1.692 1 0 0 0 0 1 1.180 0 0 0 0 1 0 1.676 1 0 0 0 1 0 1.164 0 0 0 0 1 1 1.660 1 0 0 0 1 1 1.148 0 0 0 1 0 0 1.644 1 0 0 1 0 0 1.132 0 0 0 1 0 1 1.628 1 0 0 1 0 1 1.116 0 0 0 1 1 0 1.612 1 0 0 1 1 0 1.100 0 0 0 1 1 1 1.596 1 0 0 1 1 1 1.084 0 0 1 0 0 0 1.580 1 0 1 0 0 0 1.068 0 0 1 0 0 1 1.564 1 0 1 0 0 1 1.052 0 0 1 0 1 0 1.548 1 0 1 0 1 0 1.036 0 0 1 0 1 1 1.532 1 0 1 0 1 1 1.020 0 0 1 1 0 0 1.516 1 0 1 1 0 0 1.004 0 0 1 1 0 1 1.500 1 0 1 1 0 1 0.988 0 0 1 1 1 0 1.484 1 0 1 1 1 0 0.972 0 0 1 1 1 1 1.468 1 0 1 1 1 1 0.956 0 1 0 0 0 0 1.452 1 1 0 0 0 0 0.940 0 1 0 0 0 1 1.436 1 1 0 0 0 1 0.924 0 1 0 0 1 0 1.420 1 1 0 0 1 0 0.908 0 1 0 0 1 1 1.404 1 1 0 0 1 1 0.892 0 1 0 1 0 0 1.388 1 1 0 1 0 0 0.876 0 1 0 1 0 1 1.372 1 1 0 1 0 1 0.860 0 1 0 1 1 0 1.356 1 1 0 1 1 0 0.844 0 1 0 1 1 1 1.340 1 1 0 1 1 1 0.828 0 1 1 0 0 0 1.324 1 1 1 0 0 0 0.812 0 1 1 0 0 1 1.308 1 1 1 0 0 1 0.796 0 1 1 0 1 0 1.292 1 1 1 0 1 0 0.780 0 1 1 0 1 1 1.276 1 1 1 0 1 1 0.764 0 1 1 1 0 0 1.260 1 1 1 1 0 0 0.748 0 1 1 1 0 1 1.244 1 1 1 1 0 1 0.732 0 1 1 1 1 0 1.228 1 1 1 1 1 0 0.716 0 1 1 1 1 1 1.212 1 1 1 1 1 1 0.700 www.semtech.com SC453 POWER MANAGEMENT Applications Information (Cont.) CORE CONVERTER CONTROLLER Core Comparator This is an ultra-fast hysteretic comparator with a typical propagation delay of 20ns for 20mV overdrive. Hysteresis is generated by the current set at the HYS pin impressed upon an external resistor connected to the CMP pin. DAC Slew Control The output of the DAC will slew at a rate defined by the current in the SS pin and the capacitor applied externally to the SS pin. The slew rate (charge current) applied depends on which mode (soft-start, VID or sleep transition) is in effect. A 1nF capacitor is recommended for the DAC pin. Current Limit Comparator The Current Limit Comparator compares the voltage between the CL and CLREF pins. The CL pin monitors the inductor current using the voltage drop across a resistor connected in series with the inductor. The CLREF voltage determines the upper limit for the Current Limit Comparator. The upper limit is equal to the (3 x HYS) current multiplied by the resistance connected to the CLREF pin. Blanking During VID Changes On any VID change or Sleep change, the PG# and PG_ DEL signals are blanked for 62 switching cycles to prevent glitching during the transition. Sleep Function and SLPV/VID Sleep Mode By default, the controller is in SLPV controlled sleep mode. In this mode, the voltage applied to the SLPV pin appears at the DAC output when SLP is asserted high. This mode is selected by connecting the SLPV to a resistor divider from the HYS pin, A current limit condition occurs when the CL voltage exceeds the CLREF voltage, at which point the high side FETs are turned off. The high side FETs will not be enabled again until the inductor current drops below the lower current limit threshold. The upper and lower current limit thresholds are programmed by the voltage drop impressed upon an external resistor connected to the CLRF pin. The voltage drop is equal to the HYS current multiplied by the VID sleep mode is selected by connecting the SLPV pin to VCCA during startup. In this mode, the DAC output continues to be set by the VID inputs even when SLP is asserted high. During sleep mode, the hysteresis current used for PWM switching and for current limit are reduced to 70% of their nominal values. Current Limit Latch If the CORE voltage goes lower than 14% below the VID (i.e., out of the power good window), then sustained current limiting (32 current limit pulses) will cause the part to permanently latch off. The latch is inhibited during softstart. Core Converter Soft-Start Timer This block controls the start-up ramp time of the CORE voltage up to the boot voltage. The primary purpose is to reduce the initial in-rush current on the core input voltage (battery) rail. Cycle-by-Cycle Power-Save A zero crossing comparator detects when the currents through the external sense resistor reduces to zero. When the current in the external sense resistor reaches zero, the bottom FET is latched off. The latch is reset when the controller decides to switch on the top FET. This prevents excessive switching at light loads and hence saves switching power losses. © 2009 Semtech Corp. 13 www.semtech.com SC453 POWER MANAGEMENT Applications Information (Cont.) PG# Output This is an open-drain output and should be pulled up externally. This signal is asserted (pulled low) by the SC453 whenever the core voltage is within ±14% of the VID programmed value. If the chip is disabled by the EN input or by 5V UVLO, then the PG# pin is de-asserted. During start-up PG# remains de-asserted until the core voltage has reached the defined boot voltage and remains there for the BOOT period (10μS minimum). This signal is forced low (asserted) during VID and sleep transitions. and should be pulled up externally. This signal is asserted (open drain) by the SC453 whenever the core is within ±14% of the VID programmed value. If the chip is disabled or enabled in UVLO, then PG_DEL is de-asserted. The signal is forced high (open drain) during VID and sleep transitions. Start-Up and Sequencing On start-up, VCORE ramps to the boot voltage set by the BOOTV pin irrespective of the status of the VID pins. After a minimum of 10μs, PG# asserts, and VCORE will then respond to the VID inputs. The controller will then count 1007 switching cycles before asserting PG_DEL. PG_DEL Output This signal is delayed a minimum of 3mS from first assertion of the PG# signal. This is an open drain output Summary of Fault Conditions Protection Mode Latched? When Active Driver Status SS Pin Status Supply UVLO (VCCA, V5) 32 Cycle Current Limit No Yes Always SS has terminated and PGDEL is low All low TG low Low Sawtooth 114% VCORE OVP Yes SS has terminated and PGDEL is low BG high High 2.0VCORE OVP Yes Always BG high High Thermal Shutdown Yes Always BG, TG low High Driver Timing Diagram CMPRF CMP tpdlTG (see note) tfTG tpdh TG tr TG TG (see note) tpdh BG tpdlBG trBG tfBG tspd BG NOTE: Subtract 20ns (typical) for the core comparator delay since this parameter is specified from a CMP edge. © 2009 Semtech Corp. 14 www.semtech.com SC453 POWER MANAGEMENT Applications Information (Cont.) Step 2 — Output Inductor and Capacitor Selection The SC453 has passive droop. The voltage at full load is less than the DAC voltage by the voltage drop across the current sense resistor and any PCB copper losses from the sense resistor to the processor socket. The steadystate voltage at full load is as follows. DESIGN PROCEDURE Step 1 — Define Constants VINMAX := 20 V Maximum input voltage VINMIN := 8 V Minimum input voltage IMAX_FL := 20 A Maximum load current, highest output voltage ILKGMAX := 5 A Leakage current, highest output voltage VMAX_NL := 1.212 V The highest VCORE voltage VMIN_NL := 0.956 ⋅ V The lowest VCORE voltage VREF := 1.7 V SC453 Internal reference voltage C OUT := 330 ⋅ μF Output capacitance per cap R ESR := 6 m⋅ Ω ESR per cap R CS := 1 m⋅ Ω Current sense resistor ( ) VMAX_FL := VMAX_NL − R CS + R CU ⋅ IMAX_FL VMAX_FL = 1.182 V R CU := 0.5 m⋅ Ω ESR ≤ VPOS_TRANS (IMAX_FL − ILKGMAX) ( ) VNEG_TRANS ≥ deltaV C OUT Parasitic resistance from the current sense resistor to the processor VPOS_TRANS := 50 mV Voltage droop allowed for a low current to high current transient VNEG_TRANS := 50 mV Voltage rise allowed for a high current to low current transient VRIPPLE := 20 m V Output capacitance and ESR values are a function of transient requirements and output inductor value. Figure 1 illustrates the response of a hysteretic converter to a positive transient. In a hysteretic converter with passive droop, like the SC453, two conditions determine if you meet the positive transient requirements. Desired maximum output ripple Figure 1 — Hysteretic Converter Response to a Positive Transient The first condition is easy to see; if the ESR is too high, the instantaneous I•ESR drop seen at the output will be larger than the allowed limit. © 2009 Semtech Corp. 15 www.semtech.com SC453 POWER MANAGEMENT Applications Information (Cont.) The second condition occurs later after the initial transient. Due to the fast response of the hysteretic converters, less then < 100ns, the capacitor voltage does not droop very far before the inductor current starts ramping up. Once the inductor current starts to rise, the I•ESR comp onent of the capacitor voltage start to move upward. At the same time, the capacitive discharging causes the capacitor voltage to move downward. The lowest output voltage is reached when the inductor current reaches the load current (note the shaded area on the graph). If this voltage is higher than the lower limit (VPOS_TRANS), then the transient response passes. The design is based on the following three factors: 1) minimum inductance requirement; 2) low DCR; 3) height and package size consideration. The design choice is made based upon the requirement of the converter design, including minimum inductance, minimum saturation current, efficiency, foot area, maximum allowable height, and device availability. In the current demo board design, L1 := 0.60 ⋅ μH This value of inductance is required up to maximum load. Inductors with a swinging choke characteristic, where the zero current value of inductance is much less than the full load current inductance can be used, as long as the above restriction is met. Then, the worst-case (low input voltage) response time (the time for the current to reach the new transient value) is: Since the highest output voltage has the most severe requirements, any other modes are satisfied by a design optimized for the highest output voltage. ESR MAX := VPOS_TRANS (IMAX_FL − ILKGMAX) ESR MAX = 3.333 × 10 −3 dT := −6 s Add 100ns for the typical propagation delay from a change at the output to the MOSFET switch turning on in reaction. Since the shaded area is, the total charge taken out of the capacitor is ∆Q = C / dV = (dI/dt)/2. This is calculated using the following equation. C MINP := VMAX_NL (IMAX_FL − ILKGMAX)⋅ (dT + 1 ⋅ 10 − 7 ⋅ sec ) VPOS_TRANS VINMAX C MINP = 4.278 × 10 (VINMAX − VMAX_NL)⋅ (ESR MAX + R CS ) ⎝ LMIN = 5.422 × 10 −7 ESR MAX −4 F This condition applies only to the positive transient. ⎛ ESR MAX + R CS ⎞ F S ⋅ VRIPPLE ⋅ ⎜ © 2009 Semtech Corp. VINMIN − VMAX_NL dT = 1.326 × 10 F S := 350 K ⋅ Hz LMIN := dMIN ⋅ ) Ω For the second condition, the inductor value is determined, which is a function of the highest desired switching frequency. The maximum frequency occurs at the highest input voltage. As a reasonable compromise between efficiency and component size, a maximum switching frequency of 350kHz is desired. dMIN := ( L1 ⋅ IMAX_FL − ILKGMAX ⎠ H 16 www.semtech.com SC453 POWER MANAGEMENT Applications Information (Cont.) LOAD RELEASE The worst-case for the transient load release is when the hysteresis has just reached the maximum, (i.e. the highside switch has just turned of ). At this time the inductor has reached its peak current as calculated below. IRIPPLE := t := 0 , 10 n⋅ s .. 10 μ ⋅ s ⎛ IL( t) := ⎜ It0 − VMAX_FL⋅ t ⎞ ⎝ (VINMAX − VMAX_F ⎠ L1 ICAP( t) := IL( t) − ILKGMAX L1 ⋅ F S Since the output inductor is discharging at a fixed rate, there are two terms contributing to the increase of the voltage on the output capacitors: 1) is due to the ESR of the output capacitor; 2) is due to the added charge contributed by the inductor current. RIPPLE = 6.01 A It0 := IMAX ( ) ( ) ( ) VESR t , N CAP := ICAP( t) ⋅ It0 = 23.005 A R ESR N CAP The load is stepping from high to low. dVCAP t , N CAP := L RDS RCU ICAP( t) ⋅ t C OUT⋅ N CAP Rds_ON ( ) ( ) VTOTAL t , N CAP := VESR t , N CAP + dVCAP t , N CAP BG ESR_eq IMAX IMIN R_LOAD Cout_eq Rcu_rt Immediately after the load steps down from IMAX to IMIN, the high side FET is turned off, and the bottom FET is turned on after the dead time. It is assumed for the worst-case condition that at t = 0, the inductor current is initially at its maximum;. After t = 0, the inductor discharges at a rate equal to VFL / L (ignoring secondary order effects such as Rds_on drop, current sense resistor and copper losses). The energy released from the output inductor during load step-down, charges the output capacitors and is dissipated through the following means: Rds_on, Rcs, Rcu, Rcu_rt, ESR of the output capacitors and load. © 2009 Semtech Corp. The chart above shows the system response for the capacitors defined in Step 1 and the chart to follow shows the details of the response for the chosen number of output capacitors. 17 www.semtech.com SC453 POWER MANAGEMENT Applications Information (Cont.) VHYS is created by switching a current source (IHYS) through a resistor in series with the CMP pin. The IHYS value is controlled via RHYS. For simplicity it is easier to select a value for CMP resistor (R7, see Typical Application Circuit on page 2) and then calculate RHYS, as follows. R 7 := 1 K ⋅ Ω R HYS := . 2 ⋅ VREF ⎛ VHYS ⎞ ⎜ ⎝ R7 ⎠ R HYS = 102.0 KΩ In the SC453 application circuit, RHYS consists of three resistors (R3, R4 and R5) in parallel with R14. These resistors also form the dividers for BOOTV and SLPV. Note also that depending on circuit layout and parasitics, RHYS may have to be adjusted slightly to obtain optimum performance. (The above resistors will be calculated after the PBOOT and deeper sleep voltages are set later in this procedure). To increase hysteresis without having to change the divider resistors, a fourth resistor (R14), can be added. Additional hysteresis is needed when inductances in the current sense paths cause additional signal that adds to the resistive signal, limiting the accuracy of the calculations. Step 3 — Setting RHYS The next step is to calculate RHYS. Since the SC453 is a hysteretic controller, it regulates the amount of output ripple according to a hysteresis value set by RHYS. The designer must therefore decide upon the amount of desired output ripple, and then set RHYS accordingly. The hysteresis controls the amount of ripple voltage at the point of regulation, which is the point between the inductor and the current sense resistor. The amount of ripple at the output is defined by the current sense resistor and the output capacitor ESR. This factor is taken into account in the equation shown below relating VRIPPLE to VHYS. SC453 To achieve tight accuracy, it is recommended that the output ripple be set to 20mV peak-to-peak. ESR := R ESR ESR = 1.5 × 10 N CAP −3 HYS Ω R14 R5 BOOTV VRIPPLE = 0.02 V R4 VHYS := VRIPPLE ⋅ (R CS + ESR ) SLPV ESR R3 VHYS = 0.033 V © 2009 Semtech Corp. 18 www.semtech.com SC453 POWER MANAGEMENT Applications Information (Cont.) ⎛⎜ R 14 ⋅ R HYS ⎜ R 14 − R HYS v := ⎜ 0 ⎜ ⎜⎝ 0 Step 4 — BOOTV Design The boot-up voltage for VCORE is set at 1.2V. For the SC453 typical application circuit, R3, R4, and R5 form a voltage divider off VREF and are used to set the boot voltage. For simplicity RBOOT : = R3 + R4. VBOOT := 1.2 V ( R HYS := 1 R 25 R BOOT := + ) soln := lsolve M x , v 1 1 R BOOT + R 5 ⎞ ⎟ ⎟ ⎟ ⎟⎠ ⎛ 5.011 × 10 4 ⎞ ⎜ soln = ⎜ 3.007 × 10 4 ⎟ Ω ⎜ ⎟ ⎜ 4⎟ ⎝ 3.341 × 10 ⎠ 4 VBOOT⋅ R 5 R 3 := ( 1 0 0 ) ⋅ soln R 3 = 5.011 × 10 Ω VREF − VBOOT R 4 := ( 0 1 0 ) ⋅ soln R 4 = 3.007 × 10 Ω R 5 := ( 0 0 1 ) ⋅ soln R 5 = 3.341 × 10 Ω Step 5 — Sleep Voltage Design The sleep voltage is set at 0.750V nominally using the R3 - R4 - R5 divider. R5 = 33.2KΩ. R4 = 30.1KΩ R3 = 49.9KΩ (R 4 + R 5 ) VREF − VSLP Step 6 — Current Limit Calculation Setting the threshold for current limit is a relatively straightforward process. To do this the peak current calculation is based on the maximum DC value plus the worst-case ripple current. The following calculations apply for a single phase. Worst-case ripple occurs at the highest input voltage. Since ripple is also inversely proportional to inductance, it is recommended that the minimum inductance value be used based on the manufacturer’s specified tolerance: R3, R4, and R5 are calculated using a matrix to solve the simultaneous equations. R14 is set at 1MΩ as a placeholder: R 14 := 1000 KΩ 1 1 ⎛1 ⎜ VBOOT ⎜ − 1 1 VREF − VBOOT M x := ⎜ ⎜ ⎜ −1 −1 VSLP ⋅ ⎜ 1 VSLP ⋅ V − V VREF − VSLP REF SLP ⎝ 4 From the standard 1% resistor value table, the following values are chosen according to the calculation results. VSLP := 0.750 V R 3 := VSLP ⋅ 4 ⎞ LLOW := L1 ⋅ ( 1 − 20 %) ⎟ ⎟ ⎟ ⎟ ⎟ ⎠ IRIPPLE_MAX := LLOW = 4.8 × 10 −7 H (VINMAX − VMAX_NL)⋅ dMIN LLOW⋅ F S IRIPPLE_MAX = 6.777 A © 2009 Semtech Corp. 19 www.semtech.com SC453 POWER MANAGEMENT Applications Information (Cont.) The current limit is set at ICLIM = ICLMAX, and then solve for RCL, which is R6 in the typical applications circuit. For balance, R8, in series with the CLRF pin is kept the same value as R6. To calculate the maximum DC value of current the maximum DC current must be added to the maximum ripple value to obtain peak current: IPEAK := IMAX_FL + IRIPPLE_MAX 2 R CL := IPEAK = 23.389 A It is recommended that the current limit be set at 120% of the peak value to allow for inductor current overshoot during load transients. R 8 := R 6 ICLIM = 28.066 A R 6 := 681 Ω R 8 = 681 Ω Step 7 — Small Capacitors/Resistor Selection Several small capacitors are required for signal filtering. Refer to the Typical Application Circuit on page 2. Use SMT ceramic capacitors with an X7R or better temperature coefficient. COG is preferred. The Current Limit Comparator internal to the SC453 monitors the output current and turns the high side switch off when the current exceeds the upper current limit threshold, ICLMAX and re-enables only if the load current drops below the lower current limit threshold, ICLMIN. The current is sensed by monitoring the voltage drop across the current sense resistor RCS. C11 and R7 are used to filter the hysteretic ripple signal. The components are sized to provide filtering above the 5th harmonic of the fundamental. Current limiting will cycle from ICLMAX to ICLMIN for 32 switching cycles to allow for short term transients, then the converter is latched off. ICLMAX and ICLMIN are set according to the following equations. ICLMIN := 2 ⋅ VREF ⋅ 2.5 ⋅ VREF R CL = 673.59 Ω ICLIM := 120 %⋅ IPEAK ICLMAX := 3 ⋅ VREF ⋅ ICLIM ⋅ R HYS ⋅ R CS C11 := 1 2 ⋅Π ⋅R 7⋅FS ⋅5 C11 = 9.095 × 10 R CL F R HYS ⋅ R CS In the evaluation board design a 100pF ceramic capacitor is used for C11. The DAC output requires a 1nF capacitor (C23) for high frequency noise filtering. The values for C12 and C13 are calculated in a similar manner, though they are returned to the CORE pin because that is the reference point for the current limit comparator. R CL R HYS ⋅ R CS C 12 := 1 20 C 13 := C 12 2 ⋅Π ⋅R 6⋅FS ⋅5 C 12 = 1.335 × 10 © 2009 Semtech Corp. − 11 − 10 F C 13 = 1.335 × 10 − 10 F www.semtech.com SC453 POWER MANAGEMENT Applications Information (Cont.) Step 8 — Calculate Input RMS Current In order to calculate the worst-case RMS current for the input capacitors, the efficiency at VIN_MIN and full load. is conservatively set at 80%. The actual converter efficiency depends on component selection, layout, airflow, etc. Tin := POUT := IMAX_FL⋅ VMAX_FL POUT = 23.64 W C IN_MIN := PIN := dVin := 250 mV DMAX := 0.5 1 FS IPEAK 2 C IN_MIN = 3.341 × 10 POUT 2 ⎞ Tin ⋅ ⎛⎝ DMAX − DMAX −5 ⋅ dVin F 85 % C IN := 10 μF IIN_DC := IRMS := PIN VINMIN D := VMAX_FL VINMIN ⎛ CIN_MIN ⎞ IIN_DC = 3.476 A N IN_MIN_RIPPLE := ceil ⎜ ⎝ 2 Based on the above calculations, four capacitors are needed to satisfy the input ripple voltage requirement. IRMS = 7.116 A Step 9 — OVP No calculations are necessary for Over-Voltage Protection. If VCORE is greater than +14% of the DAC (i.e., out of the power good window), the SC453 will latch off and hold the low-side driver on permanently (for each phase). Either the power or EN must be recycled to clear the latch. The latch is disabled during soft-start and VID/Deeper Sleep transitions. The latch is enabled if VCORE exceeds 2V even during VID/Deeper Sleep transitions to ensure that the processor maximum is not exceeded. The table on Page 13 is a summary of fault conditions using SC453. C I_RMS := 2 A Using an RMS current rating of 2A, typical of 10μF, 25V MLCC capacitors, the number of required capacitors is calculated as shown below. ⎛ IRMS ⎞ C I_NUM := ceil ⎜ ⎝ CI_RMS ⎠ C I_NUM = 4 The calculation indicates that four capacitors are needed to satisfy the worst-case RMS current requirement. Step 10 — Soft-Start/DAC Slew Control The soft-start cap C21 in the SC453 design serves three conditions. 1) Define the start-up ramp. 2) Define the DAC slew rate during sleep and VID transitions. During VID transitions the SS current is nominally +/- 120μA; during sleep transitions the SS current increases to +/-240μA); 3) During start-up, the SS current is normally +/- 6.5μA. Input Capacitance Calculation Using Ripple Voltage The allowable input ripple voltage seen at input capacitance is denoted dVin. For this example 250mV is used as the maximum allowable input ripple voltage. The actual ripple voltage varies with duty cycle (D). The maximum value occurs at D = 0.5. © 2009 Semtech Corp. ⎠ N IN_MIN_RIPPLE = 4 ⎡⎣(IMAX_FL) − IIN_DC⎤ ⋅ D + ⎡⎣IIN_DC ⋅ ( 1 − D)⎤ 2 C IN 21 www.semtech.com SC453 POWER MANAGEMENT Applications Information (Cont.) Three soft-start examples are based on the previous three conditions for SC453 application. 1. Start-Up ISS := 6.5 μA dtSU := 3 m s dVdacSU := VMAX_NL C SS_max_startup := ISS ⋅ dtSU dVdacSU C SS_max_startup = 1.609 × 10 −8 F 2. VID Change: ISSV := 120 μA dtV := 100 μs dVdacV := VMAX_NL − VMIN_NL C SS_max_VID := ISSV ⋅ dtV dVdacV C SS_max_VID = 4.687 × 10 −8 F 3. Sleep Entry/Exit: ISSS := 240 μA dtS := 33 μs dVdacS := VMAX_NL − VSLP C SS_max_drs := ISSS ⋅ dtS dVdacS C SS_max_drs = 1.714 × 10 −8 F Example 1 predicts the maximum capacitance allowed. In order to allow tolerance C22 = 15nF is chosen. © 2009 Semtech Corp. 22 www.semtech.com SC453 POWER MANAGEMENT Outline Drawing - TSSOP-28 DIMENSIONS A DIM D e N 2X E PIN 1 INDICATOR ccc C 1 2 3 e/2 2X N/2 TIPS B aaa SEATING PLANE D C A2 C bbb C A-B NOM .382 .173 .252 BSC .026 BSC .024 .018 (.039) 28 0° .004 .004 .008 MILLIMETERS MAX .047 .006 .042 .012 .007 .386 .177 .030 8° MIN 0.05 0.80 0.19 0.09 9.60 4.30 NOM 9.70 4.40 6.40 BSC 0.65 BSC 0.60 0.45 (1.0) 28 0° 0.10 0.10 0.20 MAX 1.20 0.15 1.05 0.30 0.20 9.80 4.50 0.75 8° A H A1 bxN MIN .002 .031 .007 .003 .378 .169 A A1 A2 b c D E1 E e L L1 N 01 aaa bbb ccc E/2 E1 INCHES D c GAGE PLANE 0.25 L (L1) SEE DETAIL A 01 DETAIL A SIDE VIEW NOTES: 1. CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES). 2. DATUMS 3. DIMENSIONS "E1" AND "D" DO NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. 4. REFERENCE JEDEC STD MO-153, VARIATION AE. -A- AND TO BE DETERMINED AT DATUM PLANE -H- -B- Marking Information TSSOP-28 yyww = Date code xxxxxxxxxxx = Semtech lot number © 2009 Semtech Corp. 23 www.semtech.com SC453 POWER MANAGEMENT Land Pattern - TSSOP-28 X DIMENSIONS G (C) Z Y DIM INCHES MILLIMETERS C (.222) (5.65) G .161 4.10 P .026 0.65 X .016 0.40 Y .061 1.55 Z .283 7.20 P NOTES: 1. THIS LAND PATTERN IS FOR REFERENCE PURPOSES ONLY. CONSULT YOUR MANUFACTURING GROUP TO ENSURE YOUR COMPANY'S MANUFACTURING GUIDELINES ARE MET. © 2009 Semtech Corp. 24 www.semtech.com SC453 POWER MANAGEMENT Outline Drawing - MLPQ-32 A D B DIM PIN 1 INDICATOR (LASER MARK) A A1 A2 b D D1 E E1 e L N aaa bbb E A2 A aaa DIMENSIONS INCHES MILLIMETERS MIN NOM MAX MIN NOM MAX .031 .039 0.80 1.00 0.05 .000 .002 0.00 - (.008) (0.20) .007 .010 .012 0.18 0.25 0.30 .193 .197 .201 4.90 5.00 5.10 .140 .146 .150 3.30 3.70 3.80 .193 .197 .201 4.90 5.00 5.10 .140 .146 .150 3.30 3.70 3.80 .020 BSC 0.50 BSC .012 .016 .020 0.30 0.40 0.50 32 32 .003 0.08 .004 0.10 SEATING PLANE C C A1 D1 LxN E/2 E1 2 1 N bxN e bbb C A B D/2 NOTES: 1. CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES). 2. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. Marking Information MLPQ-32 SC453 yyww xxxxxx xxxxxx yyww = Date code xxxxxx = Semtech lot number xxxxxx = Semtech lot number © 2009 Semtech Corp. 25 www.semtech.com SC453 POWER MANAGEMENT Land Pattern - MLPQ-32 K DIMENSIONS Z H G (C) Y DIM INCHES C (.197) MILLIMETERS (5.00) G .165 4.20 H .146 3.70 K .146 3.70 P .020 0.50 X .012 0.30 Y .031 0.80 Z .228 5.80 X P NOTES: 1. THIS LAND PATTERN IS FOR REFERENCE PURPOSES ONLY. CONSULT YOUR MANUFACTURING GROUP TO ENSURE YOUR COMPANY'S MANUFACTURING GUIDELINES ARE MET. 2. THERMAL VIAS IN THE LAND PATTERN OF THE EXPOSED PAD SHALL BE CONNECTED TO A SYSTEM GROUND PLANE. FAILURE TO DO SO MAY COMPROMISE THE THERMAL AND/OR FUNCTIONAL PERFORMANCE OF THE DEVICE. 3. SQUARE PACKAGE - DIMENSIONS APPLY IN BOTH " X " AND " Y " DIRECTIONS. Contact Information Semtech Corporation Power Management Products Division 200 Flynn Road, Camarillo, CA 93012 Phone: (805) 498-2111 Fax: (805) 498-3804 www.semtech.com © 2009 Semtech Corp. 26 www.semtech.com