SPANSION S25FL004AOLMFI001

S25FL Family (Serial Peripheral Interface)
S25FL004A
4-Megabit CMOS 3.0 Volt Flash Memory
with 50 Mhz SPI Bus Interface
ADVANCE
INFORMATION
Notice to Readers: The Advance Information status indicates that this
document contains information on one or more products under development
at Spansion LLC. The information is intended to help you evaluate this product.
Do not design in this product without contacting the factory. Spansion LLC
reserves the right to change or discontinue work on this proposed product
without notice.
Publication Number S25FL004A
Revision A
Amendment 1
Issue Date March 28, 2005
Notice On Data Sheet Designations
Spansion LLC issues data sheets with Advance Information or Preliminary designations to advise readers of product information
or intended specifications throughout the product life cycle, including development, qualification, initial production, and full production. In all cases, however, readers are encouraged to verify that they have the latest information before finalizing their design. The following descriptions of Spansion data sheet designations are presented here to highlight their presence and
definitions.
Advance Information
The Advance Information designation indicates that Spansion LLC is developing one or more specific products, but has not
committed any design to production. Information presented in a document with this designation is likely to change, and in some
cases, development on the product may discontinue. Spansion LLC therefore places the following conditions upon Advance Information content:
“This document contains information on one or more products under development at Spansion LLC. The
information is intended to help you evaluate this product. Do not design in this product without contacting the factory. Spansion LLC reserves the right to change or discontinue work on this proposed
product without notice.”
Preliminary
The Preliminary designation indicates that the product development has progressed such that a commitment to production has
taken place. This designation covers several aspects of the product life cycle, including product qualification, initial production,
and the subsequent phases in the manufacturing process that occur before full production is achieved. Changes to the technical
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“This document states the current technical specifications regarding the Spansion product(s) described
herein. The Preliminary status of this document indicates that product qualification has been completed,
and that initial production has begun. Due to the phases of the manufacturing process that require
maintaining efficiency and quality, this document may be revised by subsequent versions or modifications due to changes in technical specifications.”
Combination
Some data sheets will contain a combination of products with different designations (Advance Information, Preliminary, or Full
Production). This type of document will distinguish these products and their designations wherever necessary, typically on the
first page, the ordering information page, and pages with DC Characteristics table and AC Erase and Program table (in the table
notes). The disclaimer on the first page refers the reader to the notice on this page.
Full Production (No Designation on Document)
When a product has been in production for a period of time such that no changes or only nominal changes are expected, the
Preliminary designation is removed from the data sheet. Nominal changes may include those affecting the number of ordering
part numbers available, such as the addition or deletion of a speed option, temperature range, package type, or VIO range.
Changes may also include those needed to clarify a description or to correct a typographical error or incorrect specification.
Spansion LLC applies the following conditions to documents in this category:
“This document states the current technical specifications regarding the Spansion product(s) described
herein. Spansion LLC deems the products to have been in sufficient production volume such that subsequent versions of this document are not expected to change. However, typographical or specification
corrections, or modifications to the valid combinations offered may occur.”
Questions regarding these document designations may be directed to your local AMD or Fujitsu sales office.
S25FL Family (Serial Peripheral Interface)
S25FL004A
4-Megabit CMOS 3.0 Volt Flash Memory
with 50 Mhz SPI Bus Interface
Data Sheet
ADVANCE
INFORMATION
Distinctive Characteristics
Architectural Advantages
„
„
Single power supply operation
„
— Full voltage range: 2.7 to 3.6 V read and program
operations
Memory Architecture
„
„
„
„
„
„
— Eight sectors with 512 Kb each
Program
— Page Program (up to 256 bytes) in 1.5 ms (typical)
— Program cycles are on a page by page basis
Erase
— 1.5 s typical sector erase time
— 12 s typical bulk erase time
Cycling Endurance
— 100,000 cycles per sector typical
Data Retention
— 20 years typical
Device ID
— JEDEC standard two-byte electronic signature
— RES instruction one-byte electronic signature for
backward compatibility
Process Technology
— Manufactured on 0.20 µm MirrorBitTM process
technology
Publication Number S25FL004A_00
Revision A
Package Option
— Industry Standard Pinouts
— 8-pin SO package (208 mils)
— 8-Contact USON Package (5 x 6 mm), Pb-Free
Performance Characteristics
„
„
Speed
— 50 MHz clock rate (maximum)
Power Saving Standby Mode
— Standby Mode 50 µA (max)
— Deep Power Down Mode 1 µA (typical)
Memory Protection Features
„
Memory Protection
— W# pin works in conjunction with Status Register Bits
to protect specified memory areas
— Status Register Block Protection bits (BP2, BP1, BP0)
in status register configure parts of memory as readonly
Software Features
„
SPI Bus Compatible Serial Interface
Amendment 1
Issue Date March 28, 2005
A d v a n c e
I n f o r m a t i o n
General Description
The S25FL004A device is a 3.0 Volt (2.7 V to 3.6 V) single power supply Flash
memory device. S25FL004A consists of eight sectors, each with 512 Kb memory.
Data appears on SI input pin when inputting data into the memory and on the SO
output pin when outputting data from the memory. The devices are designed to
be programmed in-system with the standard system 3.0 Volt VCC supply.
The memory can be programmed 1 to 256 bytes at a time, using the Page Program instruction.
The memory supports Sector Erase and Bulk Erase instructions.
Each device requires only a 3.0 Volt power supply (2.7 V to 3.6 V) for both read
and write functions. Internally generated and regulated voltages are provided for
the program operations. This device does not require VPP supply.
2
S25FL Family (Serial Peripheral Interface) S25FL004A
S25FL004A_00_A1 March 28, 2005
A d v a n c e
I n f o r m a t i o n
Table of Contents
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . .5
Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . .7
Table 1. S25FL Valid Combinations Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Signal Description .....................................................................................8
SPI Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 1. Bus Master and Memory Devices on the SPI Bus........................................... 9
Figure 2. SPI Modes Supported ............................................................................................. 9
Operating Features . . . . . . . . . . . . . . . . . . . . . . . . 10
Page Programming ..................................................................................10
Sector Erase, or Bulk Erase .................................................................10
Polling During a Write, Program, or Erase Cycle ........................10
Status Register .........................................................................................10
Protection Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Table 2. Protected Area Sizes (S25FL004A). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Hold Condition Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 3. Hold Condition Activation................................................................................... 12
Memory Organization . . . . . . . . . . . . . . . . . . . . . . 13
Table 3. Sector Address Table – S25FL004A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 4. Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Write Enable (WREN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Figure 4. Write Enable (WREN) Instruction Sequence................................................ 15
Write Disable (WRDI)...........................................................................16
Figure 5. Write Disable (WRDI) Instruction Sequence................................................ 16
Read Status Register (RDSR) . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Figure 6. Read Status Register (RDSR) Instruction Sequence.................................... 17
Figure 7. Status Register Format.......................................................................................... 17
Write Status Register (WRSR) . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 8. Write Status Register (WRSR) Instruction Sequence ................................ 18
Read Data Bytes (READ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 9. Read Data Bytes (READ) Instruction Sequence .......................................... 20
Read Data Bytes at Higher Speed (FAST_READ) . . . . . . . . . . 20
Figure 10. Read Data Bytes at Higher Speed (FAST_READ) Instruction Sequence 21
Read Identification (RDID) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Figure 11. Read Identification (RDID) Instruction Sequence and Data-Out Sequence
21
3
Table 6. Read Identification (RDID) Data-Out Sequence . . . . . . . . . . . . . . . . . . .22
Page Program (PP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Figure 12. Page Program (PP) Instruction Sequence ..................................................... 23
Sector Erase (SE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Figure 13. Sector Erase (SE) Instruction Sequence ........................................................ 24
Bulk Erase (BE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
Figure 14. Bulk Erase (BE) Instruction Sequence............................................................ 25
Deep Power Down (DP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
Figure 15. Deep Power Down (DP) Instruction Sequence ......................................... 26
Release from Deep Power Down (RES) . . . . . . . . . . . . . . . . . .26
Figure 16. Release from Deep Power Down Instruction Sequence......................... 27
Release from Deep Power Down and Read Electronic Signature
(RES) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Figure 17. Release from Deep Power Down and Read Electronic Signature (RES) Instruction Sequence.................................................................................................................. 28
Power-up and Power-down . . . . . . . . . . . . . . . . . . 28
Figure 18. Power-Up Timing................................................................................................. 29
Table 7. Power-Up Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
Initial Delivery State . . . . . . . . . . . . . . . . . . . . . . .
Maximum Rating . . . . . . . . . . . . . . . . . . . . . . . . . .
Absolute Maximum Ratings . . . . . . . . . . . . . . . . .
Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . .
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . .
29
29
29
29
30
Table 8. DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
Figure 19. AC Measurements I/O Waveform .................................................................. 31
Table 9. Test Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 10. AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
Figure 20. SPI Mode 0 (0,0) Input Timing......................................................................... 33
Figure 21. SPI Mode 0 (0,0) Output Timing...................................................................... 33
Figure 22. HOLD# Timing.................................................................................................... 34
Figure 23. Write Protect Setup and Hold Timing during WRSR when SRWD=1 34
Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . . . 35
S08 wide—8-pin Plastic Small Outline 208 mils Body Width Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
USON 8L (5x6mm) No-Lead Package . . . . . . . . . . . . . . . . . . .36
Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . . 37
S25FL Family (Serial Peripheral Interface) S25FL004A
S25FL004A_00_A1 March 28, 2005
A d v a n c e
I n f o r m a t i o n
Block Diagram
SRAM
PS
X
D
E
C
Array - L
Array - R
Logic
RD
DATA PATH
4
S25FL Family (Serial Peripheral Interface) S25FL004A
HOLD#
VCC
GND
SO
SI
SCK
CS#
IO
S25FL004A_00_A1 March 28, 2005
A d v a n c e
I n f o r m a t i o n
Connection Diagrams
8-pin Plastic Small Outline Package (SO)
8L USON (5x6mm2) Package
CS#
1
SO
2
W#
3
GND
4
WSON
8
Vcc
7
HOLD#
6
SCK
5
SI
Input/Output Descriptions
SCK
SI
SO
CS#
W#
HOLD#
VCC
GND
March 28, 2005 S25FL004A_00_A1
=
=
=
=
=
=
=
=
Serial Clock Input
Serial Data Input
Serial Data Output
Chip Select Input
Write Protect Input
Hold Input
Supply Voltage Input
Ground Input
S25FL Family (Serial Peripheral Interface) S25FL004A
5
A d v a n c e
I n f o r m a t i o n
Logic Symbol
VCC
SO
SI
SCK
CS#
W#
HOLD#
GND
6
S25FL Family (Serial Peripheral Interface) S25FL004A
S25FL004A_00_A1 March 28, 2005
A d v a n c e
I n f o r m a t i o n
Ordering Information
The ordering part number is formed by the following valid combinations:
S25FL
004
A
0L
M
A
1
00
1
PACKING TYPE
0 = Tray (Note 2)
1 = Tube (Standard; See Note 1)
3 = 13” Tape and Reel (Note 2)
MODEL NUMBER (Additional Ordering
Options)
00 = No additional ordering options
TEMPERATURE RANGE
I
= Industrial (-40°C to + 85°C)
PACKAGE MATERIALS
A = Standard
F = Lead (Pb)-free (Note 2)
PACKAGE TYPE
M=
N=
8-Pin Plastic Small Outline Package
8-Contact USON Package
SPEED
0L = 50 MHz
DEVICE TECHNOLOGY
A = 0.20 µm MirrorBit™ Process Technology
DENSITY
004 = 4 Mb
DEVICE FAMILY
S25FL
SpansionTM Memory 3.0 Volt-only, Serial Peripheral Interface (SPI) Flash Memory
Table 1. S25FL Valid Combinations Table
S25FL Valid Combinations
Base
Ordering Part
Number
Speed
Option
Package &
Temperature
S25FL004A
0L
NAI, NFI
Package Marking
(See Note 3)
Model
Packing
Number
Type
MAI, MFI
00
(Note 2)
0, 1, 3
(Note 1)
FL004A + (Temp) + (Note 4)
Notes:
1. Type 1 is standard. Specify other options as required.
2. Contact your local sales office for availability.
3. Package marking omits leading S25 and speed, package, and leading digit of model number form ordering part number.
4. A for standard package (non-Pb-free); F for Pb-free package.
Valid Combinations
Valid Combinations list configurations planned to be supported in volume for this device.
March 28, 2005 S25FL004A_00_A1
S25FL Family (Serial Peripheral Interface) S25FL004A
7
A d v a n c e
I n f o r m a t i o n
Signal Description
Signal Data Output (SO): This output signal is used to transfer data serially out
from the device. Data is shifted out on the falling edge of Serial Clock (SCK).
Serial Data Input (SI): This input signal is used to transfer data serially into
the device. It receives instructions, addresses, and the data to be programmed.
Values are latched on the rising edge of Serial Clock (SCK).
Serial Clock (SCK): This input signal provides the serial interface timing. Instructions, addresses, and data present at the Serial Data input (SI) are latched
on the rising edge of Serial Clock (SCK). Data on Serial Data Output (SO) changes
after the falling edge of Serial Clock (SCK).
Chip Select (CS#): When this input signal is High, the device is deselected and
Serial Data Output (SO) is at high impedance. Unless an internal Program, Erase
or Write Status Register cycle is in progress, the device is in Standby mode. Driving Chip Select (CS#) Low enables the device, placing it in the active power
mode.
After Power-up, a falling edge on Chip Select (CS#) is required prior to the start
of any instruction.
Hold (HOLD#): The Hold (HOLD#) signal is used to pause any serial communications with the device without deselecting the device.
During the Hold instruction, the Serial Data Output (SO) is high impedance, and
Serial Data Input (SI) and Serial Clock (SCK) are Don’t Care.
To start the Hold condition, the device must be selected, with Chip Select (CS#)
driven Low.
Write Protect (W#): The main purpose of this input signal is to freeze the area
memory size that is protected against program or erase instructions (as specified
by the values in the Status Register BP1 and BP0 bits).
SPI Modes
These devices can be driven by a microcontroller with its SPI peripheral running
in either of two modes:
„ CPOL = 0, CPHA = 0
„ CPOL = 1, CPHA = 1
For these two modes, input data is latched in on the rising edge of Serial Clock
(SCK), and output data is available from the falling edge of Serial Clock (SCK).
The difference between the two modes, as shown in Figure 1, on page 9, is the
clock polarity when the bus master is in Standby and not transferring data:
„ SCK remains at 0 for (CPOL = 0, CPHA = 0)
„ SCK remains at 1 for (CPOL = 1, CPHA = 1)
8
S25FL Family (Serial Peripheral Interface) S25FL004A
S25FL004A_00_A1 March 28, 2005
A d v a n c e
I n f o r m a t i o n
SO
SPI Interface with
(CPOL, CPHA) =
(0, 0) or (1, 1)
SI
SCK
SCK SO SI
SCK SO SI
SCK SO SI
Bus Master
SPI Memory
Device
CS3
CS2
SPI Memory
Device
SPI Memory
Device
CS1
CS#
W# HOLD#
CS#
W# HOLD#
CS#
W# HOLD#
Note: The Write Protect (W#) and Hold (HOLD#) signals should be driven, High or Low as appropriate.
Figure 1. Bus Master and Memory Devices on the SPI Bus
CS#
CPOL
CPHA
0
0
SCK
1
1
SCK
SI
MSB
SO
MSB
Figure 2.
March 28, 2005 S25FL004A_00_A1
SPI Modes Supported
S25FL Family (Serial Peripheral Interface) S25FL004A
9
A d v a n c e
I n f o r m a t i o n
Operating Features
All device data into and out, is shifted in 8-bit chunks.
Page Programming
To program one data byte, two instructions are required: Write Enable (WREN),
which is one byte, and a Page Program (PP) sequence, which consists of four
bytes plus data. This is followed by the internal Program cycle. To spread this
overhead, the Page Program (PP) instruction allows up to 256 bytes to be programmed at a time (changing bits from 1 to 0), provided that they lie in
consecutive addresses on the same page of memory.
Sector Erase, or Bulk Erase
The Page Program (PP) instruction allows bits to be programmed from 1 to 0. Before this can be applied, the memory bytes need to be first erased to all 1’s (FFh)
before any programming. This can be achieved in two ways:
„ A sector at a time using the Sector Erase (SE) instruction
„ The entire memory, using the Bulk Erase (BE) instruction
Polling During a Write, Program, or Erase Cycle
A further improvement in the time to Write Status Register (WRSR), Program (PP)
or Erase (SE or BE) can be achieved by not waiting for the worst-case delay. The
Write in Progress (WIP) bit is provided in the Status Register so that the application program can monitor its value, polling it to establish when the previous Write
cycle, Program cycle, or Erase cycle is complete.
Active Power and Standby Power Modes
When Chip Select (CS#) is Low, the device is enabled, and in the Active Power
mode. When Chip Select (CS#) is High, the device is disabled, but could remain
in the Active Power mode until all internal cycles have completed (Program,
Erase, Write Status Register). The device then goes into the Standby Power
mode. The device consumption drops to ISB. This can be used as an extra Deep
Power Down on mechanism, when the device is not in active use, to protect the
device from inadvertent Write, Program, or Erase instructions.
Status Register
The Status Register contains a number of status and control bits, as shown in
Figure 7, on page 17 that can be read or set (as appropriate) by specific
instructions
„ WIP bit: The Write In Progress (WIP) bit indicates whether the memory is
busy with a Write Status Register, Program or Erase cycle.
„ WEL bit: The Write Enable Latch (WEL) bit indicates the internal Write Enable
Latch status.
„ BP2, BP1, BP0 bits: The Block Protect (BP2, BP1, BP0) bits are non-volatile.
They define the area size to be software protected against Program and Erase
instructions.
„ SRWD bit: The Status Register Write Disable (SRWD) bit is operated in conjunction with the Write Protect (W#) signal. The Status Register Write Disable
(SRWD) bit and Write Protect (W#) signal allow the device to be put in the
Hardware Protected mode. In this mode, the Status Register’s non-volatile
bits (SRWD, BP2, BP1, BP0) become read-only bits.
10
S25FL Family (Serial Peripheral Interface) S25FL004A
S25FL004A_00_A1 March 28, 2005
A d v a n c e
I n f o r m a t i o n
Protection Modes
The SPI memory device boasts the following data protection mechanisms:
„ All instructions that modify data must be preceded by a Write Enable (WREN)
instruction to set the Write Enable Latch (WEL) bit. This bit is returned to its
reset state by the following events:
— Power-up
— Write Disable (WRDI) instruction completion
— Write Status Register (WRSR) instruction completion
— Page Program (PP) instruction completion
— Sector Erase (SE) instruction completion
— Bulk Erase (BE) instruction completion
„ The Block Protect (BP2, BP1, BP0) bits allow part of the memory to be configured as read-only. This is the Software Protected Mode (SPM).
„ The Write Protect (W#) signal works in cooperation with the Status Register
Write Disable (SRWD) bit to enable write-protection. This is the Hardware
Protected Mode (HPM).
„ Program, Erase and Write Status Register instructions are checked to verify
that they consist of a number of clock pulses that is a multiple of eight, before
they are accepted for execution.
Table 2. Protected Area Sizes (S25FL004A).
Protected
Memory
Area
(Top Level)
Status Register Content
Memory Content
BP2 Bit
BP1 Bit
BP0
Protected Area
Unprotected Area
0
0
0
0
none
00000-7FFFF
1/8
0
0
1
70000-7FFFF
00000-6FFFF
1/4
0
1
0
60000-7FFFF
00000-5FFFF
1/2
0
1
1
40000-7FFFF
00000-3FFFF
All
1
0
0
00000-7FFFF
none
All
1
0
1
00000-7FFFF
none
All
1
1
0
00000-7FFFF
none
All
1
1
1
00000-7FFFF
none
Hold Condition Modes
The Hold (HOLD#) signal is used to pause any serial communications with the
device without resetting the clocking sequence. Hold (HOLD#) signal gates the
clock input to the device. However, taking this signal Low does not terminate any
Write Status Register, Program or Erase Cycle that is currently in progress.
To enter the Hold condition, the device must be selected, with Chip Select (CS#)
Low. The Hold condition starts on the falling edge of the Hold (HOLD#) signal,
provided that this coincides with Serial Clock (SCK) being Low (as shown in
Figure 3, on page 12).
March 28, 2005 S25FL004A_00_A1
S25FL Family (Serial Peripheral Interface) S25FL004A
11
A d v a n c e
I n f o r m a t i o n
The Hold condition ends on the rising edge of the Hold (HOLD#) signal, provided
that this coincides with Serial Clock (SCK) being Low.
If the falling edge does not coincide with Serial Clock (SCK) being Low, the Hold
condition starts after Serial Clock (SCK) next goes Low. Similarly, if the rising
edge does not coincide with Serial Clock (SCK) being Low, the Hold condition ends
after Serial Clock (SCK) next goes Low (Figure 3). During the Hold condition, the
Serial Data Output (SO) is high impedance, and Serial Data Input (SI) and Serial
Clock (SCK) are Don’t Care.
Normally, the device remains selected, with Chip Select (CS#) driven Low, for the
entire duration of the Hold condition. This ensures that the internal logic state remains unchanged from the moment of entering the Hold condition.
If Chip Select (CS#) goes High while the device is in the Hold condition, this has
the effect of resetting the device’s internal logic. To restart communication with
the device, it is necessary to drive Hold (HOLD#) High, and then to drive Chip
Select (CS#) Low. This prevents the device from going back to the Hold condition.
SCK
HOLD#
Hold
Condition
(standard use)
Hold
Condition
(non-standard use)
Figure 3. Hold Condition Activation
12
S25FL Family (Serial Peripheral Interface) S25FL004A
S25FL004A_00_A1 March 28, 2005
A d v a n c e
I n f o r m a t i o n
Memory Organization
The memory is organized as:
„ S25FL004A: Eight sectors of 512 Kbit each.
„ Each page can be individually programmed
(bits are programmed from 1 to 0).
„ The device is Sector or Bulk erasable
(bits are erased from 0 to 1).
Table 3. Sector Address Table – S25FL004A
Sector
March 28, 2005 S25FL004A_00_A1
Address Range
SA7
70000h
7FFFFh
SA6
60000h
6FFFFh
SA5
50000h
5FFFFh
SA4
40000h
4FFFFh
SA3
30000h
3FFFFh
SA2
20000h
2FFFFh
SA1
10000h
1FFFFh
SA0
00000h
0FFFFh
S25FL Family (Serial Peripheral Interface) S25FL004A
13
A d v a n c e
I n f o r m a t i o n
Instructions
All instructions, addresses, and data are shifted in and out of the device, starting
with the most significant bit. Serial Data Input (SI) is sampled on the first rising
edge of Serial Clock (SCK) after Chip Select (CS#) is driven Low. Then, the onebyte instruction code must be shifted in to the device, most significant bit first,
on Serial Data Input (SI), each bit being latched on the rising edges of Serial
Clock (SCK). The instruction set is listed in Table 4, on page 15.
Every instruction sequence starts with a one-byte instruction code. Depending on
the instruction, this might be followed by address bytes, or by data bytes, or by
both or none. Chip Select (CS#) must be driven High after the last bit of the instruction sequence is shifted in.
In the case of a Read Data Bytes (READ), Read Status Register (RDSR), Read
Data Bytes at higher speed (FAST_READ) and Read Identification (RDID) instructions, the shifted-in instruction sequence is followed by a data-out sequence.
Chip Select (CS#) can be driven High after any bit of the data-out sequence is
being shifted out to terminate the transaction.
In the case of a Page Program (PP), Sector Erase (SE), Bulk Erase (BE), Write
Status Register (WRSR), Write Enable (WREN), or Write Disable (WRDI) instruction, Chip Select (CS#) must be driven High exactly at a byte boundary,
otherwise the instruction is rejected, and is not executed. That is, Chip Select
(CS#) must driven High when the number of clock pulses after Chip Select (CS#)
being driven Low is an exact multiple of eight.
All attempts to access the memory array during a Write Status Register cycle,
Program cycle or Erase cycle are ignored, and the internal Write Status Register
cycle, Program cycle or Erase cycle continues unaffected
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S25FL Family (Serial Peripheral Interface) S25FL004A
S25FL004A_00_A1 March 28, 2005
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Table 4.
Instruction
Instruction Set
One-Byte Instruction
Code
Description
Address
Bytes
Dummy
Byte
Data Bytes
Status Register Operations
WREN
Write Enable
06H (0000 0110)
0
0
0
WRDI
Write Disable
04H (0000 0100)
0
0
0
RDSR
Read from Status Register
05H (0000 0101)
0
0
1 to Infinity
WRSR
Write to Status Register
01H (0000 0001)
0
0
1
Read Operations
READ
Read Data Bytes
03H (0000 0011)
3
0
1 to Infinity
FAST_READ
Read Data Bytes at Higher Speed
0BH (0000 1011)
3
1
1 to Infinity
RDID
Read Identification
9FH (1001 1111)
0
0
1 to 3
Erase Operations
SE
Sector Erase
D8H (1101 1000)
3
0
0
BE
Bulk (Chip) Erase
C7H (1100 0111)
0
0
0
3
0
1 to 256
Program Operations
PP
Page Program
02H (0000 0010)
Deep Power Down Savings Mode Operations
DP
RES
Deep Power Down
B9H (1011 1001)
0
0
0
Release from Deep Power Down
ABH (1010 1011)
0
0
0
Release from Deep Power Down and
Read Electronic Signature
ABH (1010 1011)
0
3
1 to Infinity
Write Enable (WREN)
The Write Enable (WREN) instruction (Figure 4) sets the Write Enable Latch
(WEL) bit. The Write Enable Latch (WEL) bit must be set prior to every Page Program (PP), Erase (SE or BE) and Write Status Register (WRSR) instruction. The
Write Enable (WREN) instruction is entered by driving Chip Select (CS#) Low,
sending the instruction code, and then driving Chip Select (CS#) High.
CS#
0 1
2 3 4 5 6 7
SCK
Instruction
SI
High Impedance
SO
Figure 4. Write Enable (WREN) Instruction Sequence
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Write Disable (WRDI)
The Write Disable (WRDI) instruction (Figure 5) resets the Write Enable Latch
(WEL) bit. The Write Disable (WRDI) instruction is entered by driving Chip Select
(CS#) Low, sending the instruction code, and then driving Chip Select (CS#)
High.
The Write Enable Latch (WEL) bit is reset under the following conditions:
„ Power-up
„ Write Disable (WRDI) instruction completion
„ Write Status Register (WRSR) instruction completion
„ Page Program (PP) instruction completion
„ Sector Erase (SE) instruction completion
„ Bulk Erase (BE) instruction completion.
CS#
0 1 2 3 4 5 6 7
SCK
Instruction
SI
High Impedance
SO
Figure 5.
16
Write Disable (WRDI) Instruction Sequence
S25FL Family (Serial Peripheral Interface) S25FL004A
S25FL004A_00_A1 March 28, 2005
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Read Status Register (RDSR)
The Read Status Register (RDSR) instruction allows the Status Register to be
read. The Status Register may be read at any time, even while a Program, Erase,
or Write Status Register cycle is in progress. When one of these cycles is in
progress, it is recommended to check the Write In Progress (WIP) bit before
sending a new instruction to the device. It is also possible to read the Status Register continuously, as shown in Figure 6.
CS#
0 1
2 3 4 5 6 7 8 9 10 11 12 13 14 15
SCK
Instruction
SI
Status Register Out
High Impedance
SO
Status Register Out
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7
MSB
MSB
Figure 6. Read Status Register (RDSR) Instruction Sequence
b7
SRWD
b0
0
0
BP2
BP1
BP0
WEL
WIP
Status Register Write Disable
Block Protect Bits
Write Enable Latch Bit
Write In Progress Bit
Figure 7. Status Register Format
The status and control bits of the Status Register are as follows:
SRWD bit: The Status Register Write Disable (SRWD) bit is operated in conjunction with the Write Protect (W#) signal. The Status Register Write Disable
(SRWD) bit and Write Protect (W#) signal allow the device to be put in the Hardware Protected mode (when the Status Register Write Disable (SRWD) bit is set
to 1, and Write Protect (W#) is driven Low). In this mode, the non-volatile bits
of the Status Register (SRWD, BP2, BP1, BP0) become read-only bits and the
Write Status Register (WRSR) instruction is no longer accepted for execution.
BP2, BP1, BP0 bits: The Block Protect (BP2, BP1, BP0) bits are non-volatile.
They define the area size to be software protected against Program and Erase instructions. These bits are written with the Write Status Register (WRSR)
instruction. When one or both of the Block Protect (BP2, BP1, BP0) bits is set to
1, the relevant memory area (as defined in Table 2, on page 11) becomes protected against Page Program (PP), and Sector Erase (SE) instructions. The Block
Protect (BP2, BP1, BP0) bits can be written provided that the Hardware Protected
mode has not been set. The Bulk Erase (BE) instruction is executed if, and only
if, all Block Protect (BP2, BP1, BP0) bits are 0.
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WEL bit: The Write Enable Latch (WEL) bit indicates the internal Write Enable
Latch status. When set to 1, the internal Write Enable Latch is set; when set to
0, the internal Write Enable Latch is reset and no Write Status Register, Program
or Erase instruction is accepted.
WIP bit: The Write In Progress (WIP) bit indicates whether the memory is busy
with a Write Status Register, Program or Erase cycle. This bit is a read only bit
and is read by executing a RDSR instruction. If this bit is 1, such a cycle is in
progress, if it is 0, no such cycle is in progress.
Write Status Register (WRSR)
The Write Status Register (WRSR) instruction allows new values to be written to
the Status Register. Before it can be accepted, a Write Enable (WREN) instruction
must previously have been executed. After the Write Enable (WREN) instruction
is decoded and executed, the device sets the Write Enable Latch (WEL).
The Write Status Register (WRSR) instruction is entered by driving Chip Select
(CS#) Low, followed by the instruction code and the data byte on Serial Data
Input (SI).
The instruction sequence is shown in Figure 8.
The Write Status Register (WRSR) instruction has no effect on bits b6, b5, b1 and
b0 of the Status Register. Bits b6 and b5 are always read as 0.
Chip Select (CS#) must be driven High after the eighth bit of the data byte is
latched in. If not, the Write Status Register (WRSR) instruction is not executed.
As soon as Chip Select (CS#) is driven High, the self-timed Write Status Register
cycle (whose duration is tW) is initiated. While the Write Status Register cycle is
in progress, the Status Register may still be read to check the Write In Progress
(WIP) bit value. The Write In Progress (WIP) bit is 1 during the self-timed Write
Status Register cycle, and is 0 when it is completed. At some unspecified time
before the cycle is completed, the Write Enable Latch (WEL) is reset.
The WRSR instruction enables the user to select one of seven levels of protection.
The S25FL004A is divided into eight array segments. The top eighth, quarter, half,
or all of the memory segments can be protected (as defined in Table 1, on
page 7). The data within a selected segment is therefore read-only. The Write
Status Register (WRSR) instruction also allows the user to set or reset the Status
Register Write Disable (SRWD) bit in accordance with the Write Protect (W#) signal. The Status Register Write Disable (SRWD) bit and Write Protect (W#) signal
allow the device to be put in the Hardware Protected Mode (HPM). The Write Status Register (WRSR) instruction cannot be executed once the Hardware Protected
Mode (HPM) is entered.
CS#
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
SCK
Status
Register In
Instruction
SI
High Impedance
MSB
SO
Figure 8. Write Status Register (WRSR) Instruction Sequence
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S25FL Family (Serial Peripheral Interface) S25FL004A
S25FL004A_00_A1 March 28, 2005
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Table 5.
W# Signal
SRWD Bit
1
1
1
0
0
0
0
1
Protection Modes
Status Register Write
Protection
Mode
Protected Area
(See Note)
Unprotected Area
(See Note)
Software
Protected
(SPM)
Status Register is Writable (if the
Protected against Page
WREN instruction sets the WEL bit)
Program and Erase
The values in the SRWD, BP2, BP1
(SE, BE)
and BP0 bits can be changed
Ready to accept Page
Program and Sector
Erase Instructions
Hardware
Protected
(HPM)
Status Register is Hardware write
Protected against Page
protected
Program and Erase
The values in the SRWD, BP2, BP1
(SE, BE)
and BP0 bits cannot be changed
Ready to accept Page
Program and Sector
Erase Instructions
Note: As defined by the values in the Block Protect (BP2, BP1, BP0) bits of the Status Register, as shown in Table 2, on page 11.
The device protection features are summarized in Table 5.
When the Status Register Write Disable (SRWD) bit is 0 (its initial delivery state),
it is possible to write to the Status Register provided that the Write Enable Latch
(WEL) bit has previously been set by a Write Enable (WREN) instruction, regardless of whether Write Protect (W#) is driven High or Low.
When the Status Register Write Disable (SRWD) bit is set to 1, two cases need to
be considered, depending on the state of Write Protect (W#):
„ If Write Protect (W#) is driven High, it is possible to write to the Status Register provided that the Write Enable Latch (WEL) bit has previously been set
by a Write Enable (WREN) instruction.
„ If Write Protect (W#) is driven Low, it is not possible to write to the Status
Register even if the Write Enable Latch (WEL) bit has previously been set by
a Write Enable (WREN) instruction. (Attempts to write to the Status Register
are rejected, and are not accepted for execution). As a consequence, all the
data bytes in the memory area that are software protected (SPM) by the
Block Protect (BP1, BP0) bits of the Status Register, are also hardware protected against data modification.
Regardless of the two events order, the Hardware Protected Mode (HPM) can be
entered:
„ By setting the Status Register Write Disable (SRWD) bit after driving Write
Protect (W#) Low
or
„ By driving Write Protect (W#) Low after setting the Status Register Write Disable (SRWD) bit.
The only way to exit the Hardware Protected Mode (HPM) once entered is to pull
Write Protect (W#) High.
If Write Protect (W#) is permanently tied High, the Hardware Protected Mode
(HPM) can never be activated, and only the Software Protected Mode (SPM),
using the Status Register’s Block Protect (BP2, BP1, BP0) bits, can be used.
Read Data Bytes (READ)
The READ instruction reads the memory at the specified SCK frequency (fSCK)
with a maximum speed of 33 MHz.
March 28, 2005 S25FL004A_00_A1
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The device is first selected by driving Chip Select (CS#) Low. The instruction code
for the Read Data Bytes (READ) instruction is followed by a 3-byte address (A23A0), each bit being latched-in during the rising edge of Serial Clock (SCK). Then
the memory contents, at that address, are shifted out on Serial Data Output
(SO), each bit being shifted out, at a frequency fSCK, during the falling edge of
Serial Clock (SCK).
The instruction sequence is shown in Figure 9. The first byte addressed can be at
any location. The address automatically increments to the next higher address
after each byte of data is shifted out. The whole memory can, therefore, be read
with a single Read Data Bytes (READ) instruction. When the highest address is
reached, the address counter rolls over to 00000h, allowing the read sequence to
be continued indefinitely.
The Read Data Bytes (READ) instruction is terminated by driving Chip Select
(CS#) High. Chip Select (CS#) can be driven High at any time during data output.
Any Read Data Bytes (READ) instruction, while a Program, Erase, or Write cycle
is in progress, is rejected without having any effect on the cycle that is in
progress.
CS#
0 1 2 3 4 5 6 7 8 9 10
28 2 30 31 3 33 3 35 36 3 3 3
SCK
Instruction
24-Bit Address
23 22 21
SI
3 2 1 0
MSB
Data Out 1
Data Out 2
High Impedance
SO
7 6 5 4 3 2 1 0 7
MSB
Figure 9. Read Data Bytes (READ) Instruction Sequence
Read Data Bytes at Higher Speed (FAST_READ)
The FAST_READ instruction reads the memory at the specified SCK frequency
(fSCK) with a maximum speed of 50 MHz. The device is first selected by driving
Chip Select (CS#) Low. The instruction code for (FAST_READ) instruction is followed by a 3-byte address (A23-A0) and a dummy byte, each bit being latchedin during the rising edge of Serial Clock (SCK). Then the memory contents, at that
address, are shifted out on Serial Data Output (SO), each bit being shifted out,
at a maximum frequency FSCK, during the falling edge of Serial Clock (SCK).
The instruction sequence is shown in Figure 10, on page 21. The first byte addressed can be at any location. The address automatically increments to the next
higher address after each byte of data is shifted out. The whole memory can,
therefore, be read with a single (FAST_READ) instruction. When the highest address is reached, the address counter rolls over to 00000h, allowing the read
sequence to be continued indefinitely.
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S25FL Family (Serial Peripheral Interface) S25FL004A
S25FL004A_00_A1 March 28, 2005
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The (FAST_READ) instruction is terminated by driving Chip Select (CS#) High.
Chip Select (CS#) can be driven High at any time during data output. Any
(FAST_READ) instruction, while an Erase, Program or Write cycle is in progress,
is rejected without having any effects on the cycle that is in progress.
CS#
0
1
2
3
4
5
6
8
7
9
10
28 29 30 31 32 33
34 35 36 37 38 39 40 41 42 43 44 45 46
47
SCK
24-Bit
Address
Instruction
23 22 21
SI
3
Dummy Byte
2
1
0
7
6
5
4
3
2
1
0
DATA OUT 1
High Impedance
SO
6
7
5
4
3
2
DATA OUT 2
1
0
MSB
Figure 10.
7
MSB
Read Data Bytes at Higher Speed (FAST_READ) Instruction Sequence
Read Identification (RDID)
The Read Identification (RDID) instruction allows the 8-bit manufacturer identification to be read, followed by two bytes of the device identification.
The manufacturer identification byte is assigned by JEDEC, and has a value of 01h
for Spansion™ products. The device identification is assigned by the device manufacturer, and indicates the memory type in the first byte (02h), and the device’s
memory capacity in the second byte (12h).
Any Read Identification (RDID) instruction executed while an Erase, Program, or
Write Status Register cycle is in progress is not decoded, and has no effect on the
cycle that is in progress.
The device is first selected by driving Chip Select (CS#) Low. Then, the 8-bit instruction code for the instruction is shifted in, with each bit being latched in on
SI during the rising edge of SCK. This is followed by the 24-bit device identification, stored in the memory, being shifted out on Serial Data Output (SO), with
each bit being shifted out during the falling edge of Serial Clock (SCK).
The instruction sequence is shown in Figure 11.
CS#
SCK
0
1
2
3
4
5
6
7
9
8
10 11 12 13 14 15 16 17 18
28 29 30 31
Instruction
SI
Manufacturer Identification
SO
High Impedance
Device Identification
15 14 13
3
2
1
0
MSB
Figure 11. Read Identification (RDID) Instruction Sequence and Data-Out Sequence
Driving CS# high after the Device Identification is read at least once, terminates
the READ_ID instruction. The Read Identification (RDID) instruction can also be
terminated by driving CS# High at any time during data output.
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When Chip Select (CS#) is driven High, the device is put in the Stand-by Power
mode. Once in the Stand-by Power mode, the device waits to be selected, so that
it can receive, decode and execute instructions.
Table 6. Read Identification (RDID) Data-Out Sequence
Manufacturer Identification
01h
Device Identification
Memory Type
Memory Capacity
02h
12h
Page Program (PP)
The Page Program (PP) instruction allows bytes to be programmed in the memory
(changing bits from 1 to 0). Before it can be accepted, a Write Enable (WREN)
instruction must previously have been executed. After the Write Enable (WREN)
instruction is decoded, the device sets the Write Enable Latch (WEL).
The Page Program (PP) instruction is entered by driving Chip Select (CS#) Low,
followed by the instruction code, three address bytes and at least one data byte
on Serial Data Input (SI). Chip Select (CS#) must be driven Low for the entire
sequence duration.
The instruction sequence is shown in Figure 12, on page 23.
If more than 256 bytes are sent to the device, the addressing wraps to the beginning of the same page, previously latched data are discarded and the last 256
data bytes are guaranteed to be programmed correctly within the same page. If
fewer than 256 Data bytes are sent to device, they are correctly programmed at
the requested addresses without having any effects on the other bytes of the
same page.
Chip Select (CS#) must be driven High after the eighth bit of the last data byte
is latched in, otherwise the Page Program (PP) instruction is not executed. As
soon as Chip Select (CS#) is driven High, the self-timed Page Program cycle
(whose duration is tPP) is initiated. While the Page Program cycle is in progress,
the Status Register may be read to check the Write In Progress (WIP) bit value.
The Write In Progress (WIP) bit is 1 during the self-timed Page Program cycle,
and is 0 when it is completed. At some unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is reset.
A Page Program (PP) instruction applied to a page that is protected by the Block
Protect (BP2, BP1, BP0) bits (see Table 2, on page 11) is not executed.
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S25FL Family (Serial Peripheral Interface) S25FL004A
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CS#
0 1 2 3 4 5 6 7 8 9 10
28 29 30 31 32 33 34 35 36 37 38 39
SCK
24-Bit Address
Instruction
3
23 22 21
2
1
0
MSB
7
6
5 4
3
2
1
0
CS#
40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55
2072
MSB
2073
2074
2075
2076
2077
2078
2079
SI
Data Byte 1
SCK
Data Byte 2
7
SI
6
5
MSB
4
3
2
Data Byte 3
1 0
7
6
MSB
5
4
3
2
Data Byte 256
1 0
7
6
5
4
3
2
1
0
MSB
Figure 12. Page Program (PP) Instruction Sequence
Sector Erase (SE)
The Sector Erase (SE) instruction sets to 1 (FFh) all bits inside the chosen sector.
Before it can be accepted, a Write Enable (WREN) instruction must previously
have been executed. After the Write Enable (WREN) instruction is decoded, the
device sets the Write Enable Latch (WEL).
The Sector Erase (SE) instruction is entered by driving Chip Select (CS#) Low,
followed by the instruction code, and three address bytes on Serial Data Input
(SI). Any address inside the Sector (see Table 2, on page 11) is a valid address
for the Sector Erase (SE) instruction. Chip Select (CS#) must be driven Low for
the entire sequence duration.
The instruction sequence is shown in Figure 13, on page 24.
Chip Select (CS#) must be driven High after the eighth bit of the last address byte
is latched in, otherwise the Sector Erase (SE) instruction is not executed. As soon
as Chip Select (CS#) is driven High, the self-timed Sector Erase cycle (whose duration is tSE) is initiated. While the Sector Erase cycle is in progress, the Status
Register may be read to check the Write In Progress (WIP) bit value. The Write
In Progress (WIP) bit is 1 during the self-timed Sector Erase cycle, and is 0 when
it is completed. At some unspecified time before the cycle is completed, the Write
Enable Latch (WEL) bit is reset.
A Sector Erase (SE) instruction applied to any memory area that is protected by
the Block Protect (BP2, BP1, BP0) bits (see Table 2, on page 11) is not executed.
March 28, 2005 S25FL004A_00_A1
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CS#
0
1
2
3
4
5
6
7
8
9
10
28
29
30
31
1
0
SCK
Instruction
24 Bit Address
23 22
SI
21
3
2
MSB
Figure 13.
Sector Erase (SE) Instruction Sequence
Bulk Erase (BE)
The Bulk Erase (BE) instruction sets to 1 (FFh) all bits inside the entire memory.
Before it can be accepted, a Write Enable (WREN) instruction must previously
have been executed. After the Write Enable (WREN) instruction is decoded, the
device sets the Write Enable Latch (WEL).
The Bulk Erase (BE) instruction is entered by driving Chip Select (CS#) Low, followed by the instruction code, on Serial Data Input (SI). No address is required
for the Bulk Erase (BE) instruction. Chip Select (CS#) must be driven Low for the
entire sequence duration.
The instruction sequence is shown in Figure 14, on page 25.
Chip Select (CS#) must be driven High after the eighth bit of the last address byte
is latched in, otherwise the Bulk Erase (BE) instruction is not executed.
As soon as Chip Select (CS#) is driven High, the self-timed Bulk Erase cycle
(whose duration is tBE) is initiated. While the Bulk Erase cycle is in progress, the
Status Register may be read to check the value of the Write In Progress (WIP)
bit. The Write In Progress (WIP) bit is 1 during the self-timed Bulk Erase cycle,
and is 0 when it is completed. At some unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is reset.
A Bulk Erase (BE) instruction is executed only if all the Block Protect (BP2, BP1,
BP0) bits (see Table 2, on page 11) are set to 0. The Bulk Erase (BE) instruction
is ignored if one or more sectors are protected.
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S25FL Family (Serial Peripheral Interface) S25FL004A
S25FL004A_00_A1 March 28, 2005
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CS#
0
1
2
3
4
5
6
7
SCK
Instruction
SI
Figure 14.
Bulk Erase (BE) Instruction Sequence
Deep Power Down (DP)
The Deep Power Down (DP) instruction puts the device in the lowest current
mode of 1 µA typical.
It is recommended that the standard Standby mode be used for the lowest power
current draw, as well as the Deep Power Down (DP) as an extra software protection mechanism when this device is not in active use. In this mode, the device
ignores all Write, Program, and Erase instructions. Chip Select (CS#) must be
driven Low for the entire sequence duration.
The Deep Power Down (DP) instruction is entered by driving Chip Select (CS#)
Low, followed by the instruction code on Serial Data Input (SI). Chip Select (CS#)
must be driven Low for the entire sequence duration.
The instruction sequence is shown in Figure 15, on page 26.
Driving Chip Select (CS#) High after the eighth bit of the instruction code is
latched, places the device in Deep Power Down mode. The Deep Power Down
mode can only be entered by executing the Deep Power Down (DP) instruction to
reduce the standby current (from ISB to IDP as specified in Table 8, on page 30).
As soon as Chip Select (CS#) is driven high, it requires a delay of tDP currently in
progress before Deep Power Down mode is entered.
Once the device enters the Deep Power Down mode, all instructions are ignored
except the Release from Deep Power Down (RES) and Read Electronic Signature.
This releases the device from the Deep Power Down mode. The Release from
Deep Power Down and Read Electronic Signature (RES) instruction also allows the
device’s Electronic Signature to be output on Serial Data Output (SO).
The Deep Power Down mode automatically stops at Power-down, and the device
always powers up in the Standby mode.
Any Deep Power Down (DP) instruction, while an Erase, Program, or WRSR cycle
is in progress, is rejected without having any effect on the cycle in progress.
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CS#
tDP
0
1
2
3
4
5
6
7
SCK
Instruction
SI
Standby Mode
Deep Power Down Mode
Figure 15. Deep Power Down (DP) Instruction Sequence
Release from Deep Power Down (RES)
The Release from Deep Power Down (RES) instruction provides the only way to
exit the Deep Power Down mode. Once the device enters the Deep Power Down
mode, all instructions are ignored except the Release from Deep Power Down
(RES) instruction. Executing this instruction takes the device out of Deep Power
Down mode.
The Release from Deep Power Down (RES) instruction is entered by driving Chip
Select (CS#) Low, followed by the instruction code on Serial Data Input (SI). Chip
Select (CS#) must be driven Low for the entire sequence duration.
The instruction sequence is shown in Figure 16, on page 27.
Driving Chip Select (CS#) High after the 8-bit instruction byte is received by the
device, but before the whole of the 8-bit Electronic Signature is transmitted for
the first time, still insures that the device is placed into Standby mode. If the device was previously in the Deep Power Down mode, the transition to the Standby Power mode is delayed by tRES, and Chip Select (CS#) must remain High for
at least tRES(max), as specified in Table 10, on page 32. Once in the Stand-by
Power mode, the device waits to be selected, so that it can receive, decode, and
execute instructions.
26
S25FL Family (Serial Peripheral Interface) S25FL004A
S25FL004A_00_A1 March 28, 2005
A d v a n c e
I n f o r m a t i o n
CS#
0
1
2
3
4
5
6
7
SCK
Instruction
t
RES
SI
Deep Power Down Mode
Figure 16.
Standby Mode
Release from Deep Power Down Instruction Sequence
Release from Deep Power Down and Read Electronic Signature (RES)
Once the device enters Deep Power Down mode, all instructions are ignored except the RES instruction. The RES instruction can also be used to read the oldstyle 8-bit Electronic Signature on the SO pin. The RES instruction always provides access to the Electronic Signature (except while an Erase, Program or
WRSR cycle is in progress), and can be applied even if DP mode is not entered.
Any RES instruction executed while an Erase, Program, or WRSR cycle is in
progress is not decoded, and has no effect on the cycle in progress.
The device features an 8-bit Electronic Signature, whose value for the S25FL004A
is 12h. This can be read using RES instruction.
The device is first selected by driving Chip Select (CS#) Low. The instruction code
is followed by three dummy bytes, each bit being latched-in on Serial Data Input
(SI) during the rising edge of Serial Clock (SCK). Then, the 8-bit Electronic Signature, stored in the memory, is shifted out on Serial Data Output (SO), each bit
being shifted out during the falling edge of Serial Clock (SCK).
The instruction sequence is shown in Figure 17, on page 28.
The Release from Deep Power Down and Read Electronic Signature (RES) is terminated by driving Chip Select (CS#) High after the Electronic Signature is read
at least once. Sending additional clock cycles on Serial Clock (SCK), while Chip
Select (CS#) is driven Low, causes the Electronic Signature to be output
repeatedly.
When Chip Select (CS#) is driven High, the device is placed in the Stand-by
Power mode. If the device was not previously in the Deep Power Down mode, the
transition to the Stand-by Power mode is immediate. If the device was previously
in the Deep Power Down mode, the transition to the Standby mode is delayed by
tRES, and Chip Select (CS#) must remain High for at lease tRES(max), as specified
in Table 10, on page 32. Once in the Stand-by Power mode, the device waits to
be selected, so that it can receive, decode, and execute instructions.
March 28, 2005 S25FL004A_00_A1
S25FL Family (Serial Peripheral Interface) S25FL004A
27
A d v a n c e
I n f o r m a t i o n
CS#
0
1
2
3
4
5
6
7
8
9 10
28 29 30 31 32 33 34 35 36 37 38
SCK
SI
tRES
3 Dummy
Bytes
Instruction
23 22 21
3 2
1
0
Electronic ID out
MSB
SO
High Impedance
7
6
5
4
3
2
1
0
MSB
Standby Mode
Deep Power Down Mode
Figure 17. Release from Deep Power Down and Read Electronic Signature (RES) Instruction Sequence
Power-up and Power-down
The device must not be selected at power-up or power-down (that is, CS# must
follow the voltage applied on VCC) until VCC reaches the correct value as follows:
„ VCC (min) at power-up, and then for a further delay of tPU (as described in
Table 7, on page 29)
„ VSS at power-down
A simple pull-up resistor on Chip Select (CS#) can usually be used to insure safe
and proper power-up and power-down.
The device ignores all instructions until a time delay of tPU (as described in
Table 7, on page 29) has elapsed after the moment that VCC rises above the minimum VCC threshold. However, device correct operation is not guaranteed if by
this time VCC is still below VCC (min). No Write Status Register, Program, or Erase
instructions should be sent until tPU after V CC reaches the minimum V CC
threshold.
At power-up, the device is in Standby mode (not Deep Power Down mode) and
the WEL bit is reset.
Normal precautions must be taken for supply rail decoupling to stabilize the
VCC(min) feed. Each device in a system should have the VCC rail decoupled by a
suitable capacitor close to the package pins (this capacitor is generally in the
order of 0.1 µF).
At power-down, when VCC drops from the operating voltage to below the VCC(min)
threshold, all operations are disabled and the device does not respond to any instructions. (The designer needs to be aware that if a power-down occurs while a
Write, Program, or Erase cycle is in progress, data corruption can result.)
28
S25FL Family (Serial Peripheral Interface) S25FL004A
S25FL004A_00_A1 March 28, 2005
A d v a n c e
I n f o r m a t i o n
Vcc
(max)
Vcc
(min)
Vcc
tPU
Full Device Access
Time
Figure 18. Power-Up Timing
Table 7. Power-Up Timing
Symbol
VCC(min)
tPU
Parameter
Min
Max
Unit
VCC (minimum)
2.7
V
VCC (min) to device operation
10
mSec
Initial Delivery State
The device is delivered with all bits set to 1 (each byte contains FFh). The Status
Register contains 00h (all Status Register bits are 0).
Maximum Rating
Stressing the device above the rating listed in the Absolute Maximum Ratings
section may cause permanent damage to the device. These are stress ratings
only and operating the device at these or any other conditions above those indicated in the Operating sections of this specification, is not implied. Exposure to
Absolute Maximum Rating conditions for extended periods may affect device
reliability.
Absolute Maximum Ratings
Ambient Storage Temperature . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Voltage with Respect to Ground:
All Inputs and I/Os. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 4.5 V
Operating Ranges
Ambient Operating Temperature (TA)
Commercial . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C
Industrial . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to +85°C
Positive Power Supply
Voltage Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7 V to 3.6 V
Note: Operating ranges define those limits between which the device functionality is guaranteed.
March 28, 2005 S25FL004A_00_A1
S25FL Family (Serial Peripheral Interface) S25FL004A
29
A d v a n c e
I n f o r m a t i o n
DC Characteristics
This section summarizes the device DC and AC Characteristics. Designers should
check that the operating conditions in their circuit match the measurement conditions specified in the Test Specifications in Table 9, on page 31, when relying on
the quoted parameters.
CMOS Compatible
Table 8.
Parameter
VCC
ICC1
DC Characteristics
Test Conditions
(See Note)
Description
Supply Voltage
SCK = 0.1 VCC/0.9VCC
33 MHz
SCK = 0.1 VCC/0.9VCC
VCC = 3.0V
50 MHz
Active Read Current
Min
Typ.
Max
Unit
2.7
3
3.6
V
6
mA
11
mA
ICC2
Active Page Program Current
CS# = VCC
20
mA
ICC3
Active WRSR Current
CS# = VCC
24
mA
ICC4
Active Sector Erase Current
CS# = VCC
24
mA
ICC5
Active Bulk Erase Current
CS# = VCC
24
mA
50
µA
10
µA
ISB
Standby Current
VCC = 3.0 V
CS# = VCC
IDP
Deep Power Down Current
VCC = 3.0 V
CS# = VCC
ILI
Input Leakage Current
VIN = GND to VCC
1
µA
ILO
Output Leakage Current
VIN = GND to VCC
1
µA
VIL
Input Low Voltage
–0.3
0.3 VCC
V
VIH
Input High Voltage
0.7 VCC
VCC + 0.5
V
VOL
Output Low Voltage
IOL = 1.6 mA, VCC = VCC min
0.4
V
VOH
Output High Voltage
IOH = –0.1 mA
1
VCC – 0.2
V
Note: Typical values are at TA = 25°C and 3.0 V.
30
S25FL Family (Serial Peripheral Interface) S25FL004A
S25FL004A_00_A1 March 28, 2005
A d v a n c e
I n f o r m a t i o n
Test Conditions
Input and Output
Timing Reference levels
Input Levels
0.8 VCC
0.7 VCC
0.5 VCC
0.3 VCC
0.2 VCC
Figure 19. AC Measurements I/O Waveform
Table 9.
Test Specifications
Symbol
Parameter
CL
Load Capacitance
Min
Max
30
Input Rise and Fall Times
March 28, 2005 S25FL004A_00_A1
Unit
pF
5
ns
Input Pulse Voltage
0.2 VCC to 0.8 VCC
V
Input Timing Reference
Voltage
0.3 VCC to 0.7 VCC
V
Output Timing Reference
Voltage
0.5 VCC
V
S25FL Family (Serial Peripheral Interface) S25FL004A
31
A d v a n c e
I n f o r m a t i o n
AC Characteristics
Table 10. AC Characteristics
Symbol
Parameter
Min
Typ
Max
Unit
FSCK
SCK Clock Frequency READ
instruction
D.C.
33
MHz
FSCK
SCK Clock Frequency for:
FAST_READ, PP, SE, BE, DP, RES,
WREN, WRDI, RDSR, WRSR
D.C.
50
MHz
tCRT
Clock Rise Time (Slew Rate)
0.1
V/ns
tCFT
Clock Fall Time (Slew Rate)
0.1
V/ns
tWH
SCK High Time
9
ns
tWL
SCK Low Time
9
ns
tCS
CS# High Time
100
ns
tCSS (See Note 3) CS# Setup Time
5
ns
tCSH (See Note 3) CS# HOLD Time
5
ns
tHD (See Note 3) HOLD# Setup Time (relative to SCK)
5
ns
tCD (See Note 3) HOLD# Hold Time (relative to SCK)
5
ns
ns
tHC
HOLD# Setup Time (relative to SCK)
5
tCH
HOLD# Hold Time (relative to SCK)
5
tV
Output Valid
tHO
Output Hold Time
0
tHD:DAT
Data in Hold Time
5
tSU:DAT
Data in Setup Time
5
ns
10
ns
10
ns
ns
ns
tR
Input Rise Time
5
ns
tF
Input Fall Time
5
ns
tLZ (See Note 3) HOLD# to Output Low Z
10
ns
tHZ (See Note 3) HOLD# to Output High Z
10
ns
10
ns
tDIS (See Note 3) Output Disable Time
tWPS (See Note 3) Write Protect Setup Time
tWPH (See Note
3)
Write Protect Hold Time
tW
Write Status Register Time
15
ns
15
ns
65
ms
tDP
CS# High to Deep Power Down Mode
3
µs
tRES
Release DP Mode
30
µs
tPP
Page Programming Time
1.5 (See Note 1)
3 (See Note 2)
ms
tSE
Sector Erase Time
1.5 (See Note 1)
3 (See Note 2)
sec
tBE
Bulk Erase Time
12 (See Note 1)
24(See Note 2)
sec
Note:
1. Typical program and erase times assume the following conditions: 25°C, VCC = 3.0V; 10, 000 cycles; checkerboard data
pattern
2. Under worst-case conditions of 90°C; VCC = 2.7V; 100,000 cycles
3. Not 100% tested
32
S25FL Family (Serial Peripheral Interface) S25FL004A
S25FL004A_00_A1 March 28, 2005
A d v a n c e
I n f o r m a t i o n
AC Characteristics
tCS
CS#
tCSH
tCSS
tCSH
tCSS
SCK
tCFT
tSU:DAT
tHD:DAT
tCRT
SI
MSB IN
LSB IN
High Impedance
SO
Figure 20.
SPI Mode 0 (0,0) Input Timing
CS#
tWH
SCK
tV
tV
tHO
tWL
SO
LSB OUT
Figure 21.
March 28, 2005 S25FL004A_00_A1
tDIS
tHO
SPI Mode 0 (0,0) Output Timing
S25FL Family (Serial Peripheral Interface) S25FL004A
33
A d v a n c e
I n f o r m a t i o n
AC Characteristics
CS#
tCH
tHC
tHD
SCK
tCD
tHZ
SO
tLZ
SI
HOLD#
Figure 22. HOLD# Timing
W#
tWPH
tWPS
CS#
SCK
SI
SO
High Impedance
Figure 23. Write Protect Setup and Hold Timing during WRSR when SRWD=1
34
S25FL Family (Serial Peripheral Interface) S25FL004A
S25FL004A_00_A1 March 28, 2005
A d v a n c e
I n f o r m a t i o n
Physical Dimensions
S08 wide—8-pin Plastic Small Outline 208 mils Body Width Package
3
4
0.20 C
D
A
A-B
H
D
5
SEE
DETAIL B
WITH
PLATING
b1
9
3
c
4
c1
E
E1
E1/2
(b)
BASE
METAL
E/2
7
SECTION A-A
e
0.33 C
b
B
0.25 M C
5
A-B
q2
D
GAUGE
PLANE
A
0.10 C
A2
A
0.07 R MIN.
H
0.10 C
SEATING PLANE
A1
C
C
SEATING
PLANE
A
q1
L
q
L2
L1
DETAIL B
NOTES:
1.
PACKAGE
SOC 008 (inches)
SOC 008 (mm)
JEDEC
SYMBOL
MIN
MAX
MIN
MAX
A
0.069
0.085
1.753
2.159
A1
0.002
0.0098
0.051
0.249
A2
0.067
0.075
1.70
1.91
b
0.014
0.019
0.356
0.483
b1
0.013
0.018
0.330
0.457
c
0.0075
0.0095
0.191
0.241
c1
0.006
0.008
0.152
0.203
D
0.208 BSC
5.283 BSC
E
0.315 BSC
8.001 BSC
E1
0.208 BSC
5.283 BSC
e
L
.050 BSC
0.020
0.030
1.27 BSC
0.508
.055 REF
1.40 REF
L2
.010 BSC
0.25 BSC
N
8
0˚
8˚
0˚
8˚
θ1
5˚
15˚
5˚
15˚
0˚
DIMENSION D DOES NOT INCLUDE MOLD FLASH,
PROTRUSIONS OR GATE BURRS. MOLD FLASH,
PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.15 mm
PER END. DIMENSION E1 DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION INTERLEAD FLASH OR PROTRUSION
SHALL NOT EXCEED 0.25 mm PER SIDE. D AND E1
DIMENSIONS ARE DETERMINED AT DATUM H.
.
4.
THE PACKAGE TOP MAY BE SMALLER THAN THE PACKAGE
BOTTOM. DIMENSIONS D AND E1 ARE DETERMINED AT THE
OUTMOST EXTREMES OF THE PLASTIC BODY EXCLUSIVE OF
MOLD FLASH, TIE BAR BURRS, GATE BURRS AND INTERLEAD
FLASH. BUT INCLUDING ANY MISMATCH BETWEEN THE TOP
AND BOTTOM OF THE PLASTIC BODY.
5.
DATUMS A AND B TO BE DETERMINED AT DATUM H.
6.
"N" IS THE MAXIMUM NUMBER OF TERMINAL POSITIONS FOR
THE SPECIFIED PACKAGE LENGTH.
7.
THE DIMENSIONS APPLY TO THE FLAT SECTION OF THE LEAD
BETWEEN 0.10 TO 0.25 mm FROM THE LEAD TIP.
8.
DIMENSION "b" DOES NOT INCLUDE DAMBAR PROTRUSION.
ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.10 mm TOTAL
IN EXCESS OF THE "b" DIMENSION AT MAXIMUM MATERIAL
CONDITION. THE DAMBAR CANNOT BE LOCATED ON THE
LOWER RADIUS OF THE LEAD FOOT.
9.
THIS CHAMFER FEATURE IS OPTIONAL. IF IT IS NOT PRESENT,
THEN A PIN 1 IDENTIFIER MUST BE LOCATED WITHIN THE INDEX
AREA INDICATED.
8
θ
θ2
DIMENSIONING AND TOLERANCING PER ASME Y14.5M - 1994.
3.
0.762
L1
0˚
ALL DIMENSIONS ARE IN BOTH INCHES AND MILLMETERS.
2.
10. LEAD COPLANARITY SHALL BE WITHIN 0.10 mm AS MEASURED
FROM THE SEATING PLANE.
3432 \ 16-038.03 \ 10.28.04
March 28, 2005 S25FL004A_00_A1
S25FL Family (Serial Peripheral Interface) S25FL004A
35
A d v a n c e
I n f o r m a t i o n
Physical Dimensions
USON 8L (5x6mm) No-Lead Package
QUAD FLAT NO LEAD PACKAGES (UNE) - PLASTIC
1. DIMENSIONING AND TOLERANCING CONFORMS TO
ASME Y14.5M-1994.
DIMENSIONS
SYMBOL
MIN
MAX
NOTE
e
1.27 BSC
N
8
3
ND
4
5
2. ALL DIMENSIONS ARE IN MILLIMETERS, 0 IS IN DEGREES.
3. N IS THE TOTAL NUMBER OF TERMINALS.
4. DIMENSION b APPLIES TO METALLIZED TERMINAL AND IS
MEASURED BETWEEN 0.15 AND 0.30 mm FROM TERMINAL TIP.
IF THE TERMINAL HAS THE OPTIONAL RADIUS ON THE OTHER
END OF THE TERMINAL, THE DIMENSION b SHOULD NOT BE
MEASURED IN THAT RADIUS AREA.
L
0.55
0.60
0.65
b
0.35
0.40
0.45
D2
3.90
4.00
4.10
5.
ND REFERS TOT HE NUMBER OF TERMINALS ON D SIDE.
E2
3.30
3.40
3.50
6.
MAXIMUM PACKAGE WARPAGE IS 0.05 mm.
4
D
5.00 BSC
7.
MAXIMUM ALLOWABLE BURRS IS 0.076 mm IN ALL DIRECTIONS.
E
6.00 BSC
8.
PIN #1 ID ON TOP WILL BE LASER MARKED.
9.
BILATERAL COPLANARITY ZONE APPLIES TO THE EXPOSED
HEAT SINK SLUG AS WELL AS THE TERMINALS.
A
0.45
0.50
0.55
A1
0.00
0.02
0.05
K
θ
36
NOM
NOTES:
0.20 MAX.
0
---
12
2
S25FL Family (Serial Peripheral Interface) S25FL004A
S25FL004A_00_A1 March 28, 2005
A d v a n c e
I n f o r m a t i o n
Revision Summary
Revision A0 (March 1, 2005)
Initial Release.
Revision A1 (March 28, 2005)
Updated Table 7.
Removed Commercial Temperature Range.
Changed WSON package nomenclature to USON package; updated USON package dimensions.
Added Tray option for Packing Type.
Colophon
The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary
industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for any use that
includes fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal
injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control,
medical life support system, missile launch control in weapon system), or (2) for any use where chance of failure is intolerable (i.e., submersible repeater and
artificial satellite). Please note that Spansion will not be liable to you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures
by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other
abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under
the Foreign Exchange and Foreign Trade Law of Japan, the US Export Administration Regulations or the applicable laws of any other country, the prior authorization by the respective government entity will be required for export of those products.
Trademarks and Notice
The contents of this document are subject to change without notice. This document may contain information on a Spansion LLC product under development
by Spansion LLC. Spansion LLC reserves the right to change or discontinue work on any product without notice. The information in this document is provided
as is without warranty or guarantee of any kind as to its accuracy, completeness, operability, fitness for particular purpose, merchantability, non-infringement
of third-party rights, or any other warranty, express, implied, or statutory. Spansion LLC assumes no liability for any damages of any kind arising out of the
use of the information in this document.
Copyright ©2004-2005 Spansion LLC. All rights reserved. Spansion, the Spansion logo, and MirrorBit are trademarks of Spansion LLC. Other company and
product names used in this publication are for identification purposes only and may be trademarks of their respective companies.
March 28, 2005 S25FL004A_00_A1
S25FL Family (Serial Peripheral Interface) S25FL004A
37