74LCX373 OCTAL D-TYPE LATCH NON-INVERTING (3-STATE) WITH 5V TOLERANT INPUTS AND OUTPUTS ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ 5V TOLERANT INPUTS AND OUTPUTS HIGH SPEED : tPD = 8.0 ns (MAX.) at VCC = 3V POWER DOWN PROTECTION ON INPUTS AND OUTPUTS SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 24mA (MIN) at VCC = 3V PCI BUS LEVELS GUARANTEED AT 24 mA BALANCED PROPAGATION DELAYS: tPLH ≅ tPHL OPERATING VOLTAGE RANGE: VCC(OPR) = 2.0V to 3.6V (1.5V Data Retention) PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 373 LATCH-UP PERFORMANCE EXCEEDS 500mA (JESD 17) ESD PERFORMANCE: HBM > 2000V (MIL STD 883 method 3015); MM > 200V DESCRIPTION The 74LCX373 is a low voltage CMOS OCTAL D-TYPE LATCH with 3 STATE OUTPUT NON-INVERTING fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS technology. It is ideal for low power and high speed 3.3V applications; it can be interfaced to 5V signal environment for both inputs and outputs. These 8 bit D-Type latch are controlled by a latch SOP TSSOP ORDER CODES PACKAGE TUBE T&R SOP TSSOP 74LCX373M 74LCX373MTR 74LCX373TTR enable input (LE) and an output enable input (OE). While the LE inputs is held at a high level, the Q outputs will follow the data input. When the LE is taken low, the Q outputs will be latched precisely at the logic level of D input data. While the (OE) input is low, the 8 outputs will be in a normal logic state (high or low logic level) and while (OE) is in high level, the outputs will be in a high impedance state. It has same speed performance at 3.3V than 5V AC/ACT family, combined with a lower power consumption. All inputs and outputs are equipped with protection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage. PIN CONNECTION AND IEC LOGIC SYMBOLS September 2001 1/10 74LCX373 INPUT AND OUTPUT EQUIVALENT CIRCUIT PIN DESCRIPTION PIN No SYMBOL 1 OE 2, 5, 6, 9, 12, 15, 16,19 3, 4, 7, 8, 13, 14, 17, 18 11 10 20 TRUTH TABLE NAME AND FUNCTION D0 to D7 3 State Output Enable Input (Active LOW) Data Inputs Q0 to Q7 3-State Outputs LE GND VCC Latch Enable Input Ground (0V) Positive Supply Voltage LOGIC DIAGRAM This logic diagram has not be used to estimate propagation delays 2/10 INPUT OUTPUT OE LE D Q H L L L X L H H X X L H Z NO CHANGE* L H X : Don’t Care Z : High Impedance * : Q Outputs are latched at the time when the LE input is taken LOW. 74LCX373 ABSOLUTE MAXIMUM RATINGS Symbol VCC Parameter Value Unit Supply Voltage -0.5 to +7.0 V VI DC Input Voltage -0.5 to +7.0 V VO DC Output Voltage (OFF State) VO DC Output Voltage (High or Low State) (note 1) -0.5 to +7.0 V -0.5 to VCC + 0.5 - 50 V mA IIK DC Input Diode Current IOK DC Output Diode Current (note 2) - 50 mA IO DC Output Current ± 50 mA ICC DC Supply Current per Supply Pin ± 100 mA IGND DC Ground Current per Supply Pin ± 100 mA Tstg Storage Temperature TL Lead Temperature (10 sec) -65 to +150 °C 300 °C Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied 1) IO absolute maximum rating must be observed 2) VO < GND RECOMMENDED OPERATING CONDITIONS Symbol VCC Parameter Supply Voltage (note 1) Value Unit 2.0 to 3.6 V VI Input Voltage 0 to 5.5 V VO Output Voltage (OFF State) 0 to 5.5 V VO Output Voltage (High or Low State) 0 to VCC V IOH, IOL High or Low Level Output Current (VCC = 3.0 to 3.6V) ± 24 mA IOH, IOL High or Low Level Output Current (VCC = 2.7V) ± 12 mA Top dt/dv Operating Temperature Input Rise and Fall Time (note 2) -55 to 125 °C 0 to 10 ns/V 1) Truth Table guaranteed: 1.5V to 3.6V 2) VIN from 0.8V to 2V at VCC = 3.0V 3/10 74LCX373 DC SPECIFICATIONS Test Condition Symbol VIH VIL VOH Parameter High Level Input Voltage Low Level Input Voltage High Level Output Voltage Low Level Output Voltage Ioff IOZ ICC ∆ICC Input Leakage Current Power Off Leakage Current High Impedance Output Leakage Current Quiescent Supply Current ICC incr. per Input Min. Max. 2.0 -55 to 125 °C Min. Unit Max. 2.0 V 2.7 to 3.6 0.8 0.8 2.7 to 3.6 IO=-100 µA VCC-0.2 VCC-0.2 2.7 IO=-12 mA 2.2 2.2 IO=-18 mA 2.4 2.4 IO=-24 mA 2.2 2.2 V V 2.7 to 3.6 IO=100 µA 0.2 0.2 2.7 IO=12 mA 0.4 0.4 IO=16 mA 0.4 0.4 IO=24 mA 0.55 0.55 2.7 to 3.6 VI = 0 to 5.5V ±5 ±5 µA 0 VI or VO = 5.5V 10 10 µA 2.7 to 3.6 VI = VIH or VIL VO = 0 to VCC ±5 ±5 µA 2.7 to 3.6 VI = VCC or GND VI or VO= 3.6 to 5.5V 10 10 ± 10 ± 10 2.7 to 3.6 VIH = VCC - 0.6V 500 500 3.0 II -40 to 85 °C VCC (V) 3.0 VOL Value V µA µA DYNAMIC SWITCHING CHARACTERISTICS Test Condition Symbol VOLP VOLV Parameter Dynamic Low Level Quiet Output (note 1) TA = 25 °C VCC (V) 3.3 Value Min. CL = 50pF VIL = 0V, VIH = 3.3V Typ. 0.8 -0.8 Unit Max. V 1) Number of outputs defined as "n". Measured with "n-1" outputs switching from HIGH to LOW or LOW to HIGH. The remaining output is measured in the LOW state. 4/10 74LCX373 AC ELECTRICAL CHARACTERISTICS Test Condition Symbol Parameter tPLH tPHL Propagation Delay Time (Dn to Qn) tPLH tPHL Propagation Delay Time (LE to Qn) tPZL tPZH Output Enable Time to HIGH and LOW level Output Disable Time from HIGH to LOW level Set-Up Time, HIGH or LOW level (Dn to LE) Hold Time, HIGH or LOW level (Dn to LE) LE Pulse Width, HIGH tPLZ tPHZ tS th tW tOSLH tOSHL Output To Output Skew Time (note1, 2) VCC (V) 2.7 3.0 to 3.6 2.7 3.0 to 3.6 2.7 3.0 to 3.6 CL (pF) RL (Ω) Value ts = t r (ns) 50 500 2.5 50 500 2.5 50 500 2.5 50 500 2.5 50 500 2.5 50 500 2.5 50 500 2.5 50 500 2.5 2.7 3.0 to 3.6 2.7 3.0 to 3.6 2.7 3.0 to 3.6 2.7 3.0 to 3.6 3.0 to 3.6 -40 to 85 °C -55 to 125 °C Min. Max. Min. Max. 1.5 1.5 1.5 1.5 1.5 9.0 8.0 9.5 8.5 9.5 1.5 1.5 1.5 1.5 1.5 9.0 8.0 9.5 8.5 9.5 1.5 8.5 1.5 8.5 1.5 8.5 1.5 8.5 1.5 7.5 1.5 7.5 2.5 2.5 2.5 2.5 1.5 1.5 1.5 1.5 3.3 3.3 3.3 3.3 1.0 Unit ns ns ns ns ns ns ns 1.0 ns 1) Skew is defined as the absolute value of the difference between the actual propagation delay for any two outputs of the same device switching in the same direction, either HIGH or LOW (tOSLH = | tPLHm - t PLHn|, tOSHL = | tPHLm - tPHLn|) 2) Parameter guaranteed by design CAPACITIVE CHARACTERISTICS Test Condition Symbol CIN Parameter Input Capacitance COUT Output Capacitance CPD Power Dissipation Capacitance (note 1) Value TA = 25 °C VCC (V) Min. Typ. Unit Max. 3.3 VIN = 0 to VCC 6 pF 3.3 VIN = 0 to VCC 12 pF 3.3 fIN = 10MHz VIN = 0 or VCC 50 pF 1) CPD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. ICC(opr) = C PD x VCC x fIN + ICC/8 (per latch) 5/10 74LCX373 TEST CIRCUIT TEST tPLH, tPHL SWITCH Open tPZL, tPLZ 6V tPZH, tPHZ GND CL = 50 pF or equivalent (includes jig and probe capacitance) RL = R1 = 500Ω or equivalent RT = ZOUT of pulse generator (typically 50Ω) WAVEFORM 1 : LE TO Qn PROPAGATION DELAYS, LE MINIMUM PULSE WIDTH, Dn TO LE SETUP AND HOLD TIMES (f=1MHz; 50% duty cycle) 6/10 74LCX373 WAVEFORM 2 : OUTPUT ENABLE AND DISABLE TIMES (f=1MHz; 50% duty cycle) WAVEFORM 3 : PROPAGATION DELAY TIME (f=1MHz; 50% duty cycle) 7/10 74LCX373 SO-20 MECHANICAL DATA mm. inch DIM. MIN. TYP A a1 MAX. MIN. TYP. 2.65 0.1 0.104 0.2 a2 MAX. 0.004 0.008 2.45 0.096 b 0.35 0.49 0.014 0.019 b1 0.23 0.32 0.009 0.012 C 0.5 0.020 c1 45° (typ.) D 12.60 13.00 0.496 0.512 E 10.00 10.65 0.393 0.419 e 1.27 0.050 e3 11.43 0.450 F 7.40 7.60 0.291 0.300 L 0.50 1.27 0.020 0.050 M S 0.75 0.029 8° (max.) PO13L 8/10 74LCX373 TSSOP20 MECHANICAL DATA mm. inch DIM. MIN. TYP MAX. A MIN. TYP. MAX. 1.2 A1 0.05 A2 0.8 b 0.047 0.15 0.002 0.004 0.006 1.05 0.031 0.039 0.041 0.19 0.30 0.007 0.012 c 0.09 0.20 0.004 0.0089 D 6.4 6.5 6.6 0.252 0.256 0.260 E 6.2 6.4 6.6 0.244 0.252 0.260 E1 4.3 4.4 4.48 0.169 0.173 0.176 1 e 0.65 BSC K 0° L 0.45 A 0.0256 BSC 0.60 8° 0° 0.75 0.018 8° 0.024 0.030 A2 A1 b K e L E c D E1 PIN 1 IDENTIFICATION 1 0087225C 9/10 74LCX373 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. 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