74LCX16373 LOW VOLTAGE CMOS 16-BIT D-TYPE LATCH (3-STATE) WITH 5V TOLERANT INPUTS AND OUTPUTS ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ 5V TOLERANT INPUTS AND OUTPUTS HIGH SPEED : tPD = 5.4 ns (MAX.) at VCC = 3V POWER DOWN PROTECTION ON INPUTS AND OUTPUTS SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 24mA (MIN) at VCC = 3V PCI BUS LEVELS GUARANTEED AT 24 mA BALANCED PROPAGATION DELAYS: tPLH ≅ tPHL OPERATING VOLTAGE RANGE: VCC(OPR) = 2.0V to 3.6V (1.5V Data Retention) PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 16373 LATCH-UP PERFORMANCE EXCEEDS 500mA (JESD 17) ESD PERFORMANCE: HBM > 2000V (MIL STD 883 method 3015); MM > 200V TSSOP ORDER CODES PACKAGE TSSOP TUBE T &R 74LCX16373TTR PIN CONNECTION DESCRIPTION The 74LCX16373 is a low voltage CMOS 16 BIT D-TYPE LATCH with 3 STATE OUTPUTS NON INVERTING fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS technology. It is ideal for low power and high speed 3.3V applications; it can be interfaced to 5V signal environment for both inputs and outputs. These 16 bit D-TYPE latches are byte controlled by two latch enable inputs (nLE) and two output enable inputs(OE). While the nLE input is held at a high level, the nQ outputs will follow the data input precisely. When the nLE is taken LOW, the nQ outputs will be latched precisely at the logic level of D input data. While the (nOE) input is low, the nQ outputs will be in a normal logic state (high or low logic level) and while high level the outputs will be in a high impedance state. It has same speed performance at 3.3V than 5V AC/ACT family, combined with a lower power consumption. All inputs and outputs are equipped with protection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage. September 2001 1/9 74LCX16373 INPUT AND OUTPUT EQUIVALENT CIRCUIT PIN DESCRIPTION PIN No SYMBOL 1 1OE IEC LOGIC SYMBOLS NAME AND FUNCTION 3 State Output Enable Input (Active LOW) 1Q0 to 1Q7 3-State Outputs 2, 3, 5, 6, 8, 9, 11, 12 13, 14, 16, 17, 2Q0 to 2Q7 3-State Outputs 19, 20, 22, 23 24 2OE 3 State Output Enable Input (Active LOW) 25 2LE Latch Enable Input 36, 35, 33, 32, 2D0 to 2D7 Data Inputs 30, 29, 27, 26 47, 46, 44, 43, 1D0 to 1D7 Data Inputs 41, 40, 38, 37 48 1LE Latch Enable Input 4, 10, 15, 21, GND Ground (0V) 28, 34, 39, 45 7, 18, 31, 42 VCC Positive Supply Voltage TRUTH TABLE INPUTS OUTPUT OE LE D Q H L L L X L H H X X L H Z NO CHANGE * L H X : Don‘t Care Z : High Impedance * : Q outputs are latched at the time when the LE input is taken low logic level. 2/9 74LCX16373 LOGIC DIAGRAM This logic diagram has not to be used to estimate propagation delays ABSOLUTE MAXIMUM RATINGS Symbol V CC Parameter Value Unit Supply Voltage -0.5 to +7.0 V VI DC Input Voltage -0.5 to +7.0 V VO DC Output Voltage (OFF State) VO DC Output Voltage (High or Low State) (note 1) -0.5 to +7.0 V -0.5 to VCC + 0.5 - 50 V mA IIK DC Input Diode Current IOK DC Output Diode Current (note 2) - 50 mA IO DC Output Current ± 50 mA ICC DC Supply Current per Supply Pin ± 100 mA IGND DC Ground Current per Supply Pin ± 100 mA Tstg Storage Temperature -65 to +150 °C TL Lead Temperature (10 sec) 300 °C Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied 1) IO absolute maximum rating must be observed 2) VO < GND RECOMMENDED OPERATING CONDITIONS Symbol V CC Parameter Supply Voltage (note 1) Value Unit 2.0 to 3.6 V 0 to 5.5 V VI Input Voltage VO Output Voltage (OFF State) 0 to 5.5 V VO Output Voltage (High or Low State) 0 to VCC V IOH, IOL High or Low Level Output Current (V CC = 3.0 to 3.6V) ± 24 mA IOH, IOL High or Low Level Output Current (V CC = 2.7V) Operating Temperature ± 12 mA Top dt/dv Input Rise and Fall Time (note 2) -55 to 125 °C 0 to 10 ns/V 1) Truth Table guaranteed: 1.5V to 3.6V 2) VIN from 0.8V to 2V at VCC = 3.0V 3/9 74LCX16373 DC SPECIFICATIONS Test Condition Symbol VIH VIL VOH Parameter High Level Input Voltage Low Level Input Voltage High Level Output Voltage Low Level Output Voltage Ioff IOZ ICC ∆ICC Input Leakage Current Power Off Leakage Current High Impedance Output Leakage Current Quiescent Supply Current ICC incr. per Input Min. Max. 2.0 -55 to 125 °C Min. Unit Max. 2.0 V 2.7 to 3.6 0.8 0.8 2.7 to 3.6 I O=-100 µA VCC-0.2 VCC-0.2 2.7 IO=-12 mA 2.2 2.2 IO=-18 mA 2.4 2.4 IO=-24 mA 2.2 V V 2.2 2.7 to 3.6 IO=100 µA 0.2 0.2 2.7 IO=12 mA 0.4 0.4 IO=16 mA 0.4 0.4 IO=24 mA 0.55 0.55 2.7 to 3.6 VI = 0 to 5.5V ±5 ±5 µA 0 V I or VO = 5.5V 10 10 µA 2.7 to 3.6 V I = VIH or VIL VO = 0 to VCC ±5 ±5 µA 2.7 to 3.6 VI = VCC or GND VI or VO= 3.6 to 5.5V 20 20 ± 20 ± 20 2.7 to 3.6 VIH = VCC - 0.6V 500 500 3.0 II -40 to 85 °C VCC (V) 3.0 VOL Value V µA µA DYNAMIC SWITCHING CHARACTERISTICS Test Condition Symbol VOLP V OLV Parameter Dynamic Low Level Quiet Output (note 1) TA = 25 °C VCC (V) 3.3 Value Min. CL = 50pF VIL = 0V, V IH = 3.3V Typ. 0.8 -0.8 Unit Max. V 1) Number of outputs defined as ”n”. Measured with ”n-1” outputs switching from HIGH to LOW or LOW to HIGH. The remaining output is measured in the LOW state. 4/9 74LCX16373 AC ELECTRICAL CHARACTERISTICS Test Conditi on Symbol Parameter tPLH tPHL Propagation Delay Time (Dn to Qn) tPLH tPHL Propagation Delay Time (LE to Qn) tPZL tPZH Output Enable Time to HIGH and LOW level Output Disable Time from HIGH to LOW level Set-Up Time, HIGH or LOW level (Dn to LE) Hold Time, HIGH or LOW level (Dn to LE) LE Pulse Width, HIGH tPLZ tPHZ tS th tW tOSLH tOSHL Output To Output Skew Time (note1, 2) VCC (V) 2.7 3.0 to 3.6 2.7 3.0 to 3.6 2.7 3.0 to 3.6 CL (pF) RL (Ω) Value ts = t r (ns) 50 500 2.5 50 500 2.5 50 500 2.5 50 500 2.5 50 500 2.5 50 500 2.5 50 500 2.5 50 500 2.5 2.7 3.0 to 3.6 2.7 3.0 to 3.6 2.7 3.0 to 3.6 2.7 3.0 to 3.6 3.0 to 3.6 -40 to 85 °C -55 to 125 °C Min. Max. Min. Max. 1.5 1.5 1.5 1.5 1.5 5.9 5.4 6.4 5.5 6.5 1.5 1.5 1.5 1.5 1.5 5.9 5.4 6.4 5.5 6.5 1.5 6.1 1.5 6.1 1.5 6.3 1.5 6.3 1.5 6.0 1.5 6.0 2.5 2.5 2.5 2.5 1.5 1.5 1.5 1.5 3.0 3.0 3.0 3.0 1.0 Unit ns ns ns ns ns ns ns 1.0 ns 1) Skew is defined as the absolute value of the difference between the actual propagation delay for any two outputs of the same device switching in the same direction, either HIGH or LOW (tOSLH = | tPLHm - tPLHn|, tOSHL = | tPHLm - tPHLn|) 2) Parameter guaranteed by design CAPACITIVE CHARACTERISTICS Test Condition Symbol Parameter Input Capacitance C OUT Output Capacitance CPD Power Dissipation Capacitance (note 1) CIN Value TA = 25 °C VCC (V) Min. Typ. Unit Max. 3.3 VIN = 0 to VCC 7 pF 3.3 VIN = 0 to VCC 8 pF 3.3 fIN = 10MHz V IN = 0 or VCC 20 pF 1) CPD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. ICC(opr) = CPD x VCC x fIN + ICC/16 (per circuit) 5/9 74LCX16373 TEST CIRCUIT TEST tPLH, tPHL SWITCH Open tPZL, tPLZ 6V tPZH, tPHZ GND C L = 50 pF or equivalent (includes jig and probe capacitance) R L = R1 = 500Ω or equivalent R T = ZOUT of pulse generator (typically 50Ω) WAVEFORM 1 : LE TO Qn PROPAGATION DELAYS, LE MINIMUM PULSE WIDTH, Dn TO LE SETUP AND HOLD TIMES (f=1MHz; 50% duty cycle) 6/9 74LCX16373 WAVEFORM 2 : OUTPUT ENABLE AND DISABLE TIME (f=1MHz; 50% duty cycle) WAVEFORM 3 : PROPAGATION DELAY TIME (f=1MHz; 50% duty cycle) 7/9 74LCX16373 TSSOP48 MECHANICAL DATA mm. inch DIM. MIN. TYP MAX. A MIN. TYP. 1.1 A1 0.05 0.043 0.15 A2 MAX. 0.002 0.006 0.9 0.035 b 0.17 0.27 0.0067 0.011 c 0.09 0.20 0.0035 0.0079 D 12.4 12.6 0.408 0.496 E 7.95 8.25 0.313 0.325 E1 6.0 6.2 0.236 0.244 e 0.5 BSC 0.0197 BSC K 0° 8° 0° 8° L 0.50 0.75 0.020 0.030 A A2 A1 b K e L E c D E1 PIN 1 IDENTIFICATION 1 7065588A 8/9 74LCX16373 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringe ment of patents or other righ ts of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this pub lication are subject to change without notice. Thi s pub lication supersedes and replaces all information previously supplied. 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