L4903 DUAL 5V REGULATOR WITH RESET AND DISABLE FUNCTIONS . . . . . . .. . .. . PRELIMINARY DATA OUTPUT CURRENTS : I01 = 50mA I02 = 100mA FIXED PRECISION OUTPUT VOLTAGE 5V ± 2 % RESET FUNCTION CONTROLLED BY INPUT VOLTAGE AND OUTPUT 1 VOLTAGE RESET FUNCTION EXTERNALLY PROGRAMMABLE TIMING RESET OUTPUT LEVEL RELATED TO OUTPUT 2 OUTPUT 2 INTERNALLY SWITCHED WITH ACTIVE DISCHARGING OUTPUT 2 DISABLE LOGICAL INPUT LOW LEAKAGE CURRENT, LESS THAN 1µA AT OUTPUT 1 INPUT OVERVOLTAGE PROTECTION UP TO 60V RESET OUTPUT NORMALLY LOW OUTPUT TRANSISTORS SOA PROTECTION SHORT CIRCUIT AND THERMAL OVERLOAD PROTECTION Minidip ORDERING NUMBERS : L4903 DESCRIPTION The L4903 is a monolithic low drop dual 5 V regulator designed mainly for supplying microprocessor systems. Reset, data save functions and remote switch on/off control can be realized. PIN CONNECTION July1993 1/8 L4903 PIN FUNCTIONS N° 1 2 3 4 5 6 Name Input 1 Input 2 Timing Capacitor GND Disable Input Reset Output 7 Output 2 8 Output 1 Function Low Quiescent Current 50mA Regulator Input 100mA Regulator Input. If Reg. 2 is switched-ON the delay capacitor is charged with a 10µA constant current. When Reg. 2 is switched-OFF the delay capacitor is discharged. Common Ground A high level (> VDT) disables output Reg. 2. When pin 3 reaches 5V the reset output is switched low. 5V ) ; tRD (ms) = Ct (nF). Therefore tRD = C t ( 10µA 5V – 100mA Regulator Output. Enabled if Vo 1 > VRT. DISABLE INPUT < VDT and VIN 2 > VIT. If Reg. 2 is switched-OFF the C02 capacitor is discharged. 5V – 50mA regulator output with low leakage in switch-OFF condition. BLOCK DIAGRAM SCHEMATIC DIAGRAM 2/8 L4903 ABSOLUTE MAXIMUM RATINGS Symbol VIN Vt Ptot Tstg, Tj Parameter DC Input Voltage Transient Input Overvoltage (t = 40ms) Power Dissipation at Tamb = 50°C Storage and Junction Temperature Value 24 60 1 – 40 to 150 Unit V V W °C Value 70 100 Unit °C/W °C/W THERMAL DATA Symbol Rth (j-pin) R th (j-a) Parameter Thermal Resistance Junction-pin 4 Thermal Resistance Junction-ambient Max. Max. ELECTRICAL CHARACTERISTICS (VIN = 14.4V, Tamb = 25oC unless otherwise specified) Symbol Vi V01 V02 H V02 L I01 IL01 I02 VI01 Parameter DC Operating Input Voltage Output Voltage 1 Output Voltage 2 HIGH Output Voltage 2 LOW Output Current 1 max. (*) Leakage Output 1 Current Output Current 2 max. (*) Output 1 Dropout Voltage (*) VIT VITH ∆V01 ∆V02 ∆V01 ∆V02 IQ Input Threshold Voltage Input Threshold Voltage Hyst. Line Regulation 1 Line Regulation 2 Load Regulation 1 Load Regulation 2 Quiescent Current IQ1 VRT VRTH VRH VRL tRD td VDT ID Quiescent Current 1 Reset Threshold Voltage Reset Threshold Hysteresis Reset Output Voltage HIGH Reset Output Voltage LOW Reset Pulse Delay Timing Capacitor Discharge Time V02 Disable Threshold Voltage V02 Disable Input Current ∆V01 ∆V02 , Thermal Drift ∆T ∆T SVR1 Supply Voltage Rejection SVR2 Supply Voltage Rejection TJSD Thermal Shut Down Test Conditions R Load 1kΩ R Load 1kΩ I02 = – 5mA ∆V01 = – 100mV VIN = 0, V01 ≤ 3V ∆V02 = – 100mV I01 = 10mA I01 = 50mA Min. Typ. 4.95 V01 –0.1 5.05 5 0.1 Max. 20 5.15 V01 50 1 100 Unit V V V V mA µA mA V V V mV mV mV mV mV mA 0.7 0.75 6.4 250 5 5 5 10 0.8 0.9 V01 + 1.7 4.5 2.7 1.6 0.6 6.5 4.5 3.5 0.9 mA 4.7 50 4.12 0.25 5 V02 – 0.02 80 V02 0.4 11 20 V mV V V ms µs 1.25 - 150 30 2.4 VD ≤ 0.4V VD ≥ 2.4V V µA µA – 20°C ≤ Tamb ≤ 125°C 0.3 - 0.8 mV/°C 84 80 dB dB 150 °C V01 + 1.2 7V < VIN < 18V, I01 = 5mA 7V < VIN < 18V, I02 = 5mA VIN1 = 8V, 5mA < I01 < 50mA VIN1 = 8V, 5mA < I02 < 100mA I01 = I02 ≤ 5mA 0 < VIN < 13V 7V < VIN < 13V V02 LOW 7V < VIN < 13V V02 HIGH 6.3V < VIN1 < 13V, VIN2 = 0 I01 ≤ 5mA, I02 = 0 IR = 500µA IR = – 5mA C t = 10nF C t = 10nF f = 100Hz, VR = 0.5V, Io = 50mA f = 100Hz, VR = 0.5V, Io = 100mA V02 – 0.04 30 V02 – 1 3 50 50 50 50 20 50 * The dropout voltage is defined as the difference between the input and the output voltage when the output voltage is lowered of 25 mV under constant output current condition. 3/8 L4903 TEST CIRCUIT Figure 1 : P.C. Board and Components Layout of the Test Circuit APPLICATION INFORMATION In power supplies for µP systems it is necessary to provide power continuously to avoid loss of information in memories and in time of day clocks, or to savedata when the primary supply is removed. The L4903 makes it very easy to supply such equipments ; it provides two voltage regulators (both 5 V high precision) with separate inputs plus a reset output for the data save function and Reg. 2 disable input. CIRCUIT OPERATION (see Figure 2) After switch on Reg. 1 saturates until V01 rises to the nominal value. When the input 2 reaches VIT and the output 1 is higher than VRT the output 2 (V02 and VR) switches on and the reset output (VR) goes low after a programmable time TRD (timing capacitor). V02 is switched at low level and VR at high level when one of the following conditions occurs ; - a high level (> VDT) is applied on pin 5 ; - an input overvoltage ; - an overload on the output 1 (V01 < VRT) ; - a switch off (VIN < VIT - VITH) ; and they start again as before when the condition 4/8 is removed. An overload on output 2 does not switch Reg. 2, and does not influence Reg. 1. The V01 output features : - 5 V internal reference without voltage divider between the output and the error comparator - very low drop series regulator element utilizing current mirrors permit high output impedance and then very low leakage current even in power conditions. This output may thereforebe used to supply circuits continuously, such as volatile RAMs, allowing the use of a back-up battery. The V02 can supply other non essential 5 V circuits which may be powered down when the system is inactive, or that must be powered down to prevent uncorrect operation for supply voltages below the minimum value. The reset output can beused as a ”POWER DOWN INTERRUPT”, permitting RAM access only in correct power conditions, or as a ”BACK-UP ENABLE” to transfer data into in a NV SHADOW MEMORY when the supply is interrupted. The disable function can be used for remote on/off control of circuits connected to the V02 output. L4903 Figure 2 APPLICATION SUGGESTION Figure 3 illustrates how the L4903’s disable input may be used in a CMOS µComputer application. The V01 regulator (low consumption) supply permanently a CMOS time of day clock and a CMOS computer chip with volatile memory. V 02 output, supplying non-essential circuits, is turned OFF under control of a µP unit. Configurations of this type are used in products where the OFF switch is part of a keyboard scanned by a micro which operates continuously even in the OFF state. Figure 3 5/8 L4903 Figure 4 : Quiescent Current (reg. 1) versus Output Current Figure 5 : Quiescent Current (reg. 1 versus Input Voltage Figure 6 : Total Quiescent Current versus Input Voltage Figure 7 : Supply Voltage Rejection Regulators 1 and 2 versus Input Ripple Frequence 6/8 L4903 MINIDIP PACKAGE MECHANICAL DATA mm DIM. MIN. A TYP. inch MAX. MIN. 3.32 TYP. MAX. 0.131 a1 0.51 0.020 B 1.15 1.65 0.045 0.065 b 0.356 0.55 0.014 0.022 b1 0.204 0.304 0.008 0.012 D E 10.92 7.95 9.75 0.430 0.313 0.384 e 2.54 0.100 e3 7.62 0.300 e4 7.62 0.300 F 6.6 0.260 I 5.08 0.200 L Z 3.18 3.81 1.52 0.125 0.150 0.060 7/8 L4903 Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. SGS-THOMSON Microelectronics products are not authorized for use as critical components inlife support devices or systems without express written approval of SGS-THOMSON Microelectronics. 1994 SGS-THOMSON Microelectronics - All Rights Reserved SGS-THOMSON Microelectronics GROUP OF COMPANIES Australia - Brazil - France - Germany - Hong Kong - Italy - Japan - Korea - Malaysia - Malta - Morocco - The Netherlands - Singapore - Spain - Sweden - Switzerland - Taiwan - Thaliand - United Kingdom - U.S.A. 8/8