L4938N/ND L4938NPD DUAL MULTIFUNCTION VOLTAGE REGULATOR . . . . . .. . . . . . STANDBYOUTPUT VOLTAGEPRECISION 5V ± 2% OUTPUT 2 TRACKED TO THE STANDBY OUTPUT OUTPUT 2 DISABLE FUNCTION FOR STANDBY MODE VERY LOW QUIESCENT CURRENT, LESS THAN 250µA, IN STANDBY MODE OUTPUT 2 VOLTAGE SETTABLE FROM 5 TO 20V OUTPUT CURRENTS : I01 = 50mA, I02 = 500mA VERY LOW DROPOUT (max 0.4V/0.6V) OPERATING TRANSIENT SUPPLY VOLTAGE UP TO 40V POWER-ON RESET CIRCUIT SENSING THE STANDBY OUTPUT VOLTAGE POWER-ON RESET DELAY PULSE DEFINED BY THE EXTERNAL CAPACITOR EARLY WARNING OUTPUT FOR SUPPLY UNDERVOLTAGE THERMAL SHUTDOWN AND SHORTCIRCUIT PROTECTIONS PowerDIP (12+2+2) SO20 (12+4+4) PowerSO20 ORDERING NUMBERS: L4938N (PDIP) L4938ND (SO) L4938NPD (PSO20) DESCRIPTION The L4938N is a monolithic integrated dual voltage regulatorswith two very low dropout outputsand additional functions such as power-on reset and input voltage sense. They are designedfor supplying microcomputer controlled systems specially in automotive applications. PIN CONNECTION (top view) POWERDIP N.C. 16 1 SO20 SI PowerSO20 N.C. 1 20 SI GND 1 20 GND C7 2 19 VS1 N.C. 2 19 N.C. CT 2 15 VS1 EN 3 18 VS2 3 18 EN 3 14 VS2 VS2 VO2 GND 4 17 GND VS1 4 17 ADJ GND 4 13 GND GND 5 16 GND SI 5 16 VO1 GND 5 12 GND GND 6 15 GND N.C. 6 15 SO RES 6 11 VO2 GND 7 14 GND CT 7 14 RESET SO 7 10 VO2 RES 8 13 VO2 EN 8 13 N.C. VO1 8 9 ADJ SO 9 12 VO2 N.C. 9 12 N.C. VO1 10 11 ADJ GND 10 11 GND D95AT156 D93AT004 April 1999 D95AT169A 1/12 This is advanced information on a new product now in development or undergoing evaluation. Details are subject to change without notice. L4938N - L4938ND - L4938NPD BLOCK DIAGRAM VS1 VO1 1.23V REFERENCE REG1 VO2 VS2 EN ADJ REG2 CT 1.23V 2µ RES 2.0V RESET SO SI SENSE (optional) 1.23V GND D94AT143A THERMAL DATA Symbol Rthj-case Rthj-amb 2/12 Parameter Thermal Resistance Junction-Case Thermal Resistance Junction-Ambient Max. Max. Powerdip PowerSO20 SO20 Unit 14 90 <2 – – 20 °C/W °C/W L4938N - L4938ND - L4938NPD ABSOLUTE MAXIMUM RATINGS Symbol VS Parameter Value Unit DC Supply Voltage 28 V Transient Supply Voltage (T < 1s) 40 V –55 to 150 °C ±1 mA Enable Input Current (VEN ≤0.3V) ±1 mA Enable Input Voltage VS VRES, V SO Reset and Sense Output Voltage 20 V IRES, ISO Reset and Sense Output Current 5 mA 875 mW Tj, Tstg Junction and Storage Temperature Range ISI Sense Input Current (VSI ≤0.3V or VSI > VS) IEN VEN PD Power Dissipation Note : The circuit is ESD protected according to MIL–STD–883C. APPLICATION CIRCUIT VS1 V O1 CS CO1 REFERENCE 1.23V REG1 V O2 VS2 ADJ EN CO2 REG2 CT 1.23V CT RES 2µ RRES VO1 2.0V RESET RSO SI SO SENSE (optional) 1.23V GND D94AT144A CS ≥ 1µF ; C01 ≥ 6µF ; C02 ≥ 10µF, ESR < 10Ω at 10KHz 3/12 L4938N - L4938ND - L4938NPD ELECTRICAL CHARACTERISTICS (VS = 14V; –40°C ≤ TJ ≤ 125°C unless otherwise specified) Symbol Parameter Test Conditions Min. VS Operating Supply Voltage V O1 Standby Output Voltage 6V ≤ VS ≤ 25V 1mA ≤ IO1 ≤ 50mA 4.90 Output Voltage 2 Tracking Error (note 1) 6V ≤ VS ≤ 25V 5mA ≤ IO2 ≤ 500mA Enable = LOW –25 –1 VO2 - VO1 Typ. Max. Unit 25 V 5.10 V +25 mV 0.1 1 µA 0.1 0.2 0.25 0.4 V V 0.4 V 0.3 0.6 V V 5.00 IADJ ADJ Input Current IO1 = 1mA; IO2 = 5mA VDP1 Dropout Voltage 1 IO1 = 10mA IO1 = 50mA V IO1 Input to Output Voltage Difference in Undervoltage Condition VS = 4V, I O1 = 35mA VDP2 Dropout Voltage 2 IO1 = 100mA IO1 = 500mA V IO2 Input to Output Voltage Difference in Undervoltage Condition VS = 4.6V, IO1 = 350mA 0.6 V VOL 1.2 Line Regulation 6V ≤ VS ≤ 25V IO1 = 1mA; IO2 = 5mA 20 mV VOLO1 Load Regulation 1 1mA ≤ IO1 ≤ 50mA 25 mV VOLO2 0.2 0.3 Load Regulation 2 5mA ≤ IO2 ≤ 500mA 50 mV ILIM1 Current Limit 1 VO1 = 4.5V VO1 = 0V (note 2) 55 25 100 50 200 100 mA mA ILIM2 Current Limit 2 VO2 = 0V 550 1000 1700 mA IQSB Quiescent Current Standby Mode IO1 = 0.3mA; T J < 100°C (output 2 disabled) VEN ≥ 2.4V VS = 14V VS = 3.5V 210 340 290 850 µA µA 30 mA IQ Quiescent Current IO1 = 50mA IO1 = 500mA ENABLE VENL Enable Input LOW Voltage (output 2 active) –0.3 1.5 V VENH Enable Input HIGH Voltage 2.4 7 V VENhyst IEN 4/12 Enable Hysteresis Enable Input Current 0V < VEN < 1.2V 2.5V < VEN < 7V 30 75 200 mV –10 –1 –1.5 0 –0.5 +1 µA µA L4938N - L4938ND - L4938NPD ELECTRICAL CHARACTERISTICS (continued) RESET Symbol Parameter VRt Reset Low Threshold Voltage VRth Reset Threshold Hysteresis Test Conditions Min. Typ. Max. Unit Vo1 -0.4 4.7 Vo1 -0.1 V 50 100 200 mV tRD Reset Pulse Delay CT = 100nF; tR > 100µs 55 100 180 mV tRR Reset Reaction Time CT = 100nF 1 10 50 µs VRL Reset Output LOW Voltage RRES = 10KΩ to V01 VS = 1.5V 0.4 V ILRES Reset Output HIGH Leakage VRES = 5V 1 µA VCTh Delay Comparator Threshold 2.0 V VCTh, hyst Delay Comparator Threshold Hysteresis 100 mV SENSE VSlth Sense Threshold Voltage VSlth, hyst Sense Threshold Hysteresis VSOL Sense Output LOW Voltage ILSO Sense Output Leakage 1.16 1.23 1.35 V 40 100 200 mV VSI = 1,16V; V S ≥ 3V RSO = 10KΩ to V01 0.4 V VSO = 5V; VSI ≥ 1.5V 1 µA Note : 1 : VO2 connected to ADJ.VO2 can be set to higher values by inserting an external resistor divider. 2 : Foldback characteristic FUNCTIONAL DESCRIPTION The L4938N is based on the STMicroelectronics modular voltage regulator approach. Several outstanding features and auxiliary functions are provided to meet the requirements of supplying the microprocessor systems used in automotive applications. Furthermore the device is suitable also in other applications requiring two stabilized voltages. The modular approach allows other features and functions to be realized easily when required. STANDBY REGULATOR The standby regulator uses an Isolated Collector Vertical PNP transistor as the regulating element. This structure allows a very low dropout voltage at currents up to 50mA. The dropout operation of the standby regulator is maintained down to 2V input supply voltage. The output voltage is regulated up to the transientinput supplyvoltageof 40V.This feature avoids functional interruptions which could be generated by overvoltage pulses. The typical curve of the standby output voltage as a functionof theinput supply voltage is shown in fig. 1. The current consumption of the device (quiescent current) is less than 250µA when output 2 is disabled (standby mode). The dropout voltage is controlled to reduce the quiescent current peak in the undervoltage region and to improve the transient response in this region. The quiescentcurrent isshown in fig. 2 as a function of the supply input voltage 2. OUTPUT 2 VOLTAGE The output 2 regulator uses the same output structure as the standbyregulator, but rated for anoutput current of 500mA. The output 2 regulatorworks in tracking mode with the standby output voltage as a reference voltage when the output 2 programming pin ADJ is connected to VO2. By connecting a resistor divider R1, R2 to the pin ADJ as shown in fig. 3, the output voltage 2 can be programmed to the value : VO2 = VO1 (1 + R1/R2) The output 2 regulator can be switched off via the Enable input. If a fixed 5 regulation is required ADJ Pin has to be connectedto V02 Pin. 5/12 L4938N - L4938ND - L4938NPD Figure 1 : Output Voltage vs. Input Voltage. Figure 2 : QuiescentCurrent vs. Supply Voltage. 400µ 200µ Figure 3 : Programmable Output 2 Voltage with External Resistors. 6/12 L4938N - L4938ND - L4938NPD RESET CIRCUIT Theblockcircuit diagramof theresetcircuit isshown in fig.4. The resetcircuit supervisesthe standbyoutput voltage. The reset threshold of 4.7V is defined by the internal reference voltage and the standby output divider. The reset pulse delay time tRD, is defined by the charge time of an external capacitor CT : CT x 2V tRD = 2µA Thereaction time of the reset circuit dependson the discharge time limitation of the reset capacitor CT and is proportional to the value of CT. The reaction time of the reset circuit increases the noise immunity. In fact,if the standbyoutputvoltage drops below the reset threshold for a time shorter than the reaction time tRR, no reset output variation occurs. The nominal reset delay is generated for standby output voltage drops longer than the time necessary for the complete discharging of the capacitor CT. This time is typically equal to 50µs if CT = 100nF.The typical reset outputwaveformsare shown in fig. 5. SENSE COMPARATOR This circuit comparesan input signal withan internal voltage reference of typically 1.23V. The use of an externalvoltage divider makes the comparatorvery flexible in the application. This function can be used to supervisethe input voltage - eitherbefore or after the protectiondiode - and togive additionalinformationtothe microprocessorsuch aslow voltagewarnings. If this feature is not used SI and SO have to connected to GND. In this case the St-by quiescent current (14V) increases from 290µA to 300µA. Figure 4: Block Diagram of the Reset Circuit. 7/12 L4938N - L4938ND - L4938NPD Figure 5 : Typical Reset Output Waveforms. 1.5V 8/12 L4938N - L4938ND - L4938NPD mm DIM. MIN. a1 0.51 B 0.85 b b1 TYP. inch MAX. MIN. TYP. MAX. 0.020 1.40 0.033 0.50 0.38 0.055 0.020 0.50 D 0.015 0.020 20.0 0.787 E 8.80 0.346 e 2.54 0.100 e3 17.78 0.700 F 7.10 0.280 I 5.10 0.201 L Z OUTLINE AND MECHANICAL DATA 3.30 0.130 1.27 Powerdip 16 0.050 9/12 L4938N - L4938ND - L4938NPD DIM. A a1 a2 a3 b c D (1) D1 E e e3 E1 (1) E2 E3 G H h L N S T MIN. mm TYP. 0.1 0 0.4 0.23 15.8 9.4 13.9 MAX. 3.6 0.3 3.3 0.1 0.53 0.32 16 9.8 14.5 MIN. 0.004 0.000 0.016 0.009 0.622 0.370 0.547 1.27 11.43 10.9 inch TYP. 0.050 0.450 11.1 0.429 2.9 6.2 0.228 0.1 0.000 15.9 0.610 1.1 1.1 0.031 10° (max.) 8° (max.) 5.8 0 15.5 0.8 OUTLINE AND MECHANICAL DATA MAX. 0.142 0.012 0.130 0.004 0.021 0.013 0.630 0.386 0.570 10 0.437 0.114 0.244 0.004 0.626 0.043 0.043 JEDEC MO-166 0.394 PowerSO20 (1) ”D and F” do not include mold flash or protrusions. - Mold flash or protrusions shall not exceed 0.15 mm (0.006”). - Critical dimensions: ”E”, ”G” and ”a3” N R N a2 b A e DETAIL A c a1 DETAIL B E e3 H DETAIL A lead D slug a3 DETAIL B 20 11 0.35 Gage Plane - C- S SEATING PLANE L G E2 E1 BOTTOM VIEW T E3 1 h x 45 10/12 10 PSO20MEC C (COPLANARITY) D1 L4938N - L4938ND - L4938NPD mm DIM. MIN. TYP. inch MAX. MIN. TYP. MAX. A 2.35 2.65 0.093 0.104 A1 0.1 0.3 0.004 0.012 B 0.33 0.51 0.013 0.020 C 0.23 0.32 0.009 0.013 D 12.6 13 0.496 0.512 E 7.4 7.6 0.291 0.299 e 1.27 OUTLINE AND MECHANICAL DATA 0.050 H 10 10.65 0.394 0.419 h 0.25 0.75 0.010 0.030 L 0.4 1.27 0.016 0.050 SO20 K 0° (min.)8° (max.) L h x 45° A B e A1 K C H D 20 11 E 1 1 0 SO20MEC 11/12 L4938N - L4938ND - L4938NPD Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics 1999 STMicroelectronics – Printed in Italy – All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - France - Germany - Italy - Japan - Korea - Malaysia - Malta - Mexico - Morocco - The Netherlands Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A. http://www.st.com 12/12