L6275 5V DISK DRIVE SPINDLE & VCM, POWER & CONTROL “COMBO” PRODUCT PREVIEW GENERAL 5V (+/- 10%) OPERATION. REGISTER BASED ARCHITECTURE MINIMUM EXTERNAL COMPONENTS BICMOS + VERTICAL DMOS (1.5mm) VCM DRIVER 1.5A DRIVE CAPABILITY 0.9Ω TOTAL BRIDGE IMPEDANCE AT 25°C LINEAR MODE PHASE SHIFT MODULATION (PWM MODE) INSTANTANEOUS, (GLICH FREE) SWITCH BETWEEN THE 2 MODES CLASS AB OUTPUT DRIVERS ZERO CROSSOVER DISTORSION 14 BIT DAC DEFINE OUTPUT CURRENT SELECTABLE TRANSCONDUCTANCE 4 PROGRAMMABLE PARKING VOLTAGE DYNAMIC BRAKE SPINDLE DRIVER 2.0A DRIVE CAPABILITY 0.8Ω TOTAL BRIDGE IMPEDANCE AT 25°C BEMF, INTERNAL OR EXTERNAL, PROCESSING SENSOR-LESS MOTOR COMMUTATION PROGRAMMABLE COMMUTATION PHASE DELAY LINEAR MODE AND CONSTANT TOFF PWM OPERATION MODE INTERNAL FREQUENCY LOCKED LOOP SPEED CONTROL (FLL) BEMF RECTIFICATION DURING RETRACT BUILT-IN ALIGNAMENT&GO START-UP INDUCTIVE SENSING START UP OPTION RESYNCHRONIZATION DYNAMIC & REVERSE BRAKE CONTROLLABLE OUTPUT SLEW RATE OTHER FUNCTIONS 5V MONITORING WITH EXTERNAL SET TRIP POINTS AND HYSTERESIS POWER UP/DOWN SEQUENCING LOW VOLTAGE SENSE BICMOS TECHNOLOGY TQFP44 (10x10mm) ORDERING NUMBER: L6275 3.3V INPUT LOGIC COMPATIBILITY THERMAL SHUTDOWN AND PRETHERMAL WARNING SYSTEM CLOCK WATCHDOG DESCRIPTION The L6275 integrates into a single chip both spindle and VCM controllers as well as power stages. The device is designed for 12V disk drive application requiring up to 2.0A of spindle and 1.5A of VCM peak currents. A serial port with up to 25 MHz capability provides easy interface to the microprocessor. A register controlled Frequency Locked Loop (FLL) allows flexibility in setting the spindle speed. Integrated BEMF processing, digital masking, digital delay, and sequencing minimize the number of external components required. Power On Reset (POR) circuitry is included. Upon detection of a low voltage condition, POR is asserted, the internal registers are reset, and spindle power circuitry is tri-stated. The BEMF is rectified providing power for actuator retraction followed by dynamic spindle braking. The device is built in BICMOS technology allowing dense digital/analog circuitry to be combined with a high power DMOS output stage. April 1999 This is preliminary information on a new product now in development. Details are subject to change without notice. 1/17 L6275 CS FREQUENCY LOCK LOOP CHARGE PUMP VDD PWM/SLEW BRK_CAP SPN_COMP FCOM SYS_CLK INDEX FLL_FILTER CP FLL_RES BLOCK DIAGRAM SPINDLE SEQUENCER A OUT_A CTAP START-UP SW1 ISO DRIVER RE_SYNC B ZERO CROSS DETECTION C DYNAMIC/ REVERSE BRAKE SDATA SCLK BEMF PROCESSING SERIAL INTERFACE REGISTERS OUT_B RSENSE OUT_C ISENSE SPINDLE CURRENT CONTROL PWM/LIN VCM CURRENT CONTROL PSM/LIN A+ PARKING VCM_A+ VDD SDEN VCM CALIBRATION BEMF RECTIFICATION A- VCM_AVCM_GND THERMAL SENSE_OUT - ERROR_IN DAC DGND VDD GND PORB POR_DELAY A=4 + + REFERENCE VOLTAGE GENERATOR 14 BIT VCM DAC SUPPLY ERROR_OUT SUPPLY & CLOCK FAULT MONITORS VCM_CAL TR_5V V5/2 CLK_MON 44 43 42 41 40 2/17 PORB TR_5V POR_DELAY SENSE_OUT ERROR_OUT ERROR_IN CLK_MON DAC AGND VDD SPN_COMP PIN CONNECTION 39 38 37 36 35 34 SW1 2 32 FLL_RES PWM/SLEW 3 31 VDD OUT_C 4 30 VCM_A+ I_SENSE 5 29 SENSE_IN- R_SENSE 6 28 VCM_GND OUT_B 7 27 SENSE_IN+ GND 8 26 VCM_A- R_SENSE 9 25 VDD OUT_A 10 24 CS INDEX 11 23 CP VCM_CAL FLL_FILTER V5/2 VDD SCLK SDEN SYS_CLK VDD 17 18 19 20 21 22 DGND 12 13 14 15 16 SDATA 33 CTAP BRK_CAP FCOM 1 D99IN1051 SENSE_INSENSE_IN+ D99IN1050 L6275 PIN DESCRIPTION (Pin Types: D = Digital, P = Power, A = Analog) N. Name 1 FCOM 2 CTAP 3 PWM/SLEW Function Output of the Spindle zero cross or Current Sense circuit. Spindle Central Tap used for differential BEMF sensing. RC network sets the Spindle Linear Slew Rate and PWM OFF-Tim e. 4 OUT_C 5 I_SENSE Input to sense the voltage the SPINDLE Sense Resistor. Spindle DMOS Half Bridge Output and Input C for BEMF sensing. 6 R_SENSE Output connection for the Motor Current Sense Resistor to ground. 7 OUT_B 8 GND 9 R_SENSE 10 OUT_A Spindle DMOS Half Bridge Output and Input A for BEMF sensing. 11 INDEX Input to allow Spindle to be locked to Index (servo) pulse. 12 BRK_CAP 13 VDD Spindle DMOS Half Bridge Output and Input B for BEMF sensing. Spindle Ground (Substrate). Output connection for the Motor Current Sense Resistor to ground. Storage Capacitor for brake circuit. typically 5.9V. +5V Power Supply for Spindle Power section. 14 DGND 15 SYS_CLK 16 SDEN Serial Data Enable. Active high input pin for the serial port enable. 17 SDATA Serial Port Data. Input/Output pin for serial data, 8bits of instruction/address followed by 8 bits of data. Open pin is at logic low as an input. 18 SCLK Serial Port Data Clock. Positive edge triggered clock input for the serial data. 19 VDD Digital/Analog power supply. +5V nominally. 20 V12/2 Reference Output for VCM control loop. Typically, half of the VCC except when parking. 21 FLL_FILTER 22 VCM_CAL 23 CP 24 CS 25 VDD Digital Ground. Clock Frequency for system timers and counters. Speed loop R/C compensation connection used for FLL mode operation. VCM loop offset voltage used for calibration. External Main Charge Pump Capacitor, Typically, Vz+Vcc is about 17.8V External Charge Pump Capacitor. +5V Power Supply for VCM Power section. 26 VCM_A- 27 SENSE_IN+ VCM Power Amplifier negative output terminal. Non inverting Input of the Sense Amplifier for VCM block. 28 VCM_GND Ground for VCM Power section. 29 SENSE_IN- Inverting Input of the Sense Amplifier for VCM block. 30 VCM_A+ 31 VDD 32 FLL_RES 33 SW1 VCM Power Amplifier positive output terminal. +5V Power Supply for VCM Power section. Resistor for setting accurate bias current sources for the chip (62K required). External ISOFET driver. 34 PORB Power on Reset Output. Low signal indicates the failure of the supplies. 35 TR_5V Set Point Input for 5V Supply Monitor ( 2V threshold, 100mV Hysteresis) 36 POR_DELAY Capacitor connection to set the Power on Reset Delay (3V threshold, 2µA charging) 37 SENSE_OUT Output of the Sense Amplifier. 38 ERROR_OUT Output of the Error Amplifier. 39 ERROR_IN 40 CLK_MON 41 DAC 42 AGND 43 VCC 44 SPN_COMP Inverting Input of the Error Amplifier. Watchdog clock monitoring pin Output of the VCM DAC. Analog Ground. For bang gap voltage reference. +12V Power Supply for Spindle Power section. External RC network that defines the compensation of the Spindle Transconductance Loop in Linear Mode. 3/17 L6275 ABSOLUTE MAXIMUM RATINGS Symbol Parameter Value Unit VCC Maximum Supply voltage -0.5 to 14 V Vdd Maximum Logic supply -0.5 to 6 V Vin max Maximum digital input voltage Vdd +0.3V V Vin min Minimum digital input voltage GND - 0.3V V 2.1 A SPINDLE Ipeak VCM Ipeak Spindle peak sink/source output current VCM peak sink/source output current Ptot (*) Maximum Total Power Dissipation Tstg, Tj Maximum Storage/Junction Temperature 1.6 A ≈ 1.7 W -40 to 150 °C Value Unit THERMAL DATA Symbol Rth j-case Rth j-amb (*) Parameter Thermal Resistance Junction to Case ≈ 20 °C/W Thermal Resistance to Junction to ambient ≈ 40 °C/W Value Unit (*) In typical application with multilayer 120X120mm Printed Circuit Board RECOMMENDED OPERATING CONDITIONS Symbol Parameter Vdd Supply Voltage 4.5 to 5.5 V Tamb Operating Ambient Temperature 0 to 70 °C Junction Temperature 0 to 125 °C Tj ELECTRICAL CHARACTERISTICS (All specifications are for 0 < Tamb < 70°C, VCC = 12V; VDD = 5V, FLL_RES = 62kΩ, unless otherwise specified.) Symbol Parameter Test Condition Min. Typ. Max. Unit POWER SUPPLIES Vrectified VCC Supply Rectified 3.5 13.2 V V dd 5V supply 4.5 5.5 V IVdd 5V supply SPINDLE + VCM 6 mA SPINDLE ONLY 7 mA VCM ONLY 12 mA THERMAL SENSING 4/17 TSD Shutdown Temperature THYS Hysteresis TEW Early Warning 150 180 °C 60 °C TSD-25 °C L6275 ELECTRICAL CHARACTERISTICS (Continued) Symbol Parameter Test Condition Min. Typ. Max. Unit 1.92 2 2.08 V SUPPLY MONITOR V TR Trip Point Input Rising VHYS Hysteresis Voltage Input falling IDLY Porb Delay Current TR_5V, TR_12V > VTR Vpordly = 2V R on_por Porb Pull Down Ron Vdd > 2V and sink 1mA Vpordly = 2V VDLY Porb Dly Threshold TR_5V > VTR Input Current VIN < 4V IIN 100 1.5 2 mV 2.5 µA 500 Ω 2.0 -1 V 1 µA VOLTAGE BOOST VBOOST Fosc Output Voltage Vdd+5 Internal Oscillator Vdd+6.3 V 130 200 250 kHz 7 10 13 µs SYSTEM CLOCK WATCHDOG Min_Clk Min. System Clock Time SW1 OUTPUT RGATE Gate Driver for External Mosfet Internal Resistor to CP VGATE Off Gate State Voltage for External Mosfet IO = 1mA Vdd = 3.5V 200 kΩ 0.7 V DIGITAL LOGIC LEVELS VIH Input Logic ”1” V IL Input Logic ”0” VOH Output Logic ”1” ISOURCE = 20µA V OL Output Logic ”0” ISOURCE = -400µA F SYSCLK 2.5 V 0.5 Vdd-0.2 V V System Clock 20 Resolution 14 0.4 V 25 MHz VCM, DAC Differential Linearity 1 LSB Change - Tested - By design Integral Linearity Midscale Offset TC -1 -0.5 1 0.5 9 Referenced to VCC/2 -5 5 mV 5 µs 4 % ±1 Referenced to VCC/2 Full Scale Error -4 LSB Bits Convertion Time Full Scale Voltage Bits V VCM, ERROR AMPLIFIER AVOL Open Loop Gain VOS Input Offset Voltage IIB VICM DC 50 -5 db 5 mV Input Bias Current --250 250 nA Input Common Mode Range VCC/20.5 VCC/2+ 0.5 V 5/17 L6275 ELECTRICAL CHARACTERISTICS (Continued) Symbol Parameter Vclamp Output Clamp Voltage FODB Unity Gain Bandwidth Test Condition Min. -1mA < IO < 1mA Lowside/Highside clamp Typ. Max. Unit Vdd/2± 1.4V V 10 MHz VCM, POWER STAGE RDS(ON) IO IO(LEAK) Output ON Resistance (Each device) 0.5 0.8 1.3 A VCC = 5.5V 1.0 mA 4.12 V/V -0.3 Vdd+0.3 V 2 Vdd-2 V -15 15 mV Operating Current Output Leakage Current Ω Ω Tj = 25°C Tj = 125°C VCM, CURRENT SENSE AMPLIFIER AV Voltage Gain 3.88 VICM Input Common Mode Range VOCM Output Common Mode Range -3mA < IO < 3mA VOS Output Offset Voltage SENSE_IN (±) = Vdd/2 F3dB 3dB Bandwidth 4 1 MHz CMRR Input Common Mode Rejection 50 dB PSRR Power Supply Rejection Ratio 60 dB VCM, RETRACT Vpark Tretract RETRACT VOLTAGE PKV_1 = 0 & PKV_2 = 0 PKV_1 = 0 & PKV_2 = 1 PKV_1 = 1 & PKV_2 = 0 PKV_1 = 1 & PKV_2 = 1 Retract Time limited by the internal oscillator 200kHz RT0 = 0 & RT1 RT0 = 0 & RT1 RT0 = 1 & RT1 RT0 = 1 & RT1 =0 =1 =0 =1 0.850 0.650 1.600 1.150 mV mV mV mV 160 320 80 160 ms ms ms ms SPINDLE, PWM CURRENT SENSE COMPARATOR TDLY Delay to FCOM Out 200 500 ns Tj = 25°C Tj = 125°C 0.45 0.74 Ω Ω 2 A 1.0 mA 0.5 V/µs SPINDLE, POWER STAGE RDS(ON) IO Output On Resistance (Each device) Start-Up Current IO(LEAK) Output Leakage Current VCC = 14V dVO/dt Output Slew Rate (Linear) Rslew = 100kΩ Output Slew Rate (PWM) Reg#8Eh, Bit 0 = 0 Reg#8Eh, Bit 0 = 1 BEMFMIN VHYS Minimum BENF Voltage for Detection 0.2 0.3 10 20 20 Hysteresis 28 V/µs V/µs 40 15 mVp-p mV FLL CHARGE PUMP OUTPUT ILEAK Off State Leakage 0 < Vfll_res , 3V -50 IO On State Current FLL_RES = 62kΩ ICP = ”1” ICP = ”0” 22 80 FLL_RES = 62kΩ 1.18 VRCP 6/17 Current Set Voltage +50 nA 25 100 32 120 µA µA 1.225 1.25 V L6275 ELECTRICAL CHARACTERISTICS (Continued) Symbol Parameter Test Condition Min. Typ. Max. Unit CURRENT SENSE AMPLIFIER IBIAS Av dVo/dt 2 µA 4.2 V/V Input Bias Current Voltage Gain 3.8 4.0 Output Slew Rate 20 V/µs SERIAL PORT Symbol Parameter Min. Typ. Max. Unit TSCK SCLK Period 40 ns TCKL SCLK low time 15 ns TCKH SCLK high time 15 ns TSDENS Enable to SCLK 35 ns TSDENH SCLK to disable 20 ns TDS Data set-up time before rising edge SCLK 10 ns TDH Data Hold Time 10 ns Minimum SDEN Low Time 50 ns TSDV SCLK falling edge (A6) to SDATA valid on READ op. 3 10 ns TSDV SCLK rising edge (D0-D7) to SDATA Transition on READ op. 5 35 ns TSDENL Figure 1. Serial Port Timing Information. SDEN SCLK SDATA 0 A0 A1 A6 D0 D1 1st Byte D2 D7 2nd Byte SERIAL PORT WRITE TIMING SDEN SCLK SDATA 1 A0 A1 A6 D0 D1 1st Byte D2 D7 2nd Byte SERIAL PORT READ TIMING D98IN844 7/17 L6275 SERIAL PORT OPERATION The serial port interface is a bi-directional port for reading and writing programming data from/to the internal registers of this device. For data transfers SDEN* is brought high, serial data is presented at the SDATA pin, and a serial clock is applied to the SCLK pin. After the SDEN* goes high , the first 16 pulses applied to the SCLK pin will shift the data presented at the SDATA pin into an internal shift register on the rising edge of each clock. An internal counter prevents more than 16 bits from being shifted into the register. The data in the shift register is latched after the 16th SCLK pulse. If less than 16 clock pulses are provided before SDEN* goes low, the data transfer is aborted. All transfers are shifted into the serial port LSB first. The first byte of the transfer is for R/W and address and instruction information. The first bit is R/W instruction bit, 0 is for WRITE and 1 is for READ. Following 7 bits are Address. Figure 2. Serial Port Data Transfer Format. SDEN INSTRUCTION, 1 BIT ADDRESS, 7 BITS SDATA DATA, 8 BITS SCLK D98IN845 INTERNAL REGISTER DEFINITION Reg: Name: Type: Address: 0 VCM DAC (High) Register Write only 0Eh BIT LABEL DESCRIPTION 0 VDAC BIT8 VCM DAC bit 8 1 VDAC BIT9 VCM DAC bit 9 2 VDAC BIT10 VCM DAC bit 10 3 VDAC BIT11 VCM DAC bit 11 4 VDAC BIT12 VCM DAC bit 12 5 VDAC BIT13 MSB resistor ladder of the 14 bit VCM DAC 6 PSM/LINEAR Selects Voice Coil PSM or Linear Output Current Control. 1=PSM 0=Linear. 7 VCM_CAL VCM calibration. 1 = Enables VCM control circuits and tristates VCM power transistors. 8/17 L6275 INTERNAL REGISTER DEFINITION VCM DAC (High and Low) Registers Bit 0 through 5 of the VCM DAC (High) Registers and bit 0 through 7 of the VCM DAC (Low) Registers control the absolute value of the voice coil current. Bit is the sign bit, controlling the current direction. All the 13 bits are part of a resistor divider network. Note. It is required to write on register 1 to make effective changes on register 0. Reg: Name: Type: Address: 1 VCM DAC (Low) Registers Write only 1Eh BIT LABEL DESCRIPTION 0 VDAC BIT0 LSB resistor ladder of the 14 bit VCM DAC 1 VDAC BIT1 VCM DAC bit 1 2 VDAC BIT2 VCM DAC bit2 3 VDAC BIT3 VCM DAC bit3 4 VDAC BIT4 VCM DAC bit4 5 VDAC BIT5 VCM DAC bit5 6 VDAC BIT6 VCM DAC bit6 7 VDAC BIT7 VCM DAC bit7 Reg: Name: Type: Address: 2 Spindle Control Register Write only 2Eh BIT LABEL DESCRIPTION 0 INCRE_SEQ A 0 to 1 transition of this bit increments the spindle Sequencer. 1 START_UP 1 = Spindle Internal start up, 0 = Spindle External start up 2 R_SEQ Reset Spindle sequencer. 1 = Reset sequencer to phase 1. 3 RUN 1 = Start Spindle ALIGN & GO, 0 = Reset Spindle control logic. 4 SPIN_EN Enable Spindle section. 1 = Enable, 0 = Disable. 5 MEC/ELEC Specifies electrical or mechanical cycle for Spindle FLL control. 1=Electrical, 0 = Mechanical. 6 PWM/LINEAR Selects Spindle PWM or Linear Output Current Control. 1 = PWM, 0=Linear. 7 EXT/INT External or internal Spindle loop feedback. 1 = external feedback via index pin. 9/17 L6275 INTERNAL REGISTER DEFINITION Reg: Name: Type: Address: 3 Spindle Delay Register Write only 3Eh BIT LABEL DESCRIPTION 0 MASK_TIME Spindle BEMF Mask Time. 0 = 15 degree, 1 = 7.5 degree 1 MIN2 Control Spindle PWM on time 2 Min 1 Min2 Min. on Time 0 0 5.9µs 0 1 1.4µs 1 0 12µs 1 1 5.21µs MIN1 3 8_12_POLE Selects 8 or 12 pole motors. 1 = 8 pole, 0 = 12 pole. 4 SD3 Spindle commutation delay MSB 5 SD2 Spindle commutation delay bit 6 SD1 Spindle commutation delay bit 7 SD0 Spindle commutation delay LSB SPINDLE PHASE DELAY SD3-0 set the phase delay from BEMF zero crossing to the next commutation. The 30 theoretical degree value can be changed to compensate for switching and other delays that are always present. The delay adjustment range is from 1.875 through to 30 electrical degrees in 1.875 degree increments. Reg: Name: Type: Address: 4 FLL Coarse Counter Register Write only 4Eh BIT LABEL DESCRIPTION 0 C4 Bit 4 of Spindle FLL Coarse Counter 1 C5 Bit 5 of Spindle FLL Coarse Counter 2 C6 Bit 6 of Spindle FLL Coarse Counter 3 C7 Bit 7 of Spindle FLL Coarse Counter 4 C8 Bit 8 of Spindle FLL Coarse Counter 5 C9 Bit 9 of Spindle FLL Coarse Counter 6 C10 Bit 10 of Spindle FLL Coarse Counter 7 C11 MSB of Spindle FLL Coarse Counter 10/17 L6275 INTERNAL REGISTER DEFINITION Reg: Name: Type: Address: 5 FLL Coarse/Fine Counter Register Write only 5Eh BIT LABEL DESCRIPTION 0 F8 Bit 8 of Spindle FLL Fine Counter 1 F9 Bit 9 of Spindle FLL Fine Counter 2 F10 MSB of Spindle FLL Fine Counter 3 Unused. Set = 0 4 C0 LSB of Spindle FLL Coarse Counter 5 C1 Bit 1 of Spindle FLL Coarse Counter 6 C2 Bit 2 of Spindle FLL Coarse Counter 7 C3 Bit 3 of Spindle FLL Coarse Counter Reg: Name: Type: Address: 6 FLL Fine Counter Register Write only 6Eh BIT LABEL DESCRIPTION 0 F0 LSB of Spindle FLL Fine Counter 1 F1 Bit 1 of Spindle FLL Fine Counter 2 F2 Bit 2 of Spindle FLL Fine Counter 3 F3 Bit 3 of Spindle FLL Fine Counter 4 F4 Bit 4 of Spindle FLL Fine Counter 5 F5 Bit 5 of Spindle FLL Fine Counter 6 F6 Bit 6 of Spindle FLL Fine Counter 7 F7 Bit 7 of Spindle FLL Fine Counter 11/17 L6275 INTERNAL REGISTER DEFINITION Reg: Name: Type: Address: 7 Spindle Status Register Read only 7Eh BIT LABEL DESCRIPTION 0 THERMAL Thermal Shutdown = 0 indicates that the chip temperature has exceeded 160°C. The bit will reset (=1) when the temperature falls below 130°C. When Thermal Shutdown =0, the spindle logic will tristate both high and low side drivers, protecting the output circuitry. 1 THERM_WARN Thermal Shutdown Warning =0 indicates that the chip temperature is approximately 25°C before the device goes in thermal shut down. 2 ROTOR_STUCK 0 = A sequential Spindle BEMF has not been detected 3 FAULT 1 = Rapid deceleration of the Spindle motor or High frequency on FCOM signal. 4 MASK_TIME Mask Time toggled to ”0” indicates that the Spindle BEMF is masked. 5 ERROR_LOCK 0 = Indicates error Spindle speed > 16msec/sample, either electrical or mechanical. 6 ALIGN 0 indicate that the Spindle is in the Internal Start-Up Align Phase. 7 GO 0 indicate that the Spindle is in the Internal Start-Up Go Phase. Reg: Name: Type: Address: 8 Spindle FLL Register Write only 8Eh BIT LABEL DESCRIPTION 0 SSLEW Spindle PWM (chopping) Slew Rate. 0 = 10VµS, 1 = 20Vµs 1 ICP Spindle FLL Charge pump current. 1= 25µA, 0 = 100µA. 2 Unused. Set = 0. 3 ISNS 1 = Puts output of the Spindle sense amplifier on FCOM pin and changes limit to roughly 1/3 of normal. 4 IL1 Adjust maximum voltage on Spindle Rsense 5 IL0 Adjust maximum voltage on Spindle Rsense 6 CPL 1 = Spindle FLL Charge pump low 7 CPH 1 = Spindle FLL Charge pump high 12/17 ”IL0” ”IL1” ”ISNS” V(I_SENSE) LIMIT (±10%) 0 0 0 0.45V 1 0 0 0.50V 0 1 0 0.55V 1 1 0 0.75V 0 0 1 0.15V 1 0 1 0.20V 0 1 1 0.25V 1 1 1 0.30V L6275 INTERNAL REGISTER DEFINITION Reg: Name: Type: Address: 9 System Control Register Write only 9Eh BIT LABEL DESCRIPTION 0 PKV_1 VCM Parking Voltage 1 PKV_2 VCM Parking Voltage 2 VR 1 = connects internal VR reference (2V) to level shift Opamp (for Vcm calibration). 3 RT0 (*) VCM Retract Time 4 DOUBLE 1 = Spindle Internal Start-Up Align and Energization time doubled. 5 VCM_EN Enable VCM section. 1 = Enable, 0 = Disable. 6 RT1 (*) VCM Retract Time 7 RETRACT 1= VCM retract ”PKV_1” ”PKV_2” ”PARKING VOLTAGE” 0 0 0.850V 0 1 0.650V 1 0 1.600V 1 1 1.150V ”RT0” ”RT1” ”RETRACT TIME” 0 0 160ms 0 1 320ms 1 0 80ms 1 1 160ms (*) When program Retract Time (RT0 and RT1), Bit 2 REG#8Eh must be always written to 0. 13/17 L6275 INTERNAL REGISTER DEFINITION Reg: Name: Type: Address: 10 Test Control Register Write only AEh BIT LABEL DESCRIPTION 0 Unused. Set = 0 1 Unused. Set = 0 2 Unused. Set = 0 3 Unused. Set = 0 4 FLL_OUT 1 = Spindle Mech/Elec (see bit 5 register 2) output, 0 = Spindle zero crossing output. 5 REV_BRAKE Spindle Reverse Brake command. 1 = Brake. “0” has to be reinserted to enable the spindle start up. 6 Unused. Set = 0 7 VB/DIS Reg: Name: Type: Address: 1 = Disable Vboost 11 VCM Control Register Write only BEh BIT LABEL DESCRIPTION 0 VCMS VCM PSM (chopping) Slew Rate. 0 = 10V/µs, 1 = 20V/µs 1 VCMH 1 = Forces VCM outputs to be High in PSM mode. 2 SLEEP Unused (for future power saving mode). 3 COMSLEW Spindle PWM (phase commutation) Slew Rate. 0 = 30Vµs, 1 = 2Vµs. 4 Unused. Set = 0 5 1 = Tristate the VCM outputs for half of the Retract Time during retract. 6 1 = Brakes the VCM outputs for half of the Retract Time during retract. 7 Unused. Set = 0 14/17 L6275 INTERNAL REGISTER DEFINITION Reg: Name: Type: Address: 12 Chip ID Register Read only FFh BIT LABEL DESCRIPTION 0 ID_REV_0 Minor Revision Bit 0. 1 ID_REV_1 Minor Revision Bit 1. 2 ID_REV_2 Minor Revision Bit 2. 3 ID_REV_3 Minor Revision Bit 3. 4 ID_REV_4 Minor Revision Bit 0. 5 ID_REV_5 Minor Revision Bit 1. 6 ID_REV_6 Minor Revision Bit 2. 7 ID_REV_7 Minor Revision Bit 3. Figure 3. Application Circuit. 5V_VDD STN4NE03 VCC 0.3(1W) 22µF 16V (1) 20µH 22µF 16V (1) 1Ω 1µF VCC 2N2222 1N4148 CS CP SW1 100nF POR_DELAY 2.2µF BRK_CAP 220pF(3) PWM/SLEW 51K CTAP OUT_A OUT_B OUT_C 100nF DGND RSENSE 13,43 ISENSE 6,9 CTAP 5 OUT_A 2 OUT_B 10 OUT_C 7 4 24 26 27 23 30 33 29 36 21 12 32 10nF(4) AGND 12V_VCC 5K(4) CLK_MON 15K GND 5V_VDD 20K VDD 22µF 16V (1) 25,31 44 11 42 1 34 40 VCM_A+ SENSE_IN1µF FLL-FILTER 620K FLL_RES VCC 100nF VCC INDEX INDEX FCOM FCOM 4.7K PORB 5V_VDD PORB 8 15 19 18 100nF 17 TR_5V 0.25(1W) VCM_A+ 62K 14 35 16 22 20 VCM_CAL V12/2 18.2K VCM_A- SENSE_IN+ 3 5K(4) SPN_COMP VCM_A- 41 DAC 39 ERROR_IN 10K 38 37 ERROR_OUT SENSE_OUT 62K 10K SYS_CLK SCLK SYS_CLK SCLK SDATA SDATA SDEN SDEN 28 VCM_GND D99IN1052 1nF Voice Coil Ground Analog Ground Power Ground Digital Ground (1) (2) (3) (4) This capacitor must be Tantalum Place these components close to thedevice Do not mount this component if Spindle Linear mode is used Do not mount this component if Spindle Pwm mode is used 15/17 L6275 mm DIM. MIN. TYP. A inch MAX. MIN. TYP. 1.60 A1 0.05 A2 1.35 B 0.30 C 0.09 0.063 0.15 0.002 1.40 1.45 0.053 0.055 0.057 0.37 0.45 0.012 0.014 0.018 0.20 0.004 0.006 0.008 D 12.00 0.472 D1 10.00 0.394 D3 8.00 0.315 e 0.80 0.031 E 12.00 0.472 E1 10.00 0.394 E3 8.00 0.315 L 0.45 0.60 0.75 OUTLINE AND MECHANICAL DATA MAX. 0.018 0.024 L1 1.00 K 0°(min.), 3.5°(typ.), 7°(max.) 0.030 0.039 TQFP44 (10 x 10) D D1 A A2 A1 33 23 34 22 0.10mm .004 B E B E1 Seating Plane 12 44 11 1 C L e K TQFP4410 16/17 L6275 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics 1999 STMicroelectronics – Printed in Italy – All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - France - Germany - Italy - Japan - Korea - Malaysia - Malta - Mexico - Morocco - The Netherlands Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A. http://www.st.com 17/17