M28C16B M28C17B 16 Kbit (2K x 8) Parallel EEPROM With Software Data Protection PRELIMINARY DATA ■ Fast Access Time: 90 ns at VCC=5V ■ Single Supply Voltage: – 4.5 V to 5.5 V for M28CxxB – 2.7 V to 3.6 V for M28CxxB-W ■ Low Power Consumption ■ Fast BYTE and PAGE WRITE (up to 64 Bytes) – 3 ms at VCC=4.5 V – 5 ms at VCC=2.7 V ■ Enhanced Write Detection and Monitoring: – Data Polling PLCC32 (K) – Toggle Bit – Page Load Timer Status ■ JEDEC Approved Bytewide Pin-Out ■ Software Data Protection ■ 100000 Erase/Write Cycles (minimum) ■ Data Retention (minimum): 40 Years DESCRIPTION The M28C16B and M28C17B devices consist of 2048x8 bits of low power, parallel EEPROM, fabricated with STMicroelectronics’ proprietary single polysilicon CMOS technology. The devices offer fast access time, with low power dissipation, and require a single voltage supply. Figure 1. Logic Diagram VCC Table 1. Signal Names A0-A10 Address Input DQ0-DQ7 Data Input / Output W Write Enable E Chip Enable G Output Enable RB Ready/Busy (M28C17B only) VCC Supply Voltage VSS Ground 11 8 A0-A10 W DQ0-DQ7 M28C16B M28C17B E RB (M28C17B only) G VSS AI02816 February 1999 This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice. 1/17 M28C16B, M28C17B A7 NC NC RB VCC W NC Figure 2B. PLLC Connections NC NC VCC W NC A7 NC Figure 2A. PLLC Connections 1 32 A6 A5 A4 A3 A2 A1 A0 NC DQ0 9 M28C16B 1 32 25 A8 A9 NC NC G A10 E DQ7 DQ6 A6 A5 A4 A3 A2 A1 A0 NC DQ0 9 M28C17B DQ1 DQ2 VSS NC DQ3 DQ4 DQ5 17 DQ1 DQ2 VSS NC DQ3 DQ4 DQ5 17 25 A8 A9 NC NC G A10 E DQ7 DQ6 AI02817 AI02830 Note: 1. NC = Not Connected Note: 1. NC = Not Connected The M28C17B is like the M28C16B in every way, except that it has an extra ready/busy (RB) output. The device has been designed to offer a flexible microcontroller interface, featuring software handshaking, with Data Polling and Toggle Bit. The device supports a 64 byte Page Write operation. Software Data Protection (SDP) is also supported, using the standard JEDEC algorithm. DEVICE OPERATION In order to prevent data corruption and inadvertent write operations, an internal VCC comparator inhibits the Write operations if the V CC voltage is lower than V WI (see Table 4A). Once the voltage applied on the VCC pin goes over the VWI threshold (V CC>VWI), write access to the memory is allowed after a time-out t PUW, as specified in Table 4A. Further protection against data corruption is offered by the E and W low pass filters: any glitch, on the E and W inputs, with a pulse width less than 10 ns (typical) is internally filtered out to prevent inadvertent write operations to the memory. Read The device is accessed like a static RAM. When E and G are low, and W is high, the contents of the addressed location are presented on the I/O pins. Otherwise, when either G or E is high, the I/O pins revert to their high impedance state. Write Write operations are initiated when both W and E are low and G is high. The device supports both W-controlled and E-controlled write cycles (as shown in Figure 11 and Figure 12). The address is latched during the falling edge of W or E (which ever occurs later) and the data is latched on the rising edge of W or E (which ever occurs first). After a delay, tWLQ5H, that cannot be shorter than the value specified in Table 10A, the internal write cycle starts. It continues, under internal timing control, until the write operation is complete. The commencement of this period can be detected by reading the Page Load Timer Status on DQ5. The SIGNAL DESCRIPTION The external connections to the device are summarized in Table 1, and their use in Table 3. Addresses (A0-A10). The address inputs are used to select one byte from the memory array during a read or write operation. Data In/Out (DQ0-DQ7). The contents of the data byte are written to, or read from, the memory array through the Data I/O pins. Chip Enable (E). The chip enable input must be held low to enable read and write operations. When Chip Enable is high, power consumption is reduced. Output Enable (G). The Output Enable input controls the data output buffers, and is used to initiate read operations. Write Enable (W). The Write Enable input controls whether the addressed location is to be read, from or written to. Ready/Busy (RB). Ready/Busy (on the M28C17B only) is an open drain output that can be used to detect the end of the internal write cycle. 2/17 M28C16B, M28C17B Table 2. Absolute Maximum Ratings 1 Symbol Value Unit Ambient Operating Temperature -40 to 125 °C TSTG Storage Temperature -65 to 150 °C VCC Supply Voltage -0.3 to 6.5 V VIO Input or Output Voltage -0.6 to VCC+0.6 V VI Input Voltage -0.3 to 6.5 V 4000 V TA VESD Parameter Electrostatic Discharge Voltage (Human Body model) 2 Note: 1. Except for the rating “Operating Temperature Range”, stresses above those listed in the Table “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the ST SURE Program and other relevant quality documents. 2. MIL-STD-883C, 3015.7 (100 pF, 1500 Ω) Figure 3. Block Diagram E A6-A10 (Page Address) A0-A5 RESET ADDRESS LATCH X DECODE VPP GEN G W CONTROL LOGIC 16K ARRAY ADDRESS LATCH Y DECODE SENSE AND DATA LATCH I/O BUFFERS PAGE LOAD TIMER STATUS TOGGLE BIT DATA POLLING DQ0-DQ7 AI02818 3/17 M28C16B, M28C17B Table 3. Operating Modes 1 Mode E G W DQ0-DQ7 Stand-by 1 X X Hi-Z Output Disable X 1 X Hi-Z Write Disable X X 1 Hi-Z Read 0 0 1 Data Out Write 0 1 0 Data In Chip Erase 0 V 0 Hi-Z Note: 1. 0=VIL; 1=VIH; X = VIH or VIL; V=12V ± 5%. end of the cycle can be detected by reading the status of the Data Polling and the Toggle Bit functions on DQ7 and DQ6. Page Write The Page Write mode allows up to 64 bytes to be written on a single page in a single go. This is achieved through a series of successive Write operations, no two of which are separated by more than the tWLQ5H value (as specified in Table 10A). The page write can be initiated during any byte write operation. Following the first byte write instruction the host may send another address and data with a minimum data transfer rate of: 1/t WLQ5H. The internal write cycle can start at any instant after tWLQ5H. Once initiated, the write operation is internally timed, and continues, uninterrupted, until completion. All bytes must be located on the same page address (A10-A6 must be the same for all bytes). Otherwise, the Page Write operation is not executed. As with the single byte Write operation, described above, the DQ5, DQ6 and DQ7 lines can be used to detect the beginning and end of the internally controlled phase of the Page Write cycle. Software Data Protection (SDP) The device offers a software-controlled write-protection mechanism that allows the user to inhibit all write operations to the device. This can be useful for protecting the memory from inadvertent write cycles that may occur during periods of instability (uncontrolled bus conditions when excessive noise is detected, or when power supply levels are outside their specified values). By default, the device is shipped in the “unprotected” state: the memory contents can be freely changed by the user. Once the Software Data Protection Mode is enabled, all write commands are Table 4A. Power-Up Timing1 for M28CxxB (5V range) (TA = 0 to 70 °C or -40 to 85 °C; VCC = 4.5 to 5.5 V) Symbol Parameter Min. Max. Unit tPUR Time Delay to Read Operation 1 µs tPUW Time Delay to Write Operation (once VCC ≥ VWI) 10 ms 3.0 4.2 V Min. Max. Unit VWI Write Inhibit Threshold Note: 1. Sampled only, not 100% tested. Table 4B. Power-Up Timing1 for M28CxxB-W (3V range) (TA = 0 to 70 °C or -40 to 85 °C; VCC = 2.7 to 3.6 V) Symbol Parameter tPUR Time Delay to Read Operation 1 µs tPUW Time Delay to Write Operation (once VCC ≥ VWI) 15 ms 2.5 V VWI Write Inhibit Threshold Note: 1. Sampled only, not 100% tested. 4/17 1.5 M28C16B, M28C17B Figure 4. Software Data Protection Enable Algorithm and Memory Write Write AAh in Address 555h Page Write Timing (see note 1) Write AAh in Address 555h Page Write Timing (see note 1) Write 55h in Address 2AAh Write 55h in Address 2AAh Write A0h in Address 555h Write A0h in Address 555h Write is Enabled SDP is set Physical Page Write Instruction SDP Enable Algorithm Page Write (1 up to 64 bytes) Write to Memory When SDP is SET AI02819 Note: 1. The most significant address bits (A10 to A6) differ during these specific Page Write operations. ignored, and have no effect on the memory contents. The device remains in this mode until a valid Software Data Protection disable sequence is received. The device reverts to its “unprotected” state. The status of the Software Data Protection (enabled or disabled) is represented by a non-volatile latch, and is remembered across periods of the power being off. The Software Data Protection Enable command consists of the writing of three specific data bytes to three specific memory locations (each location being on a different page), as shown in Figure 4. Similarly to disable the Software Data Protection, the user has to write specific data bytes into six dif- ferent locations, as shown in Figure 6. This complex series of operations protects against the chance of inadvertent enabling or disabling of the Software Data Protection mechanism. Figure 6. Software Data Protection Disable Algorithm Write AAh in Address 555h Write 55h in Address 2AAh Page Write Timing Figure 5. Status Bit Assignment Write 80h in Address 555h Write AAh in Address 555h DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0 DP TB PLTS Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z DP TB PLTS Hi-Z Write 55h in Address 2AAh Write 20h in Address 555h = Data Polling = Toggle Bit = Page Load Timer Status = High impedance Unprotected State AI02815 AI02820 5/17 M28C16B, M28C17B Figure 7. Chip Erase AC Waveforms tWHEH E G tGLWH W tELWL tWLWH2 tWHRH AI01484B Table 5. Chip Erase AC Characteristics1 (TA = 0 to 70 °C or -40 to 85 °C; VCC = 4.5 to 5.5 V or 2.7 to 3.6 V) Symbol Parameter Test Condition Min. Max. Unit tELWL Chip Enable Low to Write Enable Low G = VCC + 7V 1 µs tWHEH Write Enable High to Chip Enable High G = VCC + 7V 0 ns tWLWH2 Write Enable Low to Write Enable High G = VCC + 7V 10 ms tGLWH Output Enable Low to Write Enable High G = VCC + 7V 1 µs tWHRH Write Enable High to Write Enable Low G = VCC + 7V 3 ms Note: 1. Sampled only, not 100% tested. When SDP is enabled, the memory array can still have data written to it, but the sequence is more complex (and hence better protected from inadvertent use). The sequence is as shown in Figure 4. This consists of an unlock key, to enable the write action, at the end of which the SDP continues to be enabled. This allows the SDP to be enabled, and data to be written, within a single Write cycle (tWC). Software Chip Erase The contents of the entire memory are erased (set to FFh) by holding Chip Enable (E) low, and holding Output Enable (G) at VCC+7.0V. The chip is cleared when a 10 ms low pulse is applied to the Write Enable (W) signal (see Figure 7 and Table 5 for details). Status Bits The devices provide three status bits (DQ7, DQ6 and DQ5), for use during write operations. These allow the application to use the write time latency of the device for getting on with other work. These signals are available on the I/O port bits DQ7, DQ6 and DQ5 (but only during programming cycle, 6/17 once a byte or more has been latched into the memory). Data Polling bit (DQ7). The internally timed write cycle starts after tWLQ5H (defined in Table 10A) has elapsed since the previous byte was latched in to the memory. The value of the DQ7 bit of this last byte, is used as a signal throughout this write operation: it is inverted while the internal write operation is underway, and is inverted back to its original value once the operation is complete. Toggle bit (DQ6). The device offers another way for determining when the internal write cycle is completed. During the internal Erase/Write cycle, DQ6 toggles from ’0’ to ’1’ and ’1’ to ’0’ (the first read value being ’0’) on subsequent attempts to read any byte of the memory. When the internal write cycle is complete, the toggling is stopped, and the values read on DQ7-DQ0 are those of the addressed memory byte. This indicates that the device is again available for new Read and Write operations. Page Load Timer Status bit (DQ5). An internal timer is used to measure the period between suc- M28C16B, M28C17B Table 6A. Read Mode DC Characteristics for M28CxxB (5V range) (TA = 0 to 70 °C or -40 to 85 °C; VCC = 4.5 to 5.5 V) Symbol Parameter Test Condition ILI Input Leakage Current ILO Output Leakage Current Max. Unit 0 V ≤ VIN ≤ VCC 10 µA 0 V ≤ VOUT ≤ VCC 10 µA Supply Current (TTL inputs) E = VIL, G = VIL , f = 5 MHz 30 mA Supply Current (CMOS inputs) E = VIL, G = VIL , f = 5 MHz 25 mA ICC1 1 Supply Current (Stand-by) TTL E = VIH 1 mA ICC2 1 Supply Current (Stand-by) CMOS E > VCC - 0.3V 100 µA ICC 1 Min. VIL Input Low Voltage -0.3 0.8 V VIH Input High Voltage 2 VCC + 0.5 V VOL Output Low Voltage IOL = 2.1 mA 0.4 V VOH Output High Voltage IOH = -400 µA 2.4 V Note: 1. All inputs and outputs open circuit. Table 6B. Read Mode DC Characteristics for M28CxxB-W (3V range) (TA = 0 to 70 °C or -40 to 85 °C; VCC = 2.7 to 3.6 V) Symbol Parameter Test Condition ILI Input Leakage Current ILO Output Leakage Current ICC 1 Supply Current (CMOS inputs) ICC2 1 Supply Current (Stand-by) CMOS Min. Max. Unit 0 V ≤ VIN ≤ VCC 10 µA 0 V ≤ VOUT ≤ VCC 10 µA E = VIL, G = VIL , f = 5 MHz, VCC = 3.3V 8 mA E = VIL, G = VIL , f = 5 MHz, VCC = 3.6V 10 mA E > VCC - 0.3V 20 µA VIL Input Low Voltage -0.3 0.6 V VIH Input High Voltage 2 VCC + 0.5 V VOL Output Low Voltage IOL = 1.6 mA 0.2 VCC V VOH Output High Voltage IOH = -400 µA 0.8 VCC V Note: 1. All inputs and outputs open circuit. cessive Write operations, up to t WLQ5H (defined in Table 10A). The DQ5 line is held low to show when this timer is running (hence showing that the device has received one write operation, and is waiting for the next). The DQ5 line is held high when the counter has overflowed (hence showing that the device is now starting the internal write to the memory array). 7/17 M28C16B, M28C17B Table 7. Input and Output Parameters 1 (TA = 25 °C, f = 1 MHz) Symbol CIN COUT Parameter Test Condition Input Capacitance Output Capacitance Min. Max. Unit VIN = 0 V 6 pF VOUT = 0 V 12 pF Note: 1. Sampled only, not 100% tested. Table 8. AC Measurement Conditions ≤ 20 ns Input Rise and Fall Times Input Pulse Voltages 0.4 V to 2.4 V Input and Output Timing Reference Voltages 0.8 V to 2.0 V Figure 8. AC Testing Input Output Waveforms Figure 9. AC Testing Equivalent Load Circuit IOL 2.4V 0.4V 2.0V 0.8V DEVICE UNDER TEST OUT IOH CL = 100pF AI02821 8/17 CL includes JIG capacitance AI02102B M28C16B, M28C17B Table 9A. Read Mode AC Characteristics for M28CxxB (5V range) (TA = 0 to 70 °C or -40 to 85 °C; VCC = 4.5 to 5.5 V) M28CxxB Symbol Alt. Parameter Test Condition -90 Min -12 Max Min Unit Max tAVQV tACC Address Valid to Output Valid E = VIL, G = VIL 90 120 ns tELQV tCE Chip Enable Low to Output Valid G = VIL 90 120 ns tGLQV tOE Output Enable Low to Output Valid E = VIL 40 45 ns tEHQZ1 tDF Chip Enable High to Output Hi-Z G = VIL 0 40 0 45 ns tGHQZ1 tDF Output Enable High to Output Hi-Z E = VIL 0 40 0 45 ns tAXQX tOH Address Transition to Output Transition E = VIL, G = VIL 0 0 ns Note: 1. Output Hi-Z is defined as the point at which data is no longer driven. Table 9B. Read Mode AC Characteristics for M28CxxB-W (3V range) (TA = 0 to 70 °C or -40 to 85 °C; VCC = 2.7 to 3.6 V) M28CxxB-W Symbol Alt. Parameter Test Condition -12 Min -15 Max Min Unit Max tAVQV tACC Address Valid to Output Valid E = VIL, G = VIL 120 150 ns tELQV tCE Chip Enable Low to Output Valid G = VIL 120 150 ns tGLQV tOE Output Enable Low to Output Valid E = VIL 80 80 ns tEHQZ1 tDF Chip Enable High to Output Hi-Z G = VIL 0 45 0 50 ns tGHQZ1 tDF Output Enable High to Output Hi-Z E = VIL 0 45 0 50 ns tAXQX tOH Address Transition to Output Transition E = VIL, G = VIL 0 0 ns Note: 1. Output Hi-Z is defined as the point at which data is no longer driven. 9/17 M28C16B, M28C17B Table 10A. Write Mode AC Characteristics for M28CxxB (5V range) (TA = 0 to 70 °C or -40 to 85 °C; VCC = 4.5 to 5.5 V) M28C17B Symbol Alt. Parameter Test Condition Unit Min Max tAVWL tAS Address Valid to Write Enable Low E = VIL, G = VIH 0 ns tAVEL tAS Address Valid to Chip Enable Low G = VIH, W = VIL 0 ns tELWL tCES Chip Enable Low to Write Enable Low G = VIH 0 ns tGHWL tOES Output Enable High to Write Enable Low E = VIL 0 ns tGHEL tOES Output Enable High to Chip Enable Low W = VIL 0 ns tWLEL tWES Write Enable Low to Chip Enable Low G = VIH 0 ns tWLAX tAH Write Enable Low to Address Transition 50 ns tELAX tAH Chip Enable Low to Address Transition 50 ns tWLDV tDV Write Enable Low to Input Valid E = VIL, G = VIH 1 µs tELDV tDV Chip Enable Low to Input Valid G = VIH, W = VIL 1 µs tELEH tWP Chip Enable Low to Chip Enable High 50 ns tWHEH tCEH Write Enable High to Chip Enable High 0 ns tWHGL tOEH Write Enable High to Output Enable Low 0 ns tEHGL tOEH Chip Enable High to Output Enable Low 0 ns tEHWH tWEH Chip Enable High to Write Enable High 0 ns tWHDX tDH Write Enable High to Input Transition 0 ns tEHDX tDH Chip Enable High to Input Transition 0 ns tWHWL tWPH Write Enable High to Write Enable Low 50 ns tWLWH tWP Write Enable Low to Write Enable High 50 ns tWLQ5H tBLC Time-out After the Last Byte Write 100 µs tQ5HQ5X tWC Write Cycle Time tDVWH tDS Data Valid before Write Enable High 50 ns tDVEH tDS Data Valid before Chip Enable High 50 ns 10/17 3 ms M28C16B, M28C17B Table 10B. Write Mode AC Characteristics for M28CxxB-W (3V range) (TA = 0 to 70 °C or -40 to 85 °C; VCC = 2.7 to 3.6 V) M28C17B-xxW Symbol Alt. Parameter Test Condition Unit Min Max tAVWL tAS Address Valid to Write Enable Low E = VIL, G = VIH 0 ns tAVEL tAS Address Valid to Chip Enable Low G = VIH, W = VIL 0 ns tELWL tCES Chip Enable Low to Write Enable Low G = VIH 0 ns tGHWL tOES Output Enable High to Write Enable Low E = VIL 0 ns tGHEL tOES Output Enable High to Chip Enable Low W = VIL 0 ns tWLEL tWES Write Enable Low to Chip Enable Low G = VIH 0 ns tWLAX tAH Write Enable Low to Address Transition 100 ns tELAX tAH Chip Enable Low to Address Transition 100 ns tWLDV tDV Write Enable Low to Input Valid E = VIL, G = VIH 1 µs tELDV tDV Chip Enable Low to Input Valid G = VIH, W = VIL 1 µs tELEH tWP Chip Enable Low to Chip Enable High 100 1000 ns tWHEH tCEH Write Enable High to Chip Enable High 0 ns tWHGL tOEH Write Enable High to Output Enable Low 0 ns tEHGL tOEH Chip Enable High to Output Enable Low 0 ns tEHWH tWEH Chip Enable High to Write Enable High 0 ns tWHDX tDH Write Enable High to Input Transition 0 ns tEHDX tDH Chip Enable High to Input Transition 0 ns tWHWL tWPH Write Enable High to Write Enable Low 50 tWLWH tWP Write Enable Low to Write Enable High 100 ns tWLQ5H tBLC Time-out after the last byte write 100 µs tQ5HQ5X tWC Write Cycle Time tDVWH tDS Data Valid before Write Enable High 50 ns tDVEH tDS Data Valid before Chip Enable High 50 ns 1000 5 ns ms 11/17 M28C16B, M28C17B Figure 10. Read Mode AC Waveforms (with Write Enable, W, high) VALID A0-A10 tAVQV tAXQX E tGLQV tEHQZ G tELQV tGHQZ DQ0-DQ7 Hi-Z DATA OUT AI02822 Note: 1. Write Enable (W) = VIH Figure 11. Write Mode AC Waveforms (Write Enable, W, controlled) VALID A0-A10 tAVWL tWLAX E tELWL tWHEH G tGHWL tWLWH tWHGL W tWLDV DQ0-DQ7 tWHWL DATA IN tDVWH tWHDX RB tWHRL AI02823 12/17 M28C16B, M28C17B Figure 12. Write Mode AC Waveforms (Chip Enable, E, controlled) VALID A0-A10 tAVEL tELAX E tGHEL tELEH G tWLEL tEHGL W tELDV tEHWH DATA IN DQ0-DQ7 tDVEH tEHDX RB tEHRL AI02824 Figure 13. Page Write Mode AC Waveforms (Write Enable, W, controlled) Addr 0 A0-A10 Addr 1 Addr 2 Addr n E G tWHWL W tWLWH DQ0-DQ7 (in) Byte 0 Byte 1 Byte 2 Byte n DQ5 (out) tWHRL tWLQ5H tQ5HQ5X RB AI02825 13/17 M28C16B, M28C17B Figure 14. Software Protected Write Cycle Waveforms G E tWLWH tWHWL tWHWH W tAVEL tWLAX A0-A5 Byte Address tWHDX A6-A10 555h 2AAh 555h Page Address tDVWH DQ0-DQ7 AAh 55h Byte 0 A0h Byte 62 Byte 63 AI02826 Note: 1. A10 to A6 must specify the same page address during each high-to-low transition of W (or E). G must be high only when W and E are both low. Figure 15. Data Polling Sequence Waveforms A0-A10 Address of the last byte of the Page Write instruction E G W DQ7 DQ7 Last WRITE DQ7 DQ7 DQ7 Internal Write Sequence DQ7 Ready AI02827 14/17 M28C16B, M28C17B Figure 16. Toggle Bit Sequence Waveforms A0-A10 E G W DQ6 (1) TOGGLE Internal Write Sequence Last WRITE Ready AI02828 Note: 1. The Toggle Bit is first set to ‘0’. Table 11. Ordering Information Scheme Example: M28C16 – 120 W K 6 TR Option Ready/Busy 16 Pin 1 = Not Connected 17 Pin 1 = Ready/Busy TR Speed Tape and Reel Packing Temperature Range 90 90 ns (5V range only) 1 0 °C to 70 °C 120 120 ns 6 –40 °C to 85 °C 150 150 ns (3V range only) Operating Voltage blank 4.5 V to 5.5 V W Package K PLCC32 2.7 V to 3.6 V ORDERING INFORMATION Devices are shipped from the factory with the memory content set at all ‘1’s (FFh). The notation used for the device number is as shown in Table 11. For a list of available options (speed, package, etc.) or for further information on any aspect of this device, please contact the ST Sales Office nearest to you. 15/17 M28C16B, M28C17B Table 12. PLCC32 - 32 lead Plastic Leaded Chip Carrier, rectangular mm Symbol Typ. inches Min. Max. A 2.54 A1 Min. Max. 3.56 0.100 0.140 1.52 2.41 0.060 0.095 A2 – 0.38 – 0.015 B 0.33 0.53 0.013 0.021 B1 0.66 0.81 0.026 0.032 D 12.32 12.57 0.485 0.495 D1 11.35 11.56 0.447 0.455 D2 9.91 10.92 0.390 0.430 E 14.86 15.11 0.585 0.595 E1 13.89 14.10 0.547 0.555 E2 12.45 13.46 0.490 0.530 – – – – 0.00 0.25 0.000 0.010 – – – – e 1.27 F R 0.89 Typ. 0.050 0.035 N 32 32 Nd 7 7 Ne 9 9 CP 0.10 0.004 Figure 17. PLCC (K) D D1 A1 A2 1 N B1 E1 E Ne e D2/E2 F B 0.51 (.020) 1.14 (.045) A Nd R PLCC Note: 1. Drawing is not to scale. 16/17 CP M28C16B, M28C17B Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. © 1999 STMicroelectronics - All Rights Reserved The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners. 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