STMICROELECTRONICS M29W017D90N6T

M29W017D
16 Mbit (2Mb x8, Uniform Block)
3V Supply Flash Memory
PRELIMINARY DATA
FEATURES SUMMARY
■ SUPPLY VOLTAGE
Figure 1. Packages
– VCC = 2.7V to 3.6V for Program, Erase and
Read
■
ACCESS TIME: 70, 90ns
■
PROGRAMMING TIME
– 10µs per Byte typical
■
32 UNIFORM 64 KByte MEMORY BLOCKS
■
PROGRAM/ERASE CONTROLLER
TSOP40 (N)
10 x 20mm
– Embedded Byte Program algorithms
■
ERASE SUSPEND and RESUME MODES
– Read and Program another Block during
Erase Suspend
■
FBGA
UNLOCK BYPASS PROGRAM COMMAND
– Faster Production/Batch Programming
■
TEMPORARY BLOCK UNPROTECTION
MODE
■
COMMON FLASH INTERFACE
TFBGA48 (ZA)
6 x 8 ball array
– 64 bit Security Code
■
LOW POWER CONSUMPTION
– Standby and Automatic Standby
■
100,000 PROGRAM/ERASE CYCLES per
BLOCK
■
ELECTRONIC SIGNATURE
– Manufacturer Code: 20h
– Device Code: C8h
April 2002
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
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M29W017D
TABLE OF CONTENTS
SUMMARY DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 3. TSOP Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 4. TFBGA Connections (Top view through package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Table 16. Block Addresses, M29W017D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
SIGNAL DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Address Inputs (A0-A20). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Data Inputs/Outputs (DQ0-DQ7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Chip Enable (E). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Chip Enable (E). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Output Enable (G). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Write Enable (W). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Reset/Block Temporary Unprotect (RP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Ready/Busy Output (RB). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
VCC Supply Voltage (2.7V to 3.6V).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
VSS Ground. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
BUS OPERATIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Bus Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Bus Write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Output Disable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Standby. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Automatic Standby. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Special Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Electronic Signature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Block Protection and Blocks Unprotection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 2. Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
COMMAND INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Read/Reset Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Auto Select Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Program Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Unlock Bypass Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Unlock Bypass Program Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Unlock Bypass Reset Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Chip Erase Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Block Erase Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Erase Suspend Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Erase Resume Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Read CFI Query Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Block Protect and Chip Unprotect Commands. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
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M29W017D
Table 3. Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Table 4. Program, Erase Times and Program, Erase Endurance Cycles . . . . . . . . . . . . . . . . . . . . 14
STATUS REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Data Polling Bit (DQ7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Toggle Bit (DQ6).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Error Bit (DQ5). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Erase Timer Bit (DQ3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Alternative Toggle Bit (DQ2).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 5. Status Register Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 6. Data Polling Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 7. Data Toggle Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 6. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
DC and AC PARAMETERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 7. Operating and AC Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 8. AC Measurement I/O Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 9. AC Measurement Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 8. Device Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 9. DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 10. Read AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 10. Read AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 11. Write AC Waveforms, Write Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 11. Write AC Characteristics, Write Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 12. Write AC Waveforms, Chip Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 12. Write AC Characteristics, Chip Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 13. Reset/Block Temporary Unprotect AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 13. Reset/Block Temporary Unprotect AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 23
PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
TSOP40 – 40 lead Plastic Thin Small Outline, 10 x 20mm, Package Outline . . . . . . . . . . . . . . . . 24
TSOP40 – 40 lead Plastic Thin Small Outline, 10 x 20mm, Package Mechanical Data . . . . . . . . 24
TFBGA48 8x9mm – 6x8 active ball array – 0.80mm pitch, Bottom View Package Outline . . . . . . 25
TFBGA48 8x9mm – 6x8 active ball array – 0.80mm pitch, Package Mechanical Data . . . . . . . . . 25
PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 14. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
REVISION HISTORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 15. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
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M29W017D
APPENDIX A. BLOCK ADDRESS TABLE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 16. Block Addresses, M29W017D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
APPENDIX B. COMMON FLASH INTERFACE (CFI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 17. Query Structure Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 18. CFI Query Identification String . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 19. CFI Query System Interface Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 20. Device Geometry Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 21. Primary Algorithm-Specific Extended Query Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 22. Security Code Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
APPENDIX C. BLOCK PROTECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Programmer Technique . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
In-System Technique . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 23. Programmer Technique Bus Operations, BYTE = V IH or VIL . . . . . . . . . . . . . . . . . . . . . 31
Figure 14. Programmer Equipment Block Protect Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 15. Programmer Equipment Chip Unprotect Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 16. In-System Equipment Block Protect Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 17. In-System Equipment Chip Unprotect Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
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M29W017D
SUMMARY DESCRIPTION
The M29W017D is a 16 Mbit (2Mb x8) non-volatile
memory that can be read, erased and reprogrammed. These operations can be performed using a single low voltage (2.7 to 3.6V) supply. On
power-up the memory defaults to its Read mode
where it can be read in the same way as a ROM or
EPROM.
The memory is divided into 32 blocks of 64KBytes
(see Table 16, Block Addresses) that can be
erased independently so it is possible to preserve
valid data while old data is erased. Each block can
be protected independently to prevent accidental
Program or Erase commands from modifying the
memory. Program and Erase commands are written to the Command Interface of the memory. An
on-chip Program/Erase Controller simplifies the
process of programming or erasing the memory by
taking care of all of the special operations that are
required to update the memory contents. The end
of a program or erase operation can be detected
and any error conditions identified. The command
set required to control the memory is consistent
with JEDEC standards.
Chip Enable, Output Enable and Write Enable signals control the bus operation of the memory.
They allow simple connection to most microprocessors, often without additional logic.
The memory is offered in TSOP40 (10 x 20mm) and
TFBGA48 (0.8mm pitch) packages. The memory is
supplied with all the bits erased (set to ’1’).
Figure 2. Logic Diagram
Table 1. Signal Names
VCC
21
8
A0-A20
Address Inputs
DQ0-DQ7
Data Inputs/Outputs
E
Chip Enable
G
Output Enable
W
Write Enable
RP
Reset/Block Temporary Unprotect
RB
Ready/Busy Output
VCC
Supply Voltage
VSS
Ground
NC
Not Connected Internally
DQ0-DQ7
W
E
A0-A20
M29W017D
G
RB
RP
VSS
AI04186
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M29W017D
Figure 3. TSOP Connections
A16
A15
A14
A13
A12
A11
A9
A8
W
RP
1
NC
10
11
RB
A18
A7
A6
A5
A4
A3
A2
A1
20
40
M29W017D
31
30
21
AI04187
6/36
A17
VSS
A20
A19
A10
DQ7
DQ6
DQ5
DQ4
VCC
VCC
NC
DQ3
DQ2
DQ1
DQ0
G
VSS
E
A0
M29W017D
Figure 4. TFBGA Connections (Top view through package)
1
2
3
4
5
6
A
A3
A7
RB
W
A9
A14
B
A4
A18
NC
RP
A8
A13
C
A2
A6
NC
NC
A11
A15
D
A1
A5
NC
NC
A12
A16
E
A0
DQ0
DQ2
DQ5
A19
A17
F
E
NC
DQ3
NC
A10
NC
G
G
NC
VCC
VCC
DQ6
A20
H
VSS
DQ1
NC
DQ4
DQ7
VSS
AI04188
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M29W017D
Figure 5. Block Addresses
M29W017D
Block Addresses
1FFFFFh
64 KByte
1F0000h
1EFFFFh
64 KByte
1E0000h
1DFFFFh
64 KByte
1D0000h
1CFFFFh
Total of 32
64 KByte Blocks
02FFFFh
64 KByte
020000h
01FFFFh
64 KByte
010000h
00FFFFh
64 KByte
000000h
AI05429
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M29W017D
SIGNAL DESCRIPTIONS
See Figure 2, Logic Diagram, and Table 1, Signal
Names, for a brief overview of the signals connected to this device.
Address Inputs (A0-A20). The Address Inputs
select the cells in the memory array to access during Bus Read operations. During Bus Write operations they control the commands sent to the
Command Interface of the internal state machine.
Data Inputs/Outputs (DQ0-DQ7). The Data I/O
outputs the data stored at the selected address
during a Bus Read operation. During Bus Write
operations they represent the commands sent to
the Command Interface of the internal state machine.
Chip Enable (E). The Chip Enable, E, activates
the memory, allowing Bus Read and Bus Write operations to be performed. When Chip Enable is
High, V IH, all other pins are ignored.
Output Enable (G). The Output Enable, G, controls the Bus Read operation of the memory.
Write Enable (W). The Write Enable, W, controls
the Bus Write operation of the memory’s Command Interface.
Reset/Block Temporary Unprotect (RP). The
Reset/Block Temporary Unprotect pin can be
used to apply a Hardware Reset to the memory or
to temporarily unprotect all Blocks that have been
protected.
A Hardware Reset is achieved by holding Reset/
Block Temporary Unprotect Low, V IL, for at least
tPLPX. After Reset/Block Temporary Unprotect
goes High, V IH, the memory will be ready for Bus
Read and Bus Write operations after tPHEL or
tRHEL, whichever occurs last. See the Ready/Busy
Output section, Table 13 and Figure 13, Reset/
Temporary Unprotect AC Characteristics for more
details.
Holding RP at V ID will temporarily unprotect the
protected Blocks in the memory. Program and
Erase operations on all blocks will be possible.
The transition from VIH to VID must be slower than
tPHPHH.
Ready/Busy Output (RB). The Ready/Busy pin
is an open-drain output that can be used to identify
when the device is performing a Program or Erase
operation. During Program or Erase operations
Ready/Busy is Low, V OL. Ready/Busy is high-impedance during Read mode, Auto Select mode
and Erase Suspend mode.
After a Hardware Reset, Bus Read and Bus Write
operations cannot begin until Ready/Busy becomes high-impedance. See Table 13 and Figure
13, Reset/Temporary Unprotect AC Characteristics.
The use of an open-drain output allows the Ready/
Busy pins from several memories to be connected
to a single pull-up resistor. A Low will then indicate
that one, or more, of the memories is busy.
proVCC Supply Voltage (2.7V to 3.6V). VCC
vides the power supply for all operations (Read,
Program and Erase).
The Command Interface is disabled when the V CC
Supply Voltage is less than the Lockout Voltage,
VLKO. This prevents Bus Write operations from accidentally damaging the data during power up,
power down and power surges. If the Program/
Erase Controller is programming or erasing during
this time then the operation aborts and the memory contents being altered will be invalid.
A 0.1µF capacitor should be connected between
the V CC Supply Voltage pin and the VSS Ground
pin to decouple the current surges from the power
supply. See Figure 10, AC Measurement Load Circuit. The PCB track widths must be sufficient to
carry the currents required during program and
erase operations, ICC3.
VSS Ground. VSS is the reference for all voltage
measurements.
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M29W017D
BUS OPERATIONS
There are five standard bus operations that control
the device. These are Bus Read, Bus Write, Output Disable, Standby and Automatic Standby. See
Tables 2, Bus Operations, for a summary. Typically glitches of less than 5ns on Chip Enable or Write
Enable are ignored by the memory and do not affect bus operations.
Bus Read. Bus Read operations read from the
memory cells, or specific registers in the Command Interface. A valid Bus Read operation involves setting the desired address on the Address
Inputs, applying a Low signal, V IL, to Chip Enable
and Output Enable and keeping Write Enable
High, VIH. The Data Inputs/Outputs will output the
value, see Figure 10, Read Mode AC Waveforms,
and Table 10, Read AC Characteristics, for details
of when the output becomes valid.
Bus Write. Bus Write operations write to the
Command Interface. A valid Bus Write operation
begins by setting the desired address on the Address Inputs. The Address Inputs are latched by
the Command Interface on the falling edge of Chip
Enable or Write Enable, whichever occurs last.
The Data Inputs/Outputs are latched by the Command Interface on the rising edge of Chip Enable
or Write Enable, whichever occurs first. Output Enable must remain High, VIH, during the whole Bus
Write operation. See Figures 11 and 12, Write AC
Waveforms, and Tables 11 and 12, Write AC
Characteristics, for details of the timing requirements.
Output Disable. The Data Inputs/Outputs are in
the high impedance state when Output Enable is
High, V IH.
Standby. When Chip Enable is High, VIH, the
memory enters Standby mode and the Data Inputs/Outputs pins are placed in the high-imped-
ance state. To reduce the Supply Current to the
Standby Supply Current, ICC2, Chip Enable should
be held within VCC ± 0.2V. For the Standby current
level see Table 9, DC Characteristics.
During program or erase operations the memory
will continue to use the Program/Erase Supply
Current, ICC3, for Program or Erase operations until the operation completes.
Automatic Standby. If CMOS levels (VCC ± 0.2V)
are used to drive the bus and the bus is inactive for
300ns or more the memory enters Automatic
Standby where the internal Supply Current is reduced to the Standby Supply Current, ICC2. The
Data Inputs/Outputs will still output data if a Bus
Read operation is in progress.
Special Bus Operations
Additional bus operations can be performed to
read the Electronic Signature and also to apply
and remove Block Protection. These bus operations are intended for use by programming equipment and are not usually used in applications.
They require VID to be applied to some pins.
Electronic Signature. The memory has two
codes, the manufacturer code and the device
code, that can be read to identify the memory.
These codes can be read by applying the signals
listed in Tables 2, Bus Operations.
Block Protection and Blocks Unprotection.
Each block can be separately protected against
accidental Program or Erase. Protected blocks
can be unprotected to allow data to be changed.
There are two methods available for protecting
and unprotecting the blocks, one for use on programming equipment and the other for in-system
use. Block Protect and Chip Unprotect operations
are described in Appendix C.
Table 2. Bus Operations
Operation
Address Inputs
A0-A20
Data Inputs/Outputs
DQ7-DQ0
E
G
W
Bus Read
VIL
VIL
VIH
Cell Address
Bus Write
VIL
VIH
VIL
Command Address
X
VIH
VIH
X
Hi-Z
Standby
VIH
X
X
X
Hi-Z
Read Manufacturer
Code
VIL
VIL
VIH
A0 = VIL, A1 = VIL, A9 = VID,
Others VIL or VIH
20h
Read Device Code
VIL
VIL
VIH
A0 = VIH, A1 = VIL,
A9 = VID, Others VIL or VIH
C8h
Output Disable
Note: X = VIL or VIH.
10/36
Data Output
Data Input
M29W017D
COMMAND INTERFACE
All Bus Write operations to the memory are interpreted by the Command Interface. Commands
consist of one or more sequential Bus Write operations. Failure to observe a valid sequence of Bus
Write operations will result in the memory returning to Read mode. The long command sequences
are imposed to maximize data security.
Refer to Table 3, Commands, in conjunction with
the following text descriptions.
Read/Reset Command. The Read/Reset command returns the memory to its Read mode where
it behaves like a ROM or EPROM, unless otherwise stated. It also resets the errors in the Status
Register. Either one or three Bus Write operations
can be used to issue the Read/Reset command.
The Read/Reset Command can be issued, between Bus Write cycles before the start of a program or erase operation, to return the device to
read mode. Once the program or erase operation
has started the Read/Reset command is no longer
accepted. The Read/Reset command will not
abort an Erase operation when issued while in
Erase Suspend.
Auto Select Command. The Auto Select command is used to read the Manufacturer Code, the
Device Code and the Block Protection Status.
Three consecutive Bus Write operations are required to issue the Auto Select command. Once
the Auto Select command is issued the memory
remains in Auto Select mode until a Read/Reset
command is issued. Read CFI Query and Read/
Reset commands are accepted in Auto Select
mode, all other commands are ignored.
From the Auto Select mode the Manufacturer
Code can be read using a Bus Read operation
with A0 = V IL and A1 = VIL. The other address bits
may be set to either V IL or VIH. The Manufacturer
Code for STMicroelectronics is 20h.
The Device Code can be read using a Bus Read
operation with A0 = VIH and A1 = VIL. The other
address bits may be set to either V IL or VIH. The
Device Code for the M29W017D is C8h.
The Block Protection Status of each block can be
read using a Bus Read operation with A0 = V IL ,
A1 = V IH, and A16-A20 specifying the address of
the block. The other address bits may be set to either V IL or VIH. If the addressed block is protected
then 01h is output on Data Inputs/Outputs DQ0DQ7, otherwise 00h is output.
Program Command. The Program command
can be used to program a value to one address in
the memory array at a time. The command requires four Bus Write operations, the final write operation latches the address and data in the internal
state machine and starts the Program/Erase Controller.
If the address falls in a protected block then the
Program command is ignored, the data remains
unchanged. The Status Register is never read and
no error condition is given.
During the program operation the memory will ignore all commands. It is not possible to issue any
command to abort or pause the operation. Typical
program times are given in Table 4. Bus Read operations during the program operation will output
the Status Register on the Data Inputs/Outputs.
See the section on the Status Register for more
details.
After the program operation has completed the
memory will return to the Read mode, unless an
error has occurred. When an error occurs the
memory will continue to output the Status Register. A Read/Reset command must be issued to reset the error condition and return to Read mode.
Note that the Program command cannot change a
bit set at ’0’ back to ’1’. One of the Erase Commands must be used to set all the bits in a block or
in the whole memory from ’0’ to ’1’.
Unlock Bypass Command. The Unlock Bypass
command is used in conjunction with the Unlock
Bypass Program command to program the memory. When the cycle time to the device is long (as
with some EPROM programmers) considerable
time saving can be made by using these commands. Three Bus Write operations are required
to issue the Unlock Bypass command.
Once the Unlock Bypass command has been issued the memory will only accept the Unlock Bypass Program command and the Unlock Bypass
Reset command. The memory can be read as if in
Read mode.
Unlock Bypass Program Command. The Unlock Bypass Program command can be used to
program one address in the memory array at a
time. The command requires two Bus Write operations, the final write operation latches the address and data in the internal state machine and
starts the Program/Erase Controller.
The Program operation using the Unlock Bypass
Program command behaves identically to the Program operation using the Program command. A
protected block cannot be programmed; the operation cannot be aborted and the Status Register is
read. Errors must be reset using the Read/Reset
command, which leaves the device in Unlock Bypass Mode. See the Program command for details
on the behavior.
Unlock Bypass Reset Command. The Unlock
Bypass Reset command can be used to return to
Read/Reset mode from Unlock Bypass Mode.
Two Bus Write operations are required to issue the
Unlock Bypass Reset command. Read/Reset
11/36
M29W017D
command does not exit from Unlock Bypass
Mode.
Chip Erase Command. The Chip Erase command can be used to erase the entire chip. Six Bus
Write operations are required to issue the Chip
Erase Command and start the Program/Erase
Controller.
If any blocks are protected then these are ignored
and all the other blocks are erased. If all of the
blocks are protected the Chip Erase operation appears to start but will terminate within about 100µs,
leaving the data unchanged. No error condition is
given when protected blocks are ignored.
During the erase operation the memory will ignore
all commands, including the Erase Suspend command. It is not possible to issue any command to
abort the operation. Typical chip erase times are
given in Table 4. All Bus Read operations during
the Chip Erase operation will output the Status
Register on the Data Inputs/Outputs. See the section on the Status Register for more details.
After the Chip Erase operation has completed the
memory will return to the Read Mode, unless an
error has occurred. When an error occurs the
memory will continue to output the Status Register. A Read/Reset command must be issued to reset the error condition and return to Read Mode.
The Chip Erase Command sets all of the bits in unprotected blocks of the memory to ’1’. All previous
data is lost.
Block Erase Command. The Block Erase command can be used to erase a list of one or more
blocks. Six Bus Write operations are required to
select the first block in the list. Each additional
block in the list can be selected by repeating the
sixth Bus Write operation using the address of the
additional block. The Block Erase operation starts
the Program/Erase Controller about 50µs after the
last Bus Write operation. Once the Program/Erase
Controller starts it is not possible to select any
more blocks. Each additional block must therefore
be selected within 50µs of the last block. The 50µs
timer restarts when an additional block is selected.
The Status Register can be read after the sixth
Bus Write operation. See the Status Register section for details on how to identify if the Program/
Erase Controller has started the Block Erase operation.
If any selected blocks are protected then these are
ignored and all the other selected blocks are
erased. If all of the selected blocks are protected
the Block Erase operation appears to start but will
terminate within about 100µs, leaving the data unchanged. No error condition is given when protected blocks are ignored.
During the Block Erase operation the memory will
ignore all commands except the Erase Suspend
12/36
command. Typical block erase times are given in
Table 4. All Bus Read operations during the Block
Erase operation will output the Status Register on
the Data Inputs/Outputs. See the section on the
Status Register for more details.
After the Block Erase operation has completed the
memory will return to the Read Mode, unless an
error has occurred. When an error occurs the
memory will continue to output the Status Register. A Read/Reset command must be issued to reset the error condition and return to Read mode.
The Block Erase Command sets all of the bits in
the unprotected selected blocks to ’1’. All previous
data in the selected blocks is lost.
Erase Suspend Command. The Erase Suspend
Command may be used to temporarily suspend a
Block Erase operation and return the memory to
Read mode. The command requires one Bus
Write operation.
The Program/Erase Controller will suspend within
15µs of the Erase Suspend Command being issued. Once the Program/Erase Controller has
stopped the memory will be set to Read mode and
the Erase will be suspended. If the Erase Suspend
command is issued during the period when the
memory is waiting for an additional block (before
the Program/Erase Controller starts) then the
Erase is suspended immediately and will start immediately when the Erase Resume Command is
issued. It is not possible to select any further
blocks to erase after the Erase Resume. During
Erase Suspend it is possible to Read and Program
cells in blocks that are not being erased; both
Read and Program operations behave as normal
on these blocks. If any attempt is made to program
in a protected block or in the suspended block then
the Program command is ignored and the data remains unchanged. The Status Register is not read
and no error condition is given. Reading from
blocks that are being erased will output the Status
Register.
It is also possible to issue the Auto Select, Read
CFI Query and Unlock Bypass commands during
an Erase Suspend. The Read/Reset command
must be issued to return the device to Read Array
mode before the Resume command will be accepted.
Erase Resume Command. The Erase Resume
command must be used to restart the Program/
Erase Controller after an Erase Suspend. The device must be in Read Array mode before the Resume command will be accepted. An erase can be
suspended and resumed more than once.
Read CFI Query Command. The Read CFI
Query Command is used to read data from the
Common Flash Interface (CFI) Memory Area. This
command is valid when the device is in the Read
M29W017D
Array mode, or when the device is in Autoselected
mode.
One Bus Write cycle is required to issue the Read
CFI Query Command. Once the command is issued subsequent Bus Read operations read from
the Common Flash Interface Memory Area.
The Read/Reset command must be issued to return the device to the previous mode (the Read Array mode or Autoselected mode). A second Read/
Reset command would be needed if the device is
to be put in the Read Array mode from Autoselected mode.
See Appendix B, Tables 17, 18, 19, 20, 21 and 22
for details on the information contained in the
Common Flash Interface (CFI) memory area.
Block Protect and Chip Unprotect Commands.
Each block can be separately protected against
accidental Program or Erase. The whole chip can
be unprotected to allow the data inside the blocks
to be changed.
Block Protect and Chip Unprotect operations are
described in Appendix C.
Command
Length
Table 3. Commands
Bus Write Operations
1st
2nd
Addr
Data
1
x
F0
3
x
Auto Select
3
Program
3rd
4th
Addr
Data
Addr
Data
AA
x
55
x
F0
x
AA
x
55
x
90
4
x
AA
x
55
x
A0
Unlock Bypass
3
x
AA
x
55
x
20
Unlock Bypass
Program
2
x
A0
PA
PD
Unlock Bypass Reset
2
x
90
x
00
Chip Erase
6
x
AA
x
55
x
Block Erase
6+
x
AA
x
55
x
Erase Suspend
1
x
B0
Erase Resume
1
x
30
Read CFI Query
1
55
98
5th
Addr
Data
PA
PD
80
x
80
x
6th
Addr
Data
Addr
Data
AA
x
55
x
10
AA
x
55
BA
30
Read/Reset
Note: x Don’t Care, PA Program Address, PD Program Data, BA Any address in the Block. All values in the table are in hexadecimal.
13/36
M29W017D
Table 4. Program, Erase Times and Program, Erase Endurance Cycles
Typ (1)
Typical after
100k W/E Cycles (1)
Max
Unit
Chip Erase
25
25
120
s
Block Erase (64 KBytes)
0.8
6
s
Program (Byte)
10
200
µs
Chip Program (Byte by Byte)
25
120
s
Parameter
Program/Erase Cycles (per Block)
Min
100,000
cycles
Note: 1. TA = 25°C, VCC = 3.3V.
STATUS REGISTER
Bus Read operations from any address always
read the Status Register during Program and
Erase operations. It is also read during Erase Suspend when an address within a block being erased
is accessed.
The bits in the Status Register are summarized in
Table 5, Status Register Bits.
Data Polling Bit (DQ7). The Data Polling Bit can
be used to identify whether the Program/Erase
Controller has successfully completed its operation or if it has responded to an Erase Suspend.
The Data Polling Bit is output on DQ7 when the
Status Register is read.
During Program operations the Data Polling Bit
outputs the complement of the bit being programmed to DQ7. After successful completion of
the Program operation the memory returns to
Read mode and Bus Read operations from the address just programmed output DQ7, not its complement.
During Erase operations the Data Polling Bit outputs ’0’, the complement of the erased state of
DQ7. After successful completion of the Erase operation the memory returns to Read Mode.
In Erase Suspend mode the Data Polling Bit will
output a ’1’ during a Bus Read operation within a
block being erased. The Data Polling Bit will
change from a ’0’ to a ’1’ when the Program/Erase
Controller has suspended the Erase operation.
Figure 6, Data Polling Flowchart, gives an example of how to use the Data Polling Bit. A Valid Address is the address being programmed or an
address within the block being erased.
Toggle Bit (DQ6). The Toggle Bit can be used to
identify whether the Program/Erase Controller has
successfully completed its operation or if it has responded to an Erase Suspend. The Toggle Bit is
output on DQ6 when the Status Register is read.
During Program and Erase operations the Toggle
Bit changes from ’0’ to ’1’ to ’0’, etc., with succes-
14/36
sive Bus Read operations at any address. After
successful completion of the operation the memory returns to Read mode.
During Erase Suspend mode the Toggle Bit will
output when addressing a cell within a block being
erased. The Toggle Bit will stop toggling when the
Program/Erase Controller has suspended the
Erase operation.
If any attempt is made to erase a protected block,
the operation is aborted, no error is signalled and
DQ6 toggles for approximately 100µs. If any attempt is made to program a protected block or a
suspended block, the operation is aborted, no error is signalled and DQ6 toggles for approximately
1µs.
Figure 7, Data Toggle Flowchart, gives an example of how to use the Data Toggle Bit.
Error Bit (DQ5). The Error Bit can be used to
identify errors detected by the Program/Erase
Controller. The Error Bit is set to ’1’ when a Program, Block Erase or Chip Erase operation fails to
write the correct data to the memory. If the Error
Bit is set a Read/Reset command must be issued
before other commands are issued. The Error bit
is output on DQ5 when the Status Register is read.
Note that the Program command cannot change a
bit set to ’0’ back to ’1’ and attempting to do so will
set DQ5 to ‘1’. A Bus Read operation to that address will show the bit is still ‘0’. One of the Erase
commands must be used to set all the bits in a
block or in the whole memory from ’0’ to ’1’.
Erase Timer Bit (DQ3). The Erase Timer Bit can
be used to identify the start of Program/Erase
Controller operation during a Block Erase command. Once the Program/Erase Controller starts
erasing the Erase Timer Bit is set to ’1’. Before the
Program/Erase Controller starts the Erase Timer
Bit is set to ’0’ and additional blocks to be erased
may be written to the Command Interface. The
Erase Timer Bit is output on DQ3 when the Status
Register is read.
M29W017D
Alternative Toggle Bit (DQ2). The Alternative
Toggle Bit can be used to monitor the Program/
Erase controller during Erase operations. The Alternative Toggle Bit is output on DQ2 when the
Status Register is read.
During Chip Erase and Block Erase operations the
Toggle Bit changes from ’0’ to ’1’ to ’0’, etc., with
successive Bus Read operations from addresses
within the blocks being erased. A protected block
is treated the same as a block not being erased.
Once the operation completes the memory returns
to Read mode.
During Erase Suspend the Alternative Toggle Bit
changes from ’0’ to ’1’ to ’0’, etc. with successive
Bus Read operations from addresses within the
blocks being erased. Bus Read operations to addresses within blocks not being erased will output
the memory cell data as if in Read mode.
After an Erase operation that causes the Error Bit
to be set the Alternative Toggle Bit can be used to
identify which block or blocks have caused the error. The Alternative Toggle Bit changes from ’0’ to
’1’ to ’0’, etc. with successive Bus Read Operations from addresses within blocks that have not
erased correctly. The Alternative Toggle Bit does
not change if the addressed block has erased correctly.
Table 5. Status Register Bits
Operation
Address
DQ7
DQ6
DQ5
DQ3
DQ2
RB
Program
Any Address
DQ7
Toggle
0
–
–
0
Program During Erase
Suspend
Any Address
DQ7
Toggle
0
–
–
0
Program Error
Any Address
DQ7
Toggle
1
–
–
0
Chip Erase
Any Address
0
Toggle
0
1
Toggle
0
Block Erase before
timeout
Erasing Block
0
Toggle
0
0
Toggle
0
Non-Erasing Block
0
Toggle
0
0
No Toggle
0
Erasing Block
0
Toggle
0
1
Toggle
0
Non-Erasing Block
0
Toggle
0
1
No Toggle
0
Erasing Block
1
No Toggle
0
–
Toggle
1
Block Erase
Erase Suspend
Non-Erasing Block
Data read as normal
1
Good Block Address
0
Toggle
1
1
No Toggle
0
Faulty Block Address
0
Toggle
1
1
Toggle
0
Erase Error
Note: Unspecified data bits should be ignored.
15/36
M29W017D
Figure 6. Data Polling Flowchart
Figure 7. Data Toggle Flowchart
START
START
READ
DQ5 & DQ6
READ DQ5 & DQ7
at VALID ADDRESS
READ DQ6
DQ7
=
DATA
YES
DQ6
=
TOGGLE
NO
NO
NO
YES
DQ5
=1
NO
YES
READ DQ7
at VALID ADDRESS
DQ5
=1
YES
READ DQ6
TWICE
DQ7
=
DATA
YES
DQ6
=
TOGGLE
NO
FAIL
PASS
AI05252
NO
YES
FAIL
PASS
AI05253
16/36
M29W017D
MAXIMUM RATING
Stressing the device above the rating listed in the
Absolute Maximum Ratings table may cause permanent damage to the device. Exposure to Absolute Maximum Rating conditions for extended
periods may affect device reliability. These are
stress ratings only and operation of the device at
these or any other conditions above those indicated in the Operating sections of this specification is
not implied. Refer also to the STMicroelectronics
SURE Program and other relevant quality documents.
Table 6. Absolute Maximum Ratings
Symbol
Parameter
Min
Max
Unit
TBIAS
Temperature Under Bias
–50
125
°C
TSTG
Storage Temperature
–65
150
°C
VIO
Input or Output Voltage (1,2)
–0.6
VCC +0.6
V
VCC
Supply Voltage
–0.6
4
V
VID
Identification Voltage
–0.6
13.5
V
Note: 1. Minimum voltage may undershoot to –2V during transition and for less than 20ns during transitions.
2. Maximum voltage may overshoot to V CC +2V during transition and less than 20ns during transitions.
17/36
M29W017D
DC AND AC PARAMETERS
This section summarizes the operating measurement conditions, and the DC and AC characteristics of the device. The parameters in the DC and
AC characteristics Tables that follow, are derived
from tests performed under the Measurement
Conditions summarized in Table 7, Operating and
AC Measurement Conditions. Designers should
check that the operating conditions in their circuit
match the operating conditions when relying on
the quoted parameters.
Table 7. Operating and AC Measurement Conditions
M29W017D
Parameter
70
90
Unit
Min
Max
Min
Max
VCC Supply Voltage
3.0
3.6
2.7
3.6
V
Ambient Operating Temperature
–40
85
–40
85
°C
Load Capacitance (CL)
30
100
Input Rise and Fall Times
pF
10
Input Pulse Voltages
Input and Output Timing Ref. Voltages
Figure 8. AC Measurement I/O Waveform
10
ns
0 to VCC
0 to VCC
V
VCC/2
VCC/2
V
Figure 9. AC Measurement Load Circuit
VCC
VCC
VCC
VCC/2
25kΩ
0V
DEVICE
UNDER
TEST
AI05254
0.1µF
CL
25kΩ
AI05255
CL includes JIG capacitance
Table 8. Device Capacitance
Symbol
CIN
COUT
Parameter
Input Capacitance
Output Capacitance
Note: Sampled only, not 100% tested.
18/36
Test Condition
Min
Max
Unit
VIN = 0V
6
pF
VOUT = 0V
12
pF
M29W017D
Table 9. DC Characteristics
Symbol
Parameter
Test Condition
Min
Max
Unit
0V ≤ VIN ≤ VCC
±1
µA
ILI
Input Leakage Current
ILO
Output Leakage Current
0V ≤ VOUT ≤ VCC
±1
µA
ICC1
Supply Current (Read)
E = VIL, G = VIH,
f = 6MHz
10
mA
ICC2
Supply Current (Standby)
E = VCC ±0.2V,
RP = VCC ±0.2V
100
µA
Supply Current (Program/Erase)
Program/Erase
Controller active
20
mA
ICC3 (1)
VIL
Input Low Voltage
–0.5
0.8
V
VIH
Input High Voltage
0.7VCC
VCC +0.3
V
VOL
Output Low Voltage
IOL = 1.8mA
0.45
V
VOH
Output High Voltage
IOH = –100µ A
VID
Identification Voltage
IID
Identification Current
VLKO
Program/Erase Lockout Supply
Voltage
VCC –0.4
11.5
A9 = VID
1.8
V
12.5
V
100
µA
2.3
V
Note: 1. Sampled only, not 100% tested.
19/36
M29W017D
Figure 10. Read AC Waveforms
tAVAV
A0-A20
VALID
tAVQV
tAXQX
E
tELQV
tEHQX
tELQX
tEHQZ
G
tGLQX
tGHQX
tGLQV
tGHQZ
DQ0-DQ7
VALID
AI05248
Table 10. Read AC Characteristics
M29W017D
Symbol
Alt
Parameter
Test Condition
Unit
70
90
tAVAV
tRC
Address Valid to Next Address Valid
E = VIL,
G = VIL
Min
70
90
ns
tAVQV
tACC
Address Valid to Output Valid
E = VIL,
G = VIL
Max
70
90
ns
tELQX (1)
tLZ
Chip Enable Low to Output Transition
G = VIL
Min
0
0
ns
tELQV
tCE
Chip Enable Low to Output Valid
G = VIL
Max
70
90
ns
tGLQX (1)
tOLZ
Output Enable Low to Output
Transition
E = VIL
Min
0
0
ns
tGLQV
tOE
Output Enable Low to Output Valid
E = VIL
Max
30
35
ns
tEHQZ (1)
tHZ
Chip Enable High to Output Hi-Z
G = VIL
Max
25
30
ns
tGHQZ (1)
tDF
Output Enable High to Output Hi-Z
E = VIL
Max
25
30
ns
tEHQX
tGHQX
tAXQX
tOH
Chip Enable, Output Enable or
Address Transition to Output Transition
Min
0
0
ns
Note: 1. Sampled only, not 100% tested.
20/36
M29W017D
Figure 11. Write AC Waveforms, Write Enable Controlled
tAVAV
A0-A20
VALID
tWLAX
tAVWL
tWHEH
E
tELWL
tWHGL
G
tGHWL
tWLWH
W
tWHWL
tDVWH
DQ0-DQ7
tWHDX
VALID
VCC
tVCHEL
RB
tWHRL
AI05249
Table 11. Write AC Characteristics, Write Enable Controlled
M29W017D
Symbol
Alt
Parameter
Unit
70
90
tAVAV
tWC
Address Valid to Next Address Valid
Min
70
90
ns
tELWL
tCS
Chip Enable Low to Write Enable Low
Min
0
0
ns
tWLWH
tWP
Write Enable Low to Write Enable High
Min
45
50
ns
tDVWH
tDS
Input Valid to Write Enable High
Min
45
50
ns
tWHDX
tDH
Write Enable High to Input Transition
Min
0
0
ns
tWHEH
tCH
Write Enable High to Chip Enable High
Min
0
0
ns
tWHWL
tWPH
Write Enable High to Write Enable Low
Min
30
30
ns
tAVWL
tAS
Address Valid to Write Enable Low
Min
0
0
ns
tWLAX
tAH
Write Enable Low to Address Transition
Min
45
50
ns
Output Enable High to Write Enable Low
Min
0
0
ns
tGHWL
tWHGL
tOEH
Write Enable High to Output Enable Low
Min
0
0
ns
tWHRL (1)
tBUSY
Program/Erase Valid to RB Low
Max
30
35
ns
tVCHEL
tVCS
VCC High to Chip Enable Low
Min
50
50
µs
Note: 1. Sampled only, not 100% tested.
21/36
M29W017D
Figure 12. Write AC Waveforms, Chip Enable Controlled
tAVAV
A0-A20
VALID
tELAX
tAVEL
tEHWH
W
tWLEL
tEHGL
G
tGHEL
tELEH
E
tEHEL
tDVEH
DQ0-DQ7
tEHDX
VALID
VCC
tVCHWL
RB
tEHRL
AI05250
Table 12. Write AC Characteristics, Chip Enable Controlled
M29W017D
Symbol
Alt
Parameter
Unit
70
90
tAVAV
tWC
Address Valid to Next Address Valid
Min
70
90
ns
tWLEL
tWS
Write Enable Low to Chip Enable Low
Min
0
0
ns
tELEH
tCP
Chip Enable Low to Chip Enable High
Min
45
50
ns
tDVEH
tDS
Input Valid to Chip Enable High
Min
45
50
ns
tEHDX
tDH
Chip Enable High to Input Transition
Min
0
0
ns
tEHWH
tWH
Chip Enable High to Write Enable High
Min
0
0
ns
tEHEL
tCPH
Chip Enable High to Chip Enable Low
Min
30
30
ns
tAVEL
tAS
Address Valid to Chip Enable Low
Min
0
0
ns
tELAX
tAH
Chip Enable Low to Address Transition
Min
45
50
ns
Output Enable High Chip Enable Low
Min
0
0
ns
tGHEL
tEHGL
tOEH
Chip Enable High to Output Enable Low
Min
0
0
ns
tEHRL (1)
tBUSY
Program/Erase Valid to RB Low
Max
30
35
ns
tVCHWL
tVCS
VCC High to Write Enable Low
Min
50
50
µs
Note: 1. Sampled only, not 100% tested.
22/36
M29W017D
Figure 13. Reset/Block Temporary Unprotect AC Waveforms
W, E, G
tPHWL, tPHEL, tPHGL
RB
tRHWL, tRHEL, tRHGL
tPLPX
RP
tPHPHH
tPLYH
AI02931B
Table 13. Reset/Block Temporary Unprotect AC Characteristics
M29W017D
Symbol
tPHWL (1)
tPHEL
Alt
Parameter
Unit
70
90
tRH
RP High to Write Enable Low, Chip Enable Low,
Output Enable Low
Min
50
50
ns
tRB
RB High to Write Enable Low, Chip Enable Low,
Output Enable Low
Min
0
0
ns
tPLPX
tRP
RP Pulse Width
Min
500
500
ns
tPLYH (1)
tREADY
RP Low to Read Mode
Max
10
10
µs
tPHPHH (1)
tVIDR
RP Rise Time to VID
Min
500
500
ns
tPHGL
(1)
tRHWL (1)
tRHEL (1)
tRHGL
(1)
Note: 1. Sampled only, not 100% tested.
23/36
M29W017D
PACKAGE MECHANICAL
TSOP40 – 40 lead Plastic Thin Small Outline, 10 x 20mm, Package Outline
A2
1
N
e
E
B
N/2
D1
A
CP
D
DIE
C
A1
TSOP-a
α
L
Note: Drawing is not to scale.
TSOP40 – 40 lead Plastic Thin Small Outline, 10 x 20mm, Package Mechanical Data
millimeters
inches
Symbol
Typ
Min
A
Typ
Min
1.200
Max
0.0472
A1
0.050
0.150
0.0020
0.0059
A2
0.950
1.050
0.0374
0.0413
B
0.170
0.270
0.0067
0.0106
C
0.100
0.210
0.0039
0.0083
D
19.800
20.200
0.7795
0.7953
D1
18.300
18.500
0.7205
0.7283
E
9.900
10.100
0.3898
0.3976
–
–
–
–
L
0.500
0.700
0.0197
0.0276
α
0°
5°
0°
5°
N
40
e
CP
24/36
Max
0.500
0.0197
40
0.100
0.0039
M29W017D
TFBGA48 8x9mm – 6x8 active ball array – 0.80mm pitch, Bottom View Package Outline
D
D1
FD
FE
E
SD
SE
E1
ddd
BALL "A1"
e
b
A2
A
A1
BGA-Z14
Note: Drawing is not to scale.
TFBGA48 8x9mm – 6x8 active ball array – 0.80mm pitch, Package Mechanical Data
millimeters
inches
Symbol
Typ
Min
A
A1
Max
Typ
Min
1.350
0.300
0.200
A2
0.350
0.0531
0.0118
0.0079
1.000
b
0.300
0.550
Max
0.0138
0.0394
0.0118
0.0217
D
8.000
7.900
8.100
0.3150
0.3110
0.3189
D1
4.000
–
–
0.1575
–
–
ddd
0.100
0.0039
e
0.800
–
–
0.0315
–
–
E
9.000
8.900
9.100
0.3543
0.3504
0.3583
E1
5.600
–
–
0.2205
–
–
FD
2.000
–
–
0.0787
–
–
FE
1.700
–
–
0.0669
–
–
SD
0.400
–
–
0.0157
–
–
SE
0.400
–
–
0.0157
–
–
25/36
M29W017D
PART NUMBERING
Table 14. Ordering Information Scheme
M29W017D
Example:
90
N
1
T
Device Type
M29
Operating Voltage
W = VCC = 2.7 to 3.6V
Device Function
017D = 16 Mbit (x8), Uniform Block
Speed
70 = 70 ns
90 = 90 ns
Package
N = TSOP40: 10 x 20 mm
ZA = TFBGA48: 0.80mm pitch
Temperature Range
1 = 0 to 70 °C
6 = –40 to 85 °C
Option
T = Tape & Reel Packing
Devices are shipped from the factory with the memory content bits erased to ’1’.
For a list of available options (Speed, Package, etc...) or for further information on any aspect of this device, please contact the ST Sales Office nearest to you.
REVISION HISTORY
Table 15. Document Revision History
Date
Version
May-2001
-01
First Issue (Brief Data)
18-Jun-2001
-02
Document expanded to full Product Preview, TFBGA Package Mechanical changed.
26-Jul-2001
-03
Document type: from Product Preview to Preliminary Data
03-Dec-2001
-04
Block Protection Appendix added, Read/Reset operation during Erase Suspend clarified .
05-Apr-2002
-05
Description of Ready/Busy signal clarified (and Figure 13 modified)
Clarified allowable commands during block erase
Clarified the mode the device returns to in the CFI Read Query command section
26/36
Revision Details
M29W017D
APPENDIX A. BLOCK ADDRESS TABLE
Table 16. Block Addresses, M29W017D
#
Size
(KBytes)
Address Range
31
64
1F0000h-1FFFFFh
30
64
1E0000h-1EFFFFh
29
64
1D0000h-1DFFFFh
28
64
1C0000h-1CFFFFh
27
64
1B0000h-1BFFFFh
26
64
1A0000h-1AFFFFh
25
64
190000h-19FFFFh
24
64
180000h-18FFFFh
23
64
170000h-17FFFFh
22
64
160000h-16FFFFh
21
64
150000h-15FFFFh
20
64
140000h-14FFFFh
19
64
130000h-13FFFFh
18
64
120000h-12FFFFh
17
64
110000h-11FFFFh
16
64
100000h-10FFFFh
#
Size
(KBytes)
Address Range
15
64
0F0000h-0FFFFFh
14
64
0E0000h-0EFFFFh
13
64
0D0000h-0DFFFFh
12
64
0C0000h-0CFFFFh
11
64
0B0000h-0BFFFFh
10
64
0A0000h-0AFFFFh
9
64
090000h-09FFFFh
8
64
080000h-08FFFFh
7
64
070000h-07FFFFh
6
64
060000h-06FFFFh
5
64
050000h-05FFFFh
4
64
040000h-04FFFFh
3
64
030000h-03FFFFh
2
64
020000h-02FFFFh
1
64
010000h-01FFFFh
0
64
000000h-00FFFFh
27/36
M29W017D
APPENDIX B. COMMON FLASH INTERFACE (CFI)
The Common Flash Interface is a JEDEC approved, standardized data structure that can be
read from the Flash memory device. It allows a
system software to query the device to determine
various electrical and timing parameters, density
information and functions supported by the memory. The system can interface easily with the device, enabling the software to upgrade itself when
necessary.
When the CFI Query Command is issued the device enters CFI Query mode and the data structure
is read from the memory. Tables 17, 18, 19, 20, 21
and 22 show the addresses used to retrieve the
data.
The CFI data structure also contains a security
area where a 64 bit unique security number is written (see Table 22, Security Code area). This area
can be accessed only in Read mode by the final
user. It is impossible to change the security number after it has been written by ST. Issue a Read/
Reset command to return to Read mode.
Table 17. Query Structure Overview
Address
Sub-section Name
Description
10h
CFI Query Identification String
Command set ID and algorithm data offset
1Bh
System Interface Information
Device timing & voltage information
27h
Device Geometry Definition
Flash device layout
40h
Primary Algorithm-specific Extended Query
table
Additional information specific to the Primary
Algorithm (optional)
61h
Security Code Area
64 bit unique device number
Note: Query data are always presented on the lowest order data outputs.
Table 18. CFI Query Identification String
Address
Data
Description
10h
51h
11h
52h
12h
59h
13h
02h
14h
00h
15h
40h
16h
00h
17h
00h
18h
00h
Alternate Vendor Command Set and Control Interface ID Code second vendor
- specified algorithm supported
19h
00h
Address for Alternate Algorithm extended Query table
1Ah
00h
"Q"
Query Unique ASCII String "QRY"
"R"
"Y"
Primary Algorithm Command Set and Control Interface ID code 16 bit ID code
defining a specific algorithm
Address for Primary Algorithm extended Query table (see Table 20)
28/36
Value
AMD
Compatible
P = 40h
NA
NA
M29W017D
Table 19. CFI Query System Interface Information
Address
Data
Description
Value
1Bh
27h
VCC Logic Supply Minimum Program/Erase voltage
bit 7 to 4
BCD value in volts
bit 3 to 0
BCD value in 100 mV
2.7V
1Ch
36h
VCC Logic Supply Maximum Program/Erase voltage
bit 7 to 4
BCD value in volts
bit 3 to 0
BCD value in 100 mV
3.6V
1Dh
00h
VPP [Programming] Supply Minimum Program/Erase voltage
NA
1Eh
00h
VPP [Programming] Supply Maximum Program/Erase voltage
NA
1Fh
04h
Typical timeout per single byte/word program = 2n µs
20h
00h
Typical timeout for minimum size write buffer program = 2n µs
NA
21h
0Ah
Typical timeout per individual block erase = 2n ms
1s
22h
00h
Typical timeout for full chip erase = 2n ms
NA
23h
04h
Maximum timeout for byte/word program = 2n times typical
24h
00h
Maximum timeout for write buffer program = 2n times typical
NA
25h
03h
Maximum timeout per individual block erase = 2n times typical
8s
26h
00h
Maximum timeout for chip erase = 2n times typical
NA
16µs
256µs
Table 20. Device Geometry Definition
Address
Data
Description
Value
27h
15h
Device Size = 2n in number of bytes
28h
29h
00h
00h
Flash Device Interface Code description
2Ah
2Bh
00h
00h
Maximum number of bytes in multi-byte program or page = 2n
2Ch
01h
Number of Erase Block Regions within the device.
It specifies the number of regions within the device containing contiguous
Erase Blocks of the same size.
1
2Dh
2Eh
1Fh
00h
Region 1 Information
Number of identical size erase block = 001Fh+1
32
2Fh
30h
00h
01h
Region 1 Information
Block size in Region 1 = 0100h * 256 byte
2 MByte
x8
Async.
NA
64 KByte
29/36
M29W017D
Table 21. Primary Algorithm-Specific Extended Query Table
Address
Data
Description
40h
50h
41h
52h
42h
49h
43h
31h
Major version number, ASCII
"1"
44h
30h
Minor version number, ASCII
"0"
45h
01h
Address Sensitive Unlock (bits 1 to 0)
00 = required, 01= not required
Silicon Revision Number (bits 7 to 2)
No
46h
02h
Erase Suspend
00 = not supported, 01 = Read only, 02 = Read and Write
2
47h
01h
Block Protection
00 = not supported, x = number of blocks per group
1
48h
01h
Temporary Block Unprotect
00 = not supported, 01 = supported
49h
04h
Block Protect /Unprotect
04 = M29W400B mode
4Ah
00h
Simultaneous Operations, 00 = not supported
No
4Bh
00h
Burst Mode, 00 = not supported, 01 = supported
No
4Ch
00h
Page Mode, 00 = not supported, 01 = 4 page word, 02 = 8 page word
No
"P"
Primary Algorithm extended Query table unique ASCII string “PRI”
"R"
"I"
Yes
4
Table 22. Security Code Area
Address
Data
61h
XX
62h
XX
63h
XX
64h
XX
65h
XX
66h
XX
67h
XX
68h
XX
30/36
Value
Description
64 bit: unique device number
M29W017D
APPENDIX C. BLOCK PROTECTION
Block protection can be used to prevent any operation from modifying the data stored in the Flash.
Each Block can be protected individually. Once
protected, Program and Erase operations on the
block fail to change the data.
There are three techniques that can be used to
control Block Protection, these are the Programmer technique, the In-System technique and Temporary Unprotection. Temporary Unprotection is
controlled by the Reset/Block Temporary Unprotection pin, RP; this is described in the Signal Descriptions section.
Unlike the Command Interface of the Program/
Erase Controller, the techniques for protecting and
unprotecting blocks change between different
Flash memory suppliers. For example, the techniques for AMD parts will not work on STMicroelectronics parts. Care should be taken when
changing drivers for one part to work on another.
Programmer Technique
The Programmer technique uses high (V ID) voltage levels on some of the bus pins. These cannot
be achieved using a standard microprocessor bus,
therefore the technique is recommended only for
use in Programming Equipment.
To protect a block follow the flowchart in Figure 14,
Programmer Equipment Block Protect Flowchart.
To unprotect the whole chip it is necessary to protect all of the blocks first, then all blocks can be unprotected at the same time. To unprotect the chip
follow Figure 15, Programmer Equipment Chip
Unprotect Flowchart. Table 23, Programmer
Technique Bus Operations, gives a summary of
each operation.
The timing on these flowcharts is critical. Care
should be taken to ensure that, where a pause is
specified, it is followed as closely as possible. Do
not abort the procedure before reaching the end.
Chip Unprotect can take several seconds and a
user message should be provided to show that the
operation is progressing.
In-System Technique
The In-System technique requires a high voltage
level on the Reset/Blocks Temporary Unprotect
pin, RP. This can be achieved without violating the
maximum ratings of the components on the microprocessor bus, therefore this technique is suitable
for use after the Flash has been fitted to the system.
To protect a block follow the flowchart in Figure 16,
In-System Block Protect Flowchart. To unprotect
the whole chip it is necessary to protect all of the
blocks first, then all the blocks can be unprotected
at the same time. To unprotect the chip follow Figure 17, In-System Chip Unprotect Flowchart.
The timing on these flowcharts is critical. Care
should be taken to ensure that, where a pause is
specified, it is followed as closely as possible. Do
not allow the microprocessor to service interrupts
that will upset the timing and do not abort the procedure before reaching the end. Chip Unprotect
can take several seconds and a user message
should be provided to show that the operation is
progressing.
Table 23. Programmer Technique Bus Operations, BYTE = V IH or VIL
E
G
W
Address Inputs
A0-A20
Data Inputs/Outputs
DQ15A–1, DQ14-DQ0
Block Protect
VIL
VID
VIL Pulse
A9 = VID, A12-A20 Block Address
Others = X
X
Chip Unprotect
VID
VID
VIL Pulse
A9 = VID, A12 = VIH, A15 = VIH
Others = X
X
Block Protection
Verify
VIL
VIL
VIH
A0 = VIL, A1 = VIH, A6 = VIL, A9 = VID,
A12-A20 Block Address
Others = X
Pass = XX01h
Retry = XX00h
Block Unprotection
Verify
VIL
VIL
VIH
A0 = VIL, A1 = VIH, A6 = VIH, A9 = VID,
A12-A20 Block Address
Others = X
Retry = XX01h
Pass = XX00h
Operation
31/36
M29W017D
Figure 14. Programmer Equipment Block Protect Flowchart
START
Set-up
ADDRESS = BLOCK ADDRESS
W = VIH
n=0
G, A9 = VID,
E = VIL
Protect
Wait 4µs
W = VIL
Wait 100µs
W = VIH
E, G = VIH,
A0, A6 = VIL,
A1 = VIH
E = VIL
Verify
Wait 4µs
G = VIL
Wait 60ns
Read DATA
DATA
NO
=
01h
YES
A9 = VIH
E, G = VIH
++n
= 25
NO
End
YES
PASS
A9 = VIH
E, G = VIH
FAIL
32/36
AI03469
M29W017D
Figure 15. Programmer Equipment Chip Unprotect Flowchart
START
Set-up
PROTECT ALL BLOCKS
n=0
CURRENT BLOCK = 0
A6, A12, A15 = VIH(1)
E, G, A9 = VID
Unprotect
Wait 4µs
W = VIL
Wait 10ms
W = VIH
E, G = VIH
ADDRESS = CURRENT BLOCK ADDRESS
A0 = VIL, A1, A6 = VIH
E = VIL
Wait 4µs
G = VIL
INCREMENT
CURRENT BLOCK
Verify
Wait 60ns
Read DATA
NO
End
NO
++n
= 1000
DATA
=
00h
YES
LAST
BLOCK
YES
YES
A9 = VIH
E, G = VIH
A9 = VIH
E, G = VIH
FAIL
PASS
NO
AI03470
33/36
M29W017D
Figure 16. In-System Equipment Block Protect Flowchart
Set-up
START
n=0
RP = VID
Protect
WRITE 60h
ADDRESS = BLOCK ADDRESS
A0 = VIL, A1 = VIH, A6 = VIL
WRITE 60h
ADDRESS = BLOCK ADDRESS
A0 = VIL, A1 = VIH, A6 = VIL
Wait 100µs
Verify
WRITE 40h
ADDRESS = BLOCK ADDRESS
A0 = VIL, A1 = VIH, A6 = VIL
Wait 4µs
READ DATA
ADDRESS = BLOCK ADDRESS
A0 = VIL, A1 = VIH, A6 = VIL
DATA
NO
=
01h
YES
End
RP = VIH
ISSUE READ/RESET
COMMAND
PASS
++n
= 25
NO
YES
RP = VIH
ISSUE READ/RESET
COMMAND
FAIL
AI03471
34/36
M29W017D
Figure 17. In-System Equipment Chip Unprotect Flowchart
START
Set-up
PROTECT ALL BLOCKS
n=0
CURRENT BLOCK = 0
RP = VID
WRITE 60h
ANY ADDRESS WITH
A0 = VIL, A1 = VIH, A6 = VIH
Unprotect
WRITE 60h
ANY ADDRESS WITH
A0 = VIL, A1 = VIH, A6 = VIH
Wait 10ms
Verify
WRITE 40h
ADDRESS = CURRENT BLOCK ADDRESS
A0 = VIL, A1 = VIH, A6 = VIH
Wait 4µs
READ DATA
ADDRESS = CURRENT BLOCK ADDRESS
A0 = VIL, A1 = VIH, A6 = VIH
NO
End
NO
++n
= 1000
YES
DATA
=
00h
INCREMENT
CURRENT BLOCK
YES
LAST
BLOCK
NO
YES
RP = VIH
RP = VIH
ISSUE READ/RESET
COMMAND
ISSUE READ/RESET
COMMAND
FAIL
PASS
AI03472
35/36
M29W017D
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
The ST logo is registered trademark of STMicroelectronics
All other names are the property of their respective owners
© 2002 STMicroelectronics - All Rights Reserved
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36/36