M68AR024D 16 Mbit (1M x16) 1.8V Asynchronous SRAM PRELIMINARY DATA FEATURES SUMMARY ■ SUPPLY VOLTAGE: 1.65 to 1.95V ■ I/O SUPPLY VOLTAGE: 1.5 to 1.95V ■ 1M WORDS x 16 bits LOW POWER SRAM ■ EQUAL CYCLE and ACCESS TIME: 70ns ■ ■ LOW VCC DATA RETENTION: 1.0V LOW STANDBY CURRENT ■ TRI-STATE COMMON I/O ■ SINGLE BYTE READ/WRITE ■ AUTOMATIC POWER DOWN Figure 1. Packages BGA TFBGA48 (ZH) 8 x 10 mm (for Engineering Samples only) BGA TFBGA48 (ZB) 6.5 x 10 mm October 2002 This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice. 1/19 M68AR024D TABLE OF CONTENTS SUMMARY DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Figure 3. TFBGA Connections (Top view through package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Figure 4. Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Table 2. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Table 3. Operating and AC Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Figure 5. AC Measurement I/O Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Figure 6. AC Measurement Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Table 4. Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Table 5. DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Table 6. Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Read Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Figure 7. Address Controlled, Read Mode AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Figure 8. Chip Enable or Output Enable Controlled, Read Mode AC Waveforms . . . . . . . . . . . . . . 9 Figure 9. Chip Enable or UB/LB Controlled, Standby Mode AC Waveforms . . . . . . . . . . . . . . . . . . 9 Table 7. Read and Standby Mode AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Write Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Figure 10. Write Enable Controlled, Write AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Figure 11. Chip Enable E1 Controlled, Write AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Figure 12. UB/LB Controlled, Write AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Table 8. Write Mode AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Figure 13. E1 Controlled, Low VCC Data Retention AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . 14 Figure 14. E2 Controlled, Low VCC Data Retention AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . 14 Table 9. Low VCC Data Retention Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Figure 15. TFBGA48 6.5x10mm - 6x8 ball array, 0.75 mm pitch, Bottom View Package Outline. . 15 Table 11. TFBGA48 8x10mm - 6x8 ball array, 0.75 mm pitch, Package Mechanical Data. . . . . . . 16 PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Table 12. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 7 REVISION HISTORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Table 13. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2/19 M68AR024D SUMMARY DESCRIPTION The M68AR024D is a 16 Mbit (16,777,216 bit) Low Power SRAM fabricated in STMicroelectronics advanced CMOS technology, organized as 1,048,576 words by 16 bits. The device exhibits fully static operation requiring no external clocks or timing strobes. It needs 1.65 to 1.95V supply voltage. By using the VCCQ pin all the outputs can be powered independently from the core supply voltage allowing to drive the I/O pins down to 1.5V. V CCQ pin can be tied to Vcc if the feature is not required. Figure 2. Logic Diagram VCC Table 1. Signal Names VCCQ 20 16 A0-A19 This device has a standard Asynchronous SRAM Interface. Read and Write cycles can be performed on a single byte by using UB/LB signals. The device can be put into standby mode by using E1/E2 pins. The same pins can be used to cascade more devices in order to achieve deep memory expansion. Standby mode allows a low current consumption, up to 99%, by reducing internal activities. The M68AR024D is available in TFBGA48 (0.75 mm pitch) package with industrial standard footprint. DQ0-DQ15 W A0-A19 Address Inputs DQ0-DQ15 Data Input/Output E1, E2 Chip Enables G Output Enable W Write Enable UB Upper Byte Enable Input LB Lower Byte Enable Input VCC Supply Voltage VCCQ I/O Supply Voltage VSS Ground NC Not Connected Internally DU Don’t Use as Internally Connected E1 E2 M68AR024D G UB LB VSS AI05400c 3/19 M68AR024D Figure 3. TFBGA Connections (Top view through package) 1 2 3 4 5 6 A LB G A0 A1 A2 E2 B DQ8 UB A3 A4 E1 DQ0 C DQ9 DQ10 A5 A6 DQ1 DQ2 D VSS DQ11 A17 A7 DQ3 VCC E VCCQ DQ12 NC A16 DQ4 VSS F DQ14 DQ13 A14 A15 DQ5 DQ6 G DQ15 A19 A12 A13 W DQ7 H A18 A8 A9 A10 A11 DU AI05918 4/19 M68AR024D Figure 4. Block Diagram A19 ROW DECODER MEMORY ARRAY A8 DQ15 (8) I/O CIRCUITS UB COLUMN DECODER DQ0 E1 Ex E2 (8) LB UB LB A0 A7 (8) UB W (8) LB G AI05924 MAXIMUM RATING Stressing the device above the rating listed in the Absolute Maximum Ratings table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not im- plied. Exposure to Absolute Maximum Rating conditions for periods greater than 1 sec may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents. Table 2. Absolute Maximum Ratings Symbol Value Unit Output Current 20 mA PD Power Dissipation 1 W TA Ambient Operating Temperature –55 to 125 °C TSTG Storage Temperature –65 to 150 °C VCC Supply Voltage –0.5 to 2.5 V VCCQ I/O Supply Voltage –0.5 to 2.5 V VIO (2) Input or Output Voltage –0.5 to VCCQ +0.5 V IO (1) Parameter Note: 1. One output at time not to exceed 1 second duration. 2. Up to a maximum operating VCC or VCCQ of 1.95V only. 5/19 M68AR024D DC AND AC PARAMETERS This section summarizes the operating and measurement conditions, as well as the DC and AC characteristics of the device. The parameters in the following DC and AC Characteristic tables are derived from tests performed under the Measure- ment Conditions listed in the relevant tables. Designers should check that the operating conditions in their projects match the measurement conditions when using the quoted parameters. Table 3. Operating and AC Measurement Conditions Parameter M68AR024D VCC Supply Voltage 1.65 to 1.95V VCCQ I/O Supply Voltage (VCCQ ≤ VCC) 1.5 to 1.95V Range 1 0 to 70°C Range 6 –40 to 85°C Ambient Operating Temperature Load Capacitance (CL) 30pF Output Circuit Protection Resistance (R1) 15.3kΩ Load Resistance (R2) 11.3kΩ Input Rise and Fall Times ≤ 1ns/V 0 to VCCQ Input Pulse Voltages Input and Output Timing Ref. Voltages VCCQ/2 Output Transition Timing Ref. Voltages VRL = 0.3VCCQ; VRH = 0.7VCCQ Figure 5. AC Measurement I/O Waveform Figure 6. AC Measurement Load Circuit VCCQ I/O Timing Reference Voltage R1 VCCQ VCCQ/2 0V DEVICE UNDER TEST OUT CL I/O Transition Timing Reference Voltage VCCQ 0V R2 0.7VCCQ 0.3VCCQ AI05987 CL includes JIG capacitance AI05988 6/19 M68AR024D Table 4. Capacitance CIN COUT (3) Test Condition Parameter (1,2) Symbol Input Capacitance on all pins (except DQ) Output Capacitance Min Max Unit VIN = 0V 6 pF VOUT = 0V 8 pF Note: 1. Sampled only, not 100% tested. 2. At TA = 25°C, f = 1MHz, VCC = 1.8V. 3. Outputs deselected. Table 5. DC Characteristics Symbol Parameter Test Condition ICC1 (1,2) Operating Supply Current VCC = 1.95V, f = 1/tAVAV, IOUT = 0mA ICC2 (3) Operating Supply Current VCC = 1.95V, f = 1MHz, IOUT = 0mA ILI Input Leakage Current ILO (4) Output Leakage Current Min Typ Max Unit 5 25 mA 3 mA 0V ≤ VIN ≤ VCC –1 1 µA 0V ≤ VOUT ≤ VCC –1 1 µA 15 µA VCC = 1.95V, E1 ≥ VCCQ –0.2V OR E2 ≤ 0.2V OR UB, LB ≥ VCCQ –0.2V, f=0 1 ISB Standby Supply Current CMOS VIH Input High Voltage VCCQ – 0.4 VCCQ + 0.3 V VIL Input Low Voltage –0.3 0.4 V VOH Output High Voltage IOH = –100µA VOL Output Low Voltage IOL = 100µA Note: 1. 2. 3. 4. VCCQ – 0.2 V 0.2 V Average AC current, cycling at tAVAV minimum. E1 = V IL, E2 = VIH, UB OR/AND LB = V IL, VIN = VIH OR VIL. E1 ≤ 0.2V or E2 ≥ V CCQ –0.2V, UB OR/AND LB ≤ 0.2V, VIN ≤ 0.2V or VIN ≥ VCCQ –0.2V. Output disabled. 7/19 M68AR024D OPERATION The M68AR024D has a Chip Enable power down feature which invokes an automatic standby mode whenever Chip Enable is de-asserted (E1 = High) or Chip Select is asserted (E2 = Low), or UB/LB are de-asserted (UB/LB = High). An Output Enable (G) signal provides a high speed tri-state con- trol, allowing fast read/write cycles to be achieved with the common I/O data bus. Operational modes are determined by device control inputs W, E1, LB and UB as summarized in the Operating Modes table (see Table 6). Table 6. Operating Modes Operation E1 E2 W G LB UB DQ0-DQ7 DQ8-DQ15 Power Deselected/Standby VIH X X X X X Hi-Z Hi-Z Standby (ISB) Deselected/Standby X VIL X X X X Hi-Z Hi-Z Standby (ISB) Deselected/Standby X X X X VIH VIH Hi-Z Hi-Z Standby (ISB) Lower Byte Read VIL VIH VIH VIL VIL VIH Data Output Hi-Z Active (ICC) Lower Byte Write VIL VIH VIL X VIL VIH Data Input Hi-Z Active (ICC) Output Disabled VIL VIH VIH VIH X X Hi-Z Hi-Z Active (ICC) Upper Byte Read VIL VIH VIH VIL VIH VIL Hi-Z Data Output Active (ICC) Upper Byte Write VIL VIH VIL X VIH VIL Hi-Z Data Input Active (ICC) Word Read VIL VIH VIH VIL VIL VIL Data Output Data Output Active (ICC) Word Write VIL VIH VIL X VIL VIL Data Input Data Input Active (ICC) Note: 1. X = VIH or VIL. Read Mode The M68AR024D, when Chip Select (E2) is High, is in the read mode whenever Write Enable (W) is High with Output Enable (G) Low, and Chip Enable (E1) is asserted. This provides access to data from eight or sixteen, depending on the status of the signal UB and LB, of the 16,777,216 locations in the static memory array, specified by the 20 address inputs. Valid data will be available at the eight or sixteen output pins within tAVQV after the last stable address, providing G is Low and E1 is Low. If Chip Enable or Output Enable access times are not met, data access will be measured from the limiting parameter (tELQV, tGLQV or tBLQV) rather than the address. Data out may be indeterminate at tELQX, tGLQX and tBLQX, but data lines will always be valid at tAVQV Figure 7. Address Controlled, Read Mode AC Waveforms tAVAV A0-A19 VALID tAVQV DQ0-DQ7 and/or DQ8-DQ15 tAXQX DATA VALID AI05403 Note: E1 = Low, E2 = High, G = Low, W = High, UB = Low and/or LB = Low. 8/19 M68AR024D Figure 8. Chip Enable or Output Enable Controlled, Read Mode AC Waveforms tAVAV VALID A0-A19 tAVQV tAXQX tELQV tEHQZ E1 E2 tELQX tGLQV tGHQZ G tGLQX DQ0-DQ15 VALID tBLQV tBHQZ UB, LB tBLQX AI07730 Note: Write Enable (W) = High Figure 9. Chip Enable or UB/LB Controlled, Standby Mode AC Waveforms E1, UB, LB E2 ICC ISB tPU tPD 50% AI05990 9/19 M68AR024D Table 7. Read and Standby Mode AC Characteristics M68AR024D Symbol Parameter Unit 70 tAVAV Read Cycle Time Min 70 ns tAVQV Address Valid to Output Valid Max 70 ns Data hold from address change Min 5 ns tBHQZ (2, 3) Upper/Lower Byte Enable High to Output Hi-Z Max 25 ns tBLQV Upper/Lower Byte Enable Low to Output Valid Max 70 ns Upper/Lower Byte Enable Low to Output Transition Min 5 ns tEHQZ (2, 3) Chip Enable High to Output Hi-Z Max 25 ns tELQV Chip Enable Low to Output Valid Max 70 ns Chip Enable Low to Output Transition Min 5 ns tGHQZ (2, 3) Output Enable High to Output Hi-Z Max 25 ns tGLQV Output Enable Low to Output Valid Max 35 ns Output Enable Low to Output Transition Min 5 ns tPD (4) Chip Enable High to Power Down Max 0 ns tPU (4) Chip Enable Low to Power Up Min 70 ns tAXQX (1) tBLQX (1) tELQX (1) tGLQX (1) Note: 1. Test conditions assume transition timing reference level = 0.3VCCQ to 0.7VCCQ. 2. At any given temperature and voltage condition, tGHQZ is less than tGLQX, tBHQZ is less than tBLQX and tEHQZ is less than tELQX for any given device. 3. These parameters are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels. 4. Tested initially and after any design or process changes that may affect these parameters. 10/19 M68AR024D Write Mode The M68AR024D, when Chip Select (E2) is High, is in the Write Mode whenever the W and E1 are Low. Either the Chip Enable Input (E1) or the Write Enable input (W) must be de-asserted during Address transitions for subsequent write cycles. When E1 or W is Low, and UB or LB is Low, write cycle begins on the W or E1 falling edge. When E1 and W are Low, and UB = LB = High, write cycle begins on the first falling edge of UB or LB. Therefore, address setup time is referenced to Write Enable, Chip Enables and UB/LB as t AVWL, tAVEL and tAVBL respectively, and is determined by the latter occurring falling edge. The Write cycle can be terminated by the earlier rising edge of E1, W, UB and LB. If the Output is enabled (E1 = Low, E2 = High, G = Low, LB or UB = Low), then W will return the outputs to high impedance within tWLQZ of its falling edge. Care must be taken to avoid bus contention in this type of operation. Data input must be valid for t DVWH before the rising edge of Write Enable, or for tDVEH before the rising edge of E1 or for t DVBH before the rising edge of UB/LB, whichever occurs first, and remain valid for t WHDX, tEHDX and tBHDX respectively. Figure 10. Write Enable Controlled, Write AC Waveforms tAVAV VALID A0-A19 tAVWH tELWH tAVEL tWHAX E1 E2 tWLWH tAVWL W tWLQZ tWHQX tWHDX DATA INPUT DQ0-DQ15 tDVWH tBLBH UB, LB AI05991 11/19 M68AR024D Figure 11. Chip Enable E1 Controlled, Write AC Waveforms tAVAV VALID A0-A19 tAVEH tELEH tAVEL tEHAX E1 E2 tAVWL tWLEH W tEHDX DATA INPUT DQ0-DQ15 tDVEH tBLBH UB, LB AI05992 Figure 12. UB/LB Controlled, Write AC Waveforms tAVAV VALID A0-A19 tAVBH tBHAX E1 E2 tWLBH tAVWL W tWLQZ DQ0-DQ15 tBHDX DATA (1) DATA INPUT tDVBH tAVBL tBLBH UB, LB AI05993 Note: 1. During this period DQ0-DQ15 are in output state and input signals should not be applied. 12/19 M68AR024D Table 8. Write Mode AC Characteristics M68AR024D Symbol Parameter Unit 70 tAVAV Write Cycle Time Min 70 ns tAVBH Address Valid to LB, UB High Min 60 ns tAVBL Addess Valid to LB, UB Low Min 0 ns tAVEH Address Valid to Chip Enable High Min 60 ns tAVEL Address valid to Chip Enable Low Min 0 ns tAVWH Address Valid to Write Enable High Min 60 ns tAVWL Address Valid to Write Enable Low Min 0 ns tBHAX LB, UB High to Address Transition Min 0 ns tBHDX LB, UB High to Input Transition Min 0 ns tBLBH LB, UB Low to LB, UB High Min 60 ns tBLEH LB, UB Low to Chip Enable High Min 60 ns tBLWH LB, UB Low to Write Enable High Min 60 ns tDVBH Input Valid to LB, UB High Min 30 ns tDVEH Input Valid to Chip Enable High Min 30 ns tDVWH Input Valid to Write Enable High Min 30 ns tEHAX Chip Enable High to Address Transition Min 0 ns tEHDX Chip enable High to Input Transition Min 0 ns tELBH Chip Enable Low to LB, UB High Min 60 ns tELEH Chip Enable Low to Chip Enable High Min 60 ns tELWH Chip Enable Low to Write Enable High Min 60 ns tWHAX Write Enable High to Address Transition Min 0 ns tWHDX Write Enable High to Input Transition Min 0 ns Write Enable High to Output Transition Min 5 ns tWLBH Write Enable Low to LB, UB High Min 60 ns tWLEH Write Enable Low to Chip Enable High Min 60 ns Write Enable Low to Output Hi-Z Max 20 ns Write Enable Low to Write Enable High Min 50 ns tWHQX (1) tWLQZ (1, 2) tWLWH Note: 1. At any given temperature and voltage condition, tWHQZ is less than t WLQX for any given device. 2. These parameters are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels. 13/19 M68AR024D Figure 13. E1 Controlled, Low VCC Data Retention AC Waveforms DATA RETENTION MODE 1.95V VCC 1.65V VDR > 1.0V tCDR tR E1 ≥ VDR – 0.2V E1 AI05855 Figure 14. E2 Controlled, Low VCC Data Retention AC Waveforms DATA RETENTION MODE 1.95V VCC 1.65V VDR > 1.0V tCDR tR E2 E2 ≤ 0.2V AI05875 Table 9. Low V CC Data Retention Characteristics Symbol ICCDR (1) Parameter Supply Current (Data Retention) Test Condition Min VCC = 1.0V, E1 ≥ VCCQ –0.2V OR E2 ≤ 0.2V OR UB, LB ≥ VCCQ –0.2V, Typ Max Unit 0.5 5 µA f=0 tCDR (2) tR (2) VDR (1) Chip deselected to Data Retention Time Operation Recovery Time Supply Voltage (Data Retention) E1 ≥ VCCQ –0.2V OR E2 ≤ 0.2V OR UB, LB ≥ VCCQ –0.2V, f=0 0 ns tAVAV ns 1.0 V Note: 1. All other Inputs at V IH ≥ VCCQ –0.2V or VIL ≤ 0.2V. 2. Tested initially and after any design or process changes that may affect these parameters. tAVAV is Read cycle time. 3. No input may exceed VCC +0.2V. 14/19 M68AR024D PACKAGE MECHANICAL Figure 15. TFBGA48 6.5x10mm - 6x8 ball array, 0.75 mm pitch, Bottom View Package Outline D D1 SD FD FE SE E E1 e BALL "A1" ddd e b A2 A A1 BGA-Z30 Note: Drawing is not to scale. Table 10. TFBGA48 6.5x10mm - 6x8 ball array, 0.75 mm pitch, Package Mechanical Data millimeters inches Symbol Typ Min A Typ Min 1.200 A1 A2 Max 0.300 b 0.0472 0.400 0.790 Max 0.0118 0.0157 0.0138 0.0177 0.0311 0.350 0.450 D 6.500 6.400 6.600 0.2559 0.2520 0.2598 D1 3.750 – – 0.1476 – – ddd 0.100 0.0039 E 10.000 9.900 10.100 0.3937 0.3898 0.3976 E1 5.250 – – 0.2067 – – e 0.750 – – 0.0295 – – FD 0.875 – – 0.0344 – – FE 3.125 – – 0.1230 – – SD 0.375 – – 0.0148 – – SE 0.375 – – 0.0148 – – 15/19 M68AR024D Figure 16. TFBGA48 8x10mm - 6x8 ball array, 0.75 mm pitch, Bottom View Package Outline D D1 FD FE E SD SE E1 ddd BALL "A1" A e A2 b A1 BGA-Z28 Note: Drawing is not to scale. Table 11. TFBGA48 8x10mm - 6x8 ball array, 0.75 mm pitch, Package Mechanical Data millimeters Symbol Typ Min A Max Typ Min 1.200 A1 0.0102 0.900 b Max 0.0472 0.260 A2 0.350 0.450 0.0354 0.0138 0.0177 D 8.000 7.900 8.100 0.3150 0.3110 0.3189 D1 3.750 – – 0.1476 – – ddd 16/19 inches 0.100 0.0039 E 10.000 9.900 10.100 0.3937 0.3898 0.3976 E1 5.250 – – 0.2067 – – e 0.750 – – 0.0295 – – FD 2.125 – – 0.0837 – – FE 2.375 – – 0.0935 – – SD 0.375 – – 0.0148 – – SE 0.375 – – 0.0148 – – M68AR024D PART NUMBERING Table 12. Ordering Information Scheme Example: M68AR016 D N 70 ZB 6 T Device Type M68 Mode A = Asynchronous Operating Voltage R = 1.65 to 1.95V Array Organization 024 = 16 Mbit (1M x16) Option 1 D = 2 Chip Enable; Write and Standby from UB and LB Option 2 N = N-Die Speed Class 70 = 70 ns Package ZH = TFBGA48: 0.75 mm pitch (8x10mm) (1) ZB = TFBGA48: 0.75 mm pitch (6.5x10mm) Operative Temperature 1 = 0 to 70°C 6 = –40 to 85 °C Shipping T = Tape & Reel Packing Note: 1. This package is available for Engineering Samples only. 17/19 M68AR024D REVISION HISTORY Table 13. Document Revision History Date Version July 2001 -01 First Issue 24-Oct-2001 -02 Table of Contents added Block Diagram added, Data Retention AC Waveforms clarified Package Mechanical Data and Drawing added 07-Nov-2001 -03 Voltage range extended up to 2.2V 19-Feb-2002 -04 Document totally revised 12-Mar-2002 -05 Features Summary clarified Tables 2, 3, 4, 5, 6, 7, 8 and 9 clarified Figures 8, 10, 11 and 12 clarified 20-Mar-2002 -06 TFBGA 6.5x10 package added 19-Apr-2002 -07 Chip Enable Controlled, Low VCC Data Retention AC Waveforms clarified (Figures 13 and 14) 02-Oct-2002 7.1 Revision numbering modified: a minor revision will be indicated by incrementing the digit after the dot, and a major revision, by incrementing the digit before the dot (revision version 07 equals 7.0). Part number changed. 04-Oct-2002 7.2 Document status changed from Target Specification to Preliminary Data. 09-Oct-2002 7.3 Part number modified. 18/19 Revision Details M68AR024D Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. 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