STMICROELECTRONICS ST72F561AR9

ST72561
8-BIT MCU WITH FLASH OR ROM,
10-BIT ADC, 5 TIMERS, SPI, LINSCI, ACTIVE CAN
PRELIMINARY DATA
■
■
■
■
■
Memories
– 32K to 60K High Density Flash (HDFlash) or
ROM with read-out protection capability. InApplication Programming and In-Circuit Programming for HDFlash devices
– 1 to 2K RAM
– HDFlash endurance: 100 cycles, data retention: 20 years at 55°C
Clock, Reset and Supply Management
– Low power crystal/ceramic resonator oscillators and bypass for external clock
– PLL for 2x frequency multiplication
– Five Power Saving Modes: Halt, Auto Wake
Up From Halt, Active-Halt, Wait and Slow
Interrupt Management
– Nested interrupt controller
– 14 interrupt vectors plus TRAP and RESET
– TLI top level interrupt (on 64-pin devices)
– Up to 21 external interrupt lines (on 4 vectors)
Up to 48 I/O Ports
– Up to 48 multifunctional bidirectional I/O lines
– Up to 36 alternate function lines
– Up to 6 high sink outputs
5 Timers
– 16-bit Timer with: 2 input captures, 2 output
compares, external clock input, PWM and
pulse generator modes
– 8-bit Timer with: 1 or 2 input captures, 1 or 2
output compares, PWM and pulse generator
modes
– 8-bit PWM Auto-Reload Timer with: 1 or 2 input captures, 2 or 4 independent PWM output
channels, output compare and time base interrupt, external clock with event detector
TQFP32
7x7mm
TQFP64
14 x 14
TQFP44
10x10mm
■
■
■
■
TQFP64
10 x 10
– Main Clock Controller with: Real time base
and Clock output
– Window watchdog timer
Up to 4 Communications Interfaces
– SPI synchronous serial interface
– Master/slave LINSCI asynchronous serial
interface
– Master-only LINSCI asynchronous serial interface
– CAN 2.0B active
Analog peripheral (low current coupling)
– 10-bit A/D Converter with up to 16 inputs
– Up to 9 robust ports (low current coupling)
Instruction Set
– 8-bit data manipulation
– 63 basic instructions
– 17 main addressing modes
– 8 x 8 unsigned multiply instruction
Development Tools
– Full hardware/software development package
Device Summary
Features
ST72(F)561(AR/R/J/K)9
ST72(F)561(AR/R/J/K)6
Program memory - bytes
RAM (stack) - bytes
Operating Supply
CPU Frequency
Max. Temp. Range
Packages
60K
2K (256)
32K
1K (256)
4.5V to 5.5V
External Resonator Osc. w/ PLLx2/8MHz
-40°C to +125°C
TQFP64 10x10mm (AR), TQFP64 14x14mm (R), TQFP44 10x10mm (J), TQFP32 7x7mm (K)
Rev. 2
May 2004
1/262
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
1
Table of Contents
1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2 PIN DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3 REGISTER & MEMORY MAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4 FLASH PROGRAM MEMORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.2 MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.3 STRUCTURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.4 ICC INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.5 ICP (IN-CIRCUIT PROGRAMMING) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.6 IAP (IN-APPLICATION PROGRAMMING) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.7 RELATED DOCUMENTATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.8 REGISTER DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5 CENTRAL PROCESSING UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
5.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
5.2 MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
5.3 CPU REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
6 SUPPLY, RESET AND CLOCK MANAGEMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
6.1 PHASE LOCKED LOOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
6.2 MULTI-OSCILLATOR (MO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
6.3 RESET SEQUENCE MANAGER (RSM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
6.4 SYSTEM INTEGRITY MANAGEMENT (SI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
7 INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
7.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
7.2 MASKING AND PROCESSING FLOW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
7.3 INTERRUPTS AND LOW POWER MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
7.4 CONCURRENT & NESTED MANAGEMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
7.5 INTERRUPT REGISTER DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
7.6 EXTERNAL INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
8 POWER SAVING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
8.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
8.2 SLOW MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
8.3 WAIT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
8.4 HALT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
8.5 ACTIVE-HALT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
8.6 AUTO WAKE UP FROM HALT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
9 I/O PORTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
9.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
9.2 FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
9.3 I/O PORT IMPLEMENTATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
9.4 LOW POWER MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
262
9.5 INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
9.6 I/O PORT IMPLEMENTATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
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2
Table of Contents
10 ON-CHIP PERIPHERALS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
10.1 WINDOW WATCHDOG (WWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
10.2 MAIN CLOCK CONTROLLER WITH REAL TIME CLOCK MCC/RTC . . . . . . . . . . . . . . . 61
10.3 PWM AUTO-RELOAD TIMER (ART) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
10.4 16-BIT TIMER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
10.5 8-BIT TIMER (TIM8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
10.6 SERIAL PERIPHERAL INTERFACE (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
10.7 LINSCI SERIAL COMMUNICATION INTERFACE (LIN MASTER/SLAVE) . . . . . . . . . . . 124
10.8 LINSCI SERIAL COMMUNICATION INTERFACE (LIN MASTER ONLY) . . . . . . . . . . . . 155
10.9 BECAN CONTROLLER (BECAN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
10.1010-BIT A/D CONVERTER (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211
11 INSTRUCTION SET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
11.1 CPU ADDRESSING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
11.2 INSTRUCTION GROUPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218
12 ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221
12.1 PARAMETER CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221
12.2 ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222
12.3 OPERATING CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223
12.4 SUPPLY CURRENT CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225
12.5 CLOCK AND TIMING CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229
12.6 AUTO WAKEUP FROM HALT OSCILLATOR (AWU) . . . . . . . . . . . . . . . . . . . . . . . . . . . 232
12.7 MEMORY CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233
12.8 EMC CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234
12.9 I/O PORT PIN CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236
12.10CONTROL PIN CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241
12.11TIMER PERIPHERAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243
12.12COMMUNICATION INTERFACE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . 244
12.1310-BIT ADC CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246
13 PACKAGE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250
13.1 PACKAGE MECHANICAL DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250
13.2 THERMAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252
13.3 SOLDERING AND GLUEABILITY INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253
14 DEVICE CONFIGURATION AND ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . 254
14.1 FLASH OPTION BYTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254
14.2 DEVICE ORDERING INFORMATION AND TRANSFER OF CUSTOMER CODE . . . . . 256
14.3 DEVELOPMENT TOOLS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258
15 IMPORTANT NOTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259
15.1 CLEARING ACTIVE INTERRUPTS OUTSIDE INTERRUPT ROUTINE . . . . . . . . . . . . . 259
15.2 CAN FIFO CORRUPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259
15.3 FLASH/FASTROM DEVICES ONLY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259
15.4 ROM DEVICES ONLY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260
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Table of Contents
16 REVISION HISTORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261
262
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ST72561
1 INTRODUCTION
The ST72561/ST72563 devices are members of
the ST7 microcontroller family designed for midrange applications with CAN (Controller Area Network) and LIN (Local Interconnect Network) interface.
All devices are based on a common industrystandard 8-bit core, featuring an enhanced instruction set and are available with FLASH or ROM program memory.
The enhanced instruction set and addressing
modes of the ST7 offer both power and flexibility to
software developers, enabling the design of highly
efficient and compact application code. In addition
to standard 8-bit data management, all ST7 microcontrollers feature true bit manipulation, 8x8 unsigned multiplication and indirect addressing
modes.
Figure 1. Device Block Diagram
option
OSC1
OSC2
PWM
ART
PLL x 2
OSC
/2
8-bit
TIMER
16-Bit
TIMER
VDD
VSS
TLI1
CONTROL
8-BIT CORE
ALU
PORT B
PORT C
ADDRESS AND DATA BUS
RESET
PORT A
POWER
SUPPLY
PORT D
PORT E
PORT F
PROGRAM
MEMORY
(16 - 60 K Bytes)
PA7:0
(8 bits)1
PB7:0
(8 bits)1
PC7:0
(8 bits)1
PD7:0
(8 bits)1
PE7:0
(8 bits)1
PF7:0
(8 bits)1
SPI
LINSCI2
(LIN master)
RAM
(512 - 2048 Bytes)
LINSCI1
(LIN master/slave)
CAN
(2.0B ACTIVE)
MCC
(Clock Control)
WINDOW
WATCHDOG
1
On some devices only, see Device Summary on page 1
5/262
3
ST72561
2 PIN DESCRIPTION
PF7
PF6
PD7 / AIN11
PD6 / AIN10
RESET
PD5 / LINSCI2_TDO
VDD_0
VDDA
VSS_0
VSSA
PD4 / LINSCI2_RDI
PD3 (HS)/ LINSCI2_SCK
PF5
TLI
PF4
PF3 / AIN9
Figure 2. TQFP 64-Pin Package Pinout
OSC1
OSC2
ARTIC1 / PA0
PWM0 / PA1
PWM1 / (HS) PA2
PWM2 / PA3
PWM3 / PA4
VSS_3
VDD_3
ARTCLK / (HS)PA5
ARTIC2 / (HS) PA6
T8_OCMP2 / PA7
T8_ICAP2 / PB0
T8_OCMP1 / PB1
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
48
ei3
ei3
ei3 47
46
45
44
ei0
43
ei3 42
41
40
39
ei0
38
37
36
35
ei1
34
ei1
ei2
ei1
33
18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
AIN12 / PE0
AIN13 / PE1
ICCCLK / AIN0 / PB4
AIN14 / PE2
AIN15 / PE3
ICCDATA / AIN1 / PB5
(*)T16_OCMP1 / AIN2 / PB6
VSS_2
VDD_2
(*)T16_OCMP2 / AIN3 / PB7
(*)T16_ICAP1 / AIN4 / PC0
(*)T16_ICAP2 / (HS) PC1
T16_EXTCLK / (HS) PC2
PE4
NC
ICCSEL/VPP
T8_ICAP1 / PB2
MCO / PB3
64
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
PD2 / LINSCI1_TDO
PD1 / LINSCI1_RDI
PF2 / AIN8
PF1 / AIN7
PF0
PE7
PD0 / SPI_SS / AIN6
VDD_1
VSS_1
PC7 / SPI_SCK
PC6 / SPI_MOSI
PC5 / SPI_MISO
PE6 / AIN5
PE5
PC4 / CAN_TX
PC3 / CAN_RX
(HS) 20mA high sink capability
eix
associated external interrupt vector
(*) : by option bit:
T16_ICAP1 can be moved to PD4
T16_ICAP2 can be moved to PD1
T16_OCMP1 can be moved to PD3
T16_OCMP2 can be moved to PD5
6/262
ST72561
PIN DESCRIPTION (Cont’d)
PD7 / AIN11
PD6 / AIN10
RESET
PD5 / LINSCI2_TDO 1
VDD_0
VDDA
VSS_0
VSSA
PD4 / LINSCI2_RDI
PD3 (HS) / LINSCI2_SCK
PF5
Figure 3. TQFP 44-Pin Package Pinout
44 43 42 41 40 39 38 37 36 35 34
1
33
ei3
ei3
2
32
ei3
3
31
4
30
5
ei3 29
ei0
6
28
7
27
8
26
9
25
10 ei1
24
ei2
ei1
11
23
12 13 14 15 16 17 18 19 20 21 22
ICCCLK / AIN0 / PB4
ICCDATA / AIN1 / PB5
(*)T16_OCMP1 / AIN2 / PB6
VSS_2
VDD_2
(*)T16_OCMP2 / AIN3 / PB7
(*)T16_ICAP1 / AIN4 / PC0
(*)T16_ICAP2 / (HS) PC1
T16_EXTCLK / (HS) PC2
PE4
ICCSEL/VPP
OSC1
OSC2
PWM0 / PA1
PWM1 / (HS) PA2
PWM2 / PA3
PWM3 / PA4
ARTCLK / (HS)PA5
ARTIC2 / (HS) PA6
T8_OCMP1 / PB1
T8_ICAP1 / PB2
MCO / PB3
PD2 / LINSCI1_TDO
PD1 / LINSCI1_RDI
PF2 / AIN8
PF1 / AIN7
PD0 / SPI_SS / AIN6
PC7 / SPI_SCK
PC6 / SPI_MOSI
PC5 / SPI_MISO
PE6 / AIN5
PC4 / CAN_TX
PC3 / CAN_RX
(HS) 20mA high sink capability
eix
associated external interrupt vector
(*) : by option bit:
T16_ICAP1 can be moved to PD4
T16_ICAP2 can be moved to PD1
T16_OCMP1 can be moved to PD3
T16_OCMP2 can be moved to PD5
7/262
ST72561
PIN DESCRIPTION (Cont’d)
RESET
PD5 / LINSCI2_TDO
VDD_0
VDDA
VSS_0
VSSA
PD4 / LINSCI2_RDI
PD3 (HS) / LINSCI2_SCK1
Figure 4. TQFP 32-Pin Package Pinout
1
2
3
4
5
6
7
8
32 31 30 29 28 27 26 25
24
ei3
23
ei3
22
21
ei0
20
19
18
ei1
ei2
ei1
17
9 10 11 12 13 14 15 16
ICCCLK / AIN0 / PB4
ICCDATA / AIN1 / PB5
T16_OCMP1 / AIN2 / PB6
T16_OCMP2 / AIN3 / PB7
T16_ICAP1 / AIN4 / PC0
T16_ICAP2 / (HS) PC1
T16_EXTCLK / (HS) PC2
ICCSEL/VPP
OSC1
OSC2
PWM0 / PA1
PWM1 / (HS) PA2
ARTCLK / (HS) PA5
T8_OCMP1 / PB1
T8_ICAP1 / PB2
MCO / PB3
PD2 / LINSCI1_TDO
PD1 / LINSCI1_RDI
PD0 / SPI_SS / AIN6
PC7 / SPI_SCK
PC6 / SPI_MOSI
PC5 / SPI_MISO
PC4 / CAN_TX
PC3 / CAN_RX
(HS) 20mA high sink capability
eix
associated external interrupt vector
(*) : by option bit:
T16_ICAP1 can be moved to PD4
T16_ICAP2 can be moved to PD1
T16_OCMP1 can be moved to PD3
T16_OCMP2 can be moved to PD5
For external pin connection guidelines, refer to See “ELECTRICAL CHARACTERISTICS” on page 221.
8/262
ST72561
PIN DESCRIPTION (Cont’d)
For external pin connection guidelines, refer to See “ELECTRICAL CHARACTERISTICS” on page 221.
Legend / Abbreviations for Table 1:
Type:
I = input, O = output, S = supply
In/Output level: CT= CMOS 0.3VDD/0.7VDD with Schmitt trigger
TT= TTL 0.8V / 2V with Schmitt trigger
Output level:
HS = 20mA high sink (on N-buffer only)
Port and control configuration:
– Input:
float = floating, wpu = weak pull-up, int = interrupt 1), ana = analog, RB = robust
– Output:
OD = open drain, PP = push-pull
Refer to “I/O PORTS” on page 47 for more details on the software configuration of the I/O ports.
The RESET configuration of each pin is shown in bold which is valid as long as the device is in reset state.
Table 1. Device Pin Description
2
OSC23)
I/O
Alternate function
PP
2
Main
function
Output
(after
reset)
OD
2
ana
I
int
OSC13)
Input
wpu
TQFP32
1
Port
float
TQFP44
1
Output
TQFP64
1
Pin Name
Input
Level
Type
Pin n°
External clock input or Resonator oscillator inverter input
Resonator oscillator inverter output
3
-
-
PA0 / ARTIC1
I/O CT
X
4
3
3
PA1 / PWM0
X
5
4
4
PA2 (HS) / PWM1
I/O CT
I/O CT
6
5
-
PA3 / PWM2
7
6
-
PA4 / PWM3
8
-
-
VSS_3
S
Digital Ground Voltage
9
-
-
VDD_3
S
Digital Main Supply Voltage
10
7
5
PA5 (HS) / ARTCLK
I/O CT
HS
X
11
8
-
PA6 (HS) / ARTIC2
I/O CT
I/O CT
HS
X
12
-
-
PA7 / T8_OCMP2
13
-
-
PB0 /T8_ICAP2
14
9
6
PB1 /T8_OCMP1
15 10
7
PB2 / T8_ICAP1
HS
I/O CT
I/O CT
X
ei0
ei0
ei0
X
X
ei0
ei0
ei0
ei0
X
I/O CT
I/O CT
X
X
ei0
ei1
X
ei1
X
X
Port A0
ART Input Capture 1
X
X
Port A1
ART PWM Output 0
X
X
Port A2
ART PWM Output 1
X
X
Port A3
ART PWM Output 2
X
X
Port A4
ART PWM Output 3
X
X
Port A5
ART External Clock
X
X
Port A6
ART Input Capture 2
X
X
Port A7
TIM8 Output Compare 2
X
X
Port B0
TIM8 Input Capture 2
X
X
Port B1
TIM8 Output Compare 1
X
X
Port B2
TIM8 Input Capture 1
16 11
8
PB3 / MCO
I/O CT
I/O CT
X
X
Port B3
Main clock out (fOSC2)
17
-
-
PE0 / AIN12
I/O TT
X
X
RB X
X
Port E0
ADC Analog Input 12
18
-
-
PE1 / AIN13
I/O TT
X
X
RB X
X
Port E1
ADC Analog Input 13
19 12
9
PB4 / AIN0 / ICCCLK
I/O CT
X
RB X
X
Port B4
ICC Clock
input
20
-
-
PE2 / AIN14
I/O TT
X
X
RB X
X
Port E2
ADC Analog Input 14
21
-
-
PE3 / AIN15
I/O TT
X
X
RB X
X
Port E3
ADC Analog Input 15
22 13 10 PB5 / AIN1 / ICCDATA I/O CT
X
ei1 RB X
X
Port B5
ICC Data in- ADC Analog
put
Input 1
ei1
X
ei1
ei1
ADC Analog
Input 0
9/262
ST72561
Port
PP
Main
function
Output
(after
reset)
OD
X
ana
X
int
wpu
Input
float
Output
Input
Pin Name
Type
Level
TQFP32
TQFP44
TQFP64
Pin n°
RB X
X
Alternate function
TIM16 OutADC Analog
put Compare
Input 2
1
23 14 11
PB6 / AIN2 /
T16_OCMP1
24 15
-
VSS_2
S
Digital Ground Voltage
25 16
-
VDD_2
S
Digital Main Supply Voltage
I/O CT
Port B6
26 17 12
PB7 /AIN3 /
T16_OCMP2
I/O CT
X
X
RB X
X
Port B7
TIM16 OutADC Analog
put Compare
Input 3
2
27 18 13
PC0 / AIN4 /
T16_ICAP1
I/O CT
X
X
RB X
X
Port C0
TIM16 Input
Capture 1
X
X
Port C1
TIM16 Input Capture 2
X
X
Port C2
TIM16 External Clock input
X
X
Port E4
28 19 14 PC1 (HS) / T16_ICAP2 I/O CT
HS
X
PC2 (HS) /
29 20 15
T16_EXTCLK
I/O CT
HS
X
30 21
-
PE4
I/O TT
31
-
NC
-
32 22 16 VPP
33 23 17 PC3 / CANRX
X
ei2
ei2
X
ADC Analog
Input 4
Not Connected
Flash programming voltage.Must be
tied low in user mode
I
I/O CT
I/O CT
X
I/O TT
I/O TT
X
X
X
X
X
X
Port E6
ADC Analog Input 5
X
X
X
X
Port C5
SPI Master In/Slave Out
38 27 20 PC6 / MOSI
I/O CT
I/O CT
X
X
X
X
Port C6
SPI Master Out/Slave In
39 28 21 PC7 /SCK
I/O CT
X
X
X
X
Port C7
SPI Serial Clock
34 24 18 PC4 / CANTX
35
-
36 25
-
PE5
-
PE6 / AIN5
37 26 19 PC5 /MISO
X
X
X
X
X
X
Port C3
CAN Receive Data Input
X2)
Port C4
CAN Transmit Data Output
X
Port E5
40
-
-
VSS_1
S
Digital Ground Voltage
41
-
-
VDD_1
S
Digital Main Supply Voltage
42 29 22 PD0 / SS/ AIN6
I/O CT
X
43
-
-
PE7
X
X
44
-
I/O TT
I/O TT
X
X
I/O TT
I/O TT
X
X
X
X
47 32 23 PD1 / SCI1_RDI
I/O CT
X
48 33 24 PD2 / SCI1_TDO
I/O CT
X
X
-
PF0
45 30
-
PF1 / AIN7
46 31
-
PF2 / AIN8
ei3
X
X
X
ei3
X
X
Port D0
X
X
Port E7
X
X
Port F0
X
X
Port F1
X
Port F2
ADC Analog Input 8
X
Port D1
LINSCI1 Receive Data input
X
X
Port D2
X
X
Port F3
X
X
Port F4
-
-
PF3 / AIN9
I/O TT
X
X
-
-
PF4
X
X
51
-
-
TLI
I/O TT
I CT
-
PF5
I/O TT
X
X
X
X
Port F5
X
X
X
X
Port D3
X
X
Port D4
52 34
53 35 25 PD3 (HS) / SCI2_SCK
I/O CT
54 36 26 PD4 / SCI2_RDI
I/O C T
10/262
HS
X
X
ei3
ADC Analog Input 7
X
50
X
ADC Analog
Input 6
X
49
X
SPI Slave
Select
LINSCI1 Transmit Data out-
put
ADC Analog Input 9
Top level interrupt input pin
LINSCI2 Serial Clock Out-
put
LINSCI2 Receive Data input
ST72561
Alternate function
PP
ana
int
wpu
Input
Main
function
Output
(after
reset)
OD
Port
float
Output
Input
Pin Name
Type
Level
TQFP32
TQFP44
TQFP64
Pin n°
55 37 27 VSSA
S
56 38 28 VSS_0
S
Digital Ground Voltage
57 39 29 VDDA
I
Analog Reference Voltage for ADC
58 40 30 VDD_0
S
Digital Main Supply Voltage
59 41 31 PD5 / SCI2_TDO
I/O CT
60 42 32 RESET
I/O CT
I/O CT
61 43
-
PD6 / AIN10
62 44
-
PD7 / AIN11
63
-
-
64
-
-
Analog Ground Voltage
X
X
X
X
Port D5
LINSCI2 Transmit Data out-
put
Top priority non maskable interrupt.
X
X
PF6
I/O CT
I/O TT
X
PF7
I/O TT
X
ei3
X
X
X
Port D6
ADC Analog Input 10
ei3 X
X
X
Port D7
ADC Analog Input 11
X
X
X
Port F6
X
X
X
Port F7
Notes:
1. In the interrupt input column, “eiX” defines the associated external interrupt vector. If the weak pull-up
column (wpu) is merged with the interrupt column (int), then the I/O configuration is pull-up interrupt input,
else the configuration is floating interrupt input.
2. Input mode can be used for general purpose I/O, output mode only for CANTX.
3. OSC1 and OSC2 pins connect a crystal/ceramic resonator, or an external source to the on-chip oscillator; see Section 1 and Section 12.5 "CLOCK AND TIMING CHARACTERISTICS" for more details.
4. On the chip, each I/O port has 8 pads. Pads that are not bonded to external pins are in input pull-up configuration after reset. The configuration of these pads must be kept at reset state to avoid added current
consumption.
11/262
ST72561
3 REGISTER & MEMORY MAP
As shown in Figure 5, the MCU is capable of addressing 64K bytes of memories and I/O registers.
The available memory locations consist of 128
bytes of register locations, up to 2 Kbytes of RAM
and up to 60 Kbytes of user program memory.
The RAM space includes up to 256 bytes for the
stack from 0100h to 01FFh.The highest address
bytes contain the user reset and interrupt vectors.
IMPORTANT: Memory locations marked as “Reserved” must never be accessed. Accessing a reseved area can have unpredictable effects on the
device.
Figure 5. Memory Map
0000h
007Fh
0080h
0080h
HW Registers
(see Table 2)
Short Addressing
RAM (zero page)
00FFh
0100h
RAM
(2048/1024/
512 Bytes)
256 Bytes Stack
087Fh
0880h
Reserved
027Fh
Program Memory
(60K, 32K,16K)
FFFFh
60 KBytes
16-bit Addressing
RAM
0FFFh
1000h
FFDFh
FFE0h
1000h
01FFh
0200h
8000h
32 KBytes
or 047Fh
C000h
or 087Fh
16 KBytes
Interrupt & Reset Vectors
(see Table 8)
FFDFh
Table 2. Hardware Register Map
Register
Label
Block
0000h
0001h
0002h
Port A
PADR
PADDR
PAOR
Port A Data Register
Port A Data Direction Register
Port A Option Register
00h1)
00h
00h
R/W 2)
R/W 2)
R/W 2)
0003h
0004h
0005h
Port B
PBDR
PBDDR
PBOR
Port B Data Register
Port B Data Direction Register
Port B Option Register
00h1)
00h
00h
R/W 2)
R/W 2)
R/W 2)
0006h
0007h
0008h
Port C
PCDR
PCDDR
PCOR
Port C Data Register
Port C Data Direction Register
Port C Option Register
00h1)
00h
00h
R/W 2)
R/W 2)
R/W 2)
0009h
000Ah
000Bh
Port D
PDDR
PDDDR
PDOR
Port D Data Register
Port D Data Direction Register
Port D Option Register
00h1)
00h
00h
R/W 2)
R/W 2)
R/W 2)
000Ch
000Dh
000Eh
Port E
PEDR
PEDDR
PEOR
Port E Data Register
Port E Data Direction Register
Port E Option Register
00h1)
00h
00h
R/W 2)
R/W 2)
R/W 2)
12/262
Register Name
Reset
Status
Address
Remarks
ST72561
Address
Block
000Fh
0010h
0011h
Port F
Register
Label
PFDR
PFDDR
PFOR
Register Name
Port F Data Register
Port F Data Direction Register
Port F Option Register
0012h
to
0020h
Reset
Status
00h1)
00h
00h
Remarks
R/W 2)
R/W 2)
R/W 2)
Reserved Area (15 Bytes)
0021h
0022h
0023h
SPI
SPIDR
SPICR
SPICSR
SPI Data I/O Register
SPI Control Register
SPI Control/Status Register
xxh
0xh
00h
0024h
FLASH
FCSR
Flash Control/Status Register
00h
0025h
0026h
0027h
0028h
0029h
002Ah
ITC
ISPR0
ISPR1
ISPR2
ISPR3
EICR0
EICR1
Interrupt Software Priority Register 0
Interrupt Software Priority Register 1
Interrupt Software Priority Register 2
Interrupt Software Priority Register 3
External Interrupt Control Register 0
External Interrupt Control Register 1
FFh
FFh
FFh
FFh
00h
00h
R/W
R/W
R/W
R/W
R/W
R/W
002Bh
002Ch
AWU
AWUCSR
AWUPR
Auto Wake up f. Halt Control/Status Register
Auto Wake Up From Halt Prescaler
00h
FFh
R/W
R/W
002Dh
002Eh
CKCTRL
SICSR
MCCSR
System Integrity Control / Status Register
Main Clock Control / Status Register
0xh
00h
R/W
R/W
002Fh
0030h
WWDG
WDGCR
WWDGR
Watchdog Control Register
Window Watchdog Register
7Fh
7Fh
R/W
R/W
PWMDCR3
PWMDCR2
PWMDCR1
PWMDCR0
PWMCR
ARTCSR
ARTCAR
ARTARR
ARTICCSR
ARTICR1
ARTICR2
Pulse Width Modulator Duty Cycle Register 3
PWM Duty Cycle Register 2
PWM Duty Cycle Register 1
PWM Duty Cycle Register 0
PWM Control register
Auto-Reload Timer Control/Status Register
Auto-Reload Timer Counter Access Register
Auto-Reload Timer Auto-Reload Register
ART Input Capture Control/Status Register
ART Input Capture Register 1
ART Input Capture register 2
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Read Only
Read Only
T8CR2
T8CR1
T8CSR
T8IC1R
T8OC1R
T8CTR
T8ACTR
T8IC2R
T8OC2R
Timer
Timer
Timer
Timer
Timer
Timer
Timer
Timer
Timer
00h
00h
00h
xxh
00h
FCh
FCh
xxh
00h
R/W
R/W
Read
Read
R/W
Read
Read
Read
R/W
ADCCSR
ADCDRH
ADCDRL
Control/Status Register
Data High Register
Data Low Register
00h
00h
00h
R/W
Read Only
Read Only
0031h
0032h
0033h
0034h
0035h
0036h
0037h
0038h
0039h
003Ah
003Bh
003Ch
003Dh
003Eh
003Fh
0040h
0041h
0042h
0043h
0044h
0045h
0046h
0047h
PWM
ART
8-BIT
TIMER
ADC
Control Register 2
Control Register 1
Control/Status Register
Input Capture 1 Register
Output Compare 1 Register
Counter Register
Alternate Counter Register
Input Capture 2 Register
Output Compare 2 Register
R/W
R/W
R/W
R/W
Only
Only
Only
Only
Only
13/262
ST72561
Address
0048h
0049h
004Ah
004Bh
004Ch
004Dh
004Eh
004Fh
Block
LINSCI1
(LIN Master/
Slave)
Register
Label
Register Name
Reset
Status
SCI1ISR
SCI1DR
SCI1BRR
SCI1CR1
SCI1CR2
SCI1CR3
SCI1ERPR
SCI1ETPR
SCI1 Status Register
SCI1 Data Register
SCI1 Baud Rate Register
SCI1 Control Register 1
SCI1 Control Register 2
SCI1Control Register 3
SCI1 Extended Receive Prescaler Register
SCI1 Extended Transmit Prescaler Register
C0h
xxh
00h
xxh
00h
00h
00h
00h
Read Only
R/W
R/W
R/W
R/W
R/W
R/W
R/W
00h
00h
00h
xxh
xxh
80h
00h
FFh
FCh
FFh
FCh
xxh
xxh
80h
00h
R/W
R/W
R/W
Read
Read
R/W
R/W
Read
Read
Read
Read
Read
Read
R/W
R/W
C0h
xxh
00h
xxh
00h
00h
00h
00h
Read Only
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0050h
0051h
0052h
0053h
0054h
0055h
0056h
0057h
0058h
0059h
005Ah
005Bh
005Ch
005Dh
005Eh
005Fh
0060h
0061h
0062h
0063h
0064h
0065h
0066h
0067h
14/262
Remarks
Reserved Area (1 Byte)
16-BIT
TIMER
LINSCI2
(LIN Master)
T16CR2
T16CR1
T16CSR
T16IC1HR
T16IC1LR
T16OC1HR
T16OC1LR
T16CHR
T16CLR
T16ACHR
T16ACLR
T16IC2HR
T16IC2LR
T16OC2HR
T16OC2LR
Timer
Timer
Timer
Timer
Timer
Timer
Timer
Timer
Timer
Timer
Timer
Timer
Timer
Timer
Timer
Control Register 2
Control Register 1
Control/Status Register
Input Capture 1 High Register
Input Capture 1 Low Register
Output Compare 1 High Register
Output Compare 1 Low Register
Counter High Register
Counter Low Register
Alternate Counter High Register
Alternate Counter Low Register
Input Capture 2 High Register
Input Capture 2 Low Register
Output Compare 2 High Register
Output Compare 2 Low Register
SCI2SR
SCI2DR
SCI2BRR
SCI2CR1
SCI2CR2
SCI2CR3
SCI2ERPR
SCI2ETPR
SCI2 Status Register
SCI2 Data Register
SCI2 Baud Rate Register
SCI2 Control Register 1
SCI2 Control Register 2
SCI2 Control Register 3
SCI2 Extended Receive Prescaler Register
SCI2 Extended Transmit Prescaler Register
Only
Only
Only
Only
Only
Only
Only
Only
ST72561
Address
Block
0068h
0069h
006Ah
006Bh
006Ch
006Dh
006Eh
006Fh
0070h
0071h
0072h
0073h
0074h
0075h
0076h
0077h
0078h
0079h
007Ah
007Bh
007Ch
007Dh
007Eh
007Fh
Register
Label
Register Name
Reset
Status
Remarks
CMCR
CMSR
CTSR
CTPR
CRFR
CIER
CDGR
CPSR
CAN Master Control Register
CAN Master Status Register
CAN Transmit Status Register
CAN Transmit Priority Register
CAN Receive FIFO Register
CAN Interrupt Enable Register
CAN Diagnosis Register
CAN Page Selection Register
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
PAGES
PAGE
PAGE
PAGE
PAGE
PAGE
PAGE
PAGE
PAGE
PAGE
PAGE
PAGE
PAGE
PAGE
PAGE
PAGE
PAGE
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Active CAN
REGISTER
REGISTER
REGISTER
REGISTER
REGISTER
REGISTER
REGISTER
REGISTER
REGISTER
REGISTER
REGISTER
REGISTER
REGISTER
REGISTER
REGISTER
REGISTER
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Legend: x=undefined, R/W=read/write
Notes:
1. The contents of the I/O port DR registers are readable only in output configuration. In input configuration, the values of the I/O pins are returned instead of the DR register contents.
2. The bits associated with unavailable pins must always keep their reset value.
15/262
ST72561
4 FLASH PROGRAM MEMORY
4.1 Introduction
The ST7 dual voltage High Density Flash
(HDFlash) is a non-volatile memory that can be
electrically erased as a single block or by individual sectors and programmed on a Byte-by-Byte basis using an external VPP supply.
The HDFlash devices can be programmed and
erased off-board (plugged in a programming tool)
or on-board using ICP (In-Circuit Programming) or
IAP (In-Application Programming).
The array matrix organisation allows each sector
to be erased and reprogrammed without affecting
other sectors.
Depending on the overall Flash memory size in the
microcontroller device, there are up to three user
sectors (see Table 3). Each of these sectors can
be erased independently to avoid unnecessary
erasing of the whole Flash memory when only a
partial erasing is required.
The first two sectors have a fixed size of 4 Kbytes
(see Figure 6). They are mapped in the upper part
of the ST7 addressing space so the reset and interrupt vectors are located in Sector 0 (F000hFFFFh).
Table 3. Sectors available in Flash devices
Flash Size (bytes)
Available Sectors
4K
Sector 0
4.2 Main Features
■
■
■
■
Three Flash programming modes:
– Insertion in a programming tool. In this mode,
all sectors including option bytes can be programmed or erased.
– ICP (In-Circuit Programming). In this mode, all
sectors including option bytes can be programmed or erased without removing the device from the application board.
– IAP (In-Application Programming) In this
mode, all sectors except Sector 0, can be programmed or erased without removing the device from the application board and while the
application is running.
ICT (In-Circuit Testing) for downloading and
executing user application test patterns in RAM
Read-out protection against piracy
Register Access Security System (RASS) to
prevent accidental programming or erasing
4.3 Structure
8K
Sectors 0,1
> 8K
Sectors 0,1, 2
4.3.1 Read-out Protection
Read-out protection, when selected, provides a
protection against Program Memory content extraction and against write access to Flash memory.
In Flash devices, this protection is removed by reprogramming the option. In this case, the entire
program memory is first automatically erased and
the device can be reprogrammed.
Read-out protection selection depends on the device type:
– In Flash devices it is enabled and removed
through the FMP_R bit in the option byte.
– In ROM devices it is enabled by mask option
specified in the Option List.
The Flash memory is organised in sectors and can
be used for both code and data storage.
Figure 6. Memory Map and Sector Address
4K
8K
10K
16K
24K
32K
48K
60K
1000h
FLASH
MEMORY SIZE
3FFFh
7FFFh
9FFFh
SECTOR 2
BFFFh
D7FFh
DFFFh
EFFFh
FFFFh
16/262
2 Kbytes
8 Kbytes
16 Kbytes 24 Kbytes 40 Kbytes 52 Kbytes
4 Kbytes
4 Kbytes
SECTOR 1
SECTOR 0
ST72561
FLASH PROGRAM MEMORY (Cont’d)
4.4 ICC Interface
–
–
–
–
ICCCLK: ICC output serial clock pin
ICCDATA: ICC input/output serial data pin
ICCSEL/VPP: programming voltage
OSC1(or OSCIN): main clock input for external source (optional)
– VDD: application board power supply (optional, see Figure 7, Note 3)
ICC needs a minimum of 4 and up to 6 pins to be
connected to the programming tool (see Figure 7).
These pins are:
– RESET: device reset
– VSS: device power supply ground
Figure 7. Typical ICC Interface
PROGRAMMING TOOL
ICC CONNECTOR
ICC Cable
APPLICATION BOARD
(See Note 3)
ICC CONNECTOR
HE10 CONNECTOR TYPE
OPTIONAL
(See Note 4)
9
7
5
3
1
10
8
6
4
2
APPLICATION
RESET SOURCE
See Note 2
10kΩ
Notes:
1. If the ICCCLK or ICCDATA pins are only used
as outputs in the application, no signal isolation is
necessary. As soon as the Programming Tool is
plugged to the board, even if an ICC session is not
in progress, the ICCCLK and ICCDATA pins are
not available for the application. If they are used as
inputs by the application, isolation such as a serial
resistor has to implemented in case another device forces the signal. Refer to the Programming
Tool documentation for recommended resistor values.
2. During the ICC session, the programming tool
must control the RESET pin. This can lead to conflicts between the programming tool and the application reset circuit if it drives more than 5mA at
high level (push pull output or pull-up resistor<1K).
A schottky diode can be used to isolate the application RESET circuit in this case. When using a
classical RC network with R>1K or a reset man-
ICCDATA
ICCCLK
ST7
RESET
See Note 1
ICCSEL/VPP
OSC1
CL1
OSC2
VDD
CL2
VSS
APPLICATION
POWER SUPPLY
APPLICATION
I/O
agement IC with open drain output and pull-up resistor>1K, no additional components are needed.
In all cases the user must ensure that no external
reset is generated by the application during the
ICC session.
3. The use of Pin 7 of the ICC connector depends
on the Programming Tool architecture. This pin
must be connected when using most ST Programming Tools (it is used to monitor the application
power supply). Please refer to the Programming
Tool manual.
4. Pin 9 has to be connected to the OSC1 or OSCIN pin of the ST7 when the clock is not available
in the application or if the selected clock option is
not programmed in the option byte. ST7 devices
with multi-oscillator capability need to have OSC2
grounded in this case.
17/262
ST72561
FLASH PROGRAM MEMORY (Cont’d)
4.5 ICP (In-Circuit Programming)
4.7 Related Documentation
To perform ICP the microcontroller must be
switched to ICC (In-Circuit Communication) mode
by an external controller or programming tool.
Depending on the ICP code downloaded in RAM,
Flash memory programming can be fully customized (number of bytes to program, program locations, or selection serial communication interface
for downloading).
When using an STMicroelectronics or third-party
programming tool that supports ICP and the specific microcontroller device, the user needs only to
implement the ICP hardware interface on the application board (see Figure 7). For more details on
the pin locations, refer to the device pinout description.
For details on Flash programming and ICC protocol, refer to the ST7 Flash Programming Reference Manual and to the ST7 ICC Protocol Reference Manual.
4.6 IAP (In-Application Programming)
This register is reserved for use by Programming
Tool software. It controls the Flash programming
and erasing operations.
This mode uses a BootLoader program previously
stored in Sector 0 by the user (in ICP mode or by
plugging the device in a programming tool).
This mode is fully controlled by user software. This
allows it to be adapted to the user application, (user-defined strategy for entering programming
mode, choice of communications protocol used to
fetch the data to be stored, etc.). For example, it is
possible to download code from the SPI, SCI, USB
or CAN interface and program it in the Flash. IAP
mode can be used to program any of the Flash
sectors except Sector 0, which is write/erase protected to allow recovery in case errors occur during the programming operation.
4.8 Register Description
FLASH CONTROL/STATUS REGISTER (FCSR)
Read /Write
Reset Value: 0000 0000 (00h)
7
0
0
0
0
0
0
0
0
0
Table 4. Flash Control/Status Register Address and Reset Value
Address
(Hex.)
Register
Label
0024h
FCSR
Reset Value
18/262
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
ST72561
5 CENTRAL PROCESSING UNIT
5.1 INTRODUCTION
5.3 CPU REGISTERS
This CPU has a full 8-bit architecture and contains
six internal registers allowing efficient 8-bit data
manipulation.
The 6 CPU registers shown in Figure 8 are not
present in the memory mapping and are accessed
by specific instructions.
Accumulator (A)
The Accumulator is an 8-bit general purpose register used to hold operands and the results of the
arithmetic and logic calculations and to manipulate
data.
Index Registers (X and Y)
These 8-bit registers are used to create effective
addresses or as temporary storage areas for data
manipulation. (The Cross-Assembler generates a
precede instruction (PRE) to indicate that the following instruction refers to the Y register.)
The Y register is not affected by the interrupt automatic procedures.
Program Counter (PC)
The program counter is a 16-bit register containing
the address of the next instruction to be executed
by the CPU. It is made of two 8-bit registers PCL
(Program Counter Low which is the LSB) and PCH
(Program Counter High which is the MSB).
5.2 MAIN FEATURES
■
■
■
■
■
■
■
■
Enable executing 63 basic instructions
Fast 8-bit by 8-bit multiply
17 main addressing modes (with indirect
addressing mode)
Two 8-bit index registers
16-bit stack pointer
Low power HALT and WAIT modes
Priority maskable hardware interrupts
Non-maskable software/hardware interrupts
Figure 8. CPU Registers
7
0
ACCUMULATOR
RESET VALUE = XXh
7
0
X INDEX REGISTER
RESET VALUE = XXh
7
0
Y INDEX REGISTER
RESET VALUE = XXh
15
PCH
8 7
PCL
0
PROGRAM COUNTER
RESET VALUE = RESET VECTOR @ FFFEh-FFFFh
7
0
1 1 I1 H I0 N Z C
CONDITION CODE REGISTER
RESET VALUE = 1 1 1 X 1 X X X
15
8 7
0
STACK POINTER
RESET VALUE = STACK HIGHER ADDRESS
X = Undefined Value
19/262
ST72561
CENTRAL PROCESSING UNIT (Cont’d)
Condition Code Register (CC)
Read/Write
Reset Value: 111x1xxx
Bit 1 = Z Zero.
7
1
0
1
I1
H
I0
N
Z
C
The 8-bit Condition Code register contains the interrupt masks and four flags representative of the
result of the instruction just executed. This register
can also be handled by the PUSH and POP instructions.
These bits can be individually tested and/or controlled by specific instructions.
Arithmetic Management Bits
Bit 4 = H Half carry.
This bit is set by hardware when a carry occurs between bits 3 and 4 of the ALU during an ADD or
ADC instructions. It is reset by hardware during
the same instructions.
0: No half carry has occurred.
1: A half carry has occurred.
This bit is tested using the JRH or JRNH instruction. The H bit is useful in BCD arithmetic subroutines.
Bit 2 = N Negative.
This bit is set and cleared by hardware. It is representative of the result sign of the last arithmetic,
logical or data manipulation. It’s a copy of the result 7th bit.
0: The result of the last operation is positive or null.
1: The result of the last operation is negative
(i.e. the most significant bit is a logic 1).
This bit is accessed by the JRMI and JRPL instructions.
20/262
This bit is set and cleared by hardware. This bit indicates that the result of the last arithmetic, logical
or data manipulation is zero.
0: The result of the last operation is different from
zero.
1: The result of the last operation is zero.
This bit is accessed by the JREQ and JRNE test
instructions.
Bit 0 = C Carry/borrow.
This bit is set and cleared by hardware and software. It indicates an overflow or an underflow has
occurred during the last arithmetic operation.
0: No overflow or underflow has occurred.
1: An overflow or underflow has occurred.
This bit is driven by the SCF and RCF instructions
and tested by the JRC and JRNC instructions. It is
also affected by the “bit test and branch”, shift and
rotate instructions.
Interrupt Management Bits
Bit 5,3 = I1, I0 Interrupt
The combination of the I1 and I0 bits gives the current interrupt software priority.
Interrupt Software Priority
Level 0 (main)
Level 1
Level 2
Level 3 (= interrupt disable)
I1
1
0
0
1
I0
0
1
0
1
These two bits are set/cleared by hardware when
entering in interrupt. The loaded value is given by
the corresponding bits in the interrupt software priority registers (IxSPR). They can be also set/
cleared by software with the RIM, SIM, IRET,
HALT, WFI and PUSH/POP instructions.
See the interrupt management chapter for more
details.
ST72561
CENTRAL PROCESSING UNIT (Cont’d)
Stack Pointer (SP)
Read/Write
Reset Value: 01 FFh
15
0
8
0
0
0
0
0
0
7
SP7
1
0
SP6
SP5
SP4
SP3
SP2
SP1
SP0
The Stack Pointer is a 16-bit register which is always pointing to the next free location in the stack.
It is then decremented after data has been pushed
onto the stack and incremented before data is
popped from the stack (see Figure 9).
Since the stack is 256 bytes deep, the 8 most significant bits are forced by hardware. Following an
MCU Reset, or after a Reset Stack Pointer instruction (RSP), the Stack Pointer contains its reset value (the SP7 to SP0 bits are set) which is the stack
higher address.
The least significant byte of the Stack Pointer
(called S) can be directly accessed by a LD instruction.
Note: When the lower limit is exceeded, the Stack
Pointer wraps around to the stack upper limit, without indicating the stack overflow. The previously
stored information is then overwritten and therefore lost. The stack also wraps in case of an underflow.
The stack is used to save the return address during a subroutine call and the CPU context during
an interrupt. The user may also directly manipulate
the stack by means of the PUSH and POP instructions. In the case of an interrupt, the PCL is stored
at the first location pointed to by the SP. Then the
other registers are stored in the next locations as
shown in Figure 9.
– When an interrupt is received, the SP is decremented and the context is pushed on the stack.
– On return from interrupt, the SP is incremented
and the context is popped from the stack.
A subroutine call occupies two locations and an interrupt five locations in the stack area.
Figure 9. Stack Manipulation Example
CALL
Subroutine
PUSH Y
Interrupt
Event
POP Y
RET
or RSP
IRET
@ 0100h
SP
SP
CC
A
SP
CC
A
X
X
X
PCH
PCH
PCH
PCL
PCL
PCL
PCH
PCH
PCH
PCH
PCH
PCL
PCL
PCL
PCL
PCL
SP
@ 01FFh
Y
CC
A
SP
SP
Stack Higher Address = 01FFh
Stack Lower Address = 0100h
21/262
ST72561
6 SUPPLY, RESET AND CLOCK MANAGEMENT
The device includes a range of utility features for
securing the application in critical situations (for
example in case of a power brown-out), and reducing the number of external components. An
overview is shown in Figure 11.
For more details, refer to dedicated parametric
section.
6.1 PHASE LOCKED LOOP
If the clock frequency input to the PLL is in the
range 2 to 4 MHz, the PLL can be used to multiply
the frequency by two to obtain an fOSC2 of 4 to 8
MHz. The PLL is enabled by option byte. If the PLL
is disabled, then fOSC2 = fOSC/2.
Caution: The PLL is not recommended for applications where timing accuracy is required. See
“PLL Characteristics” on page 231.
Main features
Optional PLL for multiplying the frequency by 2
■ Reset Sequence Manager (RSM)
■ Multi-Oscillator Clock Management (MO)
– 4 Crystal/Ceramic resonator oscillators
■ System Integrity Management (SI)
– Main supply Low voltage detection (LVD)
– Auxiliary Voltage detector (AVD) with interrupt
capability for monitoring the main supply
■
Figure 10. PLL Block Diagram
PLL x 2
0
/2
1
fOSC
fOSC2
PLL OPTION BIT
Figure 11. Clock, Reset and Supply Block Diagram
/ 8000
OSC2
MULTI-
fOSC
OSCILLATOR
OSC1
(MO)
PLL
(option)
8-BIT TIMER
MAIN CLOCK
CONTROLLER
WITH REALTIME
CLOCK (MCC/RTC)
fOSC2
SYSTEM INTEGRITY MANAGEMENT
RESET SEQUENCE
RESET
MANAGER
(RSM)
WATCHDOG
AVD Interrupt Request
SICSR
AVD AVD LVD
0
F RF
IE
TIMER (WDG)
0
0
0
LOW VOLTAGE
VSS
DETECTOR
VDD
(LVD)
AUXILIARY VOLTAGE
DETECTOR
(AVD)
22/262
WDG
RF
fCPU
ST72561
6.2 MULTI-OSCILLATOR (MO)
External Clock Source
In external clock mode, a clock signal (square, sinus or triangle) with ~50% duty cycle has to drive
the OSC1 pin while the OSC2 pin is tied to ground.
Crystal/Ceramic Oscillators
This family of oscillators has the advantage of producing a very accurate rate on the main clock of
the ST7. The selection within a list of 5 oscillators
with different frequency ranges has to be done by
option byte in order to reduce consumption (refer
to Section 14.1 on page 254 for more details on
the frequency ranges). The resonator and the load
capacitors have to be placed as close as possible
to the oscillator pins in order to minimize output
distortion and start-up stabilization time. The loading capacitance values must be adjusted according to the selected oscillator.
These oscillators are not stopped during the
RESET phase to avoid losing time in the oscillator
start-up phase.
Table 5. ST7 Clock Sources
External Clock
Hardware Configuration
Crystal/Ceramic Resonators
The main clock of the ST7 can be generated by
three different source types coming from the multioscillator block:
■ an external source
■ a crystal or ceramic resonator oscillator
Each oscillator is optimized for a given frequency
range in terms of consumption and is selectable
through the option byte. The associated hardware
configuration are shown in Table 5. Refer to the
electrical characteristics section for more details.
Caution: The OSC1 and/or OSC2 pins must not
be left unconnected. For the purposes of Failure
Mode and Effect Analysis, it should be noted that if
the OSC1 and/or OSC2 pins are left unconnected,
the ST7 main oscillator may start and, in this configuration, could generate an fOSC clock frequency
in excess of the allowed maximum (>16MHz.),
putting the ST7 in an unsafe/undefined state. The
product behaviour must therefore be considered
undefined when the OSC pins are left unconnected.
ST7
OSC1
OSC2
EXTERNAL
SOURCE
ST7
OSC1
CL1
OSC2
LOAD
CAPACITORS
CL2
23/262
ST72561
6.3 RESET SEQUENCE MANAGER (RSM)
6.3.1 Introduction
The reset sequence manager includes three RESET sources as shown in Figure 13:
■ External RESET source pulse
■ Internal LVD RESET (Low Voltage Detection)
■ Internal WATCHDOG RESET
These sources act on the RESET pin and it is always kept low during the delay phase.
The RESET service routine vector is fixed at addresses FFFEh-FFFFh in the ST7 memory map.
The basic RESET sequence consists of 3 phases
as shown in Figure 12:
■ Active Phase depending on the RESET source
■ 256 or 4096 CPU clock cycle delay (selected by
option byte)
■ RESET vector fetch
The 256 or 4096 CPU clock cycle delay allows the
oscillator to stabilise and ensures that recovery
has taken place from the Reset state. The shorter
or longer clock cycle delay should be selected by
option byte to correspond to the stabilization time
of the external oscillator used in the application.
The RESET vector fetch phase duration is 2 clock
cycles.
Figure 12. RESET Sequence Phases
RESET
Active Phase
INTERNAL RESET
256 or 4096 CLOCK CYCLES
FETCH
VECTOR
6.3.2 Asynchronous External RESET pin
The RESET pin is both an input and an open-drain
output with integrated RON weak pull-up resistor.
This pull-up has no fixed value but varies in accordance with the input voltage. It can be pulled
low by external circuitry to reset the device. See
Electrical Characteristic section for more details.
A RESET signal originating from an external
source must have a duration of at least th(RSTL)in in
order to be recognized (see Figure 14). This detection is asynchronous and therefore the MCU
can enter reset state even in HALT mode.
Figure 13. Reset Block Diagram
VDD
RON
RESET
INTERNAL
RESET
Filter
PULSE
GENERATOR
24/262
WATCHDOG RESET
LVD RESET
ST72561
RESET SEQUENCE MANAGER (Cont’d)
The RESET pin is an asynchronous signal which
plays a major role in EMS performance. In a noisy
environment, it is recommended to follow the
guidelines mentioned in the electrical characteristics section.
6.3.3 External Power-On RESET
If the LVD is disabled by option byte, to start up the
microcontroller correctly, the user must ensure by
means of an external reset circuit that the reset
signal is held low until VDD is over the minimum
level specified for the selected fOSC frequency.
A proper reset signal for a slow rising VDD supply
can generally be provided by an external RC network connected to the RESET pin.
6.3.4 Internal Low Voltage Detector (LVD)
RESET
Two different RESET sequences caused by the internal LVD circuitry can be distinguished:
■ Power-On RESET
■ Voltage Drop RESET
The device RESET pin acts as an output that is
pulled low when VDD<VIT+ (rising edge) or
VDD<VIT- (falling edge) as shown in Figure 14.
The LVD filters spikes on VDD larger than tg(VDD) to
avoid parasitic resets.
6.3.5 Internal Watchdog RESET
The RESET sequence generated by a internal
Watchdog counter overflow is shown in Figure 14.
Starting from the Watchdog counter underflow, the
device RESET pin acts as an output that is pulled
low during at least tw(RSTL)out.
Figure 14. RESET Sequences
VDD
VIT+(LVD)
VIT-(LVD)
LVD
RESET
RUN
EXTERNAL
RESET
RUN
ACTIVE PHASE
ACTIVE
PHASE
WATCHDOG
RESET
RUN
ACTIVE
PHASE
RUN
tw(RSTL)out
th(RSTL)in
EXTERNAL
RESET
SOURCE
RESET PIN
WATCHDOG
RESET
WATCHDOG UNDERFLOW
INTERNAL RESET (256 or 4096 TCPU)
VECTOR FETCH
25/262
ST72561
6.4 SYSTEM INTEGRITY MANAGEMENT (SI)
The System Integrity Management block contains
the Low Voltage Detector (LVD) and Auxiliary Voltage Detector (AVD) functions. It is managed by
the SICSR register.
6.4.1 Low Voltage Detector (LVD)
The Low Voltage Detector function (LVD) generates a static reset when the VDD supply voltage is
below a VIT-(LVD) reference value. This means that
it secures the power-up as well as the power-down
keeping the ST7 in reset.
The VIT-(LVD) reference value for a voltage drop is
lower than the VIT+(LVD) reference value for poweron in order to avoid a parasitic reset when the
MCU starts running and sinks current on the supply (hysteresis).
The LVD Reset circuitry generates a reset when
VDD is below:
– VIT+(LVD) when VDD is rising
– VIT-(LVD) when VDD is falling
The LVD function is illustrated in Figure 15.
Provided the minimum VDD value (guaranteed for
the oscillator frequency) is above VIT-(LVD), the
MCU can only be in two modes:
– under full software control
– in static safe reset
In these conditions, secure operation is always ensured for the application without the need for external reset hardware.
During a Low Voltage Detector Reset, the RESET
pin is held low, thus permitting the MCU to reset
other devices.
Notes:
The LVD allows the device to be used without any
external RESET circuitry.
The LVD is an optional function which can be selected by option byte.
It is recommended to make sure that the VDD supply voltage rises monotonously when the device is
exiting from Reset, to ensure the application functions properly.
Figure 15. Low Voltage Detector vs Reset
VDD
Vhys
VIT+(LVD)
VIT-(LVD)
RESET
26/262
ST72561
SYSTEM INTEGRITY MANAGEMENT (Cont’d)
6.4.2 Auxiliary Voltage Detector (AVD)
The Voltage Detector function (AVD) is based on
an analog comparison between a VIT-(AVD) and
VIT+(AVD) reference value and the VDD main supply. The VIT-(AVD) reference value for falling voltage is lower than the VIT+(AVD) reference value for
rising voltage in order to avoid parasitic detection
(hysteresis).
The output of the AVD comparator is directly readable by the application software through a real
time status bit (AVDF) in the SICSR register. This
bit is read only.
Caution: The AVD function is active only if the
LVD is enabled through the option byte.
6.4.2.1 Monitoring the VDD Main Supply
If the AVD interrupt is enabled, an interrupt is generated when the voltage crosses the VIT+(AVD) or
VIT-(AVD) threshold (AVDF bit toggles).
In the case of a drop in voltage, the AVD interrupt
acts as an early warning, allowing software to shut
down safely before the LVD resets the microcontroller. See Figure 16.
The interrupt on the rising edge is used to inform
the application that the VDD warning state is over.
If the voltage rise time trv is less than 256 or 4096
CPU cycles (depending on the reset delay selected by option byte), no AVD interrupt will be generated when VIT+(AVD) is reached.
If trv is greater than 256 or 4096 cycles then:
– If the AVD interrupt is enabled before the
VIT+(AVD) threshold is reached, then 2 AVD interrupts will be received: the first when the AVDIE
bit is set, and the second when the threshold is
reached.
– If the AVD interrupt is enabled after the VIT+(AVD)
threshold is reached then only one AVD interrupt
will occur.
Figure 16. Using the AVD to Monitor VDD
VDD
Early Warning Interrupt
(Power has dropped, MCU not
not yet in reset)
Vhyst
VIT+(AVD)
VIT-(AVD)
VIT+(LVD)
VIT-(LVD)
AVDF bit
trv VOLTAGE RISE TIME
0
1
RESET VALUE
1
0
AVD INTERRUPT
REQUEST
IF AVDIE bit = 1
INTERRUPT PROCESS
INTERRUPT PROCESS
LVD RESET
27/262
ST72561
SYSTEM INTEGRITY MANAGEMENT (Cont’d)
6.4.3 Low Power Modes
Mode
WAIT
HALT
Description
No effect on SI. AVD interrupts cause the
device to exit from Wait mode.
The SICSR register is frozen.
6.4.3.1 Interrupts
The AVD interrupt event generates an interrupt if
the AVDIE bit is set and the interrupt mask in the
CC register is reset (RIM instruction).
Interrupt Event
AVD event
28/262
Enable
Event
Control
Flag
Bit
Exit
from
Wait
Exit
from
Halt
AVDF
Yes
No
AVDIE
ST72561
SYSTEM INTEGRITY MANAGEMENT (Cont’d)
6.4.4 Register Description
SYSTEM INTEGRITY (SI) CONTROL/STATUS REGISTER (SICSR)
Read /Write
Reset Value: 000x 000x (00h)
Bits 3:1 = Reserved, must be kept cleared.
7
0
0
AVD
IE
AVD
F
LVD
RF
0
0
0
WDG
RF
Bit 7 = Reserved, must be kept cleared.
Bit 6 = AVDIE Voltage Detector interrupt enable
This bit is set and cleared by software. It enables
an interrupt to be generated when the AVDF flag
changes (toggles). The pending interrupt information is automatically cleared when software enters
the AVD interrupt routine.
0: AVD interrupt disabled
1: AVD interrupt enabled
Bit 5 = AVDF Voltage Detector flag
This read-only bit is set and cleared by hardware.
If the AVDIE bit is set, an interrupt request is generated when the AVDF bit changes value. Refer to
Figure 16 and to Section 6.4.2.1 for additional details.
0: VDD over VIT+(AVD) threshold
1: VDD under VIT-(AVD) threshold
Bit 4 = LVDRF LVD reset flag
This bit indicates that the last Reset was generated by the LVD block. It is set by hardware (LVD reset) and cleared by software (writing zero). See
WDGRF flag description for more details. When
the LVD is disabled by OPTION BYTE, the LVDRF
bit value is undefined.
Bit 0 = WDGRF Watchdog reset flag
This bit indicates that the last Reset was generated by the Watchdog peripheral. It is set by hardware (watchdog reset) and cleared by software
(writing zero) or an LVD Reset (to ensure a stable
cleared state of the WDGRF flag when CPU
starts).
Combined with the LVDRF flag information, the
flag description is given by the following table.
RESET Sources
LVDRF
WDGRF
External RESET pin
Watchdog
LVD
0
0
1
0
1
X
Application notes
The LVDRF flag is not cleared when another RESET type occurs (external or watchdog), the
LVDRF flag remains set to keep trace of the original failure.
In this case, a watchdog reset can be detected by
software while an external reset can not.
CAUTION: When the LVD is not activated with the
associated option byte, the WDGRF flag can not
be used in the application.
29/262
ST72561
7 INTERRUPTS
7.1 INTRODUCTION
The ST7 enhanced interrupt management provides the following features:
■ Hardware interrupts
■ Software interrupt (TRAP)
■ Nested or concurrent interrupt management
with flexible interrupt priority and level
management:
– Up to 4 software programmable nesting levels
– Up to 16 interrupt vectors fixed by hardware
– 2 non maskable events: RESET, TRAP
– 1 maskable Top Level Event: TLI
This interrupt management is based on:
– Bit 5 and bit 3 of the CPU CC register (I1:0),
– Interrupt software priority registers (ISPRx),
– Fixed interrupt vector addresses located at the
high addresses of the memory map (FFE0h to
FFFFh) sorted by hardware priority order.
This enhanced interrupt controller guarantees full
upward compatibility with the standard (not nested) ST7 interrupt controller.
each interrupt vector (see Table 6). The processing flow is shown in Figure 17
When an interrupt request has to be serviced:
– Normal processing is suspended at the end of
the current instruction execution.
– The PC, X, A and CC registers are saved onto
the stack.
– I1 and I0 bits of CC register are set according to
the corresponding values in the ISPRx registers
of the serviced interrupt vector.
– The PC is then loaded with the interrupt vector of
the interrupt to service and the first instruction of
the interrupt service routine is fetched (refer to
“Interrupt Mapping” table for vector addresses).
The interrupt service routine should end with the
IRET instruction which causes the contents of the
saved registers to be recovered from the stack.
Note: As a consequence of the IRET instruction,
the I1 and I0 bits will be restored from the stack
and the program in the previous level will resume.
Table 6. Interrupt Software Priority Levels
Interrupt software priority
Level 0 (main)
Level 1
Level 2
Level 3 (= interrupt disable)
7.2 MASKING AND PROCESSING FLOW
The interrupt masking is managed by the I1 and I0
bits of the CC register and the ISPRx registers
which give the interrupt software priority level of
Level
Low
I1
1
0
0
1
High
I0
0
1
0
1
Figure 17. Interrupt Processing Flowchart
N
FETCH NEXT
INSTRUCTION
Y
“IRET”
N
RESTORE PC, X, A, CC
FROM STACK
EXECUTE
INSTRUCTION
Y
TLI
Interrupt has the same or a
lower software priority
than current one
THE INTERRUPT
STAYS PENDING
N
I1:0
Interrupt has a higher
software priority
than current one
PENDING
INTERRUPT
RESET
STACK PC, X, A, CC
LOAD I1:0 FROM INTERRUPT SW REG.
LOAD PC FROM INTERRUPT VECTOR
30/262
Y
ST72561
INTERRUPTS (Cont’d)
Servicing Pending Interrupts
As several interrupts can be pending at the same
time, the interrupt to be taken into account is determined by the following two-step process:
– the highest software priority interrupt is serviced,
– if several interrupts have the same software priority then the interrupt with the highest hardware
priority is serviced first.
Figure 18 describes this decision process.
Figure 18. Priority Decision Process
PENDING
INTERRUPTS
Same
SOFTWARE
PRIORITY
Different
HIGHEST SOFTWARE
PRIORITY SERVICED
HIGHEST HARDWARE
PRIORITY SERVICED
When an interrupt request is not serviced immediately, it is latched and then processed when its
software priority combined with the hardware priority becomes the highest one.
Note 1: The hardware priority is exclusive while
the software one is not. This allows the previous
process to succeed with only one interrupt.
Note 2: RESET, TRAP and TLI can be considered
as having the highest software priority in the decision process.
Different Interrupt Vector Sources
Two interrupt source types are managed by the
ST7 interrupt controller: the non-maskable type
(RESET, TRAP) and the maskable type (external
or from internal peripherals).
Non-Maskable Sources
These sources are processed regardless of the
state of the I1 and I0 bits of the CC register (see
Figure 17). After stacking the PC, X, A and CC
registers (except for RESET), the corresponding
vector is loaded in the PC register and the I1 and
I0 bits of the CC are set to disable interrupts (level
3). These sources allow the processor to exit
HALT mode.
TRAP (Non Maskable Software Interrupt)
This software interrupt is serviced when the TRAP
instruction is executed. It will be serviced according to the flowchart in Figure 17 as a TLI.
Caution: TRAP can be interrupted by a TLI.
■ RESET
The RESET source has the highest priority in the
ST7. This means that the first current routine has
the highest software priority (level 3) and the highest hardware priority.
See the RESET chapter for more details.
■
Maskable Sources
Maskable interrupt vector sources can be serviced
if the corresponding interrupt is enabled and if its
own interrupt software priority (in ISPRx registers)
is higher than the one currently being serviced (I1
and I0 in CC register). If any of these two conditions is false, the interrupt is latched and thus remains pending.
■ TLI (Top Level Hardware Interrupt)
This hardware interrupt occurs when a specific
edge is detected on the dedicated TLI pin.
Caution: A TRAP instruction must not be used in a
TLI service routine.
■ External Interrupts
External interrupts allow the processor to exit from
HALT low power mode.
External interrupt sensitivity is software selectable
through the External Interrupt Control register
(EICR).
External interrupt triggered on edge will be latched
and the interrupt request automatically cleared
upon entering the interrupt service routine.
If several input pins of a group connected to the
same interrupt line are selected simultaneously,
these will be logically ORed.
■ Peripheral Interrupts
Usually the peripheral interrupts cause the MCU to
exit from HALT mode except those mentioned in
the “Interrupt Mapping” table.
A peripheral interrupt occurs when a specific flag
is set in the peripheral status registers and if the
corresponding enable bit is set in the peripheral
control register.
The general sequence for clearing an interrupt is
based on an access to the status register followed
by a read or write to an associated register.
Note: The clearing sequence resets the internal
latch. A pending interrupt (i.e. waiting for being
serviced) will therefore be lost if the clear sequence is executed.
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INTERRUPTS (Cont’d)
7.3 INTERRUPTS AND LOW POWER MODES
7.4 CONCURRENT & NESTED MANAGEMENT
All interrupts allow the processor to exit the WAIT
low power mode. On the contrary, only external
and other specified interrupts allow the processor
to exit from the HALT modes (see column “Exit
from HALT” in “Interrupt Mapping” table). When
several pending interrupts are present while exiting HALT mode, the first one serviced can only be
an interrupt with exit from HALT mode capability
and it is selected through the same decision process shown in Figure 18.
Note: If an interrupt, that is not able to Exit from
HALT mode, is pending with the highest priority
when exiting HALT mode, this interrupt is serviced
after the first one serviced.
The following Figure 19 and Figure 20 show two
different interrupt management modes. The first is
called concurrent mode and does not allow an interrupt to be interrupted, unlike the nested mode in
Figure 20. The interrupt hardware priority is given
in this order from the lowest to the highest: MAIN,
IT4, IT3, IT2, IT1, IT0, TLI. The software priority is
given for each interrupt.
Warning: A stack overflow may occur without notifying the software of the failure.
IT0
TLI
IT3
IT4
IT1
SOFTWARE
PRIORITY
LEVEL
TLI
IT0
IT1
IT1
IT2
IT3
I1
I0
3
1 1
3
1 1
3
1 1
3
1 1
3
1 1
3
1 1
USED STACK = 10 BYTES
HARDWARE PRIORITY
IT2
Figure 19. Concurrent Interrupt Management
RIM
IT4
MAIN
MAIN
11 / 10
3/0
10
IT0
TLI
IT3
IT4
IT1
TLI
IT0
IT1
IT1
IT2
IT2
IT3
I1
I0
3
1 1
3
1 1
2
0 0
1
0 1
3
1 1
3
1 1
RIM
IT4
MAIN
11 / 10
32/262
SOFTWARE
PRIORITY
LEVEL
IT4
MAIN
10
3/0
USED STACK = 20 BYTES
HARDWARE PRIORITY
IT2
Figure 20. Nested Interrupt Management
ST72561
INTERRUPTS (Cont’d)
7.5 INTERRUPT REGISTER DESCRIPTION
INTERRUPT SOFTWARE PRIORITY REGISTERS (ISPRX)
Read/Write (bit 7:4 of ISPR3 are read only)
Reset Value: 1111 1111 (FFh)
CPU CC REGISTER INTERRUPT BITS
Read /Write
Reset Value: 111x 1010 (xAh)
7
1
7
0
1
I1
H
I0
N
Z
Level
Low
High
I1
1
0
0
1
ISPR0
I1_3
I0_3
I1_2
I0_2
I1_1
I0_1
I1_0
I0_0
ISPR1
I1_7
I0_7
I1_6
I0_6
I1_5
I0_5
I1_4
I0_4
ISPR2
I1_11 I0_11 I1_10 I0_10 I1_9
I0_9
I1_8
I0_8
C
Bit 5, 3 = I1, I0 Software Interrupt Priority
These two bits indicate the current interrupt software priority.
Interrupt Software Priority
Level 0 (main)
Level 1
Level 2
Level 3 (= interrupt disable*)
0
I0
0
1
0
1
These two bits are set/cleared by hardware when
entering in interrupt. The loaded value is given by
the corresponding bits in the interrupt software priority registers (ISPRx).
They can be also set/cleared by software with the
RIM, SIM, HALT, WFI, IRET and PUSH/POP instructions (see “Interrupt Dedicated Instruction
Set” table).
*Note: TLI, TRAP and RESET events can interrupt
a level 3 program.
ISPR3
1
1
1
1
I1_13 I0_13 I1_12 I0_12
These four registers contain the interrupt software
priority of each interrupt vector.
– Each interrupt vector (except RESET and TRAP)
has corresponding bits in these registers where
its own software priority is stored. This correspondance is shown in the following table.
Vector address
ISPRx bits
FFFBh-FFFAh
FFF9h-FFF8h
...
FFE1h-FFE0h
I1_0 and I0_0 bits*
I1_1 and I0_1 bits
...
I1_13 and I0_13 bits
– Each I1_x and I0_x bit value in the ISPRx registers has the same meaning as the I1 and I0 bits
in the CC register.
– Level 0 can not be written (I1_x=1, I0_x=0). In
this case, the previously stored value is kept. (example: previous=CFh, write=64h, result=44h)
The RESET, TRAP and TLI vectors have no software priorities. When one is serviced, the I1 and I0
bits of the CC register are both set.
*Note: Bits in the ISPRx registers which correspond to the TLI can be read and written but they
are not significant in the interrupt process management.
Caution: If the I1_x and I0_x bits are modified
while the interrupt x is executed the following behaviour has to be considered: If the interrupt x is
still pending (new interrupt or flag not cleared) and
the new software priority is higher than the previous one, the interrupt x is re-entered. Otherwise,
the software priority stays unchanged up to the
next interrupt request (after the IRET of the interrupt x).
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INTERRUPTS (Cont’d)
Table 7. Dedicated Interrupt Instruction Set
Instruction
HALT
New Description
Function/Example
Entering Halt mode
I1
H
1
IRET
Interrupt routine return
Pop CC, A, X, PC
JRM
Jump if I1:0=11 (level 3)
I1:0=11 ?
JRNM
Jump if I1:0<>11
I1:0<>11 ?
I0
N
Z
C
0
I1
H
I0
N
Z
C
I1
H
I0
N
Z
C
POP CC
Pop CC from the Stack
Mem => CC
RIM
Enable interrupt (level 0 set)
Load 10 in I1:0 of CC
1
0
SIM
Disable interrupt (level 3 set)
Load 11 in I1:0 of CC
1
1
TRAP
Software trap
Software NMI
1
1
WFI
Wait for interrupt
1
0
Note: During the execution of an interrupt routine, the HALT, POPCC, RIM, SIM and WFI instructions change the current
software priority up to the next IRET instruction or one of the previously mentioned instructions.
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ST72561
INTERRUPTS (Cont’d)
Table 8. Interrupt Mapping
N°
Source
Block
RESET
TRAP
Description
Reset
Software interrupt
External top level interrupt
Register
Label
Priority
Order
N/A
Highest
Priority
Address
Vector
yes
FFFEh-FFFFh
no
FFFCh-FFFDh
yes
FFFAh-FFFBh
yes
FFF8h-FFF9h
0
TLI
1
MCC/RTC
2
ei0/AWUFH
3
ei1/AVD
4
ei2
External interrupt ei2
EICR
FFF2h-FFF3h
5
ei3
External interrupt ei3
EICR
FFF0h-FFF1h
6
CAN
CAN peripheral interrupt - RX
CIER
no
FFEEh-FFEFh
7
CAN
CAN peripheral interrupt - TX / ER / SC
CIER
yes3)
FFECh-FFEDh
Main clock controller time base interrupt
External interrupt ei0/ Auto wake-up from Halt
External interrupt ei1/Auxiliary Voltage Detector
8
SPI
9
TIMER8
8-bit TIMER peripheral interrupts
10
TIMER16
16-bit TIMER peripheral interrupts
11
12
13
SPI peripheral interrupts
EICR
Exit
from
HALT1)
MCCSR
EICR/
AWUCSR
EICR/
SICSR
yes
FFEAh-FFEBh
no
FFE8h-FFE9h
TCR1
no
FFE6h-FFE7h
SCI2CR1
no
FFE4h-FFE5h
no4)
FFE2h-FFE3h
yes
FFE0h-FFE1h
SCI1
LINSCI1 Peripheral interrupts (LIN Master/
Slave)
SCI1CR1
8-bit PWM ART interrupts
PWMCR
PWM ART
FFF4h-FFF5h
SPICSR
LINSCI2 Peripheral interrupts
LIN
yes2)
T8_TCR1
SCI2
LIN
FFF6h-FFF7h
Lowest
Priority
Notes:
1. Valid for HALT and ACTIVE-HALT modes except for the MCC/RTC interrupt source which exits from
ACTIVE-HALT mode only.
2. Except AVD interrupt
3. Exit from Halt only when a wake-up condition is detected, generating a Status Change interrupt. See
Section 10.9.5 on page 187.
4. It is possible to exit from Halt using the external interrupt which is mapped on the RDI pin.
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ST72561
INTERRUPTS (Cont’d)
7.6 EXTERNAL INTERRUPTS
Falling and rising edge
■ Falling edge and low level
To guarantee correct functionality, the sensitivity
bits in the EICR register can be modified only
when the I1 and I0 bits of the CC register are both
set to 1 (level 3). This means that interrupts must
be disabled before changing sensitivity.
The pending interrupts are cleared by writing a different value in the ISx[1:0] of the EICR.
■
7.6.1 I/O PORT INTERRUPT SENSITIVITY
The external interrupt sensitivity is controlled by
the ISxx bits in the EICR register (Figure 21). This
control allows up to 4 fully independent external interrupt source sensitivities.
Each external interrupt source can be generated
on four (or five) different events on the pin:
■ Falling edge
■ Rising edge
Figure 21. External Interrupt Control bits
PORT A [7:0] INTERRUPTS
PAOR.0
PADDR.0
PA0
EICR
IS00
IS01
SENSITIVITY
CONTROL
PA0
PA1
PA2
PA3
ei0 INTERRUPT SOURCE
PA4
PA5
PA6
PA7
PORT B [5:0] INTERRUPTS
PBOR.0
PBDDR.0
PB0
PCOR.7
PCDDR.7
PC1
PDOR.0
PDDDR.0
AWUFH
Oscillator
IS11
SENSITIVITY
/ AWUPR
To Timer Input Capture 1
PB0
PB1
PB2
PB3
PB4
PB5
ei1 INTERRUPT SOURCE
EICR
IS20
IS21
SENSITIVITY
CONTROL
PORT D [7:6, 4, 1:0] INTERRUPTS
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IS10
CONTROL
PORT C [2:1] INTERRUPTS
PD0
EICR
PC1
PC2
ei2 INTERRUPT SOURCE
EICR
IS30
IS31
SENSITIVITY
CONTROL
PD0
PD1
PD4
PD6
PD7
ei3 INTERRUPT SOURCE
ST72561
INTERRUPTS (Cont’d)
7.6.2 Register Description
EXTERNAL INTERRUPT CONTROL
REGISTER 0 (EICR0)
Read /Write
Reset Value: 0000 0000 (00h)
These 2 bits can be written only when I1 and I0 of
the CC register are both set to 1 (level 3).
7
0
Bit 1:0 = IS0[1:0] ei0 sensitivity
The interrupt sensitivity, defined using the IS0[1:0]
bits, is applied to the ei0 external interrupts:
IS01 IS00
IS31
IS30
IS21
IS20
IS11
IS10
IS01
IS00
Bit 7:6 = IS3[1:0] ei3 sensitivity
The interrupt sensitivity, defined using the IS3[1:0]
bits, is applied to the ei3 external interrupts:
IS31 IS30
External Interrupt Sensitivity
0
0
Falling edge & low level
0
1
Rising edge only
1
0
Falling edge only
1
1
Rising and falling edge
These 2 bits can be written only when I1 and I0 of
the CC register are both set to 1 (level 3).
Bit 5:4 = IS2[1:0] ei2 sensitivity
The interrupt sensitivity, defined using the IS2[1:0]
bits, is applied to the ei2 external interrupts:
IS21 IS20
0
0
Falling edge & low level
0
1
Rising edge only
1
0
Falling edge only
1
1
Rising and falling edge
These 2 bits can be written only when I1 and I0 of
the CC register are both set to 1 (level 3).
EXTERNAL INTERUPT CONTROL REGISTER 1
(EICR1)
Read /Write
Reset Value: 0000 0000 (00h)
7
0
0
0
0
0
0
0
TLIS
TLIE
BIt 7:2 = Reserved
External Interrupt Sensitivity
0
0
0
1
Rising edge only
1
0
Falling edge only
1
1
Rising and falling edge
Falling edge & low level
These 2 bits can be written only when I1 and I0 of
the CC register are both set to 1 (level 3).
Bit 3:2 = IS1[1:0] ei1 sensitivity
The interrupt sensitivity, defined using the IS1[1:0]
bits, is applied to the ei1 external interrupts:
IS11 IS10
External Interrupt Sensitivity
External Interrupt Sensitivity
0
0
Falling edge & low level
0
1
Rising edge only
1
0
Falling edge only
1
1
Rising and falling edge
Bit 1 = TLIS Top Level Interrupt sensitivity
This bit configures the TLI edge sensitivity. It can
be set and cleared by software only when TLIE bit
is cleared.
0: Falling edge
1: Rising edge
Bit 0 = TLIE Top Level Interrupt enable
This bit allows to enable or disable the TLI capability on the dedicated pin. It is set and cleared by
software.
0: TLI disabled
1: TLI enabled
Notes:
– A parasitic interrupt can be generated when
clearing the TLIE bit.
– In some packages, the TLI pin is not available. In
this case, the TLIE bit must be kept low to avoid
parasitic TLI interrupts.
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ST72561
INTERRUPTS (Cont’d)
Table 9. Nested Interrupts Register Map and Reset Values
Address
(Hex.)
Register
Label
0025h
ISPR0
Reset Value
7
6
5
4
3
2
CLKM
ei0
I1_2
I0_2
1
1
CAN RX
I1_6
I0_6
1
1
I1_1
1
TLI
TIMER 8
I1_9
I0_9
1
1
ART
SPI
I1_8
I0_8
1
1
LINSCI 1
I1_12
1
IS01
0
TLIS
0
0026h
ISPR1
Reset Value
0027h
ISPR2
Reset Value
LINSCI 2
I1_11
I0_11
1
1
TIMER 16
I1_10
I0_10
1
1
0028h
ISPR3
Reset Value
EICR0
Reset Value
EICR1
Reset Value
1
IS31
0
1
IS30
0
1
IS21
0
1
IS20
0
I1_13
1
IS11
0
I0_13
1
IS10
0
0
0
0
0
0
0
002Ah
38/262
0
ei1
I1_3
I0_3
1
1
CAN TX/ER/SC
I1_7
I0_7
1
1
0029h
1
I0_1
1
1
ei3
I1_5
1
1
ei2
I0_5
1
I1_4
1
I0_4
1
I0_12
1
IS00
0
TLIE
0
ST72561
8 POWER SAVING MODES
8.1 INTRODUCTION
8.2 SLOW MODE
To give a large measure of flexibility to the application in terms of power consumption, five main power saving modes are implemented in the ST7 (see
Figure 22):
■ Slow
■ Wait (and Slow-Wait)
■ Active Halt
■ Auto Wake up From Halt (AWUFH)
■ Halt
After a RESET the normal operating mode is selected by default (RUN mode). This mode drives
the device (CPU and embedded peripherals) by
means of a master clock which is based on the
main oscillator frequency divided or multiplied by 2
(fOSC2).
From RUN mode, the different power saving
modes may be selected by setting the relevant
register bits or by calling the specific ST7 software
instruction whose action depends on the oscillator
status.
This mode has two targets:
– To reduce power consumption by decreasing the
internal clock in the device,
– To adapt the internal clock frequency (fCPU) to
the available supply voltage.
SLOW mode is controlled by three bits in the
MCCSR register: the SMS bit which enables or
disables Slow mode and two CPx bits which select
the internal slow frequency (fCPU).
In this mode, the master clock frequency (fOSC2)
can be divided by 2, 4, 8 or 16. The CPU and peripherals are clocked at this lower frequency
(fCPU).
Note: SLOW-WAIT mode is activated by entering
WAIT mode while the device is in SLOW mode.
Figure 23. SLOW Mode Clock Transitions
fOSC2/2
fOSC2/4
fOSC2
fCPU
Figure 22. Power Saving Mode Transitions
High
RUN
MCCSR
fOSC2
CP1:0
00
01
SMS
SLOW
NEW SLOW
FREQUENCY
REQUEST
WAIT
NORMAL RUN MODE
REQUEST
SLOW WAIT
ACTIVE HALT
AUTO WAKE UP FROM HALT
HALT
Low
POWER CONSUMPTION
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ST72561
POWER SAVING MODES (Cont’d)
8.3 WAIT MODE
WAIT mode places the MCU in a low power consumption mode by stopping the CPU.
This power saving mode is selected by calling the
‘WFI’ instruction.
All peripherals remain active. During WAIT mode,
the I[1:0] bits of the CC register are forced to ‘10’,
to enable all interrupts. All other registers and
memory remain unchanged. The MCU remains in
WAIT mode until an interrupt or RESET occurs,
whereupon the Program Counter branches to the
starting address of the interrupt or Reset service
routine.
The MCU will remain in WAIT mode until a Reset
or an Interrupt occurs, causing it to wake up.
Refer to Figure 24.
Figure 24. WAIT Mode Flow-chart
WFI INSTRUCTION
OSCILLATOR
PERIPHERALS
CPU
I[1:0] BITS
ON
ON
OFF
10
N
RESET
Y
N
INTERRUPT
Y
OSCILLATOR
PERIPHERALS
CPU
I[1:0] BITS
ON
OFF
ON
10
256 OR 4096 CPU CLOCK
CYCLE DELAY
OSCILLATOR
PERIPHERALS
CPU
I[1:0] BITS
ON
ON
ON
XX 1)
FETCH RESET VECTOR
OR SERVICE INTERRUPT
Note:
1. Before servicing an interrupt, the CC register is
pushed on the stack. The I[1:0] bits of the CC register are set to the current software priority level of
the interrupt routine and recovered when the CC
register is popped.
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ST72561
POWER SAVING MODES (Cont’d)
8.4 HALT MODE
Figure 26. HALT Mode Flow-chart
The HALT mode is the lowest power consumption
mode of the MCU. It is entered by executing the
‘HALT’ instruction when the OIE bit of the Main
Clock Controller Status register (MCCSR) is
cleared (see Section 10.2 on page 61 for more details on the MCCSR register) and when the
AWUEN bit in the AWUCSR register is cleared.
The MCU can exit HALT mode on reception of either a specific interrupt (see Table 8, “Interrupt
Mapping,” on page 35) or a RESET. When exiting
HALT mode by means of a RESET or an interrupt,
the oscillator is immediately turned on and the 256
or 4096 CPU cycle delay is used to stabilize the
oscillator. After the start up delay, the CPU
resumes operation by servicing the interrupt or by
fetching the reset vector which woke it up (see Figure 26).
When entering HALT mode, the I[1:0] bits in the
CC register are forced to ‘10b’to enable interrupts.
Therefore, if an interrupt is pending, the MCU
wakes up immediately.
In HALT mode, the main oscillator is turned off
causing all internal processing to be stopped, including the operation of the on-chip peripherals.
All peripherals are not clocked except the ones
which get their clock supply from another clock
generator (such as an external or auxiliary oscillator).
The compatibility of Watchdog operation with
HALT mode is configured by the “WDGHALT” option bit of the option byte. The HALT instruction
when executed while the Watchdog system is enabled, can generate a Watchdog RESET (see
Section 14.1 on page 254 for more details).
Figure 25. HALT Timing Overview
RUN
HALT
HALT
INSTRUCTION
[MCCSR.OIE=0]
256 OR 4096 CPU
CYCLE DELAY
HALT INSTRUCTION
(MCCSR.OIE=0)
(AWUCSR.AWUEN=0)
ENABLE
WDGHALT 1)
WATCHDOG
DISABLE
0
1
WATCHDOG
RESET
OSCILLATOR
OFF
PERIPHERALS 2) OFF
CPU
OFF
I[1:0] BITS
10
N
RESET
N
Y
INTERRUPT 3)
Y
OSCILLATOR
PERIPHERALS
CPU
I[1:0] BITS
ON
OFF
ON
XX 4)
256 OR 4096 CPU CLOCK
CYCLE DELAY
OSCILLATOR
PERIPHERALS
CPU
I[1:0] BITS
ON
ON
ON
XX 4)
FETCH RESET VECTOR
OR SERVICE INTERRUPT
RUN
RESET
OR
INTERRUPT
FETCH
VECTOR
Notes:
1. WDGHALT is an option bit. See option byte section for more details.
2. Peripheral clocked with an external clock source
can still be active.
3. Only some specific interrupts can exit the MCU
from HALT mode (such as external interrupt). Refer to Table 8, “Interrupt Mapping,” on page 35 for
more details.
4. Before servicing an interrupt, the CC register is
pushed on the stack. The I[1:0] bits of the CC register are set to the current software priority level of
the interrupt routine and recovered when the CC
register is popped.
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ST72561
POWER SAVING MODES (Cont’d)
Halt Mode Recommendations
– Make sure that an external event is available to
wake up the microcontroller from Halt mode.
– When using an external interrupt to wake up the
microcontroller, reinitialize the corresponding I/O
as “Input Pull-up with Interrupt” before executing
the HALT instruction. The main reason for this is
that the I/O may be wrongly configured due to external interference or by an unforeseen logical
condition.
– For the same reason, reinitialize the level sensitiveness of each external interrupt as a precautionary measure.
– The opcode for the HALT instruction is 0x8E. To
avoid an unexpected HALT instruction due to a
program counter failure, it is advised to clear all
occurrences of the data value 0x8E from memory. For example, avoid defining a constant in
ROM with the value 0x8E.
– As the HALT instruction clears the interrupt mask
in the CC register to allow interrupts, the user
may choose to clear all pending interrupt bits before executing the HALT instruction. This avoids
entering other peripheral interrupt routines after
executing the external interrupt routine corresponding to the wake-up event (reset or external
interrupt).
8.5 ACTIVE-HALT MODE
ACTIVE-HALT mode is the lowest power consumption mode of the MCU with a real time clock
available. It is entered by executing the ‘HALT’ instruction when MCC/RTC interrupt enable flag
(OIE bit in MCCSR register) is set and when the
AWUEN bit in the AWUCSR register is cleared
(See “Register Description” on page 46.)
MCCSR
OIE bit
Power Saving Mode entered when HALT
instruction is executed
0
HALT mode
1
ACTIVE-HALT mode
The MCU can exit ACTIVE-HALT mode on reception of the RTC interrupt and some specific interrupts (see Table 8, “Interrupt Mapping,” on page
35) or a RESET. When exiting ACTIVE-HALT
mode by means of a RESET a 4096 or 256 CPU
cycle delay occurs (depending on the option byte).
After the start up delay, the CPU resumes operation by servicing the interrupt or by fetching the reset vector which woke it up (see Figure 28).
When entering ACTIVE-HALT mode, the I[1:0] bits
in the CC register are cleared to enable interrupts.
Therefore, if an interrupt is pending, the MCU
wakes up immediately.
In ACTIVE-HALT mode, only the main oscillator
and its associated counter (MCC/RTC) are running to keep a wake-up time base. All other peripherals are not clocked except those which get their
clock supply from another clock generator (such
as external or auxiliary oscillator).
The safeguard against staying locked in ACTIVEHALT mode is provided by the oscillator interrupt.
Note: As soon as active halt is enabled, executing
a HALT instruction while the Watchdog is active
does not generate a RESET.
This means that the device cannot spend more
than a defined delay in this power saving mode.
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ST72561
POWER SAVING MODES (Cont’d)
Figure 27. ACTIVE-HALT Timing Overview
RUN
ACTIVE
256 OR 4096 CYCLE
HALT DELAY (AFTER RESET)
HALT
INSTRUCTION
(Active Halt enabled)
RESET
OR
INTERRUPT
RUN
FETCH
VECTOR
Figure 28. ACTIVE-HALT Mode Flow-chart
HALT INSTRUCTION
(MCCSR.OIE=1)
(AWUCSR.AWUEN=0)
OSCILLATOR
ON
PERIPHERALS 2) OFF
CPU
OFF
I[1:0] BITS
10
Notes:
1. This delay occurs only if the MCU exits
ACTIVE-HALT mode by means of a RESET.
2. Peripheral clocked with an external clock
source can still be active.
3. Only the RTC interrupt and some specific interrupts can exit the MCU from ACTIVE-HALT
mode (such as external interrupt). Refer to
Table 8, “Interrupt Mapping,” on page 35 for
more details.
4. Before servicing an interrupt, the CC register is
pushed on the stack. The I[1:0] bits in the CC
register are set to the current software priority
level of the interrupt routine and restored when
the CC register is popped.
N
RESET
N
Y
INTERRUPT 3)
Y
OSCILLATOR
PERIPHERALS
CPU
I[1:0] BITS
ON
OFF
ON
XX 4)
256 OR 4096 CPU CLOCK
CYCLE DELAY
OSCILLATOR
PERIPHERALS
CPU
I[1:0] BITS
ON
ON
ON
XX 4)
FETCH RESET VECTOR
OR SERVICE INTERRUPT
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ST72561
POWER SAVING MODES (Cont’d)
8.6 AUTO WAKE UP FROM HALT MODE
Auto Wake Up From Halt (AWUFH) mode is similar to Halt mode with the addition of an internal RC
oscillator for wake-up. Compared to ACTIVEHALT mode, AWUFH has lower power consumption because the main clock is not kept running,
but there is no accurate realtime clock available.
It is entered by executing the HALT instruction
when the AWUEN bit in the AWUCSR register has
been set and the OIE bit in the MCCSR register is
cleared (see Section 10.2 on page 61 for more details).
Figure 29. AWUFH Mode Block Diagram
AWU RC
oscillator
to Timer input capture
fAWU_RC
AWUFH
prescaler
/1 .. 255
/64
divider
AWUFH
interrupt
(ei0 source)
As soon as HALT mode is entered, and if the
AWUEN bit has been set in the AWUCSR register,
the AWU RC oscillator provides a clock signal
(fAWU_RC). Its frequency is divided by a fixed divider and a programmable prescaler controlled by the
AWUPR register. The output of this prescaler provides the delay time. When the delay has elapsed
the AWUF flag is set by hardware and an interrupt
wakes-up the MCU from Halt mode. At the same
time the main oscillator is immediately turned on
and a 256 or 4096 cycle delay is used to stabilize
it. After this start-up delay, the CPU resumes operation by servicing the AWUFH interrupt. The AWU
flag and its associated interrupt are cleared by
software reading the AWUCSR register.
To compensate for any frequency dispersion of
the AWU RC oscillator, it can be calibrated by
measuring the clock frequency fAWU_RC and then
calculating the right prescaler value. Measurement
mode is enabled by setting the AWUM bit in the
AWUCSR register in Run mode. This connects
fAWU_RC to the ICAP1 input of the 16-bit timer, allowing the fAWU_RC to be measured using the main
oscillator clock as a reference timebase.
Similarities with Halt mode
The following AWUFH mode behaviour is the
same as normal Halt mode:
– The MCU can exit AWUFH mode by means of
any interrupt with exit from Halt capability or a reset (see Section 8.4 "HALT MODE").
– When entering AWUFH mode, the I[1:0] bits in
the CC register are forced to 10b to enable interrupts. Therefore, if an interrupt is pending, the
MCU wakes up immediately.
– In AWUFH mode, the main oscillator is turned off
causing all internal processing to be stopped, including the operation of the on-chip peripherals.
None of the peripherals are clocked except those
which get their clock supply from another clock
generator (such as an external or auxiliary oscillator like the AWU oscillator).
– The compatibility of Watchdog operation with
AWUFH mode is configured by the WDGHALT
option bit in the option byte. Depending on this
setting, the HALT instruction when executed
while the Watchdog system is enabled, can generate a Watchdog RESET.
Figure 30. AWUF Halt Timing Diagram
tAWU
RUN MODE
HALT MODE
256 or 4096 tCPU
RUN MODE
fCPU
fAWU_RC
Clear
by software
AWUFH interrupt
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ST72561
POWER SAVING MODES (Cont’d)
Figure 31. AWUFH Mode Flow-chart
HALT INSTRUCTION
(MCCSR.OIE=0)
(AWUCSR.AWUEN=1)
ENABLE
WDGHALT 1)
WATCHDOG
DISABLE
0
1
WATCHDOG
RESET
AWU RC OSC
ON
MAIN OSC
OFF
PERIPHERALS 2) OFF
CPU
OFF
10
I[1:0] BITS
Notes:
1. WDGHALT is an option bit. See option byte section for more details.
2. Peripheral clocked with an external clock source
can still be active.
3. Only an AWUFH interrupt and some specific interrupts can exit the MCU from HALT mode (such
as external interrupt). Refer to Table 8, “Interrupt
Mapping,” on page 35 for more details.
4. Before servicing an interrupt, the CC register is
pushed on the stack. The I[1:0] bits of the CC register are set to the current software priority level of
the interrupt routine and recovered when the CC
register is popped.
N
RESET
N
Y
INTERRUPT 3)
Y
AWU RC OSC
MAIN OSC
PERIPHERALS
CPU
I[1:0] BITS
OFF
ON
OFF
ON
XX 4)
256 OR 4096 CPU CLOCK
CYCLE DELAY
AWU RC OSC
MAIN OSC
PERIPHERALS
CPU
I[1:0] BITS
OFF
ON
ON
ON
XX 4)
FETCH RESET VECTOR
OR SERVICE INTERRUPT
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ST72561
POWER SAVING MODES (Cont’d)
8.6.0.1 Register Description
0: AWUFH (Auto Wake Up From Halt) mode disabled
1: AWUFH (Auto Wake Up From Halt) mode enabled
AWUFH CONTROL/STATUS REGISTER
(AWUCSR)
Read /Write (except bit 2 read only)
Reset Value: 0000 0000 (00h)
7
0
AWUFH PRESCALER REGISTER (AWUPR)
Read /Write
Reset Value: 1111 1111 (FFh)
0
0
0
0
AWU AWU AWU
F
M
EN
0
7
0
AWU AWU AWU AWU AWU AWU AWU AWU
PR7 PR6 PR5 PR4 PR3 PR2 PR1 PR0
Bits 7:3 = Reserved.
Bit 2= AWUF Auto Wake Up Flag
This bit is set by hardware when the AWU module
generates an interrupt and cleared by software on
reading AWUCSR.
0: No AWU interrupt occurred
1: AWU interrupt occurred
Bit 1= AWUM Auto Wake Up Measurement
This bit enables the AWU RC oscillator and connects its output to the ICAP1 input of the 16-bit timer. This allows the timer to be used to measure the
AWU RC oscillator dispersion and then compensate this dispersion by providing the right value in
the AWUPR register.
0: Measurement disabled
1: Measurement enabled
Bit 0 = AWUEN Auto Wake Up From Halt Enabled
This bit enables the Auto Wake Up From Halt feature: once HALT mode is entered, the AWUFH
wakes up the microcontroller after a time delay defined by the AWU prescaler value. It is set and
cleared by software.
Bits 7:0= AWUPR[7:0] Auto Wake Up Prescaler
These 8 bits define the AWUPR Dividing factor (as
explained below:
AWUPR[7:0]
Dividing factor
00h
Forbidden (See note)
01h
1
...
...
FEh
254
FFh
255
In AWU mode, the period that the MCU stays in
Halt Mode (tAWU in Figure 30) is defined by
t
AWU
1
= 64 × AWUPR × -------------------------- + t RCSTRT
f
AWURC
This prescaler register can be programmed to
modify the time that the MCU stays in Halt mode
before waking up automatically.
Note: If 00h is written to AWUPR, depending on
the product, an interrupt is generated immediately
after a HALT instruction, or the AWUPR remains
inchanged.
Table 10. AWU Register Map and Reset Values
Address
(Hex.)
002Bh
002Ch
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Register
Label
7
6
5
4
3
2
1
0
AWUCSR
AWUF
AWUM
AWUEN
0
0
0
0
0
Reset Value
0
0
0
AWUPR
AWUPR7 AWUPR6 AWUPR5 AWUPR4 AWUPR3 AWUPR2 AWUPR1 AWUPR0
Reset Value
1
1
1
1
1
1
1
1
ST72561
9 I/O PORTS
9.1 INTRODUCTION
The I/O ports offer different functional modes:
– transfer of data through digital inputs and outputs
and for specific pins:
– external interrupt generation
– alternate signal input/output for the on-chip peripherals.
An I/O port contains up to 8 pins. Each pin can be
programmed independently as digital input (with or
without interrupt generation) or digital output.
9.2 FUNCTIONAL DESCRIPTION
Each port has 2 main registers:
– Data Register (DR)
– Data Direction Register (DDR)
and one optional register:
– Option Register (OR)
Each I/O pin may be programmed using the corresponding register bits in the DDR and OR registers: bit X corresponding to pin X of the port. The
same correspondence is used for the DR register.
The following description takes into account the
OR register, (for specific ports which do not provide this register refer to the I/O Port Implementation section). The generic I/O block diagram is
shown in Figure 32
9.2.1 Input Modes
The input configuration is selected by clearing the
corresponding DDR register bit.
In this case, reading the DR register returns the
digital value applied to the external I/O pin.
Different input modes can be selected by software
through the OR register.
Notes:
1. Writing the DR register modifies the latch value
but does not affect the pin status.
2. When switching from input to output mode, the
DR register has to be written first to drive the correct level on the pin as soon as the port is configured as an output.
3. Do not use read/modify/write instructions (BSET
or BRES) to modify the DR register
External interrupt function
When an I/O is configured as Input with Interrupt,
an event on this I/O can generate an external interrupt request to the CPU.
Each pin can independently generate an interrupt
request. The interrupt sensitivity is independently
programmable using the sensitivity bits in the
EICR register.
Each external interrupt vector is linked to a dedicated group of I/O port pins (see pinout description
and interrupt section). If several input pins are selected simultaneously as interrupt sources, these
are first detected according to the sensitivity bits in
the EICR register and then logically ORed.
The external interrupts are hardware interrupts,
which means that the request latch (not accessible
directly by the application) is automatically cleared
when the corresponding interrupt vector is
fetched. To clear an unwanted pending interrupt
by software, the sensitivity bits in the EICR register
must be modified.
9.2.2 Output Modes
The output configuration is selected by setting the
corresponding DDR register bit. In this case, writing the DR register applies this digital value to the
I/O pin through the latch. Then reading the DR register returns the previously stored value.
Two different output modes can be selected by
software through the OR register: Output push-pull
and open-drain.
DR register value and output pin status:
DR
0
1
Push-pull
VSS
VDD
Open-drain
Vss
Floating
9.2.3 Alternate Functions
When an on-chip peripheral is configured to use a
pin, the alternate function is automatically selected. This alternate function takes priority over the
standard I/O programming.
When the signal is coming from an on-chip peripheral, the I/O pin is automatically configured in output mode (push-pull or open drain according to the
peripheral).
When the signal is going to an on-chip peripheral,
the I/O pin must be configured in input mode. In
this case, the pin state is also digitally readable by
addressing the DR register.
Note: Input pull-up configuration can cause unexpected value at the input of the alternate peripheral
input. When an on-chip peripheral use a pin as input and output, this pin has to be configured in input floating mode.
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ST72561
I/O PORTS (Cont’d)
Figure 32. I/O Port General Block Diagram
ALTERNATE
OUTPUT
REGISTER
ACCESS
1
P-BUFFER
(see table below)
VDD
0
ALTERNATE
ENABLE
PULL-UP
(see table below)
DR
VDD
DDR
PULL-UP
CONDITION
DATA BUS
OR
PAD
If implemented
OR SEL
N-BUFFER
DIODES
(see table below)
DDR SEL
DR SEL
ANALOG
INPUT
CMOS
SCHMITT
TRIGGER
1
0
ALTERNATE
INPUT
EXTERNAL
INTERRUPT
SOURCE (eix)
Table 11. I/O Port Mode Options
Configuration Mode
Input
Output
Floating with/without Interrupt
Pull-up with/without Interrupt
Push-pull
Open Drain (logic level)
True Open Drain
Legend: NI - not implemented
Off - implemented not activated
On - implemented and activated
48/262
Pull-Up
P-Buffer
Off
On
Off
Off
NI
On
Off
NI
Diodes
to VDD
On
to VSS
On
NI (see note)
Note: The diode to VDD is not implemented in the
true open drain pads. A local protection between
the pad and VSS is implemented to protect the device against positive stress.
ST72561
I/O PORTS (Cont’d)
Table 12. I/O Port Configurations
Hardware Configuration
NOT IMPLEMENTED IN
TRUE OPEN DRAIN
I/O PORTS
DR REGISTER ACCESS
VDD
RPU
PULL-UP
CONDITION
DR
REGISTER
PAD
W
DATA BUS
INPUT 1)
R
ALTERNATE INPUT
EXTERNAL INTERRUPT
SOURCE (eix)
INTERRUPT
CONDITION
PUSH-PULL OUTPUT 2)
OPEN-DRAIN OUTPUT 2)
ANALOG INPUT
NOT IMPLEMENTED IN
TRUE OPEN DRAIN
I/O PORTS
DR REGISTER ACCESS
VDD
RPU
DR
REGISTER
PAD
ALTERNATE
ENABLE
NOT IMPLEMENTED IN
TRUE OPEN DRAIN
I/O PORTS
R/W
DATA BUS
ALTERNATE
OUTPUT
DR REGISTER ACCESS
VDD
RPU
PAD
DR
REGISTER
ALTERNATE
ENABLE
R/W
DATA BUS
ALTERNATE
OUTPUT
Notes:
1. When the I/O port is in input configuration and the associated alternate function is enabled as an output,
reading the DR register will read the alternate function output status.
2. When the I/O port is in output configuration and the associated alternate function is enabled as an input,
the alternate function reads the pin status given by the DR register content.
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ST72561
I/O PORTS (Cont’d)
CAUTION: The alternate function must not be activated as long as the pin is configured as input
with interrupt, in order to avoid generating spurious
interrupts.
Analog alternate function
When the pin is used as an ADC input, the I/O
must be configured as floating input. The analog
multiplexer (controlled by the ADC registers)
switches the analog voltage present on the selected pin to the common analog rail which is connected to the ADC input.
It is recommended not to change the voltage level
or loading on any port pin while conversion is in
progress. Furthermore it is recommended not to
have clocking pins located close to a selected analog pin.
WARNING: The analog input voltage level must
be within the limits stated in the absolute maximum ratings.
Figure 33. Interrupt I/O Port State Transitions
01
00
10
11
INPUT
floating/pull-up
interrupt
INPUT
floating
(reset state)
OUTPUT
open-drain
OUTPUT
push-pull
XX
= DDR, OR
9.4 LOW POWER MODES
Mode
WAIT
HALT
Description
No effect on I/O ports. External interrupts
cause the device to exit from WAIT mode.
No effect on I/O ports. External interrupts
cause the device to exit from HALT mode.
9.5 INTERRUPTS
9.3 I/O PORT IMPLEMENTATION
The hardware implementation on each I/O port depends on the settings in the DDR and OR registers
and specific feature of the I/O port such as ADC Input or true open drain.
Switching these I/O ports from one state to another should be done in a sequence that prevents unwanted side effects. Recommended safe transitions are illustrated in Figure 33 Other transitions
are potentially risky and should be avoided, since
they are likely to present unwanted side-effects
such as spurious interrupt generation.
50/262
The external interrupt event generates an interrupt
if the corresponding configuration is selected with
DDR and OR registers and the interrupt mask in
the CC register is not active (RIM instruction).
Interrupt Event
External interrupt on
selected external
event
Enable
Event
Control
Flag
Bit
-
DDRx
ORx
Exit
from
Wait
Exit
from
Halt
Yes
Yes
ST72561
I/O PORTS (Cont’d)
9.6 I/O Port Implementation
The I/O port register configurations are summarised as following.
9.6.1 Standard Ports
PB7:6, PC0, PC3, PC7:5, PD3:2, PD5, PE7:0,
PF7:0
MODE
floating input
pull-up input
open drain output
push-pull output
DDR
0
0
1
1
OR
0
1
0
1
MODE
floating input
floating interrupt input
open drain output
push-pull output
DDR
0
0
1
1
OR
0
1
0
1
9.6.3 Pull-up Input Port (CANTX requirement)
PC4
MODE
pull-up input
9.6.2 Interrupt Ports
PA0,2,4,6; PB0,2,4; PC1; PD0,6
(with pull-up)
MODE
floating input
pull-up interrupt input
open drain output
push-pull output
PA1,3,5,7; PB1,3,5; PC2; PD1,4,7
(without pull-up)
DDR
0
0
1
1
OR
0
1
0
1
The PC4 port cannot be controlled by DR/DDR/
OR in output. The CAN peripheral controls it directly when enabled. Otherwise, it is pull-up input.
However, it is still possible to read the port through
DR register (providing DDR is set properly).
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ST72561
I/O PORTS (Cont’d)
Table 13. Port Configuration
Port
Port A
Port B
Pin name
Input
OR = 0
PA0
PA1
pull-up interrupt (ei0)
floating interrupt (ei0)
PA2
PA3
PA4
pull-up interrupt (ei0)
floating interrupt (ei0)
pull-up interrupt (ei0)
floating
PA5
PA6
floating interrupt (ei0)
pull-up interrupt (ei0)
PA7
PB0
floating interrupt (ei0)
pull-up interrupt (ei1)
PB1
PB2
floating interrupt (ei1)
pull-up interrupt (ei1)
PB3
PB4
floating
PB5
PC0
Port C
PC1
PC2
floating
OR = 1
open drain
push-pull
open drain
push-pull
open drain
push-pull
pull-up
floating
controlled by CANTX *
pull-up
pull-up interrupt (ei3)
open drain
push-pull
open drain
push-pull
floating interrupt (ei3)
pull-up
floating
PD6
PD7
Port E
Port F
pull-up interrupt (ei2)
floating interrupt (ei2)
pull-up
PD1
PD3:2
PD4
PD5
floating interrupt (ei1)
pull-up interrupt (ei1)
OR = 0
floating interrupt (ei1)
pull-up
PC3
PC4
PC7:5
PD0
Port D
Output
OR = 1
floating interrupt (ei3)
pull-up
pull-up interrupt (ei3)
floating interrupt (ei3)
PE7:0
floating (TTL)
pull-up (TTL)
open drain
push-pull
PF7:0
floating (TTL)
pull-up (TTL)
open drain
push-pull
* Note: when the CANTX alternate function is selected, the I/O port operates in output push-pull mode.
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ST72561
I/O PORTS (Cont’d)
Table 14. I/O Port Register Map and Reset Values
Address
(Hex.)
Register
Label
Reset Value
of all IO port registers
0000h
PADR
0001h
PADDR
0002h
PAOR
0003h
PBDR
0004h
PBDDR
0005h
PBOR
0006h
PCDR
0007h
PCDDR
0008h
PCOR
0009h
PDDR
000Ah
PDDDR
000Bh
PDOR
000Ch
PEDR
000Dh
PEDDR
000Eh
PEOR
000Fh
PFDR
0010h
PFDDR
0011h
PFOR
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
MSB
LSB
MSB
LSB
MSB
LSB
MSB
LSB
MSB
LSB
MSB
LSB
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ST72561
10 ON-CHIP PERIPHERALS
10.1 WINDOW WATCHDOG (WWDG)
10.1.1 Introduction
The Window Watchdog is used to detect the occurrence of a software fault, usually generated by
external interference or by unforeseen logical conditions, which causes the application program to
abandon its normal sequence. The Watchdog circuit generates an MCU reset on expiry of a programmed time period, unless the program refreshes the contents of the downcounter before the T6
bit becomes cleared. An MCU reset is also generated if the 7-bit downcounter value (in the control
register) is refreshed before the downcounter has
reached the window register value. This implies
that the counter must be refreshed in a limited window.
10.1.2 Main Features
– Programmable free-running downcounter
– Conditional reset
– Reset (if watchdog activated) when the downcounter value becomes less than 40h
– Reset (if watchdog activated) if the down-
counter is reloaded outside the window (see
Figure 37)
– Hardware/Software Watchdog activation (selectable by option byte)
– Optional reset on HALT instruction (configurable
by option byte)
10.1.3 Functional Description
The counter value stored in the WDGCR register
(bits T[6:0]), is decremented every 16384 fOSC2
cycles (approx.), and the length of the timeout period can be programmed by the user in 64 increments.
If the watchdog is activated (the WDGA bit is set)
and when the 7-bit downcounter (T[6:0] bits) rolls
over from 40h to 3Fh (T6 becomes cleared), it initiates a reset cycle pulling low the reset pin for typically 30µs. If the software reloads the counter
while the counter is greater than the value stored
in the window register, then a reset is generated.
Figure 34. Watchdog Block Diagram
WATCHDOG WINDOW REGISTER (WDGWR)
RESET
-
W6
W5
W4
W3
W2
W1
W0
comparator
=1 when
T6:0 > W6:0 CMP
Write WDGCR
WATCHDOG CONTROL REGISTER (WDGCR)
WDGA
T6
T5
T3
T2
DIV 64
WDG PRESCALER
DIV 4
12-BIT MCC
RTC COUNTER
MSB
11
54/262
LSB
6 5
T1
6-BIT DOWNCOUNTER (CNT)
MCC/RTC
fOSC2
T4
0
TB[1:0] bits
(MCCSR
Register)
T0
ST72561
WINDOW WATCHDOG (Cont’d)
The application program must write in the
WDGCR register at regular intervals during normal
operation to prevent an MCU reset. This operation
must occur only when the counter value is lower
than the window register value. The value to be
stored in the WDGCR register must be between
FFh and C0h (see Figure 35):
– Enabling the watchdog:
When Software Watchdog is selected (by option
byte), the watchdog is disabled after a reset. It is
enabled by setting the WDGA bit in the WDGCR
register, then it cannot be disabled again except
by a reset.
When Hardware Watchdog is selected (by option
byte), the watchdog is always active and the
WDGA bit is not used.
– Controlling the downcounter :
This downcounter is free-running: it counts down
even if the watchdog is disabled. When the
watchdog is enabled, the T6 bit must be set to
prevent generating an immediate reset.
The T[5:0] bits contain the number of increments
which represents the time delay before the
watchdog produces a reset (see Figure 35. Approximate Timeout Duration). The timing varies
between a minimum and a maximum value due
to the unknown status of the prescaler when writing to the WDGCR register (see Figure 36).
The window register (WDGWR) contains the
high limit of the window: to prevent a reset, the
downcounter must be reloaded when its value is
lower than the window register value and greater
than 3Fh. Figure 37 describes the window watchdog process.
Note: The T6 bit can be used to generate a software reset (the WDGA bit is set and the T6 bit is
cleared).
– Watchdog Reset on Halt option
If the watchdog is activated and the watchdog reset on halt option is selected, then the HALT instruction will generate a Reset.
10.1.4 Using Halt Mode with the WDG
If Halt mode with Watchdog is enabled by option
byte (No watchdog reset on HALT instruction), it is
recommended before executing the HALT instruction to refresh the WDG counter, to avoid an unexpected WDG reset immediately after waking up
the microcontroller.
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ST72561
WINDOW WATCHDOG (Cont’d)
10.1.5 How to Program the Watchdog Timeout
Figure 35 shows the linear relationship between
the 6-bit value to be loaded in the Watchdog Counter (CNT) and the resulting timeout duration in milliseconds. This can be used for a quick calculation
without taking the timing variations into account. If
more precision is needed, use the formulae in Figure 36.
Caution: When writing to the WDGCR register, always write 1 in the T6 bit to avoid generating an
immediate reset.
Figure 35. Approximate Timeout Duration
3F
38
CNT Value (hex.)
30
28
20
18
10
08
00
1.5
18
34
50
65
82
Watchdog timeout (ms) @ 8 MHz. fOSC2
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98
114
128
ST72561
WATCHDOG TIMER (Cont’d)
Figure 36. Exact Timeout Duration (tmin and tmax)
WHERE:
tmin0 = (LSB + 128) x 64 x tOSC2
tmax0 = 16384 x tOSC2
tOSC2 = 125ns if fOSC2=8 MHz
CNT = Value of T[5:0] bits in the WDGCR register (6 bits)
MSB and LSB are values from the table below depending on the timebase selected by the TB[1:0] bits
in the MCCSR register
TB1 Bit
TB0 Bit
(MCCSR Reg.) (MCCSR Reg.)
0
0
0
1
1
0
1
1
Selected MCCSR
Timebase
MSB
LSB
2ms
4ms
10ms
25ms
4
8
20
49
59
53
35
54
To calculate the minimum Watchdog Timeout (tmin):
IF CNT < MSB
------------4
THEN t min = t m in0 + 16384 × CNT × t osc2
CNT 
4CNT
ELSE t min = tm in0 + 16384 ×  CN T – 4---------------- + ( 192 + L SB ) × 64 × ----------------MSB 
MSB
× tosc2
To calculate the maximum Watchdog Timeout (tmax):
IF CNT ≤ MSB
------------4
THEN t
max = t m ax0 + 16384 × CNT × t osc2
ELSE t
max
4CNT
= t
+ 16384 ×  C NT – ----------------- 
m ax0

MSB 
+ ( 192 + LSB ) × 64 ×
4CNT
----------------MS B
× to sc2
Note: In the above formulae, division results must be rounded down to the next integer value.
Example:
With 2ms timeout selected in MCCSR register
Value of T[5:0] Bits in
WDGCR Register (Hex.)
00
3F
Min. Watchdog
Timeout (ms)
tmin
1.496
128
Max. Watchdog
Timeout (ms)
tmax
2.048
128.552
57/262
ST72561
WINDOW WATCHDOG (Cont’d)
Figure 37. Window Watchdog Timing Diagram
T[5:0] CNT downcounter
WDGWR
3Fh
Refresh not allowed Refresh Window
time
(step = 16384/fOSC2)
T6 bit
Reset
10.1.6 Low Power Modes
Mode
SLOW
WAIT
Description
No effect on Watchdog : the downcounter continues to decrement at normal speed.
No effect on Watchdog : the downcounter continues to decrement.
OIE bit in
MCCSR
register
WDGHALT bit
in Option
Byte
No Watchdog reset is generated. The MCU enters Halt mode. The Watchdog counter is decremented once and then stops counting and is no longer
able to generate a watchdog reset until the MCU receives an external interrupt or a reset.
HALT
ACTIVE
HALT
0
0
0
1
1
x
If an interrupt is received (refer to interrupt table mapping to see interrupts
which can occur in halt mode), the Watchdog restarts counting after 256 or
4096 CPU clocks. If a reset is generated, the Watchdog is disabled (reset
state) unless Hardware Watchdog is selected by option byte. For application recommendations see Section 10.1.8 below.
A reset is generated instead of entering halt mode.
No reset is generated. The MCU enters Active Halt mode. The Watchdog
counter is not decremented. It stop counting. When the MCU receives an
oscillator interrupt or external interrupt, the Watchdog restarts counting immediately. When the MCU receives a reset the Watchdog restarts counting
after 256 or 4096 CPU clocks.
10.1.7 Hardware Watchdog Option
If Hardware Watchdog is selected by option byte,
the watchdog is always active and the WDGA bit in
the WDGCR is not used. Refer to the Option Byte
description.
58/262
10.1.8 Using Halt Mode with the WDG
(WDGHALT option)
The following recommendation applies if Halt
mode is used when the watchdog is enabled.
– Before executing the HALT instruction, refresh
the WDG counter, to avoid an unexpected WDG
reset immediately after waking up the microcontroller.
ST72561
WINDOW WATCHDOG (Cont’d)
10.1.9 Interrupts
None.
Bits 6:0 = T[6:0] 7-bit counter (MSB to LSB).
These bits contain the value of the watchdog
counter. It is decremented every 16384 fOSC2 cycles (approx.). A reset is produced when it rolls
over from 40h to 3Fh (T6 becomes cleared).
10.1.10 Register Description
CONTROL REGISTER (WDGCR)
Read /Write
Reset Value: 0111 1111 (7Fh)
7
WDGA
0
T6
T5
T4
T3
T2
T1
WINDOW REGISTER (WDGWR)
Read/Write
Reset Value: 0111 1111 (7Fh)
T0
7
Bit 7 = WDGA Activation bit.
This bit is set by software and only cleared by
hardware after a reset. When WDGA = 1, the
watchdog can generate a reset.
0: Watchdog disabled
1: Watchdog enabled
Note: This bit is not used if the hardware watchdog option is enabled by option byte.
-
0
W6
W5
W4
W3
W2
W1
W0
Bit 7 = Reserved
Bits 6:0 = W[6:0] 7-bit window value
These bits contain the window value to be compared to the downcounter.
59/262
ST72561
WATCHDOG TIMER (Cont’d)
Figure 38. Watchdog Timer Register Map and Reset Values
Address
(Hex.)
2F
30
60/262
Register
Label
7
6
5
4
3
2
1
0
WDGCR
WDGA
T6
T5
T4
T3
T2
T1
T0
Reset Value
0
1
1
1
1
1
1
1
WWDGR
-
W6
W5
W4
W3
W2
W1
W0
Reset Value
0
1
1
1
1
1
1
1
ST72561
10.2 MAIN CLOCK CONTROLLER WITH REAL TIME CLOCK MCC/RTC
The Main Clock Controller consists of three different functions:
■ a programmable CPU clock prescaler
■ a clock-out signal to supply external devices
■ a real time clock timer with interrupt capability
Each function can be used independently and simultaneously.
10.2.1 Programmable CPU Clock Prescaler
The programmable CPU clock prescaler supplies
the clock for the ST7 CPU and its internal peripherals. It manages SLOW power saving mode (See
Section 8.2 "SLOW MODE" for more details).
The prescaler selects the fCPU main clock frequency and is controlled by three bits in the MCCSR
register: CP[1:0] and SMS.
10.2.2 Clock-out Capability
The clock-out capability is an alternate function of
an I/O port pin that outputs a fOSC2 clock to drive
external devices. It is controlled by the MCO bit in
the MCCSR register.
10.2.3 Real Time Clock Timer (RTC)
The counter of the real time clock timer allows an
interrupt to be generated based on an accurate
real time clock. Four different time bases depending directly on fOSC2 are available. The whole
functionality is controlled by four bits of the MCCSR register: TB[1:0], OIE and OIF.
When the RTC interrupt is enabled (OIE bit set),
the ST7 enters ACTIVE-HALT mode when the
HALT instruction is executed. See Section 8.5
"ACTIVE-HALT MODE" for more details.
Figure 39. Main Clock Controller (MCC/RTC) Block Diagram
MCO
fOSC2
TO
WATCHDOG
TIMER
RTC
COUNTER
MCO CP1 CP0 SMS TB1 TB0
OIE
OIF
MCCSR
MCC/RTC INTERRUPT
DIV 2, 4, 8, 16
fCPU
CPU CLOCK
TO CPU AND
PERIPHERALS
61/262
ST72561
MAIN CLOCK CONTROLLER WITH REAL TIME CLOCK (Cont’d)
10.2.4 Low Power Modes
Mode
WAIT
ACTIVEHALT
HALT
and
AWUF HALT
Description
No effect on MCC/RTC peripheral.
MCC/RTC interrupt cause the device to
exit from WAIT mode.
No effect on MCC/RTC counter (OIE bit
is set), the registers are frozen.
MCC/RTC interrupt cause the device to
exit from ACTIVE-HALT mode.
MCC/RTC counter and registers are
frozen.
MCC/RTC operation resumes when
the MCU is woken up by an interrupt
with “exit from HALT” capability.
10.2.5 Interrupts
The MCC/RTC interrupt event generates an interrupt if the OIE bit of the MCCSR register is set and
the interrupt mask in the CC register is not active
(RIM instruction).
Interrupt Event
Time base overflow
event
Enable
Event
Control
Flag
Bit
OIF
OIE
Exit
from
Wait
Exit
from
Halt
Yes
No 1)
Note:
The MCC/RTC interrupt wakes up the MCU from
ACTIVE-HALT mode, not from HALT or AWUF
HALT mode.
10.2.6 Register Description
MCC CONTROL/STATUS REGISTER (MCCSR)
Read /Write
Reset Value: 0000 0000 (00h )
7
MCO
0
CP1
CP0
SMS
TB1
TB0
OIE
fCPU in SLOW mode
CP1
CP0
fOSC2 / 2
0
0
fOSC2 / 4
0
1
fOSC2/ 8
1
0
fOSC2 / 16
1
1
Bit 4 = SMS Slow mode select
This bit is set and cleared by software.
0: Normal mode. fCPU = fOSC2
1: Slow mode. fCPU is given by CP1, CP0
See Section 8.2 "SLOW MODE" and Section 10.2
"MAIN CLOCK CONTROLLER WITH REAL TIME
CLOCK MCC/RTC" for more details.
Bit 3:2 = TB[1:0] Time base control
These bits select the programmable divider time
base. They are set and cleared by software.
Time Base
Counter
Prescaler f
OSC2 =4MHz fOSC2=8MHz
16000
4ms
2ms
TB1
TB0
0
0
32000
8ms
4ms
0
1
80000
20ms
10ms
1
0
200000
50ms
25ms
1
1
A modification of the time base is taken into account at the end of the current period (previously
set) to avoid an unwanted time shift. This allows to
use this time base as a real time clock.
OIF
Bit 7 = MCO Main clock out selection
This bit enables the MCO alternate function on the
corresponding I/O port. It is set and cleared by
software.
0: MCO alternate function disabled (I/O pin free for
general-purpose I/O)
1: MCO alternate function enabled (fOSC2 on I/O
port)
62/262
Bit 6:5 = CP[1:0] CPU clock prescaler
These bits select the CPU clock prescaler which is
applied in the different slow modes. Their action is
conditioned by the setting of the SMS bit. These
two bits are set and cleared by software
Bit 1 = OIE Oscillator interrupt enable
This bit set and cleared by software.
0: Oscillator interrupt disabled
1: Oscillator interrupt enabled
This interrupt can be used to exit from ACTIVEHALT mode.
When this bit is set, calling the ST7 software HALT
instruction enters the ACTIVE-HALT power saving
mode.
ST72561
MAIN CLOCK CONTROLLER WITH REAL TIME CLOCK (Cont’d)
Bit 0 = OIF Oscillator interrupt flag
This bit is set by hardware and cleared by software
reading the CSR register. It indicates when set
that the main oscillator has reached the selected
elapsed time (TB1:0).
0: Timeout not reached
1: Timeout reached
CAUTION: The BRES and BSET instructions
must not be used on the MCCSR register to avoid
unintentionally clearing the OIF bit.
Table 15. Main Clock Controller Register Map and Reset Values
Address
(Hex.)
002Dh
002Eh
Register
Label
SICSR
Reset Value
MCCSR
Reset Value
7
6
5
4
3
0
AVDIE
AVDF
LVDRF
0
MCO
0
CP1
0
CP0
0
SMS
0
TB1
0
2
1
0
0
TB0
0
0
OIE
0
WDGRF
x
OIF
0
63/262
ST72561
10.3 PWM AUTO-RELOAD TIMER (ART)
10.3.1 Introduction
The Pulse Width Modulated Auto-Reload Timer
on-chip peripheral consists of an 8-bit auto reload
counter with compare/capture capabilities and of a
7-bit prescaler clock source.
These resources allow five possible operating
modes:
– Generation of up to 4 independent PWM signals
– Output compare and Time base interrupt
– Up to two input capture functions
– External event detector
– Up to two external interrupt sources
The three first modes can be used together with a
single counter frequency.
The timer can be used to wake up the MCU from
WAIT and HALT modes.
Figure 40. PWM Auto-Reload Timer Block Diagram
OEx
PWMCR
OCRx
DCRx
REGISTER
REGISTER
OPx
LOAD
PWMx
PORT
ALTERNATE
FUNCTION
POLARITY
CONTROL
COMPARE
8-BIT COUNTER
ARR
REGISTER
INPUT CAPTURE
CONTROL
ARTICx
ICSx
ARTCLK
ICIEx
LOAD
(CAR REGISTER)
LOAD
ICFx
ICRx
REGISTER
ICCSR
ICx INTERRUPT
fEXT
fCOUNTER
fCPU
MUX
fINPUT
EXCL
PROGRAMMABLE
PRESCALER
CC2
CC1
CC0
TCE
FCRL
OIE
OVF
ARTCSR
OVF INTERRUPT
64/262
ST72561
PWM AUTO-RELOAD TIMER (Cont’d)
10.3.2 Functional Description
Counter
The free running 8-bit counter is fed by the output
of the prescaler, and is incremented on every rising edge of the clock signal.
It is possible to read or write the contents of the
counter on the fly by reading or writing the Counter
Access register (ARTCAR).
When a counter overflow occurs, the counter is
automatically reloaded with the contents of the
ARTARR register (the prescaler is not affected).
Counter clock and prescaler
The counter clock frequency is given by:
fCOUNTER = fINPUT / 2CC[2:0]
The timer counter’s input clock (fINPUT) feeds the
7-bit programmable prescaler, which selects one
of the 8 available taps of the prescaler, as defined
by CC[2:0] bits in the Control/Status Register
(ARTCSR). Thus the division factor of the prescaler can be set to 2 n (where n = 0, 1,..7).
This fINPUT frequency source is selected through
the EXCL bit of the ARTCSR register and can be
either the fCPU or an external input frequency fEXT.
The clock input to the counter is enabled by the
TCE (Timer Counter Enable) bit in the ARTCSR
register. When TCE is reset, the counter is
stopped and the prescaler and counter contents
are frozen. When TCE is set, the counter runs at
the rate of the selected clock source.
Counter and Prescaler Initialization
After RESET, the counter and the prescaler are
cleared and fINPUT = fCPU.
The counter can be initialized by:
– Writing to the ARTARR register and then setting
the FCRL (Force Counter Re-Load) and the TCE
(Timer Counter Enable) bits in the ARTCSR register.
– Writing to the ARTCAR counter access register,
In both cases the 7-bit prescaler is also cleared,
whereupon counting will start from a known value.
Direct access to the prescaler is not possible.
Output compare control
The timer compare function is based on four different comparisons with the counter (one for each
PWMx output). Each comparison is made between the counter value and an output compare
register (OCRx) value. This OCRx register can not
be accessed directly, it is loaded from the duty cycle register (PWMDCRx) at each overflow of the
counter.
This double buffering method avoids glitch generation when changing the duty cycle on the fly.
Figure 41. Output compare control
fCOUNTER
ARTARR=FDh
COUNTER
FDh
FEh
FFh
OCRx
PWMDCRx
FDh
FEh
FFh
FDh
FFh
FEh
FDh
FDh
FEh
FEh
PWMx
65/262
ST72561
PWM AUTO-RELOAD TIMER (Cont’d)
Independent PWM signal generation
This mode allows up to four Pulse Width Modulated signals to be generated on the PWMx output
pins with minimum core processing overhead.
This function is stopped during HALT mode.
Each PWMx output signal can be selected independently using the corresponding OEx bit in the
PWM Control register (PWMCR). When this bit is
set, the corresponding I/O pin is configured as output push-pull alternate function.
The PWM signals all have the same frequency
which is controlled by the counter period and the
ARTARR register value.
fPWM = fCOUNTER / (256 - ARTARR)
When a counter overflow occurs, the PWMx pin
level is changed depending on the corresponding
OPx (output polarity) bit in the PWMCR register.
When the counter reaches the value contained in
one of the output compare register (OCRx) the
corresponding PWMx pin level is restored.
It should be noted that the reload values will also
affect the value and the resolution of the duty cycle
of the PWM output signal. To obtain a signal on a
PWMx pin, the contents of the OCRx register must
be greater than the contents of the ARTARR register.
The maximum available resolution for the PWMx
duty cycle is:
Resolution = 1 / (256 - ARTARR)
Note: To get the maximum resolution (1/256), the
ARTARR register must be 0. With this maximum
resolution, 0% and 100% can be obtained by
changing the polarity.
Figure 42. PWM Auto-reload Timer Function
COUNTER
255
DUTY CYCLE
REGISTER
(PWMDCRx)
AUTO-RELOAD
REGISTER
(ARTARR)
PWMx OUTPUT
000
t
WITH OEx=1
AND OPx=0
WITH OEx=1
AND OPx=1
Figure 43. PWM Signal from 0% to 100% Duty Cycle
fCOUNTER
ARTARR=FDh
COUNTER
FDh
FEh
FFh
FDh
FEh
FFh
FDh
FEh
PWMx OUTPUT
WITH OEx=1
AND OPx=0
OCRx=FCh
OCRx=FDh
OCRx=FEh
OCRx=FFh
t
66/262
ST72561
PWM AUTO-RELOAD TIMER (Cont’d)
Output compare and Time base interrupt
On overflow, the OVF flag of the ARTCSR register
is set and an overflow interrupt request is generated if the overflow interrupt enable bit, OIE, in the
ARTCSR register, is set. The OVF flag must be reset by the user software. This interrupt can be
used as a time base in the application.
External clock and event detector mode
Using the fEXT external prescaler input clock, the
auto-reload timer can be used as an external clock
event detector. In this mode, the ARTARR register
is used to select the nEVENT number of events to
be counted before setting the OVF flag.
nEVENT = 256 - ARTARR
Caution: The external clock function is not available in HALT mode. If HALT mode is used in the application, prior to executing the HALT instruction,
the counter must be disabled by clearing the TCE
bit in the ARTCSR register to avoid spurious counter increments.
Figure 44. External Event Detector Example (3 counts)
f EXT=fCOUNTER
ARTARR=FDh
COUNTER
FDh
FEh
FFh
FDh
FEh
FFh
FDh
OVF
ARTCSR READ
ARTCSR READ
INTERRUPT
IF OIE=1
INTERRUPT
IF OIE=1
t
67/262
ST72561
PWM AUTO-RELOAD TIMER (Cont’d)
Input Capture Function
Input Capture mode allows the measurement of
external signal pulse widths through ARTICRx
registers.
Each input capture can generate an interrupt independently on a selected input signal transition.
This event is flagged by a set of the corresponding
CFx bits of the Input Capture Control/Status register (ARTICCSR).
These input capture interrupts are enabled
through the CIEx bits of the ARTICCSR register.
The active transition (falling or rising edge) is software programmable through the CSx bits of the
ARTICCSR register.
The read only input capture registers (ARTICRx)
are used to latch the auto-reload counter value
when a transition is detected on the ARTICx pin
(CFx bit set in ARTICCSR register). After fetching
the interrupt vector, the CFx flags can be read to
identify the interrupt source.
Note: After a capture detection, data transfer in
the ARTICRx register is inhibited until the next
read (clearing the CFx bit).
The timer interrupt remains pending while the CFx
flag is set when the interrupt is enabled (CIEx bit
set). This means, the ARTICRx register has to be
read at each capture event to clear the CFx flag.
The timing resolution is given by auto-reload counter cycle time (1/fCOUNTER).
Note: During HALT mode, input capture is inhibited (the ARTICRx is never re-loaded) and only the
external interrupt capability can be used.
Note: The ARTICx signal is synchronized on CPU
clock. It takes two rising edges until ARTICRx is
latched with the counter value. Depending on the
prescaler value and the time when the ICAP event
occurs, the value loaded in the ARTICRx register
may be different.
If the counter is clocked with the CPU clock, the
value latched in ARTICRx is always the next counter value after the event on ARTICx occurred (Figure 45).
If the counter clock is prescaled, it depends on the
position of the ARTICx event within the counter cycle (Figure 46).
Figure 45. Input Capture Timing Diagram, fcounter = fcpu.
fCPU
fCOUNTER
COUNTER
01h
02h
03h
04h
05h
06h
07h
INTERRUPT
ARTICx PIN
ICAP SAMPLED
CFx FLAG
xxh
05h
ICAP SAMPLED
t
68/262
ST72561
PWM AUTO-RELOAD TIMER (Cont’d)
Figure 46. input Capture Timing Diagram, fCOUNTER = fcpu / 4.
fCPU
fCOUNTER
COUNTER
05h
04h
03h
ARTICx PIN
INTERRUPT
ICAP SAMPLED
CFx FLAG
04h
xxh
ICRx REGISTER
t
fCPU
fCOUNTER
COUNTER
04h
03h
05h
INTERRUPT
ARTICx PIN
ICAP SAMPLED
CFx FLAG
xxh
05h
ICRx REGISTER
t
69/262
ST72561
External Interrupt Capability
This mode allows the Input capture capabilities to
be used as external interrupt sources. The interrupts are generated on the edge of the ARTICx
signal.
The edge sensitivity of the external interrupts is
programmable (CSx bit of ARTICCSR register)
and they are independently enabled through CIEx
bits of the ARTICCSR register. After fetching the
interrupt vector, the CFx flags can be read to identify the interrupt source.
During HALT mode, the external interrupts can be
used to wake up the micro (if the CIEx bit is set). In
this case, the interrupt synchronization is done directly on the ARTICx pin edge (Figure 47).
70/262
Figure 47. ART External Interrupt in HALT
mode
ARTICx PIN
CFx FLAG
INTERRUPT
t
ST72561
PWM AUTO-RELOAD TIMER (Cont’d)
10.3.3 Register Description
0: New transition not yet reached
1: Transition reached
CONTROL / STATUS REGISTER (ARTCSR)
Read /Write
Reset Value: 0000 0000 (00h)
7
EXCL
0
CC2
CC1
CC0
TCE
FCRL
OIE
COUNTER ACCESS REGISTER (ARTCAR)
Read /Write
Reset Value: 0000 0000 (00h)
OVF
7
Bit 7 = EXCL External Clock
This bit is set and cleared by software. It selects the
input clock for the 7-bit prescaler.
0: CPU clock.
1: External clock.
Bit 6:4 = CC[2:0] Counter Clock Control
These bits are set and cleared by software. They
determine the prescaler division ratio from fINPUT.
fCOUNTER
fINPUT
fINPUT / 2
fINPUT / 4
fINPUT / 8
fINPUT / 16
fINPUT / 32
fINPUT / 64
fINPUT / 128
CA7
0
CA6
CA5
CA4
CA3
CA2
CA1
CA0
Bit 7:0 = CA[7:0] Counter Access Data
These bits can be set and cleared either by hardware or by software. The ARTCAR register is used
to read or write the auto-reload counter “on the fly”
(while it is counting).
With fINPUT=8 MHz CC2 CC1 CC0
8 MHz
4 MHz
2 MHz
1 MHz
500 KHz
250 KHz
125 KHz
62.5 KHz
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Bit 3 = TCE Timer Counter Enable
This bit is set and cleared by software. It puts the
timer in the lowest power consumption mode.
0: Counter stopped (prescaler and counter frozen).
1: Counter running.
Bit 2 = FCRL Force Counter Re-Load
This bit is write-only and any attempt to read it will
yield a logical zero. When set, it causes the contents
of ARTARR register to be loaded into the counter,
and the content of the prescaler register to be
cleared in order to initialize the timer before starting
to count.
Bit 1 = OIE Overflow Interrupt Enable
This bit is set and cleared by software. It allows to
enable/disable the interrupt which is generated
when the OVF bit is set.
0: Overflow Interrupt disable.
1: Overflow Interrupt enable.
Bit 0 = OVF Overflow Flag
This bit is set by hardware and cleared by software
reading the ARTCSR register. It indicates the transition of the counter from FFh to the ARTARR value.
AUTO-RELOAD REGISTER (ARTARR)
Read /Write
Reset Value: 0000 0000 (00h)
7
AR7
0
AR6
AR5
AR4
AR3
AR2
AR1
AR0
Bit 7:0 = AR[7:0] Counter Auto-Reload Data
These bits are set and cleared by software. They
are used to hold the auto-reload value which is automatically loaded in the counter when an overflow
occurs. At the same time, the PWM output levels
are changed according to the corresponding OPx
bit in the PWMCR register.
This register has two PWM management functions:
– Adjusting the PWM frequency
– Setting the PWM duty cycle resolution
PWM Frequency vs. Resolution:
ARTARR
value
Resolution
0
[ 0..127 ]
[ 128..191 ]
[ 192..223 ]
[ 224..239 ]
8-bit
> 7-bit
> 6-bit
> 5-bit
> 4-bit
fPWM
Min
Max
~0.244-KHz
~0.244-KHz
~0.488-KHz
~0.977-KHz
~1.953-KHz
31.25-KHz
62.5-KHz
125-KHz
250-KHz
500-KHz
71/262
ST72561
PWM AUTO-RELOAD TIMER (Cont’d)
PWM CONTROL REGISTER (PWMCR)
Read /Write
Reset Value: 0000 0000 (00h)
DUTY CYCLE REGISTERS (PWMDCRx)
Read /Write
Reset Value: 0000 0000 (00h)
7
OE3
OE2
OE1
OE0
OP3
OP2
OP1
0
7
OP0
DC7
Bit 7:4 = OE[3:0] PWM Output Enable
These bits are set and cleared by software. They
enable or disable the PWM output channels independently acting on the corresponding I/O pin.
0: PWM output disabled.
1: PWM output enabled.
Bit 3:0 = OP[3:0] PWM Output Polarity
These bits are set and cleared by software. They
independently select the polarity of the four PWM
output signals.
PWMx output level
OPx
Counter <= OCRx
Counter > OCRx
1
0
0
1
0
1
Note: When an OPx bit is modified, the PWMx output signal polarity is immediately reversed.
72/262
0
DC6
DC5
DC4
DC3
DC2
DC1
DC0
Bit 7:0 = DC[7:0] Duty Cycle Data
These bits are set and cleared by software.
A PWMDCRx register is associated with the OCRx
register of each PWM channel to determine the
second edge location of the PWM signal (the first
edge location is common to all channels and given
by the ARTARR register). These PWMDCR registers allow the duty cycle to be set independently
for each PWM channel.
ST72561
PWM AUTO-RELOAD TIMER (Cont’d)
INPUT CAPTURE
CONTROL / STATUS REGISTER (ARTICCSR)
Read /Write
Reset Value: 0000 0000 (00h)
INPUT CAPTURE REGISTERS (ARTICRx)
Read only
Reset Value: 0000 0000 (00h)
7
7
IC7
0
0
0
0
CS2
CS1
CIE2
CIE1
CF2
IC6
IC5
IC4
IC3
IC2
IC1
IC0
CF1
Bit 7:6 = Reserved, always read as 0.
Bit 5:4 = CS[2:1] Capture Sensitivity
These bits are set and cleared by software. They
determine the trigger event polarity on the corresponding input capture channel.
0: Falling edge triggers capture on channel x.
1: Rising edge triggers capture on channel x.
Bit 7:0 = IC[7:0] Input Capture Data
These read only bits are set and cleared by hardware. An ARTICRx register contains the 8-bit
auto-reload counter value transferred by the input
capture channel x event.
Bit 3:2 = CIE[2:1] Capture Interrupt Enable
These bits are set and cleared by software. They
enable or disable the Input capture channel interrupts independently.
0: Input capture channel x interrupt disabled.
1: Input capture channel x interrupt enabled.
Bit 1:0 = CF[2:1] Capture Flag
These bits are set by hardware and cleared by
software reading the corresponding ARTICRx register. Each CFx bit indicates that an input capture x
has occurred.
0: No input capture on channel x.
1: An input capture has occured on channel x.
73/262
ST72561
PWM AUTO-RELOAD TIMER (Cont’d)
Table 16. PWM Auto-Reload Timer Register Map and Reset Values
Address
(Hex.)
0031h
0032h
0033h
0034h
0035h
0036h
0037h
0038h
0039h
003Ah
003Bh
74/262
Register
Label
PWMDCR3
Reset Value
PWMDCR2
Reset Value
PWMDCR1
Reset Value
PWMDCR0
Reset Value
PWMCR
Reset Value
ARTCSR
Reset Value
ARTCAR
Reset Value
ARTARR
Reset Value
7
6
5
4
3
2
1
0
DC7
0
DC6
0
DC5
0
DC4
0
DC3
0
DC2
0
DC1
0
DC0
0
DC7
0
DC6
0
DC5
0
DC4
0
DC3
0
DC2
0
DC1
0
DC0
0
DC7
0
DC6
0
DC5
0
DC4
0
DC3
0
DC2
0
DC1
0
DC0
0
DC7
0
DC6
0
DC5
0
DC4
0
DC3
0
DC2
0
DC1
0
DC0
0
OE3
0
OE2
0
OE1
0
OE0
0
OP3
0
OP2
0
OP1
0
OP0
0
EXCL
0
CC2
0
CC1
0
CC0
0
TCE
0
FCRL
0
RIE
0
OVF
0
CA7
0
CA6
0
CA5
0
CA4
0
CA3
0
CA2
0
CA1
0
CA0
0
AR7
0
AR6
0
AR5
0
AR4
0
AR3
0
AR2
0
AR1
0
AR0
0
0
0
CE2
0
CE1
0
CS2
0
CS1
0
CF2
0
CF1
0
IC7
0
IC6
0
IC5
0
IC4
0
IC3
0
IC2
0
IC1
0
IC0
0
IC7
0
IC6
0
IC5
0
IC4
0
IC3
0
IC2
0
IC1
0
IC0
0
ARTICCSR
Reset Value
ARTICR1
Reset Value
ARTICR2
Reset Value
ST72561
10.4 16-BIT TIMER
10.4.1 Introduction
The timer consists of a 16-bit free-running counter
driven by a programmable prescaler.
It may be used for a variety of purposes, including
pulse length measurement of up to two input signals (input capture) or generation of up to two output waveforms (output compare and PWM).
Pulse lengths and waveform periods can be modulated from a few microseconds to several milliseconds using the timer prescaler and the CPU
clock prescaler.
Some ST7 devices have two on-chip 16-bit timers.
They are completely independent, and do not
share any resources. They are synchronized after
a MCU reset as long as the timer clock frequencies are not modified.
This description covers one or two 16-bit timers. In
ST7 devices with two timers, register names are
prefixed with TA (Timer A) or TB (Timer B).
10.4.2 Main Features
■ Programmable prescaler: fCPU divided by 2, 4 or 8.
■ Overflow status flag and maskable interrupt
■ External clock input (must be at least 4 times
slower than the CPU clock speed) with the choice
of active edge
■ 1 or 2 Output Compare functions each with:
– 2 dedicated 16-bit registers
– 2 dedicated programmable signals
– 2 dedicated status flags
– 1 dedicated maskable interrupt
■ 1 or 2 Input Capture functions each with:
– 2 dedicated 16-bit registers
– 2 dedicated active edge selection signals
– 2 dedicated status flags
– 1 dedicated maskable interrupt
■ Pulse width modulation mode (PWM)
■ One pulse mode
■ Reduced Power Mode
■ 5 alternate functions on I/O ports (ICAP1, ICAP2,
OCMP1, OCMP2, EXTCLK)*
When reading an input signal on a non-bonded
pin, the value will always be ‘1’.
10.4.3 Functional Description
10.4.3.1 Counter
The main block of the Programmable Timer is a
16-bit free running upcounter and its associated
16-bit registers. The 16-bit registers are made up
of two 8-bit registers called high & low.
Counter Register (CR):
– Counter High Register (CHR) is the most significant byte (MS Byte).
– Counter Low Register (CLR) is the least significant byte (LS Byte).
Alternate Counter Register (ACR)
– Alternate Counter High Register (ACHR) is the
most significant byte (MS Byte).
– Alternate Counter Low Register (ACLR) is the
least significant byte (LS Byte).
These two read-only 16-bit registers contain the
same value but with the difference that reading the
ACLR register does not clear the TOF bit (Timer
overflow flag), located in the Status register, (SR),
(see note at the end of paragraph titled 16-bit read
sequence).
Writing in the CLR register or ACLR register resets
the free running counter to the FFFCh value.
Both counters have a reset value of FFFCh (this is
the only value which is reloaded in the 16-bit timer). The reset value of both counters is also
FFFCh in One Pulse mode and PWM mode.
The timer clock depends on the clock control bits
of the CR2 register, as illustrated in Table 17 Clock
Control Bits. The value in the counter register repeats every 131072, 262144 or 524288 CPU clock
cycles depending on the CC[1:0] bits.
The timer frequency can be fCPU/2, fCPU/4, fCPU/8
or an external frequency.
The Block Diagram is shown in Figure 48.
*Note: Some timer pins may not be available (not
bonded) in some ST7 devices. Refer to the device
pin out description.
75/262
ST72561
16-BIT TIMER (Cont’d)
Figure 48. Timer Block Diagram
ST7 INTERNAL BUS
fCPU
MCU-PERIPHERAL INTERFACE
8 low
8
8
8
low
8
high
8
low
8
high
EXEDG
8
low
high
8
high
8-bit
buffer
low
8 high
16
1/2
1/4
1/8
OUTPUT
COMPARE
REGISTER
2
OUTPUT
COMPARE
REGISTER
1
COUNTER
REGISTER
ALTERNATE
COUNTER
REGISTER
EXTCLK
pin
INPUT
CAPTURE
REGISTER
1
INPUT
CAPTURE
REGISTER
2
16
16
16
CC[1:0]
TIMER INTERNAL BUS
16 16
OVERFLOW
DETECT
CIRCUIT
OUTPUT COMPARE
CIRCUIT
6
ICF1 OCF1 TOF ICF2 OCF2 TIMD
0
EDGE DETECT
CIRCUIT1
ICAP1
pin
EDGE DETECT
CIRCUIT2
ICAP2
pin
LATCH1
OCMP1
pin
LATCH2
OCMP2
pin
0
(Control/Status Register)
CSR
ICIE OCIE TOIE FOLV2 FOLV1 OLVL2 IEDG1 OLVL1
(Control Register 1) CR1
OC1E OC2E OPM PWM
CC1
CC0 IEDG2 EXEDG
(Control Register 2) CR2
(See note)
TIMER INTERRUPT
76/262
Note: If IC, OC and TO interrupt requests have separate vectors
then the last OR is not present (See device Interrupt Vector Table)
ST72561
16-BIT TIMER (Cont’d)
16-bit read sequence: (from either the Counter
Register or the Alternate Counter Register).
Beginning of the sequence
At t0
Read
MS Byte
LS Byte
is buffered
Other
instructions
Read
At t0 +∆t LS Byte
Returns the buffered
LS Byte value at t0
Sequence completed
The user must read the MS Byte first, then the LS
Byte value is buffered automatically.
This buffered value remains unchanged until the
16-bit read sequence is completed, even if the
user reads the MS Byte several times.
After a complete reading sequence, if only the
CLR register or ACLR register are read, they return the LS Byte of the count value at the time of
the read.
Whatever the timer mode used (input capture, output compare, one pulse mode or PWM mode) an
overflow occurs when the counter rolls over from
FFFFh to 0000h then:
– The TOF bit of the SR register is set.
– A timer interrupt is generated if:
– TOIE bit of the CR1 register is set and
– I bit of the CC register is cleared.
If one of these conditions is false, the interrupt remains pending to be issued as soon as they are
both true.
Clearing the overflow interrupt request is done in
two steps:
1. Reading the SR register while the TOF bit is set.
2. An access (read or write) to the CLR register.
Notes: The TOF bit is not cleared by accesses to
ACLR register. The advantage of accessing the
ACLR register rather than the CLR register is that
it allows simultaneous use of the overflow function
and reading the free running counter at random
times (for example, to measure elapsed time) without the risk of clearing the TOF bit erroneously.
The timer is not affected by WAIT mode.
In HALT mode, the counter stops counting until the
mode is exited. Counting then resumes from the
previous count (MCU awakened by an interrupt) or
from the reset count (MCU awakened by a Reset).
10.4.3.2 External Clock
The external clock (where available) is selected if
CC0=1 and CC1=1 in the CR2 register.
The status of the EXEDG bit in the CR2 register
determines the type of level transition on the external clock pin EXTCLK that will trigger the free running counter.
The counter is synchronized with the falling edge
of the internal CPU clock.
A minimum of four falling edges of the CPU clock
must occur between two consecutive active edges
of the external clock; thus the external clock frequency must be less than a quarter of the CPU
clock frequency.
77/262
ST72561
16-BIT TIMER (Cont’d)
Figure 49. Counter Timing Diagram, internal clock divided by 2
CPU CLOCK
INTERNAL RESET
TIMER CLOCK
FFFD FFFE FFFF 0000
COUNTER REGISTER
0001
0002
0003
TIMER OVERFLOW FLAG (TOF)
Figure 50. Counter Timing Diagram, internal clock divided by 4
CPU CLOCK
INTERNAL RESET
TIMER CLOCK
COUNTER REGISTER
FFFC
FFFD
0000
0001
TIMER OVERFLOW FLAG (TOF)
Figure 51. Counter Timing Diagram, internal clock divided by 8
CPU CLOCK
INTERNAL RESET
TIMER CLOCK
COUNTER REGISTER
FFFC
FFFD
0000
TIMER OVERFLOW FLAG (TOF)
Note: The MCU is in reset state when the internal reset signal is high, when it is low the MCU is running.
78/262
ST72561
16-BIT TIMER (Cont’d)
10.4.3.3 Input Capture
In this section, the index, i, may be 1 or 2 because
there are 2 input capture functions in the 16-bit
timer.
The two 16-bit input capture registers (IC1R and
IC2R) are used to latch the value of the free running counter after a transition is detected on the
ICAPi pin (see figure 5).
ICiR
MS Byte
ICiHR
LS Byte
ICiLR
ICiR register is a read-only register.
The active transition is software programmable
through the IEDGi bit of Control Registers (CRi).
Timing resolution is one count of the free running
counter: (fCPU/CC[1:0]).
Procedure:
To use the input capture function select the following in the CR2 register:
– Select the timer clock (CC[1:0]) (see Table 17
Clock Control Bits).
– Select the edge of the active transition on the
ICAP2 pin with the IEDG2 bit (the ICAP2 pin
must be configured as floating input or input with
pull-up without interrupt if this configuration is
available).
And select the following in the CR1 register:
– Set the ICIE bit to generate an interrupt after an
input capture coming from either the ICAP1 pin
or the ICAP2 pin
– Select the edge of the active transition on the
ICAP1 pin with the IEDG1 bit (the ICAP1pin must
be configured as floating input or input with pullup without interrupt if this configuration is available).
When an input capture occurs:
– ICFi bit is set.
– The ICiR register contains the value of the free
running counter on the active transition on the
ICAPi pin (see Figure 53).
– A timer interrupt is generated if the ICIE bit is set
and the I bit is cleared in the CC register. Otherwise, the interrupt remains pending until both
conditions become true.
Clearing the Input Capture interrupt request (i.e.
clearing the ICFi bit) is done in two steps:
1. Reading the SR register while the ICFi bit is set.
2. An access (read or write) to the ICiLR register.
Notes:
1. After reading the ICiHR register, transfer of
input capture data is inhibited and ICFi will
never be set until the ICiLR register is also
read.
2. The ICiR register contains the free running
counter value which corresponds to the most
recent input capture.
3. The 2 input capture functions can be used
together even if the timer also uses the 2 output
compare functions.
4. In One pulse Mode and PWM mode only Input
Capture 2 can be used.
5. The alternate inputs (ICAP1 & ICAP2) are
always directly connected to the timer. So any
transitions on these pins activates the input
capture function.
Moreover if one of the ICAPi pins is configured
as an input and the second one as an output,
an interrupt can be generated if the user toggles the output pin and if the ICIE bit is set.
This can be avoided if the input capture function i is disabled by reading the ICiHR (see note
1).
6. The TOF bit can be used with interrupt generation in order to measure events that go beyond
the timer range (FFFFh).
79/262
ST72561
16-BIT TIMER (Cont’d)
Figure 52. Input Capture Block Diagram
ICAP1
pin
ICAP2
pin
(Control Register 1) CR1
EDGE DETECT
CIRCUIT2
EDGE DETECT
CIRCUIT1
ICIE
IEDG1
(Status Register) SR
IC2R Register
IC1R Register
ICF1
ICF2
0
16-BIT FREE RUNNING
COUNTER
CC1
CC0 IEDG2
Figure 53. Input Capture Timing Diagram
TIMER CLOCK
FF01
FF02
FF03
ICAPi PIN
ICAPi FLAG
ICAPi REGISTER
Note: The rising edge is the active edge.
80/262
0
(Control Register 2) CR2
16-BIT
COUNTER REGISTER
0
FF03
ST72561
16-BIT TIMER (Cont’d)
10.4.3.4 Output Compare
In this section, the index, i, may be 1 or 2 because
there are 2 output compare functions in the 16-bit
timer.
This function can be used to control an output
waveform or indicate when a period of time has
elapsed.
When a match is found between the Output Compare register and the free running counter, the output compare function:
– Assigns pins with a programmable value if the
OCiE bit is set
– Sets a flag in the status register
– Generates an interrupt if enabled
Two 16-bit registers Output Compare Register 1
(OC1R) and Output Compare Register 2 (OC2R)
contain the value to be compared to the counter
register each timer clock cycle.
OCiR
MS Byte
OCiHR
LS Byte
OCiLR
These registers are readable and writable and are
not affected by the timer hardware. A reset event
changes the OCiR value to 8000h.
Timing resolution is one count of the free running
counter: (fCPU/CC[1:0]).
Procedure:
To use the output compare function, select the following in the CR2 register:
– Set the OCiE bit if an output is needed then the
OCMPi pin is dedicated to the output compare i
signal.
– Select the timer clock (CC[1:0]) (see Table 17
Clock Control Bits).
And select the following in the CR1 register:
– Select the OLVLi bit to applied to the OCMPi pins
after the match occurs.
– Set the OCIE bit to generate an interrupt if it is
needed.
When a match is found between OCRi register
and CR register:
– OCFi bit is set.
– The OCMPi pin takes OLVLi bit value (OCMPi
pin latch is forced low during reset).
– A timer interrupt is generated if the OCIE bit is
set in the CR1 register and the I bit is cleared in
the CC register (CC).
The OCiR register value required for a specific timing application can be calculated using the following formula:
∆ OCiR =
∆t * fCPU
PRESC
Where:
∆t
= Output compare period (in seconds)
fCPU
= CPU clock frequency (in hertz)
PRESC = Timer prescaler factor (2, 4 or 8 depending on CC[1:0] bits, see Table 17
Clock Control Bits)
If the timer clock is an external clock, the formula
is:
∆ OCiR = ∆t * fEXT
Where:
∆t
= Output compare period (in seconds)
fEXT
= External timer clock frequency (in hertz)
Clearing the output compare interrupt request (i.e.
clearing the OCFi bit) is done by:
1. Reading the SR register while the OCFi bit is
set.
2. An access (read or write) to the OCiLR register.
The following procedure is recommended to prevent the OCFi bit from being set between the time
it is read and the write to the OCiR register:
– Write to the OCiHR register (further compares
are inhibited).
– Read the SR register (first step of the clearance
of the OCFi bit, which may be already set).
– Write to the OCiLR register (enables the output
compare function and clears the OCFi bit).
81/262
ST72561
16-BIT TIMER (Cont’d)
Notes:
1. After a processor write cycle to the OCiHR register, the output compare function is inhibited
until the OCiLR register is also written.
2. If the OCiE bit is not set, the OCMPi pin is a
general I/O port and the OLVLi bit will not
appear when a match is found but an interrupt
could be generated if the OCIE bit is set.
3. When the timer clock is fCPU/2, OCFi and
OCMPi are set while the counter value equals
the OCiR register value (see Figure 55 on page
83). This behaviour is the same in OPM or
PWM mode.
When the timer clock is fCPU/4, fCPU/8 or in
external clock mode, OCFi and OCMPi are set
while the counter value equals the OCiR register value plus 1 (see Figure 56 on page 83).
4. The output compare functions can be used both
for generating external events on the OCMPi
pins even if the input capture mode is also
used.
5. The value in the 16-bit OCiR register and the
OLVi bit should be changed after each successful comparison in order to control an output
waveform or establish a new elapsed timeout.
Forced Compare Output capability
When the FOLVi bit is set by software, the OLVLi
bit is copied to the OCMPi pin. The OLVi bit has to
be toggled in order to toggle the OCMPi pin when
it is enabled (OCiE bit=1). The OCFi bit is then not
set by hardware, and thus no interrupt request is
generated.
The FOLVLi bits have no effect in both one pulse
mode and PWM mode.
Figure 54. Output Compare Block Diagram
16 BIT FREE RUNNING
COUNTER
OC1E OC2E
CC1
CC0
(Control Register 2) CR2
16-bit
(Control Register 1) CR1
OUTPUT COMPARE
CIRCUIT
16-bit
OCIE
FOLV2 FOLV1 OLVL2
OLVL1
16-bit
Latch
2
OC1R Register
OCF1
OCF2
0
0
0
OC2R Register
(Status Register) SR
82/262
Latch
1
OCMP1
Pin
OCMP2
Pin
ST72561
16-BIT TIMER (Cont’d)
Figure 55. Output Compare Timing Diagram, fTIMER =fCPU/2
INTERNAL CPU CLOCK
TIMER CLOCK
COUNTER REGISTER
2ECF 2ED0
2ED1 2ED2 2ED3 2ED4
OUTPUT COMPARE REGISTER i (OCRi)
2ED3
OUTPUT COMPARE FLAG i (OCFi)
OCMPi PIN (OLVLi=1)
Figure 56. Output Compare Timing Diagram, fTIMER =fCPU/4
INTERNAL CPU CLOCK
TIMER CLOCK
COUNTER REGISTER
OUTPUT COMPARE REGISTER i (OCRi)
2ECF 2ED0
2ED1 2ED2 2ED3 2ED4
2ED3
COMPARE REGISTER i LATCH
OUTPUT COMPARE FLAG i (OCFi)
OCMPi PIN (OLVLi=1)
83/262
ST72561
16-BIT TIMER (Cont’d)
10.4.3.5 One Pulse Mode
One Pulse mode enables the generation of a
pulse when an external event occurs. This mode is
selected via the OPM bit in the CR2 register.
The one pulse mode uses the Input Capture1
function and the Output Compare1 function.
Procedure:
To use one pulse mode:
1. Load the OC1R register with the value corresponding to the length of the pulse (see the formula in the opposite column).
2. Select the following in the CR1 register:
– Using the OLVL1 bit, select the level to be applied to the OCMP1 pin after the pulse.
– Using the OLVL2 bit, select the level to be applied to the OCMP1 pin during the pulse.
– Select the edge of the active transition on the
ICAP1 pin with the IEDG1 bit (the ICAP1 pin
must be configured as floating input).
3. Select the following in the CR2 register:
– Set the OC1E bit, the OCMP1 pin is then dedicated to the Output Compare 1 function.
– Set the OPM bit.
– Select the timer clock CC[1:0] (see Table 17
Clock Control Bits).
One pulse mode cycle
When
event occurs
on ICAP1
ICR1 = Counter
OCMP1 = OLVL2
Counter is reset
to FFFCh
ICF1 bit is set
When
Counter
= OC1R
OCMP1 = OLVL1
Then, on a valid event on the ICAP1 pin, the counter is initialized to FFFCh and OLVL2 bit is loaded
on the OCMP1 pin, the ICF1 bit is set and the value FFFDh is loaded in the IC1R register.
Because the ICF1 bit is set when an active edge
occurs, an interrupt can be generated if the ICIE
bit is set.
84/262
Clearing the Input Capture interrupt request (i.e.
clearing the ICFi bit) is done in two steps:
1. Reading the SR register while the ICFi bit is set.
2. An access (read or write) to the ICiLR register.
The OC1R register value required for a specific
timing application can be calculated using the following formula:
OCiR Value =
t * fCPU
-5
PRESC
Where:
t
= Pulse period (in seconds)
fCPU = CPU clock frequency (in hertz)
PRESC = Timer prescaler factor (2, 4 or 8 depending on the CC[1:0] bits, see Table 17
Clock Control Bits)
If the timer clock is an external clock the formula is:
OCiR = t * fEXT -5
Where:
t
= Pulse period (in seconds)
= External timer clock frequency (in hertz)
fEXT
When the value of the counter is equal to the value
of the contents of the OC1R register, the OLVL1
bit is output on the OCMP1 pin, (See Figure 57).
Notes:
1. The OCF1 bit cannot be set by hardware in one
pulse mode but the OCF2 bit can generate an
Output Compare interrupt.
2. When the Pulse Width Modulation (PWM) and
One Pulse Mode (OPM) bits are both set, the
PWM mode is the only active one.
3. If OLVL1=OLVL2 a continuous signal will be
seen on the OCMP1 pin.
4. The ICAP1 pin can not be used to perform input
capture. The ICAP2 pin can be used to perform
input capture (ICF2 can be set and IC2R can be
loaded) but the user must take care that the
counter is reset each time a valid edge occurs
on the ICAP1 pin and ICF1 can also generates
interrupt if ICIE is set.
5. When one pulse mode is used OC1R is dedicated to this mode. Nevertheless OC2R and
OCF2 can be used to indicate a period of time
has been elapsed but cannot generate an output waveform because the level OLVL2 is dedicated to the one pulse mode.
ST72561
16-BIT TIMER (Cont’d)
Figure 57. One Pulse Mode Timing Example
COUNTER
2ED3
01F8
IC1R
01F8
FFFC FFFD FFFE
2ED0 2ED1 2ED2
FFFC FFFD
2ED3
ICAP1
OLVL2
OCMP1
OLVL1
OLVL2
compare1
Note: IEDG1=1, OC1R=2ED0h, OLVL1=0, OLVL2=1
Figure 58. Pulse Width Modulation Mode Timing Example with 2 Output Compare Functions
COUNTER 34E2 FFFC FFFD FFFE
2ED0 2ED1 2ED2
OLVL2
OCMP1
compare2
OLVL1
compare1
34E2
FFFC
OLVL2
compare2
Note: OC1R=2ED0h, OC2R=34E2, OLVL1=0, OLVL2= 1
Note: On timers with only 1 Output Compare register, a fixed frequency PWM signal can be generated using the output compare and the counter overflow to define the pulse length.
85/262
ST72561
16-BIT TIMER (Cont’d)
10.4.3.6 Pulse Width Modulation Mode
Pulse Width Modulation (PWM) mode enables the
generation of a signal with a frequency and pulse
length determined by the value of the OC1R and
OC2R registers.
Pulse Width Modulation mode uses the complete
Output Compare 1 function plus the OC2R register, and so this functionality can not be used when
PWM mode is activated.
In PWM mode, double buffering is implemented on
the output compare registers. Any new values written in the OC1R and OC2R registers are taken
into account only at the end of the PWM period
(OC2) to avoid spikes on the PWM output pin
(OCMP1).
Procedure
To use pulse width modulation mode:
1. Load the OC2R register with the value corresponding to the period of the signal using the
formula in the opposite column.
2. Load the OC1R register with the value corresponding to the period of the pulse if (OLVL1=0
and OLVL2=1) using the formula in the opposite column.
3. Select the following in the CR1 register:
– Using the OLVL1 bit, select the level to be applied to the OCMP1 pin after a successful
comparison with the OC1R register.
– Using the OLVL2 bit, select the level to be applied to the OCMP1 pin after a successful
comparison with the OC2R register.
4. Select the following in the CR2 register:
– Set OC1E bit: the OCMP1 pin is then dedicated to the output compare 1 function.
– Set the PWM bit.
– Select the timer clock (CC[1:0]) (see Table 17
Clock Control Bits).
Pulse Width Modulation cycle
When
Counter
= OC1R
When
Counter
= OC2R
OCMP1 = OLVL1
OCMP1 = OLVL2
Counter is reset
to FFFCh
ICF1 bit is set
86/262
If OLVL1=1 and OLVL2=0 the length of the positive pulse is the difference between the OC2R and
OC1R registers.
If OLVL1=OLVL2 a continuous signal will be seen
on the OCMP1 pin.
The OCiR register value required for a specific timing application can be calculated using the following formula:
OCiR Value =
t * fCPU
-5
PRESC
Where:
t
= Signal or pulse period (in seconds)
fCPU = CPU clock frequency (in hertz)
PRESC = Timer prescaler factor (2, 4 or 8 depending on CC[1:0] bits, see Table 17 Clock
Control Bits)
If the timer clock is an external clock the formula is:
OCiR = t * fEXT -5
Where:
t
= Signal or pulse period (in seconds)
= External timer clock frequency (in hertz)
fEXT
The Output Compare 2 event causes the counter
to be initialized to FFFCh (See Figure 58)
Notes:
1. After a write instruction to the OCiHR register,
the output compare function is inhibited until the
OCiLR register is also written.
2. The OCF1 and OCF2 bits cannot be set by
hardware in PWM mode therefore the Output
Compare interrupt is inhibited.
3. The ICF1 bit is set by hardware when the counter reaches the OC2R value and can produce a
timer interrupt if the ICIE bit is set and the I bit is
cleared.
4. In PWM mode the ICAP1 pin can not be used
to perform input capture because it is disconnected to the timer. The ICAP2 pin can be used
to perform input capture (ICF2 can be set and
IC2R can be loaded) but the user must take
care that the counter is reset each period and
ICF1 can also generates interrupt if ICIE is set.
5. When the Pulse Width Modulation (PWM) and
One Pulse Mode (OPM) bits are both set, the
PWM mode is the only active one.
ST72561
16-BIT TIMER (Cont’d)
10.4.4 Low Power Modes
Mode
WAIT
HALT
Description
No effect on 16-bit Timer.
Timer interrupts cause the device to exit from WAIT mode.
16-bit Timer registers are frozen.
In HALT mode, the counter stops counting until Halt mode is exited. Counting resumes from the previous
count when the MCU is woken up by an interrupt with “exit from HALT mode” capability or from the counter
reset value when the MCU is woken up by a RESET.
If an input capture event occurs on the ICAPi pin, the input capture detection circuitry is armed. Consequently, when the MCU is woken up by an interrupt with “exit from HALT mode” capability, the ICFi bit is set, and
the counter value present when exiting from HALT mode is captured into the ICiR register.
10.4.5 Interrupts
Event
Flag
Interrupt Event
Input Capture 1 event/Counter reset in PWM mode
Input Capture 2 event
Output Compare 1 event (not available in PWM mode)
Output Compare 2 event (not available in PWM mode)
Timer Overflow event
ICF1
ICF2
OCF1
OCF2
TOF
Enable
Control
Bit
ICIE
OCIE
TOIE
Exit
from
Wait
Yes
Yes
Yes
Yes
Yes
Exit
from
Halt
No
No
No
No
No
Note: The 16-bit Timer interrupt events are connected to the same interrupt vector (see Interrupts chapter). These events generate an interrupt if the corresponding Enable Control Bit is set and the interrupt
mask in the CC register is reset (RIM instruction).
10.4.6 Summary of Timer modes
MODES
Input Capture (1 and/or 2)
Output Compare (1 and/or 2)
One Pulse Mode
PWM Mode
Input Capture 1
Yes
Yes
No
No
TIMER RESOURCES
Input Capture 2
Output Compare 1 Output Compare 2
Yes
Yes
Yes
Yes
Yes
Yes
Not Recommended1)
No
Partially 2)
3)
Not Recommended
No
No
1) See note 4 in Section 10.4.3.5 "One Pulse Mode"
2) See note 5 in Section 10.4.3.5 "One Pulse Mode"
3) See note 4 in Section 10.4.3.6 "Pulse Width Modulation Mode"
87/262
ST72561
16-BIT TIMER (Cont’d)
10.4.7 Register Description
Each Timer is associated with three control and
status registers, and with six pairs of data registers
(16-bit values) relating to the two input captures,
the two output compares, the counter and the alternate counter.
CONTROL REGISTER 1 (CR1)
Read/Write
Reset Value: 0000 0000 (00h)
7
0
Bit 4 = FOLV2 Forced Output Compare 2.
This bit is set and cleared by software.
0: No effect on the OCMP2 pin.
1: Forces the OLVL2 bit to be copied to the
OCMP2 pin, if the OC2E bit is set and even if
there is no successful comparison.
Bit 3 = FOLV1 Forced Output Compare 1.
This bit is set and cleared by software.
0: No effect on the OCMP1 pin.
1: Forces OLVL1 to be copied to the OCMP1 pin, if
the OC1E bit is set and even if there is no successful comparison.
ICIE OCIE TOIE FOLV2 FOLV1 OLVL2 IEDG1 OLVL1
Bit 7 = ICIE Input Capture Interrupt Enable.
0: Interrupt is inhibited.
1: A timer interrupt is generated whenever the
ICF1 or ICF2 bit of the SR register is set.
Bit 6 = OCIE Output Compare Interrupt Enable.
0: Interrupt is inhibited.
1: A timer interrupt is generated whenever the
OCF1 or OCF2 bit of the SR register is set.
Bit 5 = TOIE Timer Overflow Interrupt Enable.
0: Interrupt is inhibited.
1: A timer interrupt is enabled whenever the TOF
bit of the SR register is set.
88/262
Bit 2 = OLVL2 Output Level 2.
This bit is copied to the OCMP2 pin whenever a
successful comparison occurs with the OC2R register and OCxE is set in the CR2 register. This value is copied to the OCMP1 pin in One Pulse Mode
and Pulse Width Modulation mode.
Bit 1 = IEDG1 Input Edge 1.
This bit determines which type of level transition
on the ICAP1 pin will trigger the capture.
0: A falling edge triggers the capture.
1: A rising edge triggers the capture.
Bit 0 = OLVL1 Output Level 1.
The OLVL1 bit is copied to the OCMP1 pin whenever a successful comparison occurs with the
OC1R register and the OC1E bit is set in the CR2
register.
ST72561
16-BIT TIMER (Cont’d)
CONTROL REGISTER 2 (CR2)
Read/Write
Reset Value: 0000 0000 (00h)
7
0
OC1E OC2E OPM PWM CC1 CC0 IEDG2 EXEDG
Bit 7 = OC1E Output Compare 1 Pin Enable.
This bit is used only to output the signal from the
timer on the OCMP1 pin (OLV1 in Output Compare mode, both OLV1 and OLV2 in PWM and
one-pulse mode). Whatever the value of the OC1E
bit, the Output Compare 1 function of the timer remains active.
0: OCMP1 pin alternate function disabled (I/O pin
free for general-purpose I/O).
1: OCMP1 pin alternate function enabled.
Bit 6 = OC2E Output Compare 2 Pin Enable.
This bit is used only to output the signal from the
timer on the OCMP2 pin (OLV2 in Output Compare mode). Whatever the value of the OC2E bit,
the Output Compare 2 function of the timer remains active.
0: OCMP2 pin alternate function disabled (I/O pin
free for general-purpose I/O).
1: OCMP2 pin alternate function enabled.
Bit 5 = OPM One Pulse Mode.
0: One Pulse Mode is not active.
1: One Pulse Mode is active, the ICAP1 pin can be
used to trigger one pulse on the OCMP1 pin; the
active transition is given by the IEDG1 bit. The
length of the generated pulse depends on the
contents of the OC1R register.
Bit 4 = PWM Pulse Width Modulation.
0: PWM mode is not active.
1: PWM mode is active, the OCMP1 pin outputs a
programmable cyclic signal; the length of the
pulse depends on the value of OC1R register;
the period depends on the value of OC2R register.
Bit 3, 2 = CC[1:0] Clock Control.
The timer clock mode depends on these bits:
Table 17. Clock Control Bits
Timer Clock
fCPU / 4
fCPU / 2
fCPU / 8
External Clock (where
available)
CC1
0
0
1
CC0
0
1
0
1
1
Note: If the external clock pin is not available, programming the external clock configuration stops
the counter.
Bit 1 = IEDG2 Input Edge 2.
This bit determines which type of level transition
on the ICAP2 pin will trigger the capture.
0: A falling edge triggers the capture.
1: A rising edge triggers the capture.
Bit 0 = EXEDG External Clock Edge.
This bit determines which type of level transition
on the external clock pin EXTCLK will trigger the
counter register.
0: A falling edge triggers the counter register.
1: A rising edge triggers the counter register.
89/262
ST72561
16-BIT TIMER (Cont’d)
CONTROL/STATUS REGISTER (CSR)
Read/Write (bits 7:3 read only)
Reset Value: xxxx x0xx (xxh)
Note: Reading or writing the ACLR register does
not clear TOF.
7
ICF1
0
OCF1
TOF
ICF2
OCF2 TIMD
0
0
Bit 7 = ICF1 Input Capture Flag 1.
0: No input capture (reset value).
1: An input capture has occurred on the ICAP1 pin
or the counter has reached the OC2R value in
PWM mode. To clear this bit, first read the SR
register, then read or write the low byte of the
IC1R (IC1LR) register.
Bit 6 = OCF1 Output Compare Flag 1.
0: No match (reset value).
1: The content of the free running counter has
matched the content of the OC1R register. To
clear this bit, first read the SR register, then read
or write the low byte of the OC1R (OC1LR) register.
Bit 5 = TOF Timer Overflow Flag.
0: No timer overflow (reset value).
1: The free running counter rolled over from FFFFh
to 0000h. To clear this bit, first read the SR register, then read or write the low byte of the CR
(CLR) register.
90/262
Bit 4 = ICF2 Input Capture Flag 2.
0: No input capture (reset value).
1: An input capture has occurred on the ICAP2
pin. To clear this bit, first read the SR register,
then read or write the low byte of the IC2R
(IC2LR) register.
Bit 3 = OCF2 Output Compare Flag 2.
0: No match (reset value).
1: The content of the free running counter has
matched the content of the OC2R register. To
clear this bit, first read the SR register, then read
or write the low byte of the OC2R (OC2LR) register.
Bit 2 = TIMD Timer disable.
This bit is set and cleared by software. When set, it
freezes the timer prescaler and counter and disabled the output functions (OCMP1 and OCMP2
pins) to reduce power consumption. Access to the
timer registers is still available, allowing the timer
configuration to be changed, or the counter reset,
while it is disabled.
0: Timer enabled
1: Timer prescaler, counter and outputs disabled
Bits 1:0 = Reserved, must be kept cleared.
ST72561
16-BIT TIMER (Cont’d)
INPUT CAPTURE 1 HIGH REGISTER (IC1HR)
Read Only
Reset Value: Undefined
This is an 8-bit read only register that contains the
high part of the counter value (transferred by the
input capture 1 event).
OUTPUT COMPARE 1 HIGH REGISTER
(OC1HR)
Read/Write
Reset Value: 1000 0000 (80h)
This is an 8-bit register that contains the high part
of the value to be compared to the CHR register.
7
0
7
0
MSB
LSB
MSB
LSB
INPUT CAPTURE 1 LOW REGISTER (IC1LR)
Read Only
Reset Value: Undefined
This is an 8-bit read only register that contains the
low part of the counter value (transferred by the input capture 1 event).
OUTPUT COMPARE 1 LOW REGISTER
(OC1LR)
Read/Write
Reset Value: 0000 0000 (00h)
This is an 8-bit register that contains the low part of
the value to be compared to the CLR register.
7
0
7
0
MSB
LSB
MSB
LSB
91/262
ST72561
16-BIT TIMER (Cont’d)
OUTPUT COMPARE 2 HIGH REGISTER
(OC2HR)
Read/Write
Reset Value: 1000 0000 (80h)
This is an 8-bit register that contains the high part
of the value to be compared to the CHR register.
ALTERNATE COUNTER HIGH REGISTER
(ACHR)
Read Only
Reset Value: 1111 1111 (FFh)
This is an 8-bit register that contains the high part
of the counter value.
7
0
7
0
MSB
LSB
MSB
LSB
OUTPUT COMPARE 2 LOW REGISTER
(OC2LR)
Read/Write
Reset Value: 0000 0000 (00h)
This is an 8-bit register that contains the low part of
the value to be compared to the CLR register.
7
0
MSB
LSB
COUNTER HIGH REGISTER (CHR)
Read Only
Reset Value: 1111 1111 (FFh)
This is an 8-bit register that contains the high part
of the counter value.
7
0
MSB
LSB
COUNTER LOW REGISTER (CLR)
Read Only
Reset Value: 1111 1100 (FCh)
This is an 8-bit register that contains the low part of
the counter value. A write to this register resets the
counter. An access to this register after accessing
the CSR register clears the TOF bit.
7
0
MSB
LSB
92/262
ALTERNATE COUNTER LOW REGISTER
(ACLR)
Read Only
Reset Value: 1111 1100 (FCh)
This is an 8-bit register that contains the low part of
the counter value. A write to this register resets the
counter. An access to this register after an access
to CSR register does not clear the TOF bit in the
CSR register.
7
0
MSB
LSB
INPUT CAPTURE 2 HIGH REGISTER (IC2HR)
Read Only
Reset Value: Undefined
This is an 8-bit read only register that contains the
high part of the counter value (transferred by the
Input Capture 2 event).
7
0
MSB
LSB
INPUT CAPTURE 2 LOW REGISTER (IC2LR)
Read Only
Reset Value: Undefined
This is an 8-bit read only register that contains the
low part of the counter value (transferred by the Input Capture 2 event).
7
0
MSB
LSB
ST72561
16-BIT TIMER (Cont’d)
Table 18. 16-Bit Timer Register Map
Address
(Hex.)
Register
Name
7
6
5
4
3
2
1
0
51
CR2
OC1E
OC2E
OPM
PWM
CC1
CC0
IEDG2
EXEDG
52
CR1
ICIE
OCIE
TOIE
FOLV2
FOLV1
OLVL2
IEDG1
OLVL1
53
CSR
ICF1
OCF1
TOF
ICF2
OCF2
TIMD
54
IC1HR
MSB
LSB
55
IC1LR
MSB
LSB
56
OC1HR
MSB
LSB
57
OC1LR
MSB
LSB
58
CHR
MSB
LSB
59
CLR
MSB
LSB
5A
ACHR
MSB
LSB
5B
ACLR
MSB
LSB
5C
IC2HR
MSB
LSB
5D
IC2LR
MSB
LSB
5E
OC2HR
MSB
LSB
5F
OC2LR
MSB
LSB
93/262
ST72561
10.5 8-BIT TIMER (TIM8)
10.5.1 Introduction
The timer consists of a 8-bit free-running counter
driven by a programmable prescaler.
It may be used for a variety of purposes, including
pulse length measurement of up to two input signals (input capture) or generation of up to two output waveforms (output compare and PWM).
Pulse lengths and waveform periods can be modulated from a few microseconds to several milliseconds using the timer prescaler and the clock
prescaler.
10.5.2 Main Features
■ Programmable prescaler: fCPU divided by 2, 4 , 8
or fOSC2 divided by 8000.
■ Overflow status flag and maskable interrupt
■ Output compare functions with
– 2 dedicated 8-bit registers
– 2 dedicated programmable signals
– 2 dedicated status flags
– 1 dedicated maskable interrupt
■ Input capture functions with
– 2 dedicated 8-bit registers
– 2 dedicated active edge selection signals
– 2 dedicated status flags
– 1 dedicated maskable interrupt
■ Pulse width modulation mode (PWM)
■ One pulse mode
■ Reduced Power Mode
■ 4 alternate functions on I/O ports (ICAP1, ICAP2,
OCMP1, OCMP2)*
The Block Diagram is shown in Figure 59.
*Note: Some timer pins may not be available (not
bonded) in some ST7 devices. Refer to the device
pin out description.
94/262
When reading an input signal on a non-bonded
pin, the value will always be ‘1’.
10.5.3 Functional Description
10.5.3.1 Counter
The main block of the Programmable Timer is a 8bit free running upcounter and its associated 8-bit
registers.
These two read-only 8-bit registers contain the
same value but with the difference that reading the
ACTR register does not clear the TOF bit (Timer
overflow flag), located in the Status register, (SR).
Writing in the CTR register or ACTR register resets the free running counter to the FCh value.
Both counters have a reset value of FCh (this is
the only value which is reloaded in the 8-bit timer).
The reset value of both counters is also FCh in
One Pulse mode and PWM mode.
The timer clock depends on the clock control bits
of the CR2 register, as shown in Table 19 Clock
Control Bits. The value in the counter register repeats every 512, 1024, 2048 or 20480000 fCPU
clock cycles depending on the CC[1:0] bits.
The timer frequency can be fCPU/2, fCPU/4, fCPU/8
or fOSC2 /8000.
For example, if fOSC2/8000 is selected, and
fOSC2=8 MHz, the timer frequency will be 1 ms.
Refer to Table 19 on page 108.
ST72561
8-BIT TIMER (Cont’d)
Figure 59. Timer Block Diagram
ST7 INTERNAL BUS
fCPU
MCU-PERIPHERAL INTERFACE
8
8
1/2
1/4
1/8
fOSC2
OUTPUT
COMPARE
REGISTER
2
OUTPUT
COMPARE
REGISTER
1
COUNTER
REGISTER
1/8000
8
ALTERNATE
COUNTER
REGISTER
8
8
INPUT
CAPTURE
REGISTER
1
INPUT
CAPTURE
REGISTER
2
8
8
8
CC[1:0]
TIMER INTERNAL BUS
8
8
OVERFLOW
DETECT
CIRCUIT
OUTPUT COMPARE
CIRCUIT
6
ICF1 OCF1 TOF ICF2 OCF2 TIMD
0
EDGE DETECT
CIRCUIT1
ICAP1
pin
EDGE DETECT
CIRCUIT2
ICAP2
pin
LATCH1
OCMP1
pin
LATCH2
OCMP2
pin
0
(Control/Status Register)
CSR
ICIE OCIE TOIE FOLV2 FOLV1 OLVL2 IEDG1 OLVL1
(Control Register 1) CR1
OC1E OC2E OPM PWM
CC1
CC0 IEDG2
0
(Control Register 2) CR2
(See note)
TIMER INTERRUPT
Note: If IC, OC and TO interrupt requests have separate vectors
then the last OR is not present (See device Interrupt Vector Table)
95/262
ST72561
8-BIT TIMER (Cont’d)
Whatever the timer mode used (input capture, output compare, one pulse mode or PWM mode) an
overflow occurs when the counter rolls over from
FFh to 00h then:
– The TOF bit of the SR register is set.
– A timer interrupt is generated if:
– TOIE bit of the CR1 register is set and
– I bit of the CC register is cleared.
If one of these conditions is false, the interrupt remains pending to be issued as soon as they are
both true.
Clearing the overflow interrupt request is done in
two steps:
1. Reading the SR register while the TOF bit is set.
2. An access (read or write) to the CTR register.
96/262
Notes: The TOF bit is not cleared by accesses to
ACTR register. The advantage of accessing the
ACTR register rather than the CTR register is that
it allows simultaneous use of the overflow function
and reading the free running counter at random
times (for example, to measure elapsed time) without the risk of clearing the TOF bit erroneously.
The timer is not affected by WAIT mode.
In HALT mode, the counter stops counting until the
mode is exited. Counting then resumes from the
previous count (MCU awakened by an interrupt) or
from the reset count (MCU awakened by a Reset).
ST72561
8-BIT TIMER (Cont’d)
Figure 60. Counter Timing Diagram, internal clock divided by 2
fCPU CLOCK
INTERNAL RESET
TIMER CLOCK
FD
COUNTER REGISTER
FE
FF
00
01
02
03
TIMER OVERFLOW FLAG (TOF)
Figure 61. Counter Timing Diagram, internal clock divided by 4
fCPU CLOCK
INTERNAL RESET
TIMER CLOCK
COUNTER REGISTER
FC
FD
00
01
TIMER OVERFLOW FLAG (TOF)
Figure 62. Counter Timing Diagram, internal clock divided by 8
fCPU CLOCK
INTERNAL RESET
TIMER CLOCK
COUNTER REGISTER
FC
FD
00
TIMER OVERFLOW FLAG (TOF)
Note: The MCU is in reset state when the internal reset signal is high, when it is low the MCU is running.
97/262
ST72561
8-BIT TIMER (Cont’d)
10.5.3.2 Input Capture
In this section, the index, i, may be 1 or 2 because
there are 2 input capture functions in the 8-bit timer.
The two 8-bit input capture registers (IC1R and
IC2R) are used to latch the value of the free running counter after a transition is detected on the
ICAPi pin (see figure 5).
ICiR register is a read-only register.
The active transition is software programmable
through the IEDGi bit of Control Registers (CRi).
Timing resolution is one count of the free running
counter (see Table 19 Clock Control Bits).
Procedure:
To use the input capture function select the following in the CR2 register:
– Select the timer clock (CC[1:0]) (see Table 19
Clock Control Bits).
– Select the edge of the active transition on the
ICAP2 pin with the IEDG2 bit (the ICAP2 pin
must be configured as floating input or input with
pull-up without interrupt if this configuration is
available).
And select the following in the CR1 register:
– Set the ICIE bit to generate an interrupt after an
input capture coming from either the ICAP1 pin
or the ICAP2 pin
– Select the edge of the active transition on the
ICAP1 pin with the IEDG1 bit (the ICAP1 pin
must be configured as floating input or input with
pull-up without interrupt if this configuration is
available).
98/262
When an input capture occurs:
– ICFi bit is set.
– The ICiR register contains the value of the free
running counter on the active transition on the
ICAPi pin (see Figure 64).
– A timer interrupt is generated if the ICIE bit is set
and the interrrupt mask is cleared in the CC register. Otherwise, the interrupt remains pending
until both conditions become true.
Clearing the Input Capture interrupt request (i.e.
clearing the ICFi bit) is done in two steps:
1. Reading the SR register while the ICFi bit is set.
2. An access (read or write) to the ICiR register.
Notes:
6. The ICiR register contains the free running
counter value which corresponds to the most
recent input capture.
7. The 2 input capture functions can be used
together even if the timer also uses the 2 output
compare functions.
8. Once the ICIE bit is set both input capture features may trigger interrupt requests. If only one
is needed in the application, the interrupt routine software needs to discard the unwanted
capture interrupt. This can be done by checking
the ICF1 and ICF2 flags and resetting them
both.
9. In One pulse Mode and PWM mode only Input
Capture 2 can be used.
10.The alternate inputs (ICAP1 & ICAP2) are
always directly connected to the timer. So any
transitions on these pins activates the input
capture function.
Moreover if one of the ICAPi pins is configured
as an input and the second one as an output,
an interrupt can be generated if the user toggles the output pin and if the ICIE bit is set.
11.The TOF bit can be used with interrupt generation in order to measure events that go beyond
the timer range (FFh).
ST72561
8-BIT TIMER (Cont’d)
Figure 63. Input Capture Block Diagram
ICAP1
pin
ICAP2
pin
(Control Register 1) CR1
EDGE DETECT
CIRCUIT2
EDGE DETECT
CIRCUIT1
ICIE
IEDG1
(Status Register) SR
IC2R Register
IC1R Register
ICF1
ICF2
0
0
(Control Register 2) CR2
8-bit
8-bit
0
FREE RUNNING
COUNTER
CC1
CC0 IEDG2
Figure 64. Input Capture Timing Diagram
TIMER CLOCK
COUNTER REGISTER
01
02
03
ICAPi PIN
ICAPi FLAG
ICAPi REGISTER
03
Note: The rising edge is the active edge.
99/262
ST72561
8-BIT TIMER (Cont’d)
10.5.3.3 Output Compare
In this section, the index, i, may be 1 or 2 because
there are 2 output compare functions in the 8-bit
timer.
This function can be used to control an output
waveform or indicate when a period of time has
elapsed.
When a match is found between the Output Compare register and the free running counter, the output compare function:
– Assigns pins with a programmable value if the
OCiE bit is set
– Sets a flag in the status register
– Generates an interrupt if enabled
Two 8-bit registers Output Compare Register 1
(OC1R) and Output Compare Register 2 (OC2R)
contain the value to be compared to the counter
register each timer clock cycle.
These registers are readable and writable and are
not affected by the timer hardware. A reset event
changes the OCiR value to 00h.
Timing resolution is one count of the free running
counter: (fCPU/CC[1:0]).
Procedure:
To use the output compare function, select the following in the CR2 register:
– Set the OCiE bit if an output is needed then the
OCMPi pin is dedicated to the output compare i
signal.
– Select the timer clock (CC[1:0]) (see Table 19
Clock Control Bits).
And select the following in the CR1 register:
100/262
– Select the OLVLi bit to applied to the OCMPi pins
after the match occurs.
– Set the OCIE bit to generate an interrupt if it is
needed.
When a match is found between OCRi register
and CR register:
– OCFi bit is set.
– The OCMPi pin takes OLVLi bit value (OCMPi
pin latch is forced low during reset).
– A timer interrupt is generated if the OCIE bit is
set in the CR1 register and the I bit is cleared in
the CC register (CC).
The OCiR register value required for a specific timing application can be calculated using the following formula:
∆ OCiR =
∆t * fCPU
PRESC
Where:
∆t
= Output compare period (in seconds)
fCPU
= PLL output x2 clock frequency in hertz
(or fOSC/2 if PLL is not enabled)
=
Timer prescaler factor (2, 4, 8 or 8000
PRESC
depending on CC[1:0] bits, see Table
19 Clock Control Bits)
Clearing the output compare interrupt request (i.e.
clearing the OCFi bit) is done by:
1. Reading the SR register while the OCFi bit is
set.
2. An access (read or write) to the OCiR register.
ST72561
8-BIT TIMER (Cont’d)
Notes:
1. Once the OCIE bit is set both output compare
features may trigger interrupt requests. If only
one is needed in the application, the interrupt
routine software needs to discard the unwanted
compare interrupt. This can be done by checking the OCF1 and OCF2 flags and resetting
them both.
2. If the OCiE bit is not set, the OCMPi pin is a
general I/O port and the OLVLi bit will not
appear when a match is found but an interrupt
could be generated if the OCIE bit is set.
3. When the timer clock is fCPU/2, OCFi and
OCMPi are set while the counter value equals
the OCiR register value (see Figure 66 on page
102). This behaviour is the same in OPM or
PWM mode.
When the timer clock is fCPU/4, fCPU/8 or fCPU/
8000, OCFi and OCMPi are set while the counter value equals the OCiR register value plus 1
(see Figure 67 on page 102).
4. The output compare functions can be used both
for generating external events on the OCMPi
pins even if the input capture mode is also
used.
5. The value in the 8-bit OCiR register and the
OLVi bit should be changed after each suc-
cessful comparison in order to control an output
waveform or establish a new elapsed timeout.
Forced Compare Output capability
When the FOLVi bit is set by software, the OLVLi
bit is copied to the OCMPi pin. The OLVi bit has to
be toggled in order to toggle the OCMPi pin when
it is enabled (OCiE bit=1). The OCFi bit is then not
set by hardware, and thus no interrupt request is
generated.
The FOLVLi bits have no effect in both one pulse
mode and PWM mode.
Figure 65. Output Compare Block Diagram
8 BIT
FREE RUNNING
COUNTER
OC1E OC2E
CC1
CC0
(Control Register 2) CR2
8-bit
(Control Register 1) CR1
OUTPUT COMPARE
CIRCUIT
8-bit
OCIE
FOLV2 FOLV1 OLVL2
OLVL1
8-bit
Latch
1
Latch
2
OC1R Register
OCF1
OCF2
0
0
OCMP1
Pin
OCMP2
Pin
0
OC2R Register
(Status Register) SR
101/262
ST72561
8-BIT TIMER (Cont’d)
Figure 66. Output Compare Timing Diagram, fTIMER =fCPU/2
fCPU CLOCK
TIMER CLOCK
COUNTER REGISTER
CF
D0
D1
OUTPUT COMPARE REGISTER i (OCRi)
D2
D3
D4
D2
D3
D4
D3
OUTPUT COMPARE FLAG i (OCFi)
OCMPi PIN (OLVLi=1)
Figure 67. Output Compare Timing Diagram, fTIMER =fCPU/4
fCPU CLOCK
TIMER CLOCK
COUNTER REGISTER
OUTPUT COMPARE REGISTER i (OCRi)
COMPARE REGISTER i LATCH
OUTPUT COMPARE FLAG i (OCFi)
OCMPi PIN (OLVLi=1)
102/262
CF
D0
D1
D3
ST72561
8-BIT TIMER (Cont’d)
10.5.3.4 One Pulse Mode
One Pulse mode enables the generation of a
pulse when an external event occurs. This mode is
selected via the OPM bit in the CR2 register.
The one pulse mode uses the Input Capture1
function and the Output Compare1 function.
Procedure:
To use one pulse mode:
1. Load the OC1R register with the value corresponding to the length of the pulse (see the formula in the opposite column).
2. Select the following in the CR1 register:
– Using the OLVL1 bit, select the level to be applied to the OCMP1 pin after the pulse.
– Using the OLVL2 bit, select the level to be applied to the OCMP1 pin during the pulse.
– Select the edge of the active transition on the
ICAP1 pin with the IEDG1 bit (the ICAP1 pin
must be configured as floating input).
3. Select the following in the CR2 register:
– Set the OC1E bit, the OCMP1 pin is then dedicated to the Output Compare 1 function.
– Set the OPM bit.
– Select the timer clock CC[1:0] (see Table 19
Clock Control Bits).
One pulse mode cycle
When
event occurs
on ICAP1
ICR1 = Counter
OCMP1 = OLVL2
Counter is reset
to FCh
ICF1 bit is set
When
Counter
= OC1R
OCMP1 = OLVL1
Then, on a valid event on the ICAP1 pin, the counter is initialized to FCh and OLVL2 bit is loaded on
the OCMP1 pin, the ICF1 bit is set and the value
FFFDh is loaded in the IC1R register.
Because the ICF1 bit is set when an active edge
occurs, an interrupt can be generated if the ICIE
bit is set.
Clearing the Input Capture interrupt request (i.e.
clearing the ICFi bit) is done in two steps:
1. Reading the SR register while the ICFi bit is set.
2. An access (read or write) to the ICiLR register.
The OC1R register value required for a specific
timing application can be calculated using the following formula:
t * fCPU - 5
OCiR Value =
PRESC
Where:
t
= Pulse period (in seconds)
fCPU = PLL output x2 clock frequency in hertz
(or fOSC/2 if PLL is not enabled)
PRESC = Timer prescaler factor (2, 4, 8 or 8000
depending on the CC[1:0] bits, see Table 19 Clock Control Bits)
When the value of the counter is equal to the value
of the contents of the OC1R register, the OLVL1
bit is output on the OCMP1 pin, (See Figure 68).
Notes:
1. The OCF1 bit cannot be set by hardware in one
pulse mode but the OCF2 bit can generate an
Output Compare interrupt.
2. When the Pulse Width Modulation (PWM) and
One Pulse Mode (OPM) bits are both set, the
PWM mode is the only active one.
3. If OLVL1=OLVL2 a continuous signal will be
seen on the OCMP1 pin.
4. The ICAP1 pin can not be used to perform input
capture. The ICAP2 pin can be used to perform
input capture (ICF2 can be set and IC2R can be
loaded) but the user must take care that the
counter is reset each time a valid edge occurs
on the ICAP1 pin and ICF1 can also generates
interrupt if ICIE is set.
5. When one pulse mode is used OC1R is dedicated to this mode. Nevertheless OC2R and
OCF2 can be used to indicate a period of time
has been elapsed but cannot generate an output waveform because the level OLVL2 is dedicated to the one pulse mode.
103/262
ST72561
8-BIT TIMER (Cont’d)
Figure 68. One Pulse Mode Timing Example
D3
F8
IC1R
FC
F8
COUNTER
FD
FE
D0
D1
D2
FC
FD
D3
ICAP1
OLVL2
OCMP1
OLVL1
OLVL2
compare1
Note: IEDG1=1, OC1R=D0h, OLVL1=0, OLVL2=1
Figure 69. Pulse Width Modulation Mode Timing Example
COUNTER E2
FC
FD
FE
D1
OLVL2
OCMP1
compare2
Note: OC1R=D0h, OC2R=E2, OLVL1=0, OLVL2= 1
104/262
D0
D2
OLVL1
compare1
E2
FC
OLVL2
compare2
ST72561
8-BIT TIMER (Cont’d)
10.5.3.5 Pulse Width Modulation Mode
Pulse Width Modulation (PWM) mode enables the
generation of a signal with a frequency and pulse
length determined by the value of the OC1R and
OC2R registers.
Pulse Width Modulation mode uses the complete
Output Compare 1 function plus the OC2R register, and so this functionality can not be used when
PWM mode is activated.
In PWM mode, double buffering is implemented on
the output compare registers. Any new values written in the OC1R and OC2R registers are taken
into account only at the end of the PWM period
(OC2) to avoid spikes on the PWM output pin
(OCMP1).
Procedure
To use pulse width modulation mode:
1. Load the OC2R register with the value corresponding to the period of the signal using the
formula in the opposite column.
2. Load the OC1R register with the value corresponding to the period of the pulse if (OLVL1=0
and OLVL2=1) using the formula in the opposite column.
3. Select the following in the CR1 register:
– Using the OLVL1 bit, select the level to be applied to the OCMP1 pin after a successful
comparison with the OC1R register.
– Using the OLVL2 bit, select the level to be applied to the OCMP1 pin after a successful
comparison with the OC2R register.
4. Select the following in the CR2 register:
– Set OC1E bit: the OCMP1 pin is then dedicated to the output compare 1 function.
– Set the PWM bit.
– Select the timer clock (CC[1:0]) (see Table 19
Clock Control Bits).
Pulse Width Modulation cycle
When
Counter
= OC1R
When
Counter
= OC2R
If OLVL1=1 and OLVL2=0 the length of the positive pulse is the difference between the OC2R and
OC1R registers.
If OLVL1=OLVL2 a continuous signal will be seen
on the OCMP1 pin.
The OCiR register value required for a specific timing application can be calculated using the following formula:
t * fCPU - 5
OCiR Value =
PRESC
Where:
t
= Signal or pulse period (in seconds)
fCPU = PLL output x2 clock frequency in hertz
(or fOSC/2 if PLL is not enabled)
PRESC = Timer prescaler factor (2, 4, 8 or 8000
depending on CC[1:0] bits, see Table
19 Clock Control Bits)
The Output Compare 2 event causes the counter
to be initialized to FCh (See Figure 69)
Notes:
1. The OCF1 and OCF2 bits cannot be set by
hardware in PWM mode therefore the Output
Compare interrupt is inhibited.
2. The ICF1 bit is set by hardware when the counter reaches the OC2R value and can produce a
timer interrupt if the ICIE bit is set and the I bit is
cleared.
3. In PWM mode the ICAP1 pin can not be used
to perform input capture because it is disconnected to the timer. The ICAP2 pin can be used
to perform input capture (ICF2 can be set and
IC2R can be loaded) but the user must take
care that the counter is reset each period and
ICF1 can also generates interrupt if ICIE is set.
4. When the Pulse Width Modulation (PWM) and
One Pulse Mode (OPM) bits are both set, the
PWM mode is the only active one.
OCMP1 = OLVL1
OCMP1 = OLVL2
Counter is reset
to FCh
ICF1 bit is set
105/262
ST72561
8-BIT TIMER (Cont’d)
10.5.4 Low Power Modes
Mode
WAIT
HALT
Description
No effect on 8-bit Timer.
Timer interrupts cause the device to exit from WAIT mode.
8-bit Timer registers are frozen.
In HALT mode, the counter stops counting until Halt mode is exited. Counting resumes from the previous
count when the MCU is woken up by an interrupt with “exit from HALT mode” capability or from the counter
reset value when the MCU is woken up by a RESET.
If an input capture event occurs on the ICAPi pin, the input capture detection circuitry is armed. Consequently, when the MCU is woken up by an interrupt with “exit from HALT mode” capability, the ICFi bit is set, and
the counter value present when exiting from HALT mode is captured into the ICiR register.
10.5.5 Interrupts
Event
Flag
Interrupt Event
Input Capture 1 event/Counter reset in PWM mode
Input Capture 2 event
Output Compare 1 event (not available in PWM mode)
Output Compare 2 event (not available in PWM mode)
Timer Overflow event
ICF1
ICF2
OCF1
OCF2
TOF
Enable
Control
Bit
ICIE
OCIE
TOIE
Exit
from
Wait
Yes
Yes
Yes
Yes
Yes
Exit
from
Halt
No
No
No
No
No
Note: The 8-bit Timer interrupt events are connected to the same interrupt vector (see Interrupts chapter).
These events generate an interrupt if the corresponding Enable Control Bit is set and the interrupt mask
in the CC register is reset (RIM instruction).
10.5.6 Summary of Timer modes
MODES
Input Capture (1 and/or 2)
Output Compare (1 and/or 2)
One Pulse Mode
PWM Mode
Input Capture 1
Yes
Yes
No
No
AVAILABLE RESOURCES
Input Capture 2
Output Compare 1 Output Compare 2
Yes
Yes
Yes
Yes
Yes
Yes
Not Recommended1)
No
Partially 2)
3)
Not Recommended
No
No
1) See note 4 in “One Pulse Mode” on page 103
2) See note 5 in “One Pulse Mode” on page 103
3) See note 4 in “Pulse Width Modulation Mode” on page 105
106/262
ST72561
8-BIT TIMER (Cont’d)
10.5.7 Register Description
Each Timer is associated with three control and
status registers, and with six data registers (8-bit
values) relating to the two input captures, the two
output compares, the counter and the alternate
counter.
CONTROL REGISTER 1 (CR1)
Read/Write
Reset Value: 0000 0000 (00h)
7
0
Bit 4 = FOLV2 Forced Output Compare 2.
This bit is set and cleared by software.
0: No effect on the OCMP2 pin.
1: Forces the OLVL2 bit to be copied to the
OCMP2 pin, if the OC2E bit is set and even if
there is no successful comparison.
Bit 3 = FOLV1 Forced Output Compare 1.
This bit is set and cleared by software.
0: No effect on the OCMP1 pin.
1: Forces OLVL1 to be copied to the OCMP1 pin, if
the OC1E bit is set and even if there is no successful comparison.
ICIE OCIE TOIE FOLV2 FOLV1 OLVL2 IEDG1 OLVL1
Bit 7 = ICIE Input Capture Interrupt Enable.
0: Interrupt is inhibited.
1: A timer interrupt is generated whenever the
ICF1 or ICF2 bit of the SR register is set.
Bit 6 = OCIE Output Compare Interrupt Enable.
0: Interrupt is inhibited.
1: A timer interrupt is generated whenever the
OCF1 or OCF2 bit of the SR register is set.
Bit 5 = TOIE Timer Overflow Interrupt Enable.
0: Interrupt is inhibited.
1: A timer interrupt is enabled whenever the TOF
bit of the SR register is set.
Bit 2 = OLVL2 Output Level 2.
This bit is copied to the OCMP2 pin whenever a
successful comparison occurs with the OC2R register and OCxE is set in the CR2 register. This value is copied to the OCMP1 pin in One Pulse Mode
and Pulse Width Modulation mode.
Bit 1 = IEDG1 Input Edge 1.
This bit determines which type of level transition
on the ICAP1 pin will trigger the capture.
0: A falling edge triggers the capture.
1: A rising edge triggers the capture.
Bit 0 = OLVL1 Output Level 1.
The OLVL1 bit is copied to the OCMP1 pin whenever a successful comparison occurs with the
OC1R register and the OC1E bit is set in the CR2
register.
107/262
ST72561
8-BIT TIMER (Cont’d)
CONTROL REGISTER 2 (CR2)
Read/Write
Reset Value: 0000 0000 (00h)
7
OC1E OC2E OPM PWM CC1 CC0 IEDG2
0
0
Bit 7 = OC1E Output Compare 1 Pin Enable.
This bit is used only to output the signal from the
timer on the OCMP1 pin (OLV1 in Output Compare mode, both OLV1 and OLV2 in PWM and
one-pulse mode). Whatever the value of the OC1E
bit, the Output Compare 1 function of the timer remains active.
0: OCMP1 pin alternate function disabled (I/O pin
free for general-purpose I/O).
1: OCMP1 pin alternate function enabled.
Bit 6 = OC2E Output Compare 2 Pin Enable.
This bit is used only to output the signal from the
timer on the OCMP2 pin (OLV2 in Output Compare mode). Whatever the value of the OC2E bit,
the Output Compare 2 function of the timer remains active.
0: OCMP2 pin alternate function disabled (I/O pin
free for general-purpose I/O).
1: OCMP2 pin alternate function enabled.
Bit 5 = OPM One Pulse Mode.
0: One Pulse Mode is not active.
1: One Pulse Mode is active, the ICAP1 pin can be
used to trigger one pulse on the OCMP1 pin; the
active transition is given by the IEDG1 bit. The
length of the generated pulse depends on the
contents of the OC1R register.
108/262
Bit 4 = PWM Pulse Width Modulation.
0: PWM mode is not active.
1: PWM mode is active, the OCMP1 pin outputs a
programmable cyclic signal; the length of the
pulse depends on the value of OC1R register;
the period depends on the value of OC2R register.
Bit 3, 2 = CC[1:0] Clock Control.
The timer clock mode depends on these bits:
Table 19. Clock Control Bits
Timer Clock
fCPU / 4
fCPU / 2
fCPU / 8
fOSC2 / 8000*
CC1
0
0
1
1
CC0
0
1
0
1
* Not available in Slow mode in ST72F561.
Bit 1 = IEDG2 Input Edge 2.
This bit determines which type of level transition
on the ICAP2 pin will trigger the capture.
0: A falling edge triggers the capture.
1: A rising edge triggers the capture.
Bit 0 = Reserved, must be kept at 0.
ST72561
8-BIT TIMER (Cont’d)
CONTROL/STATUS REGISTER (CSR)
Read Only (except bit 2 R/W)
Reset Value: 0000 0000 (00h)
Note: Reading or writing the ACTR register does
not clear TOF.
7
ICF1
0
OCF1
TOF
ICF2
OCF2 TIMD
0
0
Bit 7 = ICF1 Input Capture Flag 1.
0: No input capture (reset value).
1: An input capture has occurred on the ICAP1 pin
or the counter has reached the OC2R value in
PWM mode. To clear this bit, first read the SR
register, then read or write the the IC1R register.
Bit 6 = OCF1 Output Compare Flag 1.
0: No match (reset value).
1: The content of the free running counter has
matched the content of the OC1R register. To
clear this bit, first read the SR register, then read
or write the OC1R register.
Bit 5 = TOF Timer Overflow Flag.
0: No timer overflow (reset value).
1: The free running counter rolled over from FFh to
00h. To clear this bit, first read the SR register,
then read or write the CTR register.
Bit 4 = ICF2 Input Capture Flag 2.
0: No input capture (reset value).
1: An input capture has occurred on the ICAP2
pin. To clear this bit, first read the SR register,
then read or write the IC2R register.
Bit 3 = OCF2 Output Compare Flag 2.
0: No match (reset value).
1: The content of the free running counter has
matched the content of the OC2R register. To
clear this bit, first read the SR register, then read
or write the OC2R register.
Bit 2 = TIMD Timer disable.
This bit is set and cleared by software. When set, it
freezes the timer prescaler and counter and disabled the output functions (OCMP1 and OCMP2
pins) to reduce power consumption. Access to the
timer registers is still available, allowing the timer
configuration to be changed, or the counter reset,
while it is disabled.
0: Timer enabled
1: Timer prescaler, counter and outputs disabled
Bits 1:0 = Reserved, must be kept cleared.
109/262
ST72561
8-BIT TIMER (Cont’d)
INPUT CAPTURE 1 REGISTER (IC1R)
Read Only
Reset Value: Undefined
This is an 8-bit read only register that contains the
counter value (transferred by the input capture 1
event).
7
0
MSB
LSB
OUTPUT COMPARE 1 REGISTER (OC1R)
Read/Write
Reset Value: 0000 0000 (00h)
This is an 8-bit register that contains the value to
be compared to the CTR register.
7
0
MSB
LSB
OUTPUT COMPARE 2 REGISTER (OC2R)
Read/Write
Reset Value: 0000 0000 (00h)
This is an 8-bit register that contains the value to
be compared to the CTR register.
7
0
MSB
LSB
110/262
COUNTER REGISTER (CTR)
Read Only
Reset Value: 1111 1100 (FCh)
This is an 8-bit register that contains the counter
value. A write to this register resets the counter.
An access to this register after accessing the CSR
register clears the TOF bit.
7
0
MSB
LSB
ALTERNATE COUNTER REGISTER (ACTR)
Read Only
Reset Value: 1111 1100 (FCh)
This is an 8-bit register that contains the counter
value. A write to this register resets the counter.
An access to this register after an access to CSR
register does not clear the TOF bit in the CSR register.
7
0
MSB
LSB
INPUT CAPTURE 2 REGISTER (IC2R)
Read Only
Reset Value: Undefined
This is an 8-bit read only register that contains the
counter value (transferred by the Input Capture 2
event).
7
0
MSB
LSB
ST72561
8-BIT TIMER (Cont’d)
10.5.8 8-bit Timer Register Map
Address
(Hex.)
Register
Name
7
6
5
4
3
2
1
0
3C
CR2
OC1E
OC2E
OPM
PWM
CC1
CC0
IEDG2
0
3D
CR1
ICIE
OCIE
TOIE
FOLV2
FOLV1
OLVL2
IEDG1
OLVL1
3E
CSR
ICF1
OCF1
TOF
ICF2
OCF2
TIMD
3F
IC1R
MSB
LSB
40
OC1R
MSB
LSB
41
CTR
MSB
LSB
42
ACTR
MSB
LSB
43
IC2R
MSB
LSB
44
OC2R
MSB
LSB
111/262
ST72561
10.6 SERIAL PERIPHERAL INTERFACE (SPI)
10.6.1 Introduction
The Serial Peripheral Interface (SPI) allows fullduplex, synchronous, serial communication with
external devices. An SPI system may consist of a
master and one or more slaves or a system in
which devices may be either masters or slaves.
10.6.2 Main Features
■ Full duplex synchronous transfers (on 3 lines)
■ Simplex synchronous transfers (on 2 lines)
■ Master or slave operation
■ Six master mode frequencies (fCPU/4 max.)
■ fCPU/2 max. slave mode frequency (see note)
■ SS Management by software or hardware
■ Programmable clock polarity and phase
■ End of transfer interrupt flag
■ Write collision, Master Mode Fault and Overrun
flags
Note: In slave mode, continuous transmission is
not possible at maximum frequency due to the
software overhead for clearing status flags and to
initiate the next transmission sequence.
112/262
10.6.3 General Description
Figure 70 shows the serial peripheral interface
(SPI) block diagram. There are 3 registers:
– SPI Control Register (SPICR)
– SPI Control/Status Register (SPICSR)
– SPI Data Register (SPIDR)
The SPI is connected to external devices through
4 pins:
– MISO: Master In / Slave Out data
– MOSI: Master Out / Slave In data
– SCK: Serial Clock out by SPI masters and input by SPI slaves
– SS: Slave select:
This input signal acts as a ‘chip select’ to let
the SPI master communicate with slaves individually and to avoid contention on the data
lines. Slave SS inputs can be driven by standard I/O ports on the master Device.
ST72561
Figure 70. Serial Peripheral Interface Block Diagram
Data/Address Bus
SPIDR
Read
Interrupt
request
Read Buffer
MOSI
SPICSR
7
MISO
8-Bit Shift Register
SPIF WCOL OVR MODF
SOD
bit
0
SOD SSM
0
SSI
Write
SS
SPI
STATE
CONTROL
SCK
7
SPIE
1
0
SPICR
0
SPE SPR2 MSTR CPOL CPHA SPR1 SPR0
MASTER
CONTROL
SERIAL CLOCK
GENERATOR
SS
113/262
ST72561
SERIAL PERIPHERAL INTERFACE (Cont’d)
10.6.3.1 Functional Description
A basic example of interconnections between a
single master and a single slave is illustrated in
Figure 71.
The MOSI pins are connected together and the
MISO pins are connected together. In this way
data is transferred serially between master and
slave (most significant bit first).
The communication is always initiated by the master. When the master device transmits data to a
slave device via MOSI pin, the slave device re-
sponds by sending data to the master device via
the MISO pin. This implies full duplex communication with both data out and data in synchronized
with the same clock signal (which is provided by
the master device via the SCK pin).
To use a single data line, the MISO and MOSI pins
must be connected at each node ( in this case only
simplex communication is possible).
Four possible data/clock timing relationships may
be chosen (see Figure 74) but master and slave
must be programmed with the same timing mode.
Figure 71. Single Master/ Single Slave Application
SLAVE
MASTER
MSBit
LSBit
8-BIT SHIFT REGISTER
SPI
CLOCK
GENERATOR
MSBit
MISO
MISO
MOSI
MOSI
SCK
SS
LSBit
8-BIT SHIFT REGISTER
SCK
+5V
SS
Not used if SS is managed
by software
114/262
ST72561
SERIAL PERIPHERAL INTERFACE (Cont’d)
10.6.3.2 Slave Select Management
As an alternative to using the SS pin to control the
Slave Select signal, the application can choose to
manage the Slave Select signal by software. This
is configured by the SSM bit in the SPICSR register (see Figure 73)
In software management, the external SS pin is
free for other application uses and the internal SS
signal level is driven by writing to the SSI bit in the
SPICSR register.
In Master mode:
– SS internal must be held high continuously
In Slave Mode:
There are two cases depending on the data/clock
timing relationship (see Figure 72):
If CPHA=1 (data latched on 2nd clock edge):
– SS internal must be held low during the entire
transmission. This implies that in single slave
applications the SS pin either can be tied to
VSS, or made free for standard I/O by managing the SS function by software (SSM= 1 and
SSI=0 in the in the SPICSR register)
If CPHA=0 (data latched on 1st clock edge):
– SS internal must be held low during byte
transmission and pulled high between each
byte to allow the slave to write to the shift register. If SS is not pulled high, a Write Collision
error will occur when the slave writes to the
shift register (see Section 10.6.5.3).
Figure 72. Generic SS Timing Diagram
MOSI/MISO
Byte 1
Byte 2
Byte 3
Master SS
Slave SS
(if CPHA=0)
Slave SS
(if CPHA=1)
Figure 73. Hardware/Software Slave Select Management
SSM bit
SSI bit
1
SS external pin
0
SS internal
115/262
ST72561
SERIAL PERIPHERAL INTERFACE (Cont’d)
10.6.3.3 Master Mode Operation
In master mode, the serial clock is output on the
SCK pin. The clock frequency, polarity and phase
are configured by software (refer to the description
of the SPICSR register).
Note: The idle state of SCK must correspond to
the polarity selected in the SPICSR register (by
pulling up SCK if CPOL=1 or pulling down SCK if
CPOL=0).
To operate the SPI in master mode, perform the
following steps in order (if the SPICSR register is
not written first, the SPICR register setting (MSTR
bit ) may be not taken into account):
1. Write to the SPICR register:
– Select the clock frequency by configuring the
SPR[2:0] bits.
– Select the clock polarity and clock phase by
configuring the CPOL and CPHA bits. Figure
74 shows the four possible configurations.
Note: The slave must have the same CPOL
and CPHA settings as the master.
2. Write to the SPICSR register:
– Either set the SSM bit and set the SSI bit or
clear the SSM bit and tie the SS pin high for
the complete byte transmit sequence.
3. Write to the SPICR register:
– Set the MSTR and SPE bits
Note: MSTR and SPE bits remain set only if
SS is high).
The transmit sequence begins when software
writes a byte in the SPIDR register.
10.6.3.4 Master Mode Transmit Sequence
When software writes to the SPIDR register, the
data byte is loaded into the 8-bit shift register and
then shifted out serially to the MOSI pin most significant bit first.
When data transfer is complete:
– The SPIF bit is set by hardware
– An interrupt request is generated if the SPIE
bit is set and the interrupt mask in the CCR
register is cleared.
Clearing the SPIF bit is performed by the following
software sequence:
1. An access to the SPICSR register while the
SPIF bit is set
2. A read to the SPIDR register.
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Note: While the SPIF bit is set, all writes to the
SPIDR register are inhibited until the SPICSR register is read.
10.6.3.5 Slave Mode Operation
In slave mode, the serial clock is received on the
SCK pin from the master device.
To operate the SPI in slave mode:
1. Write to the SPICSR register to perform the following actions:
– Select the clock polarity and clock phase by
configuring the CPOL and CPHA bits (see
Figure 74).
Note: The slave must have the same CPOL
and CPHA settings as the master.
– Manage the SS pin as described in Section
10.6.3.2 and Figure 72. If CPHA=1 SS must
be held low continuously. If CPHA=0 SS must
be held low during byte transmission and
pulled up between each byte to let the slave
write in the shift register.
2. Write to the SPICR register to clear the MSTR
bit and set the SPE bit to enable the SPI I/O
functions.
10.6.3.6 Slave Mode Transmit Sequence
When software writes to the SPIDR register, the
data byte is loaded into the 8-bit shift register and
then shifted out serially to the MISO pin most significant bit first.
The transmit sequence begins when the slave device receives the clock signal and the most significant bit of the data on its MOSI pin.
When data transfer is complete:
– The SPIF bit is set by hardware
– An interrupt request is generated if SPIE bit is
set and interrupt mask in the CCR register is
cleared.
Clearing the SPIF bit is performed by the following
software sequence:
1. An access to the SPICSR register while the
SPIF bit is set.
2. A write or a read to the SPIDR register.
Notes: While the SPIF bit is set, all writes to the
SPIDR register are inhibited until the SPICSR register is read.
The SPIF bit can be cleared during a second
transmission; however, it must be cleared before
the second SPIF bit in order to prevent an Overrun
condition (see Section 10.6.5.2).
ST72561
SERIAL PERIPHERAL INTERFACE (Cont’d)
10.6.4 Clock Phase and Clock Polarity
Four possible timing relationships may be chosen
by software, using the CPOL and CPHA bits (See
Figure 74).
Note: The idle state of SCK must correspond to
the polarity selected in the SPICSR register (by
pulling up SCK if CPOL=1 or pulling down SCK if
CPOL=0).
The combination of the CPOL clock polarity and
CPHA (clock phase) bits selects the data capture
clock edge
Figure 74, shows an SPI transfer with the four
combinations of the CPHA and CPOL bits. The diagram may be interpreted as a master or slave
timing diagram where the SCK pin, the MISO pin,
the MOSI pin are directly connected between the
master and the slave device.
Note: If CPOL is changed at the communication
byte boundaries, the SPI must be disabled by resetting the SPE bit.
Figure 74. Data Clock Timing Diagram
CPHA =1
SCK
(CPOL = 1)
SCK
(CPOL = 0)
MISO
(from master)
MOSI
(from slave)
MSBit
Bit 6
Bit 5
Bit 4
Bit3
Bit 2
Bit 1
LSBit
MSBit
Bit 6
Bit 5
Bit 4
Bit3
Bit 2
Bit 1
LSBit
SS
(to slave)
CAPTURE STROBE
CPHA =0
SCK
(CPOL = 1)
SCK
(CPOL = 0)
MISO
(from master)
MOSI
(from slave)
MSBit
MSBit
Bit 6
Bit 5
Bit 4
Bit3
Bit 2
Bit 1
LSBit
Bit 6
Bit 5
Bit 4
Bit3
Bit 2
Bit 1
LSBit
SS
(to slave)
CAPTURE STROBE
Note: This figure should not be used as a replacement for parametric information.
Refer to the Electrical Characteristics chapter.
117/262
ST72561
SERIAL PERIPHERAL INTERFACE (Cont’d)
10.6.5 Error Flags
10.6.5.1 Master Mode Fault (MODF)
Master mode fault occurs when the master device
has its SS pin pulled low.
When a Master mode fault occurs:
– The MODF bit is set and an SPI interrupt request is generated if the SPIE bit is set.
– The SPE bit is reset. This blocks all output
from the Device and disables the SPI peripheral.
– The MSTR bit is reset, thus forcing the Device
into slave mode.
Clearing the MODF bit is done through a software
sequence:
1. A read access to the SPICSR register while the
MODF bit is set.
2. A write to the SPICR register.
Notes: To avoid any conflicts in an application
with multiple slaves, the SS pin must be pulled
high during the MODF bit clearing sequence. The
SPE and MSTR bits may be restored to their original state during or after this clearing sequence.
Hardware does not allow the user to set the SPE
and MSTR bits while the MODF bit is set except in
the MODF bit clearing sequence.
In a slave device, the MODF bit can not be set, but
in a multi master configuration the Device can be in
slave mode with the MODF bit set.
The MODF bit indicates that there might have
been a multi-master conflict and allows software to
handle this using an interrupt routine and either
perform to a reset or return to an application default state.
10.6.5.2 Overrun Condition (OVR)
An overrun condition occurs, when the master device has sent a data byte and the slave device has
not cleared the SPIF bit issued from the previously
transmitted byte.
When an Overrun occurs:
– The OVR bit is set and an interrupt request is
generated if the SPIE bit is set.
In this case, the receiver buffer contains the byte
sent after the SPIF bit was last cleared. A read to
the SPIDR register returns this byte. All other
bytes are lost.
The OVR bit is cleared by reading the SPICSR
register.
10.6.5.3 Write Collision Error (WCOL)
A write collision occurs when the software tries to
write to the SPIDR register while a data transfer is
taking place with an external device. When this
happens, the transfer continues uninterrupted;
and the software write will be unsuccessful.
Write collisions can occur both in master and slave
mode. See also Section 10.6.3.2 "Slave Select
Management".
Note: a "read collision" will never occur since the
received data byte is placed in a buffer in which
access is always synchronous with the CPU operation.
The WCOL bit in the SPICSR register is set if a
write collision occurs.
No SPI interrupt is generated when the WCOL bit
is set (the WCOL bit is a status flag only).
Clearing the WCOL bit is done through a software
sequence (see Figure 75).
Figure 75. Clearing the WCOL bit (Write Collision Flag) Software Sequence
Clearing sequence after SPIF = 1 (end of a data byte transfer)
1st Step
Read SPICSR
RESULT
2nd Step
Read SPIDR
SPIF =0
WCOL=0
Clearing sequence before SPIF = 1 (during a data byte transfer)
1st Step
Read SPICSR
RESULT
2nd Step
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Read SPIDR
WCOL=0
Note: Writing to the SPIDR register instead of reading it does not
reset the WCOL bit
ST72561
SERIAL PERIPHERAL INTERFACE (Cont’d)
10.6.5.4 Single Master and Multimaster
Configurations
There are two types of SPI systems:
– Single Master System
– Multimaster System
Single Master System
A typical single master system may be configured,
using a device as the master and four devices as
slaves (see Figure 76).
The master device selects the individual slave devices by using four pins of a parallel port to control
the four SS pins of the slave devices.
The SS pins are pulled high during reset since the
master device ports will be forced to be inputs at
that time, thus disabling the slave devices.
Note: To prevent a bus conflict on the MISO line
the master allows only one active slave device
during a transmission.
For more security, the slave device may respond
to the master with the received data byte. Then the
master will receive the previous byte back from the
slave device if all MISO and MOSI pins are connected and the slave has not written to its SPIDR
register.
Other transmission security methods can use
ports for handshake lines or data bytes with command fields.
Multi-Master System
A multi-master system may also be configured by
the user. Transfer of master control could be implemented using a handshake method through the
I/O ports or by an exchange of code messages
through the serial peripheral interface system.
The multi-master system is principally handled by
the MSTR bit in the SPICR register and the MODF
bit in the SPICSR register.
Figure 76. Single Master / Multiple Slave Configuration
SS
SCK
Slave
Device
SS
SCK
Slave
Device
SS
SCK
Slave
Device
SS
SCK
Slave
Device
MOSI MISO
MOSI MISO
MOSI MISO
MOSI MISO
SCK
Master
Device
5V
Ports
MOSI MISO
SS
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ST72561
SERIAL PERIPHERAL INTERFACE (Cont’d)
10.6.6 Low Power Modes
Mode
WAIT
HALT
Description
No effect on SPI.
SPI interrupt events cause the Device to exit
from WAIT mode.
SPI registers are frozen.
In HALT mode, the SPI is inactive. SPI operation resumes when the Device is woken up
by an interrupt with “exit from HALT mode”
capability. The data received is subsequently
read from the SPIDR register when the software is running (interrupt vector fetching). If
several data are received before the wakeup event, then an overrun error is generated.
This error can be detected after the fetch of
the interrupt routine that woke up the Device.
10.6.6.1 Using the SPI to wake-up the Device
from Halt mode
In slave configuration, the SPI is able to wake-up
the Device from HALT mode through a SPIF interrupt. The data received is subsequently read from
the SPIDR register when the software is running
(interrupt vector fetch). If multiple data transfers
have been performed before software clears the
SPIF bit, then the OVR bit is set by hardware.
Note: When waking up from Halt mode, if the SPI
remains in Slave mode, it is recommended to perform an extra communications cycle to bring the
SPI from Halt mode state to normal state. If the
SPI exits from Slave mode, it returns to normal
state immediately.
Caution: The SPI can wake-up the Device from
Halt mode only if the Slave Select signal (external
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SS pin or the SSI bit in the SPICSR register) is low
when the Device enters Halt mode. So if Slave selection is configured as external (see Section
10.6.3.2), make sure the master drives a low level
on the SS pin when the slave enters Halt mode.
10.6.7 Interrupts
Interrupt Event
Event
Flag
SPI End of TransSPIF
fer Event
Master Mode
MODF
Fault Event
Overrun Error
OVR
Enable
Control
Bit
SPIE
Exit
from
Wait
Exit
from
Halt
Yes
Yes
Yes
No
Yes
No
Note: The SPI interrupt events are connected to
the same interrupt vector (see Interrupts chapter).
They generate an interrupt if the corresponding
Enable Control Bit is set and the interrupt mask in
the CC register is reset (RIM instruction).
ST72561
SERIAL PERIPHERAL INTERFACE (Cont’d)
10.6.8 Register Description
CONTROL REGISTER (SPICR)
Read/Write
Reset Value: 0000 xxxx (0xh)
7
SPIE
0
SPE
SPR2
MSTR
CPOL
CPHA
SPR1
SPR0
Bit 7 = SPIE Serial Peripheral Interrupt Enable.
This bit is set and cleared by software.
0: Interrupt is inhibited
1: An SPI interrupt is generated whenever an End
of Transfer event, Master Mode Fault or Overrun error occurs (SPIF=1, MODF=1 or OVR=1
in the SPICSR register)
Bit 6 = SPE Serial Peripheral Output Enable.
This bit is set and cleared by software. It is also
cleared by hardware when, in master mode, SS=0
(see Section 10.6.5.1 "Master Mode Fault
(MODF)"). The SPE bit is cleared by reset, so the
SPI peripheral is not initially connected to the external pins.
0: I/O pins free for general purpose I/O
1: SPI I/O pin alternate functions enabled
Bit 5 = SPR2 Divider Enable.
This bit is set and cleared by software and is
cleared by reset. It is used with the SPR[1:0] bits to
set the baud rate. Refer to Table 20 SPI Master
mode SCK Frequency.
0: Divider by 2 enabled
1: Divider by 2 disabled
Note: This bit has no effect in slave mode.
Bit 4 = MSTR Master Mode.
This bit is set and cleared by software. It is also
cleared by hardware when, in master mode, SS=0
(see Section 10.6.5.1 "Master Mode Fault
(MODF)").
0: Slave mode
1: Master mode. The function of the SCK pin
changes from an input to an output and the functions of the MISO and MOSI pins are reversed.
Bit 3 = CPOL Clock Polarity.
This bit is set and cleared by software. This bit determines the idle state of the serial Clock. The
CPOL bit affects both the master and slave
modes.
0: SCK pin has a low level idle state
1: SCK pin has a high level idle state
Note: If CPOL is changed at the communication
byte boundaries, the SPI must be disabled by resetting the SPE bit.
Bit 2 = CPHA Clock Phase.
This bit is set and cleared by software.
0: The first clock transition is the first data capture
edge.
1: The second clock transition is the first capture
edge.
Note: The slave must have the same CPOL and
CPHA settings as the master.
Bits 1:0 = SPR[1:0] Serial Clock Frequency.
These bits are set and cleared by software. Used
with the SPR2 bit, they select the baud rate of the
SPI serial clock SCK output by the SPI in master
mode.
Note: These 2 bits have no effect in slave mode.
Table 20. SPI Master mode SCK Frequency
Serial Clock
SPR2
SPR1
SPR0
fCPU/4
1
0
0
fCPU/8
0
0
0
fCPU/16
0
0
1
fCPU/32
1
1
0
fCPU/64
0
1
0
fCPU/128
0
1
1
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ST72561
SERIAL PERIPHERAL INTERFACE (Cont’d)
CONTROL/STATUS REGISTER (SPICSR)
Read/Write (some bits Read Only)
Reset Value: 0000 0000 (00h)
7
SPIF
0
WCOL
OVR
MODF
-
SOD
SSM
SSI
Bit 7 = SPIF Serial Peripheral Data Transfer Flag
(Read only).
This bit is set by hardware when a transfer has
been completed. An interrupt is generated if
SPIE=1 in the SPICR register. It is cleared by a
software sequence (an access to the SPICSR
register followed by a write or a read to the
SPIDR register).
0: Data transfer is in progress or the flag has been
cleared.
1: Data transfer between the Device and an external device has been completed.
Note: While the SPIF bit is set, all writes to the
SPIDR register are inhibited until the SPICSR register is read.
Bit 6 = WCOL Write Collision status (Read only).
This bit is set by hardware when a write to the
SPIDR register is done during a transmit sequence. It is cleared by a software sequence (see
Figure 75).
0: No write collision occurred
1: A write collision has been detected
Bit 5 = OVR SPI Overrun error (Read only).
This bit is set by hardware when the byte currently
being received in the shift register is ready to be
transferred into the SPIDR register while SPIF = 1
(See Section 10.6.5.2). An interrupt is generated if
SPIE = 1 in the SPICR register. The OVR bit is
cleared by software reading the SPICSR register.
0: No overrun error
1: Overrun error detected
Bit 4 = MODF Mode Fault flag (Read only).
This bit is set by hardware when the SS pin is
pulled low in master mode (see Section 10.6.5.1
"Master Mode Fault (MODF)"). An SPI interrupt
can be generated if SPIE=1 in the SPICR register.
This bit is cleared by a software sequence (An access to the SPICSR register while MODF=1 followed by a write to the SPICR register).
0: No master mode fault detected
1: A fault in master mode has been detected
Bit 3 = Reserved, must be kept cleared.
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Bit 2 = SOD SPI Output Disable.
This bit is set and cleared by software. When set, it
disables the alternate function of the SPI output
(MOSI in master mode / MISO in slave mode)
0: SPI output enabled (if SPE=1)
1: SPI output disabled
Bit 1 = SSM SS Management.
This bit is set and cleared by software. When set, it
disables the alternate function of the SPI SS pin
and uses the SSI bit value instead. See Section
10.6.3.2 "Slave Select Management".
0: Hardware management (SS managed by external pin)
1: Software management (internal SS signal controlled by SSI bit. External SS pin free for general-purpose I/O)
Bit 0 = SSI SS Internal Mode.
This bit is set and cleared by software. It acts as a
‘chip select’ by controlling the level of the SS slave
select signal when the SSM bit is set.
0 : Slave selected
1 : Slave deselected
DATA I/O REGISTER (SPIDR)
Read/Write
Reset Value: Undefined
7
D7
0
D6
D5
D4
D3
D2
D1
D0
The SPIDR register is used to transmit and receive
data on the serial bus. In a master device, a write
to this register will initiate transmission/reception
of another byte.
Notes: During the last clock cycle the SPIF bit is
set, a copy of the received data byte in the shift
register is moved to a buffer. When the user reads
the serial peripheral data I/O register, the buffer is
actually being read.
While the SPIF bit is set, all writes to the SPIDR
register are inhibited until the SPICSR register is
read.
Warning: A write to the SPIDR register places
data directly into the shift register for transmission.
A read to the SPIDR register returns the value located in the buffer and not the content of the shift
register (see Figure 70).
ST72561
SERIAL PERIPHERAL INTERFACE (Cont’d)
Table 21. SPI Register Map and Reset Values
Address
Register
Label
7
6
5
4
3
2
1
0
21
SPIDR
Reset Value
MSB
x
x
x
x
x
x
x
LSB
x
22
SPICR
Reset Value
SPIE
0
SPE
0
SPR2
0
MSTR
0
CPOL
x
CPHA
x
SPR1
x
SPR0
x
23
SPICSR
Reset Value
SPIF
0
WCOL
0
OR
0
MODF
0
0
SOD
0
SSM
0
SSI
0
(Hex.)
123/262
ST72561
10.7 LINSCI SERIAL COMMUNICATION INTERFACE (LIN MASTER/SLAVE)
10.7.1 Introduction
The Serial Communications Interface (SCI) offers
a flexible means of full-duplex data exchange with
external equipment requiring an industry standard
NRZ asynchronous serial data format. The SCI offers a very wide range of baud rates using two
baud rate generator systems.
The LIN-dedicated features support the LIN (Local
Interconnect Network) protocol for both master
and slave nodes.
This chapter is divided into SCI Mode and LIN
mode sections. For information on general SCI
communications, refer to the SCI mode section.
For LIN applications, refer to both the SCI mode
and LIN mode sections.
10.7.2 SCI Features
■ Full duplex, asynchronous communications
■ NRZ standard format (Mark/Space)
■ Independently
programmable transmit and
receive baud rates up to 500K baud.
■ Programmable data word length (8 or 9 bits)
■ Receive buffer full, Transmit buffer empty and
End of Transmission flags
■ Two receiver wake-up modes:
– Address bit (MSB)
– Idle line
■ Muting function for multiprocessor configurations
■ Separate enable bits for Transmitter and
Receiver
■ Overrun, Noise and Frame error detection
124/262
Six interrupt sources
– Transmit data register empty
– Transmission complete
– Receive data register full
– Idle line received
– Overrun error
– Parity interrupt
■ Parity control:
– Transmits parity bit
– Checks parity of received data byte
■ Reduced power consumption mode
10.7.3 LIN Features
– LIN Master
– 13-bit LIN Synch Break generation
– LIN Slave
– Automatic Header Handling
– Automatic baud rate re-synchronization
based on recognition and measurement of the
LIN Synch Field (for LIN slave nodes)
– Automatic baud rate adjustment (at CPU frequency precision)
– 11-bit LIN Synch Break detection capability
– LIN Parity check on the LIN Identifier Field
(only in reception)
– LIN Error management
– LIN Header Timeout
– Hot plugging support
■
ST72561
LINSCI
SERIAL COMMUNICATION INTERFACE (Cont’d)
10.7.4 General Description
– A conventional type for commonly-used baud
rates.
The interface is externally connected to another
device by two pins:
– An extended type with a prescaler offering a very
wide range of baud rates even with non-standard
– TDO: Transmit Data Output. When the transmitoscillator frequencies.
ter is disabled, the output pin returns to its I/O
port configuration. When the transmitter is ena– A LIN baud rate generator with automatic resynbled and nothing is to be transmitted, the TDO
chronization.
pin is at high level.
– RDI: Receive Data Input is the serial data input.
Oversampling techniques are used for data recovery by discriminating between valid incoming
data and noise.
Through these pins, serial data is transmitted and
received as characters comprising:
– An Idle Line prior to transmission or reception
– A start bit
– A data word (8 or 9 bits) least significant bit first
– A Stop bit indicating that the character is complete.
This interface uses three types of baud rate generator:
125/262
ST72561
LINSCI
SERIAL COMMUNICATION INTERFACE (SCI Mode) (Cont’d)
Figure 77. SCI Block Diagram (in Conventional Baud Rate Generator Mode)
Write
Read
(DATA REGISTER) SCIDR
Received Data Register (RDR)
Transmit Data Register (TDR)
TDO
Receive Shift Register
Transmit Shift Register
RDI
SCICR1
R8
TRANSMIT
WAKE
UP
CONTROL
UNIT
T8
SCID
M
WAKE PCE
PS PIE
RECEIVER
CLOCK
RECEIVER
CONTROL
SCISR
SCICR2
TIE TCIE RIE
ILIE
TE
RE RWU SBK
OR/
TDRE TC RDRF IDLE
LHE
NF
FE
SCI
INTERRUPT
CONTROL
TRANSMITTER
CLOCK
TRANSMITTER RATE
fCPU
CONTROL
/16
/PR
SCIBRR
SCP1 SCP0 SCT2 SCT1 SCT0 SCR2 SCR1SCR0
RECEIVER RATE
CONTROL
CONVENTIONAL BAUD RATE GENERATOR
126/262
PE
ST72561
LINSCI SERIAL COMMUNICATION INTERFACE (SCI Mode) (Cont’d)
10.7.5 SCI Mode - Functional Description
10.7.5.1 Serial Data Format
Conventional Baud Rate Generator Mode
Word length may be selected as being either 8 or 9
bits by programming the M bit in the SCICR1 regThe block diagram of the Serial Control Interface
ister (see Figure 78).
in conventional baud rate generator mode is
shown in Figure 77.
The TDO pin is in low state during the start bit.
It uses 4 registers:
The TDO pin is in high state during the stop bit.
– Two control registers (SCICR1 and SCICR2)
An Idle character is interpreted as a continuous
logic high level for 10 (or 11) full bit times.
– A status register (SCISR)
A Break character is a character with a sufficient
– A baud rate register (SCIBRR)
number of low level bits to break the normal data
Extended Prescaler Mode
format followed by an extra “1” bit to acknowledge
the start bit.
Two additional prescalers are available in extended prescaler mode. They are shown in Figure 79.
– An extended prescaler receiver register (SCIERPR)
– An extended prescaler transmitter register (SCIETPR)
Figure 78. Word length programming
9-bit Word length (M bit is set)
Possible
Parity
Bit
Data Character
Start
Bit
Bit0
Bit2
Bit1
Bit3
Bit4
Bit5
Bit6
Start
Bit
Break Character
Extra
’1’
Possible
Parity
Bit
Data Character
Bit0
Bit8
Next
Stop Start
Bit
Bit
Idle Line
8-bit Word length (M bit is reset)
Start
Bit
Bit7
Next Data Character
Bit1
Bit2
Bit3
Bit4
Bit5
Bit6
Bit7
Start
Bit
Next Data Character
Stop
Bit
Next
Start
Bit
Idle Line
Start
Bit
Break Character
Extra Start
Bit
’1’
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ST72561
LINSCI SERIAL COMMUNICATION INTERFACE (SCI Mode) (Cont’d)
10.7.5.2 Transmitter
When no transmission is taking place, a write instruction to the SCIDR register places the data diThe transmitter can send data words of either 8 or
rectly in the shift register, the data transmission
9 bits depending on the M bit status. When the M
starts, and the TDRE bit is immediately set.
bit is set, word length is 9 bits and the 9th bit (the
MSB) has to be stored in the T8 bit in the SCICR1
When a character transmission is complete (after
register.
the stop bit or after the break character) the TC bit
is set and an interrupt is generated if the TCIE is
Character Transmission
set and the I[1:0] bits are cleared in the CCR regDuring an SCI transmission, data shifts out least
ister.
significant bit first on the TDO pin. In this mode,
Clearing the TC bit is performed by the following
the SCIDR register consists of a buffer (TDR) besoftware sequence:
tween the internal bus and the transmit shift regis1. An access to the SCISR register
ter (see Figure 77).
2. A write to the SCIDR register
Procedure
Note: The TDRE and TC bits are cleared by the
– Select the M bit to define the word length.
same software sequence.
– Select the desired baud rate using the SCIBRR
Break Characters
and the SCIETPR registers.
Setting the SBK bit loads the shift register with a
– Set the TE bit to send a preamble of 10 (M=0) or
break character. The break character length de11 (M=1) consecutive ones (Idle Line) as first
pends on the M bit (see Figure 78)
transmission.
As long as the SBK bit is set, the SCI sends break
– Access the SCISR register and write the data to
characters to the TDO pin. After clearing this bit by
send in the SCIDR register (this sequence clears
software, the SCI inserts a logic 1 bit at the end of
the TDRE bit). Repeat this sequence for each
the last break character to guarantee the recognidata to be transmitted.
tion of the start bit of the next character.
Clearing the TDRE bit is always performed by the
Idle Line
following software sequence:
Setting the TE bit drives the SCI to send a pream1. An access to the SCISR register
ble of 10 (M=0) or 11 (M=1) consecutive ‘1’s (idle
2. A write to the SCIDR register
line) before the first character.
The TDRE bit is set by hardware and it indicates:
In this case, clearing and then setting the TE bit
– The TDR register is empty.
during a transmission sends a preamble (idle line)
after the current word. Note that the preamble du– The data transfer is beginning.
ration (10 or 11 consecutive ‘1’s depending on the
– The next data can be written in the SCIDR regisM bit) does not take into account the stop bit of the
ter without overwriting the previous data.
previous character.
This flag generates an interrupt if the TIE bit is set
Note: Resetting and setting the TE bit causes the
and the I[|1:0] bits are cleared in the CCR register.
data in the TDR register to be lost. Therefore the
When a transmission is taking place, a write inbest time to toggle the TE bit is when the TDRE bit
struction to the SCIDR register stores the data in
is set i.e. before writing the next byte in the SCIDR.
the TDR register and which is copied in the shift
register at the end of the current transmission.
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LINSCI SERIAL COMMUNICATION INTERFACE (SCI Mode) (Cont’d)
10.7.5.3 Receiver
– The OR bit is set.
The SCI can receive data words of either 8 or 9
– The RDR content will not be lost.
bits. When the M bit is set, word length is 9 bits
– The shift register will be overwritten.
and the MSB is stored in the R8 bit in the SCICR1
– An interrupt is generated if the RIE bit is set and
register.
the I[|1:0] bits are cleared in the CCR register.
Character reception
The OR bit is reset by an access to the SCISR regDuring a SCI reception, data shifts in least signifiister followed by a SCIDR register read operation.
cant bit first through the RDI pin. In this mode, the
Noise Error
SCIDR register consists or a buffer (RDR) between the internal bus and the received shift regisOversampling techniques are used for data recovter (see Figure 77).
ery by discriminating between valid incoming data
and noise.
Procedure
When noise is detected in a character:
– Select the M bit to define the word length.
– The NF bit is set at the rising edge of the RDRF
– Select the desired baud rate using the SCIBRR
bit.
and the SCIERPR registers.
– Data is transferred from the Shift register to the
– Set the RE bit, this enables the receiver which
SCIDR register.
begins searching for a start bit.
– No interrupt is generated. However this bit rises
When a character is received:
at the same time as the RDRF bit which itself
– The RDRF bit is set. It indicates that the content
generates an interrupt.
of the shift register is transferred to the RDR.
The NF bit is reset by a SCISR register read oper– An interrupt is generated if the RIE bit is set and
ation followed by a SCIDR register read operation.
the I[1:0] bits are cleared in the CCR register.
Framing Error
– The error flags can be set if a frame error, noise
A framing error is detected when:
or an overrun error has been detected during reception.
– The stop bit is not recognized on reception at the
expected time, following either a de-synchroniClearing the RDRF bit is performed by the following
zation or excessive noise.
software sequence done by:
–
A break is received.
1. An access to the SCISR register
When the framing error is detected:
2. A read to the SCIDR register.
– the FE bit is set by hardware
The RDRF bit must be cleared before the end of the
reception of the next character to avoid an overrun
– Data is transferred from the Shift register to the
error.
SCIDR register.
Idle Line
– No interrupt is generated. However this bit rises
at the same time as the RDRF bit which itself
When an idle line is detected, there is the same
generates an interrupt.
procedure as a data received character plus an interrupt if the ILIE bit is set and the I[|1:0] bits are
The FE bit is reset by a SCISR register read opercleared in the CCR register.
ation followed by a SCIDR register read operation.
Overrun Error
Break Character
An overrun error occurs when a character is re– When a break character is received, the SCI
ceived when RDRF has not been reset. Data can
handles it as a framing error. To differentiate a
not be transferred from the shift register to the
break character from a framing error, it is necesTDR register as long as the RDRF bit is not
sary to read the SCIDR. If the received value is
cleared.
00h, it is a break character. Otherwise it is a
framing error.
When an overrun error occurs:
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LINSCI SERIAL COMMUNICATION INTERFACE (SCI Mode) (Cont’d)
10.7.5.4 Conventional Baud Rate Generation
10.7.5.5 Extended Baud Rate Generation
The baud rate for the receiver and transmitter (Rx
The extended prescaler option gives a very fine
and Tx) are set independently and calculated as
tuning on the baud rate, using a 255 value prescalfollows:
er, whereas the conventional Baud Rate Generator retains industry standard software compatibilifCPU
fCPU
ty.
Rx =
Tx =
The extended baud rate generator block diagram
(16*PR)*RR
(16*PR)*TR
is described in Figure 79.
with:
The output clock rate sent to the transmitter or to
PR = 1, 3, 4 or 13 (see SCP[1:0] bits)
the receiver will be the output from the 16 divider
divided by a factor ranging from 1 to 255 set in the
TR = 1, 2, 4, 8, 16, 32, 64,128
SCIERPR or the SCIETPR register.
(see SCT[2:0] bits)
Note: the extended prescaler is activated by setRR = 1, 2, 4, 8, 16, 32, 64,128
ting the SCIETPR or SCIERPR register to a value
(see SCR[2:0] bits)
other than zero. The baud rates are calculated as
follows:
All these bits are in the SCIBRR register.
Example: If fCPU is 8 MHz (normal mode) and if
fCPU
fCPU
PR=13 and TR=RR=1, the transmit and receive
Rx =
Tx =
baud rates are 38400 baud.
16*ERPR*(PR*TR)
16*ETPR*(PR*TR)
Note: the baud rate registers MUST NOT be
changed while the transmitter or the receiver is enwith:
abled.
ETPR = 1,..,255 (see SCIETPR register)
ERPR = 1,.. 255 (see SCIERPR register)
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LINSCI
SERIAL COMMUNICATION INTERFACE (SCI Mode) (Cont’d)
Figure 79. SCI Baud Rate and Extended Prescaler Block Diagram
TRANSMITTER
CLOCK
EXTENDED PRESCALER TRANSMITTER RATE CONTROL
SCIETPR
EXTENDED TRANSMITTER PRESCALER REGISTER
SCIERPR
EXTENDED RECEIVER PRESCALER REGISTER
RECEIVER
CLOCK
EXTENDED PRESCALER RECEIVER RATE CONTROL
EXTENDED PRESCALER
fCPU
TRANSMITTER RATE
CONTROL
/16
/PR
SCIBRR
SCP1 SCP0 SCT2 SCT1 SCT0 SCR2 SCR1SCR0
RECEIVER RATE
CONTROL
CONVENTIONAL BAUD RATE GENERATOR
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LINSCI SERIAL COMMUNICATION INTERFACE (SCI Mode) (Cont’d)
10.7.5.6 Receiver Muting and Wake-up Feature
ceived an address character (most significant bit
=’1’), the receivers are waken up. The receivers
In multiprocessor configurations it is often desirawhich are not addressed set RWU bit to enter in
ble that only the intended message recipient
mute mode. Consequently, they will not treat the
should actively receive the full message contents,
next characters constituting the next part of the
thus reducing redundant SCI service overhead for
message.
all non-addressed receivers.
10.7.5.7 Parity Control
The non-addressed devices may be placed in
sleep mode by means of the muting function.
Hardware byte Parity control (generation of parity
bit in transmission and parity checking in recepSetting the RWU bit by software puts the SCI in
tion) can be enabled by setting the PCE bit in the
sleep mode:
SCICR1 register. Depending on the character forAll the reception status bits can not be set.
mat defined by the M bit, the possible SCI character formats are as listed in Table 22.
All the receive interrupts are inhibited.
Note: In case of wake up by an address mark, the
A muted receiver may be woken up in one of the
MSB bit of the data is taken into account and not
following ways:
the parity bit
– by Idle Line detection if the WAKE bit is reset,
– by Address Mark detection if the WAKE bit is set.
Table 22. Character Formats
Idle Line Detection
M bit PCE bit
Character format
0
0
| SB | 8 bit data | STB |
Receiver wakes-up by Idle Line detection when
the Receive line has recognised an Idle Line. Then
0
1
| SB | 7-bit data | PB | STB |
the RWU bit is reset by hardware but the IDLE bit
1
0
| SB | 9-bit data | STB |
is not set.
1
1
| SB | 8-bit data | PB | STB |
This feature is useful in a multiprocessor system
Legend: SB = Start Bit, STB = Stop Bit,
when the first characters of the message deterPB = Parity Bit
mine the address and when each message ends
Even parity: the parity bit is calculated to obtain
by an idle line: As soon as the line becomes idle,
an even number of “1s” inside the character made
every receivers is waken up and analyse the first
of the 7 or 8 LSB bits (depending on whether M is
characters of the message which indicates the adequal to 0 or 1) and the parity bit.
dressed receiver. The receivers which are not addressed set RWU bit to enter in mute mode. ConEx: data=00110101; 4 bits set => parity bit will be
sequently, they will not treat the next characters
0 if even parity is selected (PS bit = 0).
constituting the next part of the message. At the
Odd parity: the parity bit is calculated to obtain an
end of the message, an idle line is sent by the
odd number of “1s” inside the character made of
transmitter: this wakes up every receivers which
the 7 or 8 LSB bits (depending on whether M is
are ready to analyse the addressing characters of
equal to 0 or 1) and the parity bit.
the new message.
Ex: data=00110101; 4 bits set => parity bit will be
In such a system, the inter-characters space must
1 if odd parity is selected (PS bit = 1).
be smaller than the idle time.
Transmission mode: If the PCE bit is set then the
Address Mark Detection
MSB bit of the data written in the data register is
Receiver wakes-up by Address Mark detection
not transmitted but is changed by the parity bit.
when it received a “1” as the most significant bit of
Reception mode: If the PCE bit is set then the ina word, thus indicating that the message is an adterface checks if the received data byte has an
dress. The reception of this particular word wakes
even number of “1s” if even parity is selected
up the receiver, resets the RWU bit and sets the
(PS=0) or an odd number of “1s” if odd parity is seRDRF bit, which allows the receiver to receive this
lected (PS=1). If the parity check fails, the PE flag
word normally and to use it as an address word.
is set in the SCISR register and an interrupt is genThis feature is useful in a multiprocessor system
erated if PCIE is set in the SCICR1 register.
when the most significant bit of each character
(except for the break character) is reserved for Address Detection. As soon as the receivers re-
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LINSCI SERIAL COMMUNICATION INTERFACE (SCI Mode) (Cont’d)
10.7.6 Low Power Modes
10.7.7 Interrupts
Mode
WAIT
HALT
Description
No effect on SCI.
SCI interrupts cause the device to exit
from Wait mode.
SCI registers are frozen.
In Halt mode, the SCI stops transmitting/receiving until Halt mode is exited.
Interrupt Event
Enable Exit
Event
Control from
Flag
Bit
Wait
Transmit Data Register
TDRE
Empty
Transmission ComTC
plete
Received Data Ready
RDRF
to be Read
Overrun Error or LIN
OR/
Synch Error Detected
LHE
Idle Line Detected
IDLE
Parity Error
PE
LIN Header Detection
LHDF
Exit
from
Halt
TIE
Yes
No
TCIE
Yes
No
Yes
No
Yes
No
Yes
Yes
Yes
No
No
No
RIE
ILIE
PIE
LHIE
The SCI interrupt events are connected to the
same interrupt vector (see Interrupts chapter).
These events generate an interrupt if the corresponding Enable Control Bit is set and the interrupt mask in the CC register is reset (RIM instruction).
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LINSCI SERIAL COMMUNICATION INTERFACE (SCI Mode) (Cont’d)
10.7.8 SCI Mode Register Description
Bit 3 = OR Overrun error
STATUS REGISTER (SCISR)
The OR bit is set by hardware when the word curRead Only
rently being received in the shift register is ready to
Reset Value: 1100 0000 (C0h)
be transferred into the RDR register whereas
RDRF is still set. An interrupt is generated if RIE=1
7
0
in the SCICR2 register. It is cleared by a software
sequence (an access to the SCISR register folTDRE
TC
RDRF IDLE
OR1)
NF1)
FE1)
PE1)
lowed by a read to the SCIDR register).
0: No Overrun error
1: Overrun error detected
Bit 7 = TDRE Transmit data register empty.
Note: When this bit is set, RDR register contents
This bit is set by hardware when the content of the
TDR register has been transferred into the shift
will not be lost but the shift register will be overwritten.
register. An interrupt is generated if the TIE =1 in
the SCICR2 register. It is cleared by a software sequence (an access to the SCISR register followed
Bit 2 = NF Character Noise flag
by a write to the SCIDR register).
0: Data is not transferred to the shift register
This bit is set by hardware when noise is detected
1: Data is transferred to the shift register
on a received character. It is cleared by a software
sequence (an access to the SCISR register followed by a read to the SCIDR register).
Bit 6 = TC Transmission complete.
0: No noise
This bit is set by hardware when transmission of a
1: Noise is detected
character containing Data is complete. An interNote: This bit does not generate interrupt as it aprupt is generated if TCIE=1 in the SCICR2 regispears at the same time as the RDRF bit which itter. It is cleared by a software sequence (an acself generates an interrupt.
cess to the SCISR register followed by a write to
the SCIDR register).
0: Transmission is not complete
Bit 1 = FE Framing error.
1: Transmission is complete
This bit is set by hardware when a de-synchronizaNote: TC is not set after the transmission of a Pretion, excessive noise or a break character is deamble or a Break.
tected. It is cleared by a software sequence (an
access to the SCISR register followed by a read to
the SCIDR register).
Bit 5 = RDRF Received data ready flag.
0: No Framing error
This bit is set by hardware when the content of the
1: Framing error or break character detected
RDR register has been transferred to the SCIDR
Notes:
register. An interrupt is generated if RIE=1 in the
SCICR2 register. It is cleared by a software se– This bit does not generate an interrupt as it apquence (an access to the SCISR register followed
pears at the same time as the RDRF bit which itby a read to the SCIDR register).
self generates an interrupt. If the word currently
0: Data is not received
being transferred causes both a frame error and
1: Received data is ready to be read
an overrun error, it will be transferred and only
the OR bit will be set.
Bit 4 = IDLE Idle line detected.
Bit 0 = PE Parity error.
This bit is set by hardware when an Idle Line is deThis bit is set by hardware when a byte parity error
tected. An interrupt is generated if the ILIE=1 in
occurs (if the PCE bit is set) in receiver mode. It is
the SCICR2 register. It is cleared by a software secleared by a software sequence (a read to the staquence (an access to the SCISR register followed
tus register followed by an access to the SCIDR
by a read to the SCIDR register).
data register). An interrupt is generated if PIE=1 in
0: No Idle Line is detected
the SCICR1 register.
1: Idle Line is detected
0: No parity error
1: Parity error detected
Note: The IDLE bit will not be set again until the
RDRF bit has been set itself (i.e. a new idle line occurs).
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LINSCI SERIAL COMMUNICATION INTERFACE (SCI Mode) (Cont’d)
CONTROL REGISTER 1 (SCICR1)
Read/Write
Bit 3 = WAKE Wake-Up method.
Reset Value: x000 0000 (x0h)
This bit determines the SCI Wake-Up method, it is
set or cleared by software.
7
0
0: Idle Line
1: Address Mark
R8
T8
SCID
M
WAKE PCE1)
PS
PIE
Note: If the LINE bit is set, the WAKE bit is de-activated and replaced by the LHDM bit
1)This
bit has a different function in LIN mode, please
refer to the LIN mode register description.
Bit 7 = R8 Receive data bit 8.
This bit is used to store the 9th bit of the received
word when M=1.
Bit 6 = T8 Transmit data bit 8.
This bit is used to store the 9th bit of the transmitted word when M=1.
Bit 5 = SCID Disabled for low power consumption
When this bit is set the SCI prescalers and outputs
are stopped and the end of the current byte transfer in order to reduce power consumption.This bit
is set and cleared by software.
0: SCI enabled
1: SCI prescaler and outputs disabled
Bit 4 = M Word length.
This bit determines the word length. It is set or
cleared by software.
0: 1 Start bit, 8 Data bits, 1 Stop bit
1: 1 Start bit, 9 Data bits, 1 Stop bit
Note: The M bit must not be modified during a data
transfer (both transmission and reception).
Bit 2 = PCE Parity control enable.
This bit is set and cleared by software. It selects
the hardware parity control (generation and detection for byte parity, detection only for LIN parity).
0: Parity control disabled
1: Parity control enabled
Bit 1 = PS Parity selection.
This bit selects the odd or even parity when the
parity generation/detection is enabled (PCE bit
set). It is set and cleared by software. The parity
will be selected after the current byte.
0: Even parity
1: Odd parity
Bit 0 = PIE Parity interrupt enable.
This bit enables the interrupt capability of the hardware parity control when a parity error is detected
(PE bit set). The parity error involved can be a byte
parity error (if bit PCE is set and bit LPE is reset) or
a LIN parity error (if bit PCE is set and bit LPE is
set).
0: Parity error interrupt disabled
1: Parity error interrupt enabled
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LINSCI SERIAL COMMUNICATION INTERFACE (SCI Mode) (Cont’d)
CONTROL REGISTER 2 (SCICR2)
1: Receiver is enabled and begins searching for a
Read/Write
start bit
Reset Value: 0000 0000 (00 h)
Bit 1 = RWU Receiver wake-up.
7
0
This bit determines if the SCI is in mute mode or
not. It is set and cleared by software and can be
TIE
TCIE
RIE
ILIE
TE
RE
RWU1) SBK1)
cleared by hardware when a wake-up sequence is
recognized.
1)This bit has a different function in LIN mode, please
0: Receiver in active mode
1: Receiver in mute mode
refer to the LIN mode register description.
Notes:
Bit 7 = TIE Transmitter interrupt enable.
This bit is set and cleared by software.
– Before selecting Mute mode (by setting the RWU
0: Interrupt is inhibited
bit) the SCI must first receive a data byte, other1: In SCI interrupt is generated whenever TDRE=1
wise it cannot function in Mute mode with wakein the SCISR register
up by Idle line detection.
– In Address Mark Detection Wake-Up configuraBit 6 = TCIE Transmission complete interrupt enation (WAKE bit=1) the RWU bit cannot be modible
fied by software while the RDRF bit is set.
This bit is set and cleared by software.
0: Interrupt is inhibited
Bit 0 = SBK Send break.
1: An SCI interrupt is generated whenever TC=1 in
This
bit set is used to send break characters. It is
the SCISR register
set and cleared by software.
0: No break character is transmitted
Bit 5 = RIE Receiver interrupt enable.
1: Break characters are transmitted
This bit is set and cleared by software.
Note: If the SBK bit is set to “1” and then to “0”, the
0: Interrupt is inhibited
transmitter will send a BREAK word at the end of
1: An SCI interrupt is generated whenever OR=1
the current word.
or RDRF=1 in the SCISR register
Bit 4 = ILIE Idle line interrupt enable.
This bit is set and cleared by software.
0: Interrupt is inhibited
1: An SCI interrupt is generated whenever IDLE=1
in the SCISR register.
Bit 3 = TE Transmitter enable.
This bit enables the transmitter. It is set and
cleared by software.
0: Transmitter is disabled
1: Transmitter is enabled
Notes:
– During transmission, a “0” pulse on the TE bit
(“0” followed by “1”) sends a preamble (idle line)
after the current word.
– When TE is set there is a 1 bit-time delay before
the transmission starts.
Bit 2 = RE Receiver enable.
This bit enables the receiver. It is set and cleared
by software.
0: Receiver is disabled in the SCISR register
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DATA REGISTER (SCIDR)
Read/Write
Reset Value: Undefined
Contains the Received or Transmitted data character, depending on whether it is read from or written to.
7
DR7
0
DR6
DR5
DR4
DR3
DR2
DR1
DR0
The Data register performs a double function (read
and write) since it is composed of two registers,
one for transmission (TDR) and one for reception
(RDR).
The TDR register provides the parallel interface
between the internal bus and the output shift register (see Figure 77).
The RDR register provides the parallel interface
between the input shift register and the internal
bus (see Figure 77).
ST72561
LINSCI SERIAL COMMUNICATION INTERFACE (SCI Mode) (Cont’d)
BAUD RATE REGISTER (SCIBRR)
TR dividing factor
Read/Write
1
Reset Value: 0000 0000 (00h)
7
0
SCP1
SCP0
SCT2
SCT1
SCT0
SCR2
SCR1 SCR0
Note: When LIN slave mode is disabled, the SCIBRR register controls the conventional baud rate
generator.
Bit 7:6= SCP[1:0] First SCI Prescaler
These 2 prescaling bits allow several standard
clock division ranges:
PR Prescaling factor
SCP1
SCP0
1
0
0
3
0
1
4
1
0
13
1
1
Bit 5:3 = SCT[2:0] SCI Transmitter rate divisor
These 3 bits, in conjunction with the SCP1 & SCP0
bits define the total division applied to the bus
clock to yield the transmit rate clock in conventional Baud Rate Generator mode.
SCT2
SCT1
SCT0
0
0
0
2
0
0
1
4
0
1
0
8
0
1
1
16
1
0
0
32
1
0
1
64
1
1
0
128
1
1
1
Bit 2:0 = SCR[2:0] SCI Receiver rate divider.
These 3 bits, in conjunction with the SCP[1:0] bits
define the total division applied to the bus clock to
yield the receive rate clock in conventional Baud
Rate Generator mode.
RR dividing factor
SCR2
SCR1
SCR0
1
0
0
0
2
0
0
1
4
0
1
0
8
0
1
1
16
1
0
0
32
1
0
1
64
1
1
0
128
1
1
1
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LINSCI SERIAL COMMUNICATION INTERFACE (SCI Mode) (Cont’d)
EXTENDED RECEIVE PRESCALER DIVISION
EXTENDED TRANSMIT PRESCALER DIVISION
REGISTER (SCIERPR)
REGISTER (SCIETPR)
Read/Write
Read/Write
Reset Value: 0000 0000 (00 h)
Reset Value:0000 0000 (00h)
7
0
ERPR ERPR ERPR ERPR ERPR ERPR ERPR ERPR
7
6
5
4
3
2
1
0
Bit 7:0 = ERPR[7:0] 8-bit Extended Receive Prescaler Register.
The extended Baud Rate Generator is activated
when a value other than 00h is stored in this register. The clock frequency from the 16 divider (see
Figure 79) is divided by the binary factor set in the
SCIERPR register (in the range 1 to 255).
The extended baud rate generator is not active after a reset.
138/262
7
ETPR
7
0
ETPR
6
ETPR
5
ETPR
4
ETPR
3
ETPR
2
ETPR ETPR
1
0
Bit 7:0 = ETPR[7:0] 8-bit Extended Transmit Prescaler Register.
The extended Baud Rate Generator is activated
when a value other than 00h is stored in this register. The clock frequency from the 16 divider (see
Figure 79) is divided by the binary factor set in the
SCIETPR register (in the range 1 to 255).
The extended baud rate generator is not active after a reset.
Note: In LIN slave mode, the Conventional and
Extended Baud Rate Generators are disabled.
ST72561
LINSCI
SERIAL COMMUNICATION INTERFACE (LIN Mode)
10.7.9 LIN Mode - Functional Description.
Slave
The block diagram of the Serial Control Interface,
Set the LSLV bit in the SCICR3 register to enter
in LIN slave mode is shown in Figure 81.
LIN slave mode. In this case, setting the SBK bit
will have no effect.
It uses 6 registers:
In LIN Slave mode the LIN baud rate generator is
– Three control registers: SCICR1, SCICR2 and
selected instead of the Conventional or Extended
SCICR3
Prescaler. The LIN baud rate generator is com– Two status registers: the SCISR register and the
mon to the transmitter and the receiver.
LHLR register mapped at the SCIERPR address
Then the baud rate can be programmed using
– A baud rate register: LPR mapped at the SCILPR and LPRF registers.
BRR address and an associated fraction register
Note: It is mandatory to set the LIN configuration
LPFR mapped at the SCIETPR address
first before programming LPR and LPRF, because
The bits dedicated to LIN are located in the
the LIN configuration uses a different baud rate
SCICR3. Refer to the register descriptions in Secgenerator from the standard one.
tion 10.7.10for the definitions of each bit.
10.7.9.1 Entering LIN Mode
10.7.9.2 LIN Transmission
To use the LINSCI in LIN mode the following conIn LIN mode the same procedure as in SCI mode
figuration must be set in SCICR3 register:
has to be applied for a LIN transmission.
– Clear the M bit to configure 8-bit word length.
To transmit the LIN Header the proceed as fol– Set the LINE bit.
lows:
Master
– First set the SBK bit in the SCICR2 register to
start transmitting a 13-bit LIN Synch Break
To enter master mode the LSLV bit must be reset
In this case, setting the SBK bit will send 13 low
– reset the SBK bit
bits.
– Load the LIN Synch Field (0x55) in the SCIDR
Then the baud rate can programmed using the
register to request Synch Field transmission
SCIBRR, SCIERPR and SCIETPR registers.
– Wait until the SCIDR is empty (TDRE bit set in
In LIN master mode, the Conventional and / or Exthe SCISR register)
tended Prescaler define the baud rate (as in stand– Load the LIN message Identifier in the SCIDR
ard SCI mode)
register to request Identifier transmission.
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ST72561
Figure 80. LIN characters
8-bit Word length (M bit is reset)
Next Data Character
Data Character
Next
Start
Start
Stop
Bit
Bit Bit0 Bit1 Bit2 Bit3 Bit4 Bit5 Bit6 Bit7 Bit
Start
Bit
Idle Line
LIN Synch Field
LIN Synch Break = 13 low bits
LIN Synch Field
Next
Start
Start
Stop
Bit Bit0 Bit1 Bit2 Bit3 Bit4 Bit5 Bit6 Bit7 Bit
Bit
Measurement for baud rate autosynchronization
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Extra Start
’1’ Bit
ST72561
LINSCI
SERIAL COMMUNICATION INTERFACE (LIN Mode) (Cont’d)
Figure 81. SCI Block Diagram in LIN Slave Mode
Write
Read
(DATA REGISTER) SCIDR
Received Data Register (RDR)
Transmit Data Register (TDR)
TDO
Receive Shift Register
Transmit Shift Register
RDI
SCICR1
R8
TRANSMIT
WAKE
UP
CONTROL
UNIT
T8 SCID M
WAKE PCE
PS PIE
RECEIVER
CONTROL
RECEIVER
CLOCK
SCISR
SCICR2
TIE TCIE RIE ILIE
TE
RE RWU SBK
OR/
TDRE TC RDRF IDLE
LHE NF
FE
PE
SCI
INTERRUPT
CONTROL
TRANSMITTER
CLOCK
fCPU
SCICR3
LIN SLAVE BAUD RATE
AUTO SYNCHRONIZATION
UNIT
LDUM LINE LSLV LASE LHDM LHIE LHDF LSF
SCIBRR
LPR7
LPR0
CONVENTIONAL BAUD RATE
GENERATOR
+
EXTENDED PRESCALER
fCPU
/ LDIV
/16
0
1
LIN SLAVE BAUD RATE GENERATOR
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ST72561
LINSCI
SERIAL COMMUNICATION INTERFACE (LIN Mode) (Cont’d)
10.7.9.3 LIN Reception
Note:
In LIN mode the reception of a byte is the same as
In LIN slave mode, the FE bit detects all frame erin SCI mode but the LINSCI has features for hanror which does not correspond to a break.
dling the LIN Header automatically (identifier deIdentifier Detection (LHDM = 1):
tection) or semiautomatically (Synch Break detecThis case is the same as the previous one except
tion) depending on the LIN Header detection
that the LHDF and the RDRF flags are set only afmode. The detection mode is selected by the
ter the entire header has been received (this is
LHDM bit in the SCICR3.
true whether automatic resynchronization is enaAdditionally, an automatic resynchronization feabled or not). This indicates that the LIN Identifier is
ture can be activated to compensate for any clock
available in the SCIDR register.
deviation, for more details please refer to Section
Notes:
10.7.9.5 "LIN Baudrate".
During LIN Synch Field measurement, the SCI
LIN Header Handling by a Slave
state machine is switched off: no characters are
Depending on the LIN Header detection method
transferred to the data register.
the LINSCI will signal the detection of a LIN HeadLIN Slave parity
er after the LIN Synch Break or after the Identifier
has been successfully received.
In LIN Slave mode (LINE and LSLV bits are set)
LIN parity checking can be enabled by setting the
Note:
PCE bit.
It is recommended to combine the Header detecIn this case, the parity bits of the LIN Identifier
tion function with Mute mode. Putting the LINSCI
Field are checked. The identifier character is recin Mute mode allows the detection of Headers only
ognised as the 3rd received character after a break
and prevents the reception of any other characcharacter (included):
ters.
This mode can be used to wait for the next Header
parity bits
without being interrupted by the data bytes of the
current message in case this message is not relevant for the application.
Synch Break Detection (LHDM = 0):
When a LIN Synch Break is received:
LIN Synch
LIN Synch
Identifier
Field
Break
Field
– The RDRF bit in the SCISR register is set. It indicates that the content of the shift register is
transferred to the SCIDR register, a value of
0x00 is expected for a Break.
The bits involved are the two MSB positions (7th
and 8th bits if M=0; 8th and 9th bits if M=0) of the
– The LHDF flag in the SCICR3 register indicates
identifier character. The check is performed as
that a LIN Synch Break Field has been detected.
specified by the LIN specification:
– An interrupt is generated if the LHIE bit in the
SCICR3 register is set and the I[1:0] bits are
cleared in the CCR register.
parity bits stop bit
start bit
– Then the LIN Synch Field is received and measidentifier bits
ured.
ID0 ID1 ID2 ID3 ID4 ID5 P0 P1
– If automatic resynchronization is enabled (LASE bit = 1), the LIN Synch Field is not transIdentifier Field
ferred to the shift register: there is no need to
clear the RDRF bit.
P0 = ID0 ⊕ ID1 ⊕ ID2 ⊕ ID4
M=0
– If automatic resynchronization is disabled (LAP1 = ID1 ⊕ ID3 ⊕ ID4 ⊕ ID5
SE bit =0), the LIN Synch Field is received as
a normal character and transferred to the
SCIDR register and RDRF is set.
142/262
ST72561
LINSCI
SERIAL COMMUNICATION INTERFACE (LIN Mode) (Cont’d)
10.7.9.4 LIN Error Detection
edge of the Synch Field. Let’s refer to this period
deviation as D:
LIN Header Error Flag
If the LHE flag is set, it means that:
The LIN Header Error Flag indicates that an invalid
LIN Header has been detected.
D > 15.625%
When a LIN Header Error occurs:
If LHE flag is not set, it means that:
– The LHE flag is set
D < 16.40625%
– An interrupt is generated if the RIE bit is set and
If 15.625% ≤ D < 16.40625%, then the flag can
the I[1:0] bits are cleared in the CCR register.
be either set or reset depending on the dephasing between the signal on the RDI line and the
If autosynchronization is enabled (LASE bit =1),
CPU clock.
this can mean that the LIN Synch Field is corrupted, and that the SCI is in a blocked state (LSF bit is
– The second check is based on the measurement
set). The only way to recover is to reset the LSF bit
of each bit time between both edges of the Synch
and then to clear the LHE bit.
Field: this checks that each of these bit times is
large enough compared to the bit time of the cur– The LHE bit is reset by an access to the SCISR
rent baud rate.
register followed by a read of the SCIDR register.
When
LHE is set due to this error then the SCI
LHE/OVR Error Conditions
goes into a blocked state (LSF bit is set).
When Auto Resynchronization is disabled (LASE
LIN Header Time-out Error
bit =0), the LHE flag detects:
When the LIN Identifier Field Detection Method is
– That the received LIN Synch Field is not equal to
used (by configuring LHDM to 1) or when LIN
55h.
auto-resynchronization is enabled (LASE bit=1),
– That an overrun occurred (as in standard SCI
the
LINSCI
automatically
monitors
the
mode)
THEADER_MAX condition given by the LIN protocol.
– Furthermore, if LHDM is set it also detects that a
If the entire Header (up to and including the STOP
LIN Header Reception Timeout occurred (only if
bit of the LIN Identifier Field) is not received within
LHDM is set).
the maximum time limit of 57 bit times then a LIN
Header Error is signalled and the LHE bit is set in
When the LIN auto-resynchronization is enabled
the SCISR register.
(LASE bit=1), the LHE flag detects:
– That the deviation error on the Synch Field is
Figure 82. LIN Header Reception Timeout
outside the LIN specification which allows up to
+/-15.5% of period deviation between the slave
and master oscillators.
LIN Synch
LIN Synch
Identifier
– A LIN Header Reception Timeout occurred.
Field
Break
Field
If THEADER > THEADER_MAX then the LHE flag is
set. Refer to Figure 82. (only if LHDM is set to 1)
THEADER
– An overflow during the Synch Field Measurement, which leads to an overflow of the divider
registers. If LHE is set due to this error then the
The time-out counter is enabled at each break deSCI goes into a blocked state (LSF bit is set).
tection. It is stopped in the following conditions:
– That an overrun occurred on Fields other than
- A LIN Identifier Field has been received
the Synch Field (as in standard SCI mode)
- An LHE error occurred (other than a timeout erDeviation Error on the Synch Field
ror).
- A software reset of LSF bit (transition from high to
The deviation error is checking by comparing the
low) occurred during the analysis of the LIN Synch
current baud rate (relative to the slave oscillator)
Field or
with the received LIN Synch Field (relative to the
master oscillator). Two checks are performed in
If LHE bit is set due to this error during the LIN
parallel:
Synchr Field (if LASE bit = 1) then the SCI goes
into a blocked state (LSF bit is set).
– The first check is based on a measurement between the first falling edge and the last falling
143/262
ST72561
LINSCI
SERIAL COMMUNICATION INTERFACE (LIN Mode) (Cont’d)
If LHE bit is set due to this error during Fields other
Even if no timeout occurs on the LIN Header, it is
than LIN Synch Field or if LASE bit is reset then
possible to have access to the effective LIN headthe current received Header is discarded and the
er Length (THEADER) through the LHL register.
This allows monitoring at software level the
SCI searches for a new Break Field.
TFRAME_MAX condition given by the LIN protocol.
Note on LIN Header Time-out Limit
This feature is only available when LHDM bit =1 or
According to the LIN specification, the maximum
when LASE bit =1.
length of a LIN Header which does not cause a
Mute Mode and Errors
timeout is equal to 1.4*(34 + 1) = 49 TBIT_MASTER.
TBIT_MASTER refers to the master baud rate.
In mute mode when LHDM bit =1, if an LHE error
occurs during the analysis of the LIN Synch Field
When checking this timeout, the slave node is deor if a LIN Header Time-out occurs then the LHE
synchronized for the reception of the LIN Break
bit is set but it doesn’t wake up from mute mode. In
and Synch fields. Consequently, a margin must be
this case, the current header analysis is discarded.
allowed, taking into account the worst case: this
If needed, the software has to reset LSF bit. Then
occurs when the LIN identifier lasts exactly 10
the SCI searches for a new LIN header.
TBIT_MASTER periods. In this case, the LIN Break
and Synch fields last 49-10 = 39TBIT_MASTER periIn mute mode, if a framing error occurs on a data
ods.
(which is not a break), it is discarded and the FE bit
is not set.
Assuming the slave measures these first 39 bits
with a desynchronized clock of 15.5%. This leads
When LHDM bit =1, any LIN header which reto a maximum allowed Header Length of:
spects the following conditions causes a wake up
from mute mode:
39 x (1/0.845) TBIT_MASTER + 10TBIT_MASTER
- A valid LIN Break Field (at least 11 dominant bits
= 56.15 TBIT_SLAVE
followed by a recessive bit)
A margin is provided so that the time-out occurs
- A valid LIN Synch Field (without deviation error)
when the header length is greater than 57
TBIT_SLAVE periods. If it is less than or equal to 57
- A LIN Identifier Field without framing error. Note
TBIT_SLAVE periods, then no timeout occurs.
that a LIN parity error on the LIN Identifier Field
does not prevent wake up from mute mode.
LIN Header Length
- No LIN Header Time-out should occur during
Header reception.
Figure 83. LIN Synch Field Measurement
tCPU = CPU period
tBR = 16.LP.tCPU
tBR = Baud Rate period
SM=Synch Measurement Register (15 bits)
tBR
LIN Synch Field
Next
LIN Synch Break
Extra Start Bit0 Bit1 Bit2 Bit3 Bit4 Bit5 Bit6 Bit7 Stop Start
Bit
Bit
’1’
Bit
Measurement = 8.TBR = SM.tCPU
LPR(n+1)
LPR(n)
LPR = tBR / (16.tCPU) = Rounding (SM / 128)
144/262
ST72561
LINSCI
SERIAL COMMUNICATION INTERFACE (LIN Mode) (Cont’d)
10.7.9.5 LIN Baudrate
mitter are both set to the same value, depending
on the LIN Slave baud rate generator:
Baud rate programming is done by writing a value
in the LPR prescaler or performing an automatic
resynchronization as described below.
fCPU
Automatic Resynchronization
Tx = Rx =
(16*LDIV)
To automatically adjust the baud rate based on
measurement of the LIN Synch Field:
with:
– Write the nominal LIN Prescaler value (usually
LDIV is an unsigned fixed point number. The mandepending on the nominal baud rate) in the
tissa is coded on 8 bits in the LPR register and the
LPFR / LPR registers.
fraction is coded on 4 bits in the LPFR register.
– Set the LASE bit to enable the Auto SynchroniIf LASE bit = 1 then LDIV is automatically updated
zation Unit.
at the end of each LIN Synch Field.
When Auto Synchronization is enabled, after each
Three registers are used internally to manage the
LIN Synch Break, the time duration between 5 fallauto-update of the LIN divider (LDIV):
ing edges on RDI is sampled on fCPU and the re- LDIV_NOM (nominal value written by software at
sult of this measurement is stored in an internal
LPR/LPFR addresses)
15-bit register called SM (not user accessible)
(See Figure 83). Then the LDIV value (and its as- LDIV_MEAS (results of the Field Synch meassociated LPFR and LPR registers) are automatiurement)
cally updated at the end of the fifth falling edge.
- LDIV (used to generate the local baud rate)
During LIN Synch field measurement, the SCI
The control and interactions of these registers is
state machine is stopped and no data is transexplained in Figure 84 and Figure 85. It depends
ferred to the data register.
on the LDUM bit setting (LIN Divider Update Meth10.7.9.6 LIN Slave Baud Rate Generation
od)
In LIN mode, transmission and reception are drivNote:
en by the LIN baud rate generator
As explained in Figure 84 and Figure 85, LDIV
Note: LIN Master mode uses the Extended or
can be updated by two concurrent actions: a
Conventional prescaler register to generate the
transfer from LDIV_MEAS at the end of the LIN
baud rate.
Sync Field and a transfer from LDIV_NOM due
If LINE bit = 1 and LSLV bit = 1 then the Convento a software write of LPR. If both operations
tional and Extended Baud Rate Generators are
occur at the same time, the transfer from
disabled: the baud rate for the receiver and transLDIV_NOM has priority.
145/262
ST72561
LINSCI
SERIAL COMMUNICATION INTERFACE (LIN Mode) (Cont’d)
Figure 84. LDIV Read / Write operations when LDUM=0
Write LPR
Write LPFR
MANT(7:0) FRAC(3:0)
LDIV_NOM
LIN Sync Field
Measurement
Write LPR
MANT(7:0) FRAC(3:0) LDIV_MEAS
Update
at end of
Synch Field
Baud Rate
Generarion
MANT(7:0) FRAC(3:0) LDIV
Read LPR
Read LPFR
Figure 85. LDIV Read / Write operations when LDUM=1
Write LPR
Write LPFR
MANT(7:0) FRAC(3:0)
LDIV_NOM
LIN Sync Field
Measurement
RDRF=1
MANT(7:0) FRAC(3:0) LDIV_MEAS
Update
at end of
Synch Field
MANT(7:0) FRAC(3:0) LDIV
Read LPR
146/262
Read LPFR
Baud Rate
Generarion
ST72561
LINSCI
SERIAL COMMUNICATION INTERFACE (LIN Mode) (Cont’d)
10.7.9.7 LINSCI Clock Tolerance
Consequently, the clock frequency should not vary
more than 6/16 (37.5%) within one bit.
LINSCI Clock Tolerance when unsynchronized
The sampling clock is resynchronized at each start
When LIN slaves are unsynchronized (meaning no
bit, so that when receiving 10 bits (one start bit, 1
characters have been transmitted for a relatively
data byte, 1 stop bit), the clock deviation should
long time), the maximum tolerated deviation of the
not exceed 3.75%.
LINSCI clock is +/-15%.
10.7.9.8 Clock Deviation Causes
If the deviation is within this range then the LIN
Synch Break is detected properly when a new reThe causes which contribute to the total deviation
ception occurs.
are:
This is made possible by the fact that masters
– DTRA: Deviation due to transmitter error.
Note: the transmitter can be either a master or
send 13 low bits for the LIN Synch Break, which
a slave (in case of a slave listening to the recan be interpreted as 11 low bits (13 bits -15% =
sponse of another slave).
11.05) by a “fast” slave and then considered as a
LIN Synch Break. According to the LIN specifica– DMEAS: Error due to the LIN Synch measuretion, a LIN Synch Break is valid when its duration
ment performed by the receiver.
is greater than tSBRKTS = 10. This means that the
– DQUANT: Error due to the baud rate quantisaLIN Synch Break must last at least 11 low bits.
tion of the receiver.
Note: If the period desynchronization of the slave
–
DREC: Deviation of the local oscillator of the
is +15% (slave too slow), the character “00h”
receiver: This deviation can occur during the
which represents a sequence of 9 low bits must
reception of one complete LIN message asnot be interpreted as a break character (9 bits +
suming that the deviation has been compen15% = 10.35). Consequently, a valid LIN Synch
sated at the beginning of the message.
break must last at least 11 low bits.
–
DTCL: Deviation due to the transmission line
LINSCI Clock Tolerance when Synchronized
(generally due to the transceivers)
When synchronization has been performed, folAll the deviations of the system should be added
lowing reception of a LIN Synch Break, the LINSCI,
and compared to the LINSCI clock tolerance:
in LIN mode, has the same clock deviation tolerDTRA + DMEAS +D QUANT + DREC + D TCL < 3.75%
ance as in SCI mode, which is explained below:
During reception, each bit is oversampled 16
times. The mean of the 8th, 9thand 10th samples is
considered as the bit value.
Figure 86. Bit Sampling in Reception Mode
RDI LINE
sampled values
Sample
clock
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
6/16
7/16
7/16
One bit time
147/262
ST72561
LINSCI
SERIAL COMMUNICATION INTERFACE (LIN Mode) (Cont’d)
10.7.9.9 Error due to LIN Synch measurement
Consequently, at a given CPU frequency, the
maximum possible nominal baud rate (LPRMIN)
The LIN Synch Field is measured over eight bit
should
be chosen with respect to the maximum toltimes.
erated deviation given by the equation:
This measurement is performed using a counter
DTRA + 2 / (128*LDIVMIN) + 1 / (2*16*LDIVMIN)
clocked by the CPU clock. The edge detections
+ DREC + DTCL < 3.75%
are performed using the CPU clock cycle.
This leads to a precision of 2 CPU clock cycles for
the measurement which lasts 16*8*LDIV clock cyExample:
cles.
A nominal baud rate of 20Kbits/s at TCPU = 125ns
Consequently, this error (DMEAS) is equal to:
(8MHz) leads to LDIVNOM = 25d.
2 / (128*LDIVMIN).
LDIVMIN = 25 - 0.15*25 = 21.25
LDIVMIN corresponds to the minimum LIN prescalDMEAS = 2 / (128*LDIVMIN) * 100 = 0.00073%
er content, leading to the maximum baud rate, takD
QUANT = 1 / (2*16*LDIVMIN) * 100 = 0.0015%
ing into account the maximum deviation of +/-15%.
10.7.9.10 Error due to Baud Rate Quantisation
LIN Slave systems
The baud rate can be adjusted in steps of 1 / (16 *
LDIV). The worst case occurs when the “real”
For LIN Slave systems (the LINE and LSLV bits
baud rate is in the middle of the step.
are set), receivers wake up by LIN Synch Break or
LIN Identifier detection (depending on the LHDM
This leads to a quantization error (DQUANT) equal
bit).
to 1 / (2*16*LDIVMIN).
Hot Plugging Feature for LIN Slave Nodes
10.7.9.11 Impact of Clock Deviation on
Maximum Baud Rate
In LIN Slave Mute Mode (the LINE, LSLV and
RWU bits are set) it is possible to hot plug to a netThe choice of the nominal baud rate (LDIVNOM)
work during an ongoing communication flow. In
will influence both the quantisation error (DQUANT)
this case the SCI monitors the bus on the RDI line
and the measurement error (D MEAS). The worst
until 11 consecutive dominant bits have been decase occurs for LDIVMIN.
tected and discards all the other bits received.
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ST72561
LINSCI
SERIAL COMMUNICATION INTERFACE (LIN Mode) (Cont’d)
10.7.10 LIN Mode Register Description
framing error is detected (if the stop bit is dominant
(0) and at least one of the other bits is recessive
STATUS REGISTER (SCISR)
(1). It is not set when a break occurs, the LHDF bit
Read Only
is used instead as a break flag (if the LHDM bit=0).
Reset Value: 1100 0000 (C0h)
It is cleared by a software sequence (an access to
the SCISR register followed by a read to the
7
0
SCIDR register).
0: No Framing error
TDRE
TC
RDRF IDLE
LHE
NF
FE
PE
1: Framing error detected
Bits 7:4 = Same function as in SCI mode, please
refer to Section 10.7.8 "SCI Mode Register Description".
Bit 3 = LHE LIN Header Error.
During LIN Header this bit signals three error
types:
– The LIN Synch Field is corrupted and the SCI is
blocked in LIN Synch State (LSF bit=1).
– A timeout occurred during LIN Header reception
– An overrun error was detected on one of the
header field (see OR bit description in Section
10.7.8 "SCI Mode Register Description")).
An interrupt is generated if RIE=1 in the SCICR2
register. If blocked in the LIN Synch State, the LSF
bit must first be reset (to exit LIN Synch Field state
and then to be able to clear LHE flag). Then it is
cleared by the following software sequence : an
access to the SCISR register followed by a read to
the SCIDR register.
0: No LIN Header error
1: LIN Header error detected
Note:
Apart from the LIN Header this bit signals an Overrun Error as in SCI mode, (see description in Section 10.7.8 "SCI Mode Register Description")
Bit 2 = NF Noise flag
In LIN Master mode (LINE bit = 1 and LSLV bit = 0)
this bit has the same function as in SCI mode,
please refer to Section 10.7.8 "SCI Mode Register
Description"
In LIN Slave mode (LINE bit = 1 and LSLV bit = 1)
this bit has no meaning.
Bit 0 = PE Parity error.
This bit is set by hardware when a LIN parity error
occurs (if the PCE bit is set) in receiver mode. It is
cleared by a software sequence (a read to the status register followed by an access to the SCIDR
data register). An interrupt is generated if PIE=1 in
the SCICR1 register.
0: No LIN parity error
1: LIN Parity error detected
CONTROL REGISTER 1 (SCICR1)
Read/Write
Reset Value: x000 0000 (x0h)
7
R8
0
T8
SCID
M
WAKE
PCE
PS
PIE
Bits 7:3 = Same function as in SCI mode, please
refer to Section 10.7.8 "SCI Mode Register Description".
Bit 2 = PCE Parity control enable.
This bit is set and cleared by software. It selects
the hardware parity control for LIN identifier parity
check.
0: Parity control disabled
1: Parity control enabled
When a parity error occurs, the PE bit in the
SCISR register is set.
Bit 1 = Reserved
Bit 0 = Same function as in SCI mode, please refer
to Section 10.7.8 "SCI Mode Register Description".
Bit 1 = Bit 1 = FE Framing error.
In LIN slave mode, this bit is set only when a real
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ST72561
LINSCI
SERIAL COMMUNICATION INTERFACE (LIN Mode) (Cont’d)
CONTROL REGISTER 2 (SCICR2)
1: LDIV is updated at the next received character
Read/Write
(when RDRF=1) after a write to the LPR register
Reset Value: 0000 0000 (00 h)
Notes:
7
0
- If no write to LPR is performed between the setting of LDUM bit and the reception of the next
character, LDIV will be updated with the old value.
TIE
TCIE
RIE
ILIE
TE
RE
RWU
SBK
- After LDUM has been set, it is possible to reset
the LDUM bit by software. In this case, LDIV can
Bits 7:2 Same function as in SCI mode, please rebe modified by writing into LPR / LPFR registers.
fer to Section 10.7.8 "SCI Mode Register Description".
Bit 1 = RWU Receiver wake-up.
This bit determines if the SCI is in mute mode or
not. It is set and cleared by software and can be
cleared by hardware when a wake-up sequence is
recognized.
0: Receiver in active mode
1: Receiver in mute mode
Notes:
– Mute mode is recommended for detecting only
the Header and avoiding the reception of any
other characters. For more details please refer to
Section 10.7.9.3 "LIN Reception".
– In LIN slave mode, when RDRF is set, the software can not set or clear the RWU bit.
Bit 0 = SBK Send break.
This bit set is used to send break characters. It is
set and cleared by software.
0: No break character is transmitted
1: Break characters are transmitted
Note: If the SBK bit is set to “1” and then to “0”, the
transmitter will send a BREAK word at the end of
the current word.
CONTROL REGISTER 3 (SCICR3)
Read/Write
Reset Value: 0000 0000 (00h)
7
LDUM LINE
0
LSLV
LASE
LHDM
LHIE LHDF
LSF
Bit 7= LDUM LIN Divider Update Method.
This bit is set and cleared by software and is also
cleared by hardware (when RDRF=1). It is only
used in LIN Slave mode. It determines how the LIN
Divider can be updated by software.
0: LDIV is updated as soon as LPR is written (if no
Auto Synchronization update occurs at the
same time).
150/262
Bit 6:5 = LINE, LSLV LIN Mode Enable Bits.
These bits configure the LIN mode:
LINE
LSLV
Meaning
0
x
LIN mode disabled
1
0
LIN Master Mode
1
1
LIN Slave Mode
The LIN Master configuration enables:
The capability to send LIN Synch Breaks (13 low
bits) using the SBK bit in the SCICR2 register.
The LIN Slave configuration enables:
– The LIN Slave Baud Rate generator. The LIN
Divider (LDIV) is then represented by the LPR
and LPFR registers. The LPR and LPFR registers are read/write accessible at the address
of the SCIBRR register and the address of the
SCIETPR register
– Management of LIN Headers.
– LIN Synch Break detection (11-bit dominant).
– LIN Wake-Up method (see LHDM bit) instead
of the normal SCI Wake-Up method.
– Inhibition of Break transmission capability
(SBK has no effect)
– LIN Parity Checking (in conjunction with the
PCE bit)
Bit 4 = LASE LIN Auto Synch Enable.
This bit enables the Auto Synch Unit (ASU). It is
set and cleared by software. It is only usable in LIN
Slave mode.
0: Auto Synch Unit disabled
1: Auto Synch Unit enabled.
Bit 3 = LHDM LIN Header Detection Method
This bit is set and cleared by software. It is only usable in LIN Slave mode. It enables the Header Detection Method. In addition if the RWU bit in the
ST72561
LINSCI
SERIAL COMMUNICATION INTERFACE (LIN Mode) (Cont’d)
SCICR2 register is set, the LHDM bit selects the
Figure 87. LSF bit set and clear
Wake-Up method (replacing the WAKE bit).
11 dominant bits
parity bits
0: LIN Synch Break Detection Method
1: LIN Identifier Field Detection Method
LSF bit
Bit 2 = LHIE LIN Header Interrupt Enable
This bit is set and cleared by software. It is only usable in LIN Slave mode.
0: LIN Header Interrupt is inhibited.
1: An SCI interrupt is generated whenever
LHDF=1.
Bit 1= LHDF LIN Header Detection Flag
This bit is set by hardware when a LIN Header is
detected and cleared by a software sequence (an
access to the SCISR register followed by a read of
the SCICR3 register). It is only usable in LIN Slave
mode.
0: No LIN Header detected.
1: LIN Header detected.
Notes: The header detection method depends on
the LHDM bit:
– If LHDM=0, a header is detected as a LIN
Synch Break.
– If LHDM=1, a header is detected as a LIN
Identifier, meaning that a LIN Synch Break
Field + a LIN Synch Field + a LIN Identifier
Field have been consecutively received.
Bit 0= LSF LIN Synch Field State
This bit indicates that the LIN Synch Field is being
analyzed. It is only used in LIN Slave mode. In
Auto Synchronization Mode (LASE bit=1), when
the SCI is in the LIN Synch Field State it waits or
counts the falling edges on the RDI line.
It is set by hardware as soon as a LIN Synch Break
is detected and cleared by hardware when the LIN
Synch Field analysis is finished (See Figure 87).
This bit can also be cleared by software to exit LIN
Synch State and return to idle mode.
0: The current character is not the LIN Synch Field
1: LIN Synch Field State (LIN Synch Field undergoing analysis)
LIN Synch
Break
LIN Synch
Field
Identifier
Field
LIN DIVIDER REGISTERS
LDIV is coded using the two registers LPR and LPFR. In LIN Slave mode, the LPR register is accessible at the address of the SCIBRR register and
the LPFR register is accessible at the address of
the SCIETPR register.
LIN PRESCALER REGISTER (LPR)
Read/Write
Reset Value: 0000 0000 (00h)
7
LPR7
0
LPR6
LPR5
LPR4
LPR3
LPR2
LPR1
LPR0
LPR[7:0] LIN Prescaler (mantissa of LDIV)
These 8 bits define the value of the mantissa of the
LIN Divider (LDIV):
LPR[7:0]
Rounded Mantissa (LDIV)
00h
SCI clock disabled
01h
1
...
...
FEh
254
FFh
255
Caution: LPR and LPFR registers have different
meanings when reading or writing to them. Consequently bit manipulation instructions (BRES or
BSET) should never be used to modify the
LPR[7:0] bits, or the LPFR[3:0] bits.
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LINSCI
SERIAL COMMUNICATION INTERFACE (LIN Mode) (Cont’d)
LIN PRESCALER FRACTION REGISTER
will effectively update LDIV and so the clock gen(LPFR)
eration.
Read/Write
2. In LIN Slave mode, if the LPR[7:0] register is
Reset Value: 0000 0000 (00h)
equal to 00h, the transceiver and receiver input
clocks are switched off.
7
0
0
0
0
0
LPFR
3
LPFR
2
LPFR
1
LPFR
0
Bits 7:4= Reserved.
Bits 3:0 = LPFR[3:0] Fraction of LDIV
These 4 bits define the fraction of the LIN Divider
(LDIV):
LPFR[3:0]
Fraction (LDIV)
0h
0
1h
1/16
...
...
Eh
14/16
Fh
15/16
1. When initializing LDIV, the LPFR register must
be written first. Then, the write to the LPR register
152/262
Examples of LDIV coding:
Example 1: LPR = 27d and LPFR = 12d
This leads to:
Mantissa (LDIV) = 27d
Fraction (LDIV) = 12/16 = 0.75d
Therefore LDIV = 27.75d
Example 2: LDIV = 25.62d
This leads to:
LPFR = rounded(16*0.62d)
= rounded(9.92d) = 10d = Ah
LPR = mantissa (25.620d) = 25d = 1Bh
Example 3: LDIV = 25.99d
This leads to:
LPFR = rounded(16*0.99d)
= rounded(15.84d) = 16d
ST72561
LINSCI
SERIAL COMMUNICATION INTERFACE (LIN Mode) (Cont’d)
LIN HEADER LENGTH REGISTER (LHLR)
LHL[1:0]
Read Only
0h
Reset Value: 0000 0000 (00 h).
7
0
LHL7
LHL6
LHL5
LHL4
LHL3
LHL2
LHL1
LHL0
Note: In LIN Slave mode when LASE = 1 or LHDM
= 1, the LHLR register is accessible at the address
of the SCIERPR register.
Otherwise this register is always read as 00h.
Bit 7:0 = LHL[7:0] LIN Header Length.
This is a read-only register, which is updated by
hardware if one of the following conditions occurs:
- After each break detection, it is loaded with
“FFh”.
- If a timeout occurs on THEADER, it is loaded with
00h.
- After every successful LIN Header reception (at
the same time than the setting of LHDF bit), it is
loaded with a value (LHL) which gives access to
the number of bit times of the LIN header length
(THEADER). The coding of this value is explained
below:
LHL Coding:
THEADER_MAX = 57
LHL(7:2) represents the mantissa of (57 - THEADER)
LHL(1:0) represents the fraction (57 - THEADER)
Mantissa
(57 - THEADER)
Mantissa
(THEADER )
0h
0
57
1h
1
56
...
LHL[7:2]
...
...
39h
56
1
3Ah
57
0
3Bh
58
Never Occurs
...
...
...
3Eh
62
Never Occurs
3Fh
63
Initial value
Fraction (57 - THEADER)
0
1h
1/4
2h
1/2
3h
3/4
Example of LHL coding:
Example 1: LHL = 33h = 001100 11b
LHL(7:3) = 1100b = 12d
LHL(1:0) = 11b = 3d
This leads to:
Mantissa (57 - THEADER) = 12d
Fraction (57 - THEADER) = 3/4 = 0.75
Therefore:
(57 - THEADER) = 12.75d
and THEADER = 44.25d
Example 2:
57 - THEADER = 36.21d
LHL(1:0) = rounded(4*0.21d) = 1d
LHL(7:2) = Mantissa (36.21d) = 36d = 24h
Therefore LHL(7:0) = 10010001 = 91h
Example 3:
57 - THEADER = 36.90d
LHL(1:0) = rounded(4*0.90d) = 4d
The carry must be propagated to the matissa :
LHL(7:2) = Mantissa (36.90d) + 1= 37d =
Therefore LHL(7:0) = 10110000= A0h
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LINSCI SERIAL COMMUNICATION INTERFACE (LIN Master/Slave) (Cont’d)
Table 23. LINSCI1 Register Map and Reset Values
Addr.
(Hex.)
Register Name
7
6
5
4
3
2
1
0
48
SCI1SR
Reset Value
TDRE
1
TC
1
RDRF
0
IDLE
0
OR/LHE
0
NF
0
FE
0
PE
0
49
SCI1DR
Reset Value
DR7
-
DR6
-
DR5
-
DR4
-
DR3
-
DR2
-
DR1
-
DR0
-
4A
SCI1BRR
LPR (LIN Slave Mode)
Reset Value
SCP1
LPR7
0
SCP0
LPR6
0
SCT2
LPR5
0
SCT1
LPR4
0
SCT0
LPR3
0
SCR2
LPR2
0
SCR1
LPR1
0
SCR0
LPR0
0
4B
SCI1CR1
Reset Value
R8
x
T8
0
SCID
0
M
0
WAKE
0
PCE
0
PS
0
PIE
0
4C
SCI1CR2
Reset Value
TIE
0
TCIE
0
RIE
0
ILIE
0
TE
0
RE
0
RWU
0
SBK
0
4D
SCI1CR3
Reset Value
LDUM
0
LINE
0
LSLV
0
LASE
0
LHDM
0
LHIE
0
LHDF
0
LSF
0
4E
SCI1ERPR
LHLR (LIN Slave Mode)
Reset Value
ERPR7
LHL7
0
ERPR6
LHL6
0
ERPR5
LHL5
0
ERPR4
LHL4
0
ERPR3
LHL3
0
ERPR2
LHL2
0
ERPR1
LHL1
0
ERPR0
LHL0
0
4F
SCI1ETPR
LPFR (LIN Slave Mode)
Reset Value
ETPR7
0
0
ETPR6
0
0
ETPR5
0
0
ETPR4
0
0
ETPR3
LPFR3
0
ETPR2
LPFR2
0
ETPR1
LPFR1
0
ETPR0
LPFR0
0
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ST72561
10.8 LINSCI SERIAL COMMUNICATION INTERFACE (LIN Master Only)
10.8.1 Introduction
The Serial Communications Interface (SCI) offers
a flexible means of full-duplex data exchange with
external equipment requiring an industry standard
NRZ asynchronous serial data format. The SCI offers a very wide range of baud rates using two
baud rate generator systems.
10.8.2 Main Features
■ Full duplex, asynchronous communications
■ NRZ standard format (Mark/Space)
■ Dual baud rate generator systems
■ Independently
programmable transmit and
receive baud rates up to 500K baud.
■ Programmable data word length (8 or 9 bits)
■ Receive buffer full, Transmit buffer empty and
End of Transmission flags
■ Two receiver wake-up modes:
– Address bit (MSB)
– Idle line
■ Muting function for multiprocessor configurations
■ Separate enable bits for Transmitter and
Receiver
■ Four error detection flags:
– Overrun error
– Noise error
– Frame error
– Parity error
■ Five interrupt sources with flags:
– Transmit data register empty
– Transmission complete
– Receive data register full
– Idle line received
– Overrun error detected
■ Transmitter clock output
■ Parity control:
– Transmits parity bit
– Checks parity of received data byte
■ Reduced power consumption mode
■ LIN Synch Break send capability
10.8.3 General Description
The interface is externally connected to another
device by three pins (see Figure 88). Any SCI bidirectional communication requires a minimum of
two pins: Receive Data In (RDI) and Transmit Data
Out (TDO) :
– SCLK: Transmitter clock output. This pin outputs
the transmitter data clock for synchronous transmission (no clock pulses on start bit and stop bit,
and a software option to send a clock pulse on
the last data bit). This can be used to control peripherals that have shift registers (e.g. LCD drivers). The clock phase and polarity are software
programmable.
– TDO: Transmit Data Output. When the transmitter is disabled, the output pin returns to its I/O
port configuration. When the transmitter is enabled and nothing is to be transmitted, the TDO
pin is at high level.
– RDI: Receive Data Input is the serial data input.
Oversampling techniques are used for data recovery by discriminating between valid incoming
data and noise.
Through these pins, serial data is transmitted and
received as frames comprising:
– An Idle Line prior to transmission or reception
– A start bit
– A data word (8 or 9 bits) least significant bit first
– A Stop bit indicating that the frame is complete.
This interface uses two types of baud rate generator:
– A conventional type for commonly-used baud
rates,
– An extended type with a prescaler offering a very
wide range of baud rates even with non-standard
oscillator frequencies.
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SERIAL COMMUNICATION INTERFACE (LIN Master Only) (Cont’d)
Figure 88SCI Block Diagram
Write
Read
(DATA REGISTER) SCIDR
Received Data Register (RDR)
Transmit Data Register (TDR)
TDO
Received Shift Register
Transmit Shift Register
RDI
LINE
-
-
T8
SCID
CLKEN CPOL CPHA LBCL
SCICR3
CLOCK EXTRACTION
SCLK
PHASE AND POLARITY
CONTROL
R8
TRANSMIT
WAKE
UP
CONTROL
UNIT
M
WAKE PCE
PS
SCICR1
PIE
RECEIVER
CLOCK
RECEIVER
CONTROL
SCISR
SCICR2
TIE TCIE RIE
ILIE
TE
RE RWU SBK
TDRE TC RDRF IDLE OR
NF
FE
SCI
INTERRUPT
CONTROL
TRANSMITTER
CLOCK
TRANSMITTER RATE
fCPU
CONTROL
/16
/PR
SCIBRR
SCP1 SCP0 SCT2 SCT1 SCT0 SCR2 SCR1SCR0
RECEIVER RATE
CONTROL
CONVENTIONAL BAUD RATE GENERATOR
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PE
ST72561
LINSCI
SERIAL COMMUNICATION INTERFACE (LIN Master Only) (Cont’d)
10.8.4 Functional Description
10.8.4.1 Serial Data Format
The block diagram of the Serial Control Interface,
Word length may be selected as being either 8 or 9
is shown in Figure 88. It contains 7 dedicated regbits by programming the M bit in the SCICR1 registers:
ister (see Figure 89).
– Three control registers (SCICR1, SCICR2 &
The TDO pin is in low state during the start bit.
SCICR3)
The TDO pin is in high state during the stop bit.
– A status register (SCISR)
An Idle character is interpreted as an entire frame
– A baud rate register (SCIBRR)
of “1”s followed by the start bit of the next frame
which contains data.
– An extended prescaler receiver register (SCIERPR)
A Break character is interpreted on receiving “0”s
for some multiple of the frame period. At the end of
– An extended prescaler transmitter register (SCIthe last break frame the transmitter inserts an exETPR)
tra “1” bit to acknowledge the start bit.
Refer to the register descriptions in Section
Transmission and reception are driven by their
10.7.8for the definitions of each bit.
own baud rate generator.
Figure 89. Word length programming
9-bit Word length (M bit is set)
Possible
Parity
Bit
Data Frame
Start
Bit
Bit0
Bit2
Bit1
Bit3
Bit4
Bit5
Bit6
Bit7
Bit8
CLOCK
Next Data Frame
Next
Stop Start
Bit
Bit
**
Idle Frame
Start
Bit
Break Frame
Extra
’1’
Start
Bit
** LBCL bit controls last data clock pulse
8-bit Word length (M bit is reset)
Possible
Parity
Bit
Data Frame
Start
Bit
Bit0
Bit1
Bit2
Bit3
CLOCK
Bit4
Bit5
Bit6
Bit7
Next Data Frame
Stop
Bit
Next
Start
Bit
****
**
Idle Frame
Start
Bit
Break Frame
Extra Start
Bit
’1’
** LBCL bit controls last data clock pulse
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SERIAL COMMUNICATION INTERFACE (LIN Master Only) (Cont’d)
10.8.4.2 Transmitter
When a frame transmission is complete (after the
stop bit or after the break frame) the TC bit is set
The transmitter can send data words of either 8 or
and an interrupt is generated if the TCIE is set and
9 bits depending on the M bit status. When the M
the I bit is cleared in the CCR register.
bit is set, word length is 9 bits and the 9th bit (the
MSB) has to be stored in the T8 bit in the SCICR1
Clearing the TC bit is performed by the following
register.
software sequence:
1. An access to the SCISR register
When the transmit enable bit (TE) is set, the data
2. A write to the SCIDR register
in the transmit shift register is output on the TDO
pin and the corresponding clock pulses are output
Note: The TDRE and TC bits are cleared by the
on the SCLK pin.
same software sequence.
Character Transmission
Break Characters
During an SCI transmission, data shifts out least
Setting the SBK bit loads the shift register with a
significant bit first on the TDO pin. In this mode,
break character. The break frame length depends
the SCIDR register consists of a buffer (TDR) beon the M bit (see Figure 89).
tween the internal bus and the transmit shift regisAs long as the SBK bit is set, the SCI send break
ter (see Figure 89).
frames to the TDO pin. After clearing this bit by
Procedure
software the SCI insert a logic 1 bit at the end of
the last break frame to guarantee the recognition
– Select the M bit to define the word length.
of the start bit of the next frame.
– Select the desired baud rate using the SCIBRR
Idle Characters
and the SCIETPR registers.
Setting the TE bit drives the SCI to send an idle
– Set the TE bit to send an idle frame as first transframe before the first data frame.
mission.
Clearing and then setting the TE bit during a trans– Access the SCISR register and write the data to
mission sends an idle frame after the current word.
send in the SCIDR register (this sequence clears
the TDRE bit). Repeat this sequence for each
Note: Resetting and setting the TE bit causes the
data to be transmitted.
data in the TDR register to be lost. Therefore the
best time to toggle the TE bit is when the TDRE bit
Clearing the TDRE bit is always performed by the
is set i.e. before writing the next byte in the SCIDR.
following software sequence:
1. An access to the SCISR register
LIN Transmission
2. A write to the SCIDR register
The same procedure has to be applied for LIN
The TDRE bit is set by hardware and it indicates:
Master transmission with the following differences:
– The TDR register is empty.
– Clear the M bit to configure 8-bit word length.
– The data transfer is beginning.
– Set the LINE bit to enter LIN master mode. In this
case, setting the SBK bit will send 13 low bits.
– The next data can be written in the SCIDR register without overwriting the previous data.
This flag generates an interrupt if the TIE bit is set
and the I bit is cleared in the CCR register.
When a transmission is taking place, a write instruction to the SCIDR register stores the data in
the TDR register and which is copied in the shift
register at the end of the current transmission.
When no transmission is taking place, a write instruction to the SCIDR register places the data directly in the shift register, the data transmission
starts, and the TDRE bit is immediately set.
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LINSCI
SERIAL COMMUNICATION INTERFACE (LIN Master Only) (Cont’d)
10.8.4.3 Receiver
Overrun Error
The SCI can receive data words of either 8 or 9
An overrun error occurs when a character is rebits. When the M bit is set, word length is 9 bits
ceived when RDRF has not been reset. Data can
and the MSB is stored in the R8 bit in the SCICR1
not be transferred from the shift register to the
register.
RDR register until the RDRF bit is cleared.
Character reception
When a overrun error occurs:
During a SCI reception, data shifts in least signifi– The OR bit is set.
cant bit first through the RDI pin. In this mode, the
– The RDR content will not be lost.
SCIDR register consists or a buffer (RDR) be– The shift register will be overwritten.
tween the internal bus and the received shift register (see Figure 88).
– An interrupt is generated if the RIE bit is set and
the I bit is cleared in the CCR register.
Procedure
The OR bit is reset by an access to the SCISR reg– Select the M bit to define the word length.
ister followed by a SCIDR register read operation.
– Select the desired baud rate using the SCIBRR
Noise Error
and the SCIERPR registers.
Oversampling techniques are used for data recov– Set the RE bit, this enables the receiver which
ery by discriminating between valid incoming data
begins searching for a start bit.
and noise.
When a character is received:
When noise is detected in a frame:
– The RDRF bit is set. It indicates that the content
– The NF is set at the rising edge of the RDRF bit.
of the shift register is transferred to the RDR.
– Data is transferred from the Shift register to the
– An interrupt is generated if the RIE bit is set and
SCIDR register.
the I bit is cleared in the CCR register.
– No interrupt is generated. However this bit rises
– The error flags can be set if a frame error, noise
at the same time as the RDRF bit which itself
or an overrun error has been detected during regenerates an interrupt.
ception.
The NF bit is reset by a SCISR register read operClearing the RDRF bit is performed by the following
ation followed by a SCIDR register read operation.
software sequence done by:
Framing Error
1. An access to the SCISR register
A framing error is detected when:
2. A read to the SCIDR register.
– The stop bit is not recognized on reception at the
The RDRF bit must be cleared before the end of the
expected time, following either a de-synchronireception of the next character to avoid an overrun
zation or excessive noise.
error.
– A break is received.
Break Character
When the framing error is detected:
When a break character is received, the SPI handles it as a framing error.
– the FE bit is set by hardware
Idle Character
– Data is transferred from the Shift register to the
SCIDR register.
When an idle frame is detected, there is the same
procedure as a data received character plus an in– No interrupt is generated. However this bit rises
terrupt if the ILIE bit is set and the I bit is cleared in
at the same time as the RDRF bit which itself
the CCR register.
generates an interrupt.
The FE bit is reset by a SCISR register read operation followed by a SCIDR register read operation.
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ST72561
LINSCI
SERIAL COMMUNICATION INTERFACE (LIN Master Only) (Cont’d)
Figure 90. SCI Baud Rate and Extended Prescaler Block Diagram
TRANSMITTER
CLOCK
EXTENDED PRESCALER TRANSMITTER RATE CONTROL
SCIETPR
EXTENDED TRANSMITTER PRESCALER REGISTER
SCIERPR
EXTENDED RECEIVER PRESCALER REGISTER
RECEIVER
CLOCK
EXTENDED PRESCALER RECEIVER RATE CONTROL
EXTENDED PRESCALER
fCPU
TRANSMITTER RATE
CONTROL
/16
/PR
SCIBRR
SCP1 SCP0 SCT2 SCT1 SCT0 SCR2 SCR1SCR0
RECEIVER RATE
CONTROL
CONVENTIONAL BAUD RATE GENERATOR
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LINSCI
SERIAL COMMUNICATION INTERFACE (LIN Master Only) (Cont’d)
10.8.4.4 Conventional Baud Rate Generation
other than zero. The baud rates are calculated as
follows:
The baud rate for the receiver and transmitter (Rx
and Tx) are set independently and calculated as
fCPU
fCPU
follows
Rx =
Tx =
:
16*ERPR*(PR*RR)
16 ETPR*(PR*TR)
*
Tx =
fCPU
(16*PR)*TR
Rx =
fCPU
(16*PR)*RR
with:
PR = 1, 3, 4 or 13 (see SCP[1:0] bits)
TR = 1, 2, 4, 8, 16, 32, 64,128
(see SCT[2:0] bits)
RR = 1, 2, 4, 8, 16, 32, 64,128
(see SCR[2:0] bits)
All these bits are in the SCIBRR register.
Example: If fCPU is 8 MHz (normal mode) and if
PR=13 and TR=RR=1, the transmit and receive
baud rates are 38400 baud.
Note: the baud rate registers MUST NOT be
changed while the transmitter or the receiver is enabled.
10.8.4.5 Extended Baud Rate Generation
The extended prescaler option gives a very fine
tuning on the baud rate, using a 255 value prescaler, whereas the conventional Baud Rate Generator retains industry standard software compatibility.
The extended baud rate generator block diagram
is described in the Figure 90.
The output clock rate sent to the transmitter or to
the receiver will be the output from the 16 divider
divided by a factor ranging from 1 to 255 set in the
SCIERPR or the SCIETPR register.
Note: the extended prescaler is activated by setting the SCIETPR or SCIERPR register to a value
with:
ETPR = 1,..,255 (see SCIETPR register)
ERPR = 1,.. 255 (see SCIERPR register)
10.8.4.6 Receiver Muting and Wake-up Feature
In multiprocessor configurations it is often desirable that only the intended message recipient
should actively receive the full message contents,
thus reducing redundant SCI service overhead for
all non addressed receivers.
The non addressed devices may be placed in
sleep mode by means of the muting function.
Setting the RWU bit by software puts the SCI in
sleep mode:
All the reception status bits can not be set.
All the receive interrupts are inhibited.
A muted receiver may be awakened by one of the
following two ways:
– by Idle Line detection if the WAKE bit is reset,
– by Address Mark detection if the WAKE bit is set.
Receiver wakes-up by Idle Line detection when
the Receive line has recognised an Idle Frame.
Then the RWU bit is reset by hardware but the
IDLE bit is not set.
Receiver wakes-up by Address Mark detection
when it received a “1” as the most significant bit of
a word, thus indicating that the message is an address. The reception of this particular word wakes
up the receiver, resets the RWU bit and sets the
RDRF bit, which allows the receiver to receive this
word normally and to use it as an address word.
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LINSCI
SERIAL COMMUNICATION INTERFACE (LIN Master Only) (Cont’d)
10.8.4.7 Parity control
even number of “1s” if even parity is selected
(PS=0) or an odd number of “1s” if odd parity is seParity control (generation of parity bit in trasmislected (PS=1). If the parity check fails, the PE flag
sion and and parity chencking in reception) can be
is set in the SCISR register and an interrupt is genenabled by setting the PCE bit in the SCICR1 regerated if PIE is set in the SCICR1 register.
ister. Depending on the frame length defined by
the M bit, the possible SCI frame formats are as
listed in Table 24.
10.8.5 Low Power Modes
Table 24. Frame Formats
M bit
0
0
1
1
PCE bit
0
1
0
1
SCI frame
| SB | 8 bit data | STB |
| SB | 7-bit data | PB | STB |
| SB | 9-bit data | STB |
| SB | 8-bit data PB | STB |
Legend:
SB : Start Bit
STB : Stop Bit
PB : Parity Bit
Note: In case of wake up by an address mark, the
MSB bit of the data is taken into account and not
the parity bit
Even parity: the parity bit is calculated to obtain
an even number of “1s” inside the frame made of
the 7 or 8 LSB bits (depending on whether M is
equal to 0 or 1) and the parity bit.
Ex: data=00110101; 4 bits set => parity bit will be
0 if even parity is selected (PS bit = 0).
Odd parity: the parity bit is calculated to obtain an
odd number of “1s” inside the frame made of the 7
or 8 LSB bits (depending on whether M is equal to
0 or 1) and the parity bit.
Ex: data=00110101; 4 bits set => parity bit will be
1 if odd parity is selected (PS bit = 1).
Transmission mode: If the PCE bit is set then the
MSB bit of the data written in the data register is
not transmitted but is changed by the parity bit.
Reception mode: If the PCE bit is set then the interface checks if the received data byte has an
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Mode
Description
No effect on SCI.
WAIT
SCI interrupts cause the device to exit
from Wait mode.
SCI registers are frozen.
HALT
In Halt mode, the SCI stops transmitting/receiving until Halt mode is exited.
10.8.6 Interrupts
Interrupt Event
Enable Exit
Event
Control from
Flag
Bit
Wait
Transmit Data Register
TDRE
Empty
Transmission ComTC
plete
Received Data Ready
RDRF
to be Read
Overrun Error Detected OR
Idle Line Detected
IDLE
Parity Error
PE
Exit
from
Halt
TIE
Yes
No
TCIE
Yes
No
Yes
No
Yes
Yes
Yes
No
No
No
RIE
ILIE
PIE
The SCI interrupt events are connected to the
same interrupt vector.
These events generate an interrupt if the corresponding Enable Control Bit is set and the interrupt mask in the CC register is reset (RIM instruction).
ST72561
LINSCI
SERIAL COMMUNICATION INTERFACE (LIN Master Only) (Cont’d)
10.8.7 SCI Synchronous Transmission
These options allow the user to serially control peripherals which consist of shift registers, without
The SCI transmitter allows the user to control a
losing any functions of the SCI transmitter which
one way synchronous serial transmission. The
can still talk to other SCI receivers. These options
SCLK pin is the output of the SCI transmitter clock.
do not affect the SCI receiver which is independNo clock pulses are sent to the SCLK pin during
ent from the transmitter.
start bit and stop bit. Depending on the state of the
LBCL bit in the SCICR3 register clock pulses will
Note: The SCLK pin works in conjunction with the
or will not be generated during the last valid data
TDO pin. When the SCI transmitter is disabled (TE
bit (address mark). The CPOL bit in the SCICR3
and RE= 0), the SCLK and TDO pins go into high
register allows the user to select the clock polarity,
impedance state.
and the CPHA bit in the SCICR3 register allows
Note: The LBCL, CPOL and CPHA bits have to be
the user to select the phase of the external clock
selected before enabling the transmitter to ensure
(see Figure 91, Figure 92 & Figure 93).
that the clock pulses function correctly. These bits
During idle, preamble and send break, the external
should not be changed while the transmitter is enSCLK clock is not activated.
abled.
Figure 91. SCI Example of synchronous & asynchronous transmission
RDI
TDO
Data out
Data in
Asynchronous
(e.g. Modem)
Data in
Clock
Enable
Synchronous
(e.g. shift register)
SCI
SCLK
Output port
163/262
ST72561
LINSCI
SERIAL COMMUNICATION INTERFACE (LIN Master Only) (Cont’d)
Figure 92. SCI Data clock timing diagram (M=0)
Idle or next
Idle or preceding
Start
transmission
Stop
M=0 (8 data bits)
Clock (CPOL=0, CPHA=0)
transmission
*
Clock (CPOL=0, CPHA=1)
*
Clock (CPOL=1, CPHA=0)
*
*
Clock (CPOL=1, CPHA=1)
Data
0
Start
1
2
3
4
5
6
7
MSB Stop
LSB
* LBCL bit controls last data clock pulse
Figure 93. SCI Data clock timing diagram (M=1)
Idle or preceding
Start
transmission
M=1 (9 data bits)
Stop
Clock (CPOL=0, CPHA=0)
Idle or next
transmission
*
Clock (CPOL=0, CPHA=1)
*
Clock (CPOL=1, CPHA=0)
*
*
Clock (CPOL=1, CPHA=1)
Data
0
Start
LSB
1
2
3
4
5
6
7
8
MSB Stop
* LBCL bit controls last data clock pulse
164/262
ST72561
LINSCI
SERIAL COMMUNICATION INTERFACE (LIN Master Only) (Cont’d)
10.8.8 Register Description
Note: The IDLE bit will not be set again until the
RDRF bit has been set itself (i.e. a new idle line ocSTATUS REGISTER (SCISR)
curs).
Read Only
Reset Value: 1100 0000 (C0h)
Bit 3 = OR Overrun error.
7
0
This bit is set by hardware when the word currently
being received in the shift register is ready to be
TDRE
TC
RDRF IDLE
OR
NF
FE
PE
transferred into the RDR register while RDRF=1.
An interrupt is generated if RIE=1 in the SCICR2
register. It is cleared by a software sequence (an
Bit 7 = TDRE Transmit data register empty.
access to the SCISR register followed by a read to
This bit is set by hardware when the content of the
TDR register has been transferred into the shift
the SCIDR register).
0: No Overrun error
register. An interrupt is generated if the TIE bit =1
1: Overrun error is detected
in the SCICR2 register. It is cleared by a software
sequence (an access to the SCISR register folNote: When this bit is set, the RDR register conlowed by a write to the SCIDR register).
tent will not be lost but the shift register will be
0: Data is not transferred to the shift register
overwritten.
1: Data is transferred to the shift register
Note: Data will not be transferred to the shift regisBit 2 = NF Noise flag.
ter until the TDRE bit is cleared.
This bit is set by hardware when noise is detected
on a received frame. It is cleared by a software seBit 6 = TC Transmission complete.
quence (an access to the SCISR register followed
by a read to the SCIDR register).
This bit is set by hardware when transmission of a
0: No noise is detected
frame containing Data is complete. An interrupt is
generated if TCIE=1 in the SCICR2 register. It is
1: Noise is detected
cleared by a software sequence (an access to the
Note: This bit does not generate interrupt as it apSCISR register followed by a write to the SCIDR
pears at the same time as the RDRF bit which itregister).
self generates an interrupt.
0: Transmission is not complete
1: Transmission is complete
Bit 1 = FE Framing error.
Note: TC is not set after the transmission of a PreThis bit is set by hardware when a de-synchronizaamble or a Break.
tion, excessive noise or a break character is detected. It is cleared by a software sequence (an
Bit 5 = RDRF Received data ready flag.
access to the SCISR register followed by a read to
This bit is set by hardware when the content of the
the SCIDR register).
RDR register has been transferred to the SCIDR
0: No Framing error is detected
register. An interrupt is generated if RIE=1 in the
1: Framing error or break character is detected
SCICR2 register. It is cleared by a software seNote: This bit does not generate interrupt as it apquence (an access to the SCISR register followed
pears at the same time as the RDRF bit which itby a read to the SCIDR register).
self generates an interrupt. If the word currently
0: Data is not received
being transferred causes both frame error and
1: Received data is ready to be read
overrun error, it will be transferred and only the OR
bit will be set.
Bit 4 = IDLE Idle line detect.
This bit is set by hardware when an Idle Line is detected. An interrupt is generated if the ILIE=1 in
Bit 0 = PE Parity error.
the SCICR2 register. It is cleared by a software seThis bit is set by hardware when a parity error ocquence (an access to the SCISR register followed
curs in receiver mode. It is cleared by a software
by a read to the SCIDR register).
sequence (a read to the status register followed by
0: No Idle Line is detected
an access to the SCIDR data register). An inter1: Idle Line is detected
rupt is generated if PIE=1 in the SCICR1 register.
0: No parity error
1: Parity error
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ST72561
LINSCI
SERIAL COMMUNICATION INTERFACE (LIN Master Only) (Cont’d)
CONTROL REGISTER 1 (SCICR1)
Read/Write
Bit 3 = WAKE Wake-Up method.
This
bit determines the SCI Wake-Up method, it is
Reset Value: x000 0000 (x0h)
set or cleared by software.
0: Idle Line
7
0
1: Address Mark
R8
T8
SCID
M
WAKE
PCE
PS
PIE
Bit 7 = R8 Receive data bit 8.
This bit is used to store the 9th bit of the received
word when M=1.
Bit 6 = T8 Transmit data bit 8.
This bit is used to store the 9th bit of the transmitted word when M=1.
Bit 5 = SCID Disabled for low power consumption
When this bit is set the SCI prescalers and outputs
are stopped and the end of the current byte transfer in order to reduce power consumption.This bit
is set and cleared by software.
0: SCI enabled
1: SCI prescaler and outputs disabled
Bit 4 = M Word length.
This bit determines the word length. It is set or
cleared by software.
0: 1 Start bit, 8 Data bits, 1 Stop bit
1: 1 Start bit, 9 Data bits, 1 Stop bit
Note: The M bit must not be modified during a data
transfer (both transmission and reception).
166/262
Bit 2 = PCE Parity control enable.
This bit selects the hardware parity control (generation and detection). When the parity control is enabled, the computed parity is inserted at the MSB
position (9th bit if M=1; 8th bit if M=0) and parity is
checked on the received data. This bit is set and
cleared by software. Once it is set, PCE is active
after the current byte (in reception and in transmission).
0: Parity control disabled
1: Parity control enabled
Bit 1 = PS Parity selection.
This bit selects the odd or even parity when the
parity generation/detection is enabled (PCE bit
set). It is set and cleared by software. The parity
will be selected after the current byte.
0: Even parity
1: Odd parity
Bit 0 = PIE Parity interrupt enable.
This bit enables the interrupt capability of the hardware parity control when a parity error is detected
(PE bit set). It is set and cleared by software.
0: Parity error interrupt disabled
1: Parity error interrupt enabled
ST72561
LINSCI
SERIAL COMMUNICATION INTERFACE (LIN Master Only) (Cont’d)
CONTROL REGISTER 2 (SCICR2)
Read/Write
Bit 2 = RE Receiver enable.
This bit enables the receiver. It is set and cleared
Reset Value: 0000 0000 (00 h)
by software.
0: Receiver is disabled
7
0
1: Receiver is enabled and begins searching for a
start bit
TIE
TCIE
RIE
ILIE
TE
RE
RWU SBK
Bit 7 = TIE Transmitter interrupt enable.
This bit is set and cleared by software.
0: Interrupt is inhibited
1: An SCI interrupt is generated whenever
TDRE=1 in the SCISR register
Bit 6 = TCIE Transmission complete interrupt enable
This bit is set and cleared by software.
0: Interrupt is inhibited
1: An SCI interrupt is generated whenever TC=1 in
the SCISR register
Bit 5 = RIE Receiver interrupt enable.
This bit is set and cleared by software.
0: Interrupt is inhibited
1: An SCI interrupt is generated whenever OR=1
or RDRF=1 in the SCISR register
Bit 4 = ILIE Idle line interrupt enable.
This bit is set and cleared by software.
0: Interrupt is inhibited
1: An SCI interrupt is generated whenever IDLE=1
in the SCISR register.
Bit 3 = TE Transmitter enable.
This bit enables the transmitter. It is set and
cleared by software.
0: Transmitter is disabled
1: Transmitter is enabled
Notes:
– During transmission, a “0” pulse on the TE bit
(“0” followed by “1”) sends a preamble (idle line)
after the current word.
– When TE is set there is a 1 bit-time delay before
the transmission starts.
Bit 1 = RWU Receiver wake-up.
This bit determines if the SCI is in mute mode or
not. It is set and cleared by software and can be
cleared by hardware when a wake-up sequence is
recognized.
0: Receiver in active mode
1: Receiver in mute mode
Notes:
– Before selecting Mute mode (by setting the RWU
bit) the SCI must first receive a data byte, otherwise it cannot function in Mute mode with wakeup by Idle line detection.
– In Address Mark Detection Wake-Up configuration (WAKE bit=1) the RWU bit cannot be modified by software while the RDRF bit is set.
Bit 0 = SBK Send break.
This bit set is used to send break characters. It is
set and cleared by software.
0: No break character is transmitted
1: Break characters are transmitted
Note: If the SBK bit is set to “1” and then to “0”, the
transmitter will send a BREAK word at the end of
the current word.
167/262
ST72561
LINSCI
SERIAL COMMUNICATION INTERFACE (LIN Master Only) (Cont’d)
CONTROL REGISTER 3 (SCICR3)
0: Steady low value on SCLK pin outside transmission window.
Read/Write
1: Steady high value on SCLK pin outside transReset Value: 0000 0000 (00h)
mission window.
7
0
-
LINE
-
-
CLKEN CPOL CPHA LBCL
Bit 7= Reserved, must be ket cleared.
Bit 6 = LINE LIN Mode Enable.
This bit is set and cleared by software.
0: LIN Mode disabled
1: LIN Master mode enabled
The LIN Master mode enables the capability to
send LIN Synch Breaks (13 low bits) using the
SBK bit in the SCICR2 register
.In transmission, the LIN Synch Break low phase
duration is shown as below:
LINE
M
Number of low bits sent
during a LIN Synch Break
0
0
10
0
1
11
1
0
13
1
1
14
Bit 1= CPHA Clock Phase.
This bit allows the user to select the phase of the
clock output on the SCLK pin. It works in conjonction with the CPOL bit to produce the desired
clock/data relationship (see Figure 92 & Figure 93)
0: SCLK clock line activated in middle of data bit.
1: SCLK clock line activated at beginning of data
bit.
Bit 0= LBCL Last bit clock pulse.
This bit allows the user to select whether the clock
pulse associated with the last data bit transmitted
(MSB) has to be output on the SCLK pin.
0: The clock pulse of the last data bit is not output
to the SCLK pin.
1: The clock pulse of the last data bit is output to
the SCLK pin.
Note: The last bit is the 8th or 9th data bit transmitted depending on the 8 or 9 bit format selected by
the M bit in the SCICR1 register.
Table 25. SCI clock on SCLK pin
Bits 5:4 = Reserved, forced by hardware to 0.
These bits are not used.
Bit 3= CLKEN Clock Enable.
This bit allows the user to enable the SCLK pin.
0: SLK pin disabled
1: SLK pin enabled
Bit 2= CPOL Clock Polarity.
This bit allows the user to select the polarity of the
clock output on the SCLK pin. It works in conjonction with the CPHA bit to produce the desired
clock/data relationship (see Figure 92 & Figure 93)
168/262
Data
format
8 bit
8 bit
9 bit
9 bit
M bit
LBCL bit
Number of clock
pulses on SCLK
0
0
1
1
0
1
0
1
7
8
8
9
Note: These 3 bits (CPOL, CPHA, LBCL) should
not be written while the transmitter is enabled.
ST72561
LINSCI
SERIAL COMMUNICATION INTERFACE (LIN Master Only) (Cont’d)
DATA REGISTER (SCIDR)
Bit 5:3 = SCT[2:0] SCI Transmitter rate divisor
These 3 bits, in conjunction with the SCP1 & SCP0
Read/Write
bits define the total division applied to the bus
Reset Value: Undefined
clock to yield the transmit rate clock in conventional Baud Rate Generator mode.
Contains the Received or Transmitted data character, depending on whether it is read from or writTR dividing factor
SCT2
SCT1
SCT0
ten to.
7
0
DR7
DR6
DR5
DR4
DR3
DR2
DR1
DR0
The Data register performs a double function (read
and write) since it is composed of two registers,
one for transmission (TDR) and one for reception
(RDR).
The TDR register provides the parallel interface
between the internal bus and the output shift register (see Figure 88).
The RDR register provides the parallel interface
between the input shift register and the internal
bus (see Figure 88).
7
0
SCP0
SCT2
SCT1
SCT0
SCR2
0
0
0
2
0
0
1
4
0
1
0
8
0
1
1
16
1
0
0
32
1
0
1
64
1
1
0
128
1
1
1
Note: this TR factor is used only when the ETPR
fine tuning factor is equal to 00h; otherwise, TR is
replaced by the (TR*ETPR) dividing factor.
Bit 2:0 = SCR[2:0] SCI Receiver rate divisor.
These 3 bits, in conjunction with the SCP1 & SCP0
bits define the total division applied to the bus
clock to yield the receive rate clock in conventional
Baud Rate Generator mode.
BAUD RATE REGISTER (SCIBRR)
Read/Write
Reset Value: 0000 0000 (00h)
SCP1
1
SCR1 SCR0
Bit 7:6= SCP[1:0] First SCI Prescaler
These 2 prescaling bits allow several standard
clock division ranges:
RR dividing factor
SCR2
SCR1
SCR0
1
0
0
0
2
0
0
1
4
0
1
0
8
0
1
1
16
1
0
0
32
1
0
1
PR Prescaling factor
SCP1
SCP0
1
0
0
64
1
1
0
128
1
1
1
3
0
1
4
1
0
13
1
1
Note: This RR factor is used only when the ERPR
fine tuning factor is equal to 00h; otherwise, RR is
replaced by the (RR*ERPR) dividing factor.
169/262
ST72561
LINSCI
SERIAL COMMUNICATION INTERFACE (LIN Master Only) (Cont’d)
EXTENDED RECEIVE PRESCALER DIVISION
EXTENDED TRANSMIT PRESCALER DIVISION
REGISTER (SCIERPR)
REGISTER (SCIETPR)
Read/Write
Read/Write
Reset Value: 0000 0000 (00 h)
Reset Value:0000 0000 (00h)
7
0
7
ERPR ERPR ERPR ERPR ERPR ERPR ERPR ERPR
7
6
5
4
3
2
1
0
ETPR
7
Bit 7:0 = ERPR[7:0] 8-bit Extended Receive Prescaler Register.
The extended Baud Rate Generator is activated
when a value other than 00h is stored in this register. The clock frequency from the 16 divider (see
Figure 90) is divided by the binary factor set in the
SCIERPR register (in the range 1 to 255).
The extended baud rate generator is not active after a reset.
0
ETPR
6
ETPR
5
ETPR
4
ETPR
3
ETPR
2
ETPR ETPR
1
0
Bit 7:0 = ETPR[7:0] 8-bit Extended Transmit Prescaler Register.
The extended Baud Rate Generator is activated
when a value other than 00h is stored in this register. The clock frequency from the 16 divider (see
Figure 90) is divided by the binary factor set in the
SCIETPR register (in the range 1 to 255).
The extended baud rate generator is not active after a reset.
Table 26. Baudrate Selection
Conditions
Symbol
Parameter
fCPU
Accuracy
vs. Standard
~0.16%
fTx
fRx
Communication frequency
8MHz
~0.79%
170/262
Prescaler
Conventional Mode
TR (or RR)=128, PR=13
TR (or RR)= 32, PR=13
TR (or RR)= 16, PR=13
TR (or RR)= 8, PR=13
TR (or RR)= 4, PR=13
TR (or RR)= 16, PR= 3
TR (or RR)= 2, PR=13
TR (or RR)= 1, PR=13
Extended Mode
ETPR (or ERPR) = 35,
TR (or RR)= 1, PR=1
Standard
Baud
Rate
~300.48
300
1200 ~1201.92
2400 ~2403.84
4800 ~4807.69
9600 ~9615.38
10400 ~10416.67
19200 ~19230.77
38400 ~38461.54
14400 ~14285.71
Unit
Hz
ST72561
LINSCI SERIAL COMMUNICATIONS INTERFACE (LIN Master) (Cont’d)
Table 27. LINSCI2 Register Map and Reset Values
Address
(Hex.)
Register
Name
7
6
5
4
3
2
1
0
60
SCI2SR
Reset Value
TDRE
1
TC
1
RDRF
0
IDLE
0
OR
0
NF
0
FE
0
PE
0
61
SCI2DR
Reset Value
DR7
-
DR6
-
DR5
-
DR4
-
DR3
-
DR2
-
DR1
-
DR0
-
62
SCI2BRR
Reset Value
SCP1
0
SCP0
0
SCT2
0
SCT1
0
SCT0
0
SCR2
0
SCR1
0
SCR0
0
63
SCI2CR1
Reset Value
R8
-
T8
-
SCID
-
M
-
WAKE
-
PCE
PS
PIE
64
SCI2CR2
Reset Value
TIE
0
TCIE
0
RIE
0
ILIE
0
TE
0
RE
0
RWU
0
SBK
0
65
SCI2CR3
Reset Value
0
LINE
0
0
0
CLKEN
0
CPOL
0
CPHA
0
LBCL
0
66
SCI2ERPR
Reset Value
ERPR7
0
ERPR6
0
ERPR5
0
ERPR4
0
ERPR3
0
ERPR2
0
ERPR1
0
ERPR0
0
67
SCI2ETPR
Reset Value
ETPR7
0
ETPR6
0
ETPR5
0
ETPR4
0
ETPR3
0
ETPR2
0
ETPR1
0
ETPR0
0
171/262
ST72561
10.9 beCAN CONTROLLER (beCAN)
The beCAN controller (Basic Enhanced CAN), interfaces the CAN network and supports the CAN
protocol version 2.0A and B. It has been designed
to manage high number of incoming messages efficiently with a minimum CPU load. It also meets
the priority requirements for transmit messages.
10.9.1 Main Features
■ Supports CAN protocol version 2.0 A, B Active
■ Bit rates up to 1Mbit/s
Transmission
■ Two transmit mailboxes
■ Configurable transmit priority
Reception
■ One receive FIFO with three stages
■ Six scalable filter banks
■ Identifier list feature
■ Configurable FIFO overrun
Management
■ Maskable interrupts
■ Software-efficient mailbox mapping at a unique
address space
10.9.2 General Description
In today’s CAN applications, the number of nodes
in a network is increasing and often several networks are linked together via gateways. Typically
the number of messages in the system (and thus
to be handled by each node) has significantly increased. In addition to the application messages,
Network Management and Diagnostic messages
have been introduced.
– An enhanced filtering mechanism is required to
handle each type of message.
Furthermore, application tasks require more CPU
time, therefore real-time constraints caused by
message reception have to be reduced.
– A receive FIFO scheme allows the CPU to be
dedicated to application tasks for a long time period without losing messages.
The standard HLP (Higher Layer Protocol) based
on standard CAN drivers requires an efficient interface to the CAN controller.
– All mailboxes and registers are organized in 16byte pages mapped at the same address and selected via a page select register.
ST9 MCU
Application
CAN
Controller
CAN
Rx
CAN
Tx
CAN
Transceiver
CAN
High
CAN Bus
172/262
CAN
Low
CAN node n
CAN node 2
CAN node 1
Figure 94. CAN Network Topology
ST72561
beCAN CONTROLLER (Cont’d)
CAN 2.0B Active Core
The beCAN module handles the transmission and
the reception of CAN messages fully autonomously. Standard identifiers (11-bit) and extended identifiers (29-bit) are fully supported by hardware.
Control, Status and Configuration Registers
The application uses these registers to:
– Configure CAN parameters, e.g.baud rate
– Request transmissions
– Handle receptions
– Manage interrupts
– Get diagnostic information
Tx Mailboxes
Two transmit mailboxes are provided to the software for setting up messages. The Transmission
Scheduler decides which mailbox has to be transmitted first.
Acceptance Filters
The beCAN provides six scalable/configurable
identifier filter banks for selecting the incoming
messages the software needs and discarding the
others.
Receive FIFO
The receive FIFO is used by the CAN controller to
store the incoming messages. Three complete
messages can be stored in the FIFO. The software
always accesses the next available message at
the same address. The FIFO is managed completly by hardware.
Figure 95. CAN Block Diagram
Receive FIFO
Tx Mailboxes
Master Control
2
Mailbox 1
Master Status
Mailbox 0
1
Transmit Status
Control/Status/Configuration
Transmit Prio
Receive FiFO
Mailbox 0
Interrupt Enable
Page Select
Error Status
Acceptance Filters
Error Int. Enable
Tx Error Counter
Rx Error Counter
Transmission
Scheduler
Filter
3 4
2
1
0 1
5
Diagnostic
Bit Timing
Filter Master
CAN 2.0B Active Core
Filter Config.
173/262
ST72561
beCAN CONTROLLER (Cont’d)
Figure 96. beCAN Operating Modes
RESET
SLEEP
SLAK= 1
INAK = 0
SLE
EE
SLEEP
SL
NORMAL
EP
P
SL
EE
P
RQ
* IN
SLAK= 0
INAK = 0
10.9.3 Operating Modes
The beCAN has three main operating modes: initialization, normal and sleep. After a hardware
reset, beCAN is in sleep mode to reduce power
consumption. The software requests beCAN to
enter initialization or sleep mode by setting the
INRQ or SLEEP bits in the CMCR register. Once
the mode has been entered, beCAN confirms it by
setting the INAK or SLAK bits in the CMSR register. When neither INAK nor SLAK are set, beCAN
is in normal mode. Before entering normal mode
beCAN always has to synchronize on the CAN
bus. To synchronize, beCAN waits until the CAN
bus is idle, this means 11 consecutive recessive
bits have been monitored on CANRX.
10.9.3.1 Initialization Mode
The software initialization can be done while the
hardware is in Initialization mode. To enter this
mode the software sets the INRQ bit in the CMCR
register and waits until the hardware has confirmed the request by setting the INAK bit in the
CMSR register.
To leave Initialization mode, the software clears
the INQR bit. beCAN has left Initialization mode
once the INAK bit has been cleared by hardware.
While in Initialization mode, all message transfers
to and from the CAN bus are stopped and the sta-
174/262
SYNC
SLAK= X
INAK = X
INR
Q
INR
INRQ
Q
INITIALIZATION
SLAK= 0
INAK = 1
tus of the CAN bus output CANTX is recessive
(high).
Entering Initialization Mode does not change any
of the configuration registers.
To initialize the CAN Controller, software has to
set up the Bit Timing registers and the filter banks.
If a filter bank is not used, it is recommended to
leave it non active (leave the corresponding FACT
bit cleared).
10.9.3.2 Normal Mode
Once the initialization has been done, the software
must request the hardware to enter Normal mode,
to synchronize on the CAN bus and start reception
and transmission. Entering Normal mode is done
by clearing the INRQ bit in the CMCR register and
waiting until the hardware has confirmed the request by clearing the INAK bit in the CMSR register. Afterwards, the beCAN synchronizes with the
data transfer on the CAN bus by waiting for the occurrence of a sequence of 11 consecutive recessive bits (≡ Bus Idle) before it can take part in bus
activities and start message transfer.
The initialization of the filter values is independent
from Initialization mode but must be done while the
filter bank is not active (corresponding FACTx bit
cleared). The filter bank scale and mode configuration must be configured in initialization mode.
ST72561
beCAN CONTROLLER (Cont’d)
10.9.3.3 Low Power Mode (Sleep)
To reduce power consumption, beCAN has a low
power mode called Sleep mode. This mode is entered on software request by setting the SLEEP bit
in the CMCR register. In this mode, the beCAN
clock is stopped. Consequently, software can still
access the beCAN registers and mailboxes but the
beCAN will not update the status bits.
Example: If software requests entry to initialization mode by setting the INRQ bit while beCAN is
in sleep mode, it will not be acknowledged by the
hardware, INAK stays cleared.
beCAN can be woken up (exit Sleep mode) either
by software clearing the SLEEP bit or on detection
of CAN bus activity.
On CAN bus activity detection, hardware automatically performs the wake-up sequence by clearing
the SLEEP bit if the AWUM bit in the CMCR register is set. If the AWUM bit is cleared, software has
to clear the SLEEP bit when a wake-up interrupt
occurs, in order to exit from sleep mode.
Note: If the wake-up interrupt is enabled (WKUIE
bit set in CIER register) a wake-up interrupt will be
generated on detection of CAN bus activity, even if
the beCAN automatically performs the wake-up
sequence.
After the SLEEP bit has been cleared, Sleep mode
is exited once beCAN has synchronized with the
CAN bus, refer to Figure 96.beCAN Operating
Modes. The sleep mode is exited once the SLAK
bit has been cleared by hardware.
10.9.3.4 Test Mode
Test mode can be selected by the SILM and LBKM
bits in the CDGR register. These bits must be configured while beCAN is in Initialization mode. Once
test mode has been selected, beCAN is started in
Normal mode.
10.9.3.5 Silent Mode
The beCAN can be put in Silent mode by setting
the SILM bit in the CDGR register.
In Silent mode, the beCAN is able to receive valid
data frames and valid remote frames, but it sends
only recessive bits on the CAN bus and it cannot
start a transmission. If the beCAN has to send a
dominant bit (ACK bit, overload flag, active error
flag), the bit is rerouted internally so that the CAN
Core monitors this dominant bit, although the CAN
bus may remain in recessive state. Silent mode
can be used to analyze the traffic on a CAN bus
without affecting it by the transmission of dominant
bits (Acknowledge Bits, Error Frames).
Figure 97. beCAN in Silent Mode
beCAN
Tx
Rx
=1
CANTX CANRX
10.9.3.6 Loop Back Mode
The beCAN can be set in Loop Back Mode by setting the LBKM bit in the CDGR register. In Loop
Back Mode, the beCAN treats its own transmitted
messages as received messages and stores them
(if they pass acceptance filtering) in the FIFO.
Figure 98. beCAN in Loop Back Mode
beCAN
Tx
Rx
CANTX CANRX
This mode is provided for self-test functions. To be
independent of external events, the CAN Core ignores acknowledge errors (no dominant bit sampled in the acknowledge slot of a data / remote
frame) in Loop Back Mode. In this mode, the beCAN performs an internal feedback from its Tx
output to its Rx input. The actual value of the CANRX input pin is disregarded by the beCAN. The
transmitted messages can be monitored on the
CANTX pin.
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beCAN CONTROLLER (Cont’d)
10.9.3.7 Loop Back combined with Silent Mode
It is also possible to combine Loop Back mode and
Silent mode by setting the LBKM and SILM bits in
the CDGR register. This mode can be used for a
“Hot Selftest”, meaning the beCAN can be tested
like in Loop Back mode but without affecting a running CAN system connected to the CANTX and
CANRX pins. In this mode, the CANRX pin is disconnected from the beCAN and the CANTX pin is
held recessive.
Figure 99. beCAN in Combined Mode
beCAN
Tx
Rx
=1
CANTX CANRX
10.9.4 Functional Description
10.9.4.1 Transmission Handling
In order to transmit a message, the application
must select one empty transmit mailbox, set up
the identifier, the data length code (DLC) and the
data before requesting the transmission by setting
the corresponding TXRQ bit in the MCSR register.
Once the mailbox has left empty state, the software no longer has write access to the mailbox
registers. Immediately after the TXRQ bit has
been set, the mailbox enters pending state and
waits to become the highest priority mailbox, see
Transmit Priority. As soon as the mailbox has the
highest priority it will be scheduled for transmission. The transmission of the message of the
scheduled mailbox will start (enter transmit state)
when the CAN bus becomes idle. Once the mailbox has been successfully transmitted, it will become empty again. The hardware indicates a successful transmission by setting the RQCP and
TXOK bits in the MCSR and CTSR registers.
If the transmission fails, the cause is indicated by
the ALST bit in the MCSR register in case of an Ar-
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bitration Lost, and/or the TERR bit, in case of
transmission error detection.
Transmit Priority
By Identifier:
When more than one transmit mailbox is pending,
the transmission order is given by the identifier of
the message stored in the mailbox. The message
with the lowest identifier value has the highest priority according to the arbitration of the CAN protocol. If the identifier values are equal, the lower
mailbox number will be scheduled first.
By Transmit Request Order:
The transmit mailboxes can be configured as a
transmit FIFO by setting the TXFP bit in the CMCR
register. In this mode the priority order is given by
the transmit request order.
This mode is very useful for segmented transmission.
Abort
A transmission request can be aborted by the user
setting the ABRQ bit in the MCSR register. In
pending or scheduled state, the mailbox is aborted immediately. An abort request while the mailbox is in transmit state can have two results. If the
mailbox is transmitted successfully the mailbox
becomes empty with the TXOK bit set in the
MCSR and CTSR registers. If the transmission
fails, the mailbox becomes scheduled, the transmission is aborted and becomes empty with
TXOK cleared. In all cases the mailbox will become empty again at least at the end of the current transmission.
Non-Automatic Retransmission Mode
To configure the hardware in this mode the NART
bit in the CMCR register must be set.
In this mode, each transmission is started only
once. If the first attempt fails, due to an arbitration
loss or an error, the hardware will not automatically restart the message transmission. At the end of
the first transmission attempt, the hardware considers the request as completed and sets the
RQCP bit in the MCSR register. The result of the
transmission is indicated in the MCSR register by
the TXOK, ALST and TERR bits.
ST72561
beCAN CONTROLLER (Cont’d)
Figure 100. Transmit Mailbox States
EMPTY
RQCP=X
TXOK=X
TME = 1
TXRQ=1
PENDING
ABRQ=1
RQCP=0
TXOK=0
TME = 0
EMPTY
Mailbox does not
have highest priority
ABRQ=1
RQCP=1
TXOK=0
TME = 1
CAN Bus = IDLE
Transmit failed * NART
TRANSMIT
RQCP=0
TXOK=0
TME = 0
EMPTY
RQCP=1
TXOK=1
TME = 1
Mailbox has
highest priority
SCHEDULED
RQCP=0
TXOK=0
TME = 0
Transmit failed * NART
Transmit succeeded
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beCAN CONTROLLER (Cont’d)
10.9.4.2 Reception Handling
For the reception of CAN messages, three
mailboxes organized as a FIFO are provided. In
order to save CPU load, simplify the software and
guarantee data consistency, the FIFO is managed
completely by hardware. The application accesses
the messages stored in the FIFO through the FIFO
output mailbox.
Valid Message
A received message is considered as valid when it
has been received correctly according to the CAN
protocol (no error until the last but one bit of the
EOF field) and It passed through the identifier filtering successfully, see Section 10.9.4.3 "Identifier
Filtering".
Figure 101. Receive FIFO states
EMPTY
FMP=0x00
FOVR=0
Valid Message
Received
Release
Mailbox
PENDING_1
FMP=0x01
FOVR=0
Release
Mailbox
RFOM=1
Valid Message
Received
PENDING_2
FMP=0x10
FOVR=0
Release
Mailbox
RFOM=1
Valid Message
Received
PENDING_3
FMP=0x11
FOVR=0
Valid Message
Received
Release
Mailbox
RFOM=1
OVERRUN
FMP=0x11
FOVR=1
Valid Message
Received
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beCAN CONTROLLER (Cont’d)
FIFO Management
Starting from the empty state, the first valid message received is stored in the FIFO which becomes pending_1. The hardware signals the
event setting the FMP[1:0] bits in the CRFR register to the value 01b. The message is available in
the FIFO output mailbox. The software reads out
the mailbox content and releases it by setting the
RFOM bit in the CRFR register. The FIFO becomes empty again. If a new valid message has
been received in the meantime, the FIFO stays in
pending_1 state and the new message is available in the output mailbox.
If the application does not release the mailbox, the
next valid message will be stored in the FIFO
which enters pending_2 state (FMP[1:0] = 10b).
The storage process is repeated for the next valid
message putting the FIFO into pending_3 state
(FMP[1:0] = 11b). At this point, the software must
release the output mailbox by setting the RFOM
bit, so that a mailbox is free to store the next valid
message. Otherwise the next valid message received will cause a loss of message.
Refer also to Section 10.9.4.4 "Message Storage"
Overrun
Once the FIFO is in pending_3 state (i.e. the three
mailboxes are full) the next valid message reception will lead to an overrun and a message will be
lost. The hardware signals the overrun condition
by setting the FOVR bit in the CRFR register.
Which message is lost depends on the configuration of the FIFO:
– If the FIFO lock function is disabled (RFLM bit in
the CMCR register cleared) the last message
stored in the FIFO will be overwritten by the new
incoming message. In this case the latest messages will be always available to the application.
– If the FIFO lock function is enabled (RFLM bit in
the CMCR register set) the most recent message
will be discarded and the software will have the
three oldest messages in the FIFO available.
Reception Related Interrupts
On the storage of the first message in the FIFO FMP[1:0] bits change from 00b to 01b - an interrupt is generated if the FMPIE bit in the CIER register is set.
When the FIFO becomes full (i.e. a third message
is stored) the FULL bit in the CRFR register is set
and an interrupt is generated if the FFIE bit in the
CIER register is set.
On overrun condition, the FOVR bit is set and an
interrupt is generated if the FOVIE bit in the CIER
register is set.
10.9.4.3 Identifier Filtering
In the CAN protocol the identifier of a message is
not associated with the address of a node but related to the content of the message. Consequently
a transmitter broadcasts its message to all receivers. On message reception a receiver node decides - depending on the identifier value - whether
the software needs the message or not. If the message is needed, it is copied into the RAM. If not,
the message must be discarded without intervention by the software.
To fulfil this requirement, the beCAN Controller
provides six configurable and scalable filter banks
(0-5) in order to receive only the messages the
software needs. This hardware filtering saves
CPU resources which would be otherwise needed
to perform filtering by software. Each filter bank
consists of eight 8-bit registers, CFxR[0:7].
Scalable Width
To optimize and adapt the filters to the application
needs, each filter bank can be scaled independently. Depending on the filter scale a filter bank
provides:
– One 32-bit filter for the STDID[10:0], IDE, EXTID[17:0] and RTR bits.
– Two 16-bit filters for the STDID[10:0], RTR and
IDE bits.
– Four 8-bit filters for the STDID[10:3] bits. The
other bits are considered as don’t care.
– One 16-bit filter and two 8-bit filters for filtering
the same set of bits as the 16 and 8-bit filters described above.
Refer to Figure 102.Filter Bank Scale Configuration - Register Organisation.
Furthermore, the filters can be configured in mask
mode or in identifier list mode.
Mask mode
In mask mode the identifier registers are associated with mask registers specifying which bits of the
identifier are handled as “must match” or as “don’t
care”.
Identifier List mode
In identifier list mode, the mask registers are
used as identifier registers. Thus instead of defining an identifier and a mask, two identifiers are
specified, doubling the number of single identifiers. All bits of the incoming identifier must match
the bits specified in the filter registers.
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beCAN CONTROLLER (Cont’d)
Figure 102. Filter Bank Scale Configuration - Register Organisation
Filter Bank Scale Config. Bits1
Filter Bank Scale Configuration
One 32-Bit Filter
Identifier
Mask/Ident.
Bit Mapping
CFxR0
CFxR4
STID10:3
FSCx = 3
CFxR1
CFxR5
CFxR2
CFxR6
STID2:0 RTR IDE EXID17:15
EXID14:7
CFxR3
CFxR7
EXID6:0
Two 16-Bit Filters
Identifier
Mask/Ident.
CFxR0
CFxR2
CFxR1
CFxR3
Identifier
Mask/Ident.
Bit Mapping
CFxR4
CFxR6
CFxR5
CFxR7
FSCx = 2
STID10:3
STID2:0 RTR IDE EXID17:15
One 16-Bit / Two 8-Bit Filters
Identifier
Mask/Ident.
CFxR0
CFxR2
Identifier
Mask/Ident.
CFxR4
CFxR5
Identifier
Mask/Ident.
CFxR6
CFxR7
CFxR1
CFxR3
FSCx = 1
Four 8-Bit Filters
Identifier
Mask/Ident.
CFxR0
CFxR1
Identifier
Mask/Ident.
CFxR2
CFxR3
Identifier
Mask/Ident.
CFxR4
CFxR5
Identifier
Mask/Ident.
Bit Mapping
CFxR6
CFxR7
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STID10:3
FSCx = 0
x = filter bank number
1
These bits are located in the CFCR register
ST72561
beCAN CONTROLLER (Cont’d)
Filter Bank Scale and Mode Configuration
The filter banks are configured by means of the
corresponding CFCRx register. To configure a filter bank this must be deactivated by clearing the
FACT bit in the CFCR register. The filter scale is
configured by means of the FSC[1:0] bits in the
corresponding CFCR register, refer to Figure
102.Filter Bank Scale Configuration - Register Organisation. The identifier list or identifier mask
mode for the corresponding Mask/Identifier registers is configured by means of the FMCLx and FMCHx bits in the CFMR register. The FMCLx bit defines the mode for the two least significant bytes,
and the FMCHx bit the mode for the two most significant bytes of filter bank x. Examples:
– If filter bank 1 is configured as two 16-bit filters,
then the FMCL1 bit defines the mode of the
CF1R2 and CF1R3 registers and the FMCH1 bit
defines the mode of the CF1R6 and CF1R7 registers.
– If filter bank 2 is configured as four 8-bit filters,
then the FMCL2 bit defines the mode of the
CF2R1 and CF2R3 registers and the FMCH2 bit
defines the mode of the CF2R5 and CF2R7 registers.
Note: In 32-bit configuration, the FMCLx and FMCHx bits must have the same value to ensure that
the four Mask/Identifier registers are in the same
mode.
To filter a group of identifiers, configure the Mask/
Identifier registers in mask mode.
To select single identifiers, configure the Mask/
Identifier registers in identifier list mode.
Filters not used by the application should be left
deactivated.
Filter Match Index
Once a message has been received in the FIFO it
is available to the application. Typically application
data are copied into RAM locations. To copy the
data to the right location the application has to
identify the data by means of the identifier. To
avoid this and to ease the access to the RAM locations, the CAN controller provides a Filter Match
Index.
This index is stored in the mailbox together with
the message according to the filter priority rules.
Thus each received message has its associated
Filter Match Index.
The Filter Match Index can be used in two ways:
– Compare the Filter Match Index with a list of expected values.
– Use the Filter Match Index as an index on an array to access the data destination location.
For non-masked filters, the software no longer has
to compare the identifier.
If the filter is masked the software reduces the
comparison to the masked bits only.
Filter Priority Rules
Depending on the filter combination it may occur
that an identifier passes successfully through several filters. In this case the filter match value stored
in the receive mailbox is chosen according to the
following rules:
– A filter in identifier list mode prevails on an filter
in mask mode.
– A filter with full identifier coverage prevails over
filters covering part of the identifier, e.g. 16-bit filters prevail over 8-bit filters.
– Filters configured in the same mode and with
identical coverage are prioritized by filter number
and register number. The lower the number the
higher the priority.
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beCAN CONTROLLER (Cont’d)
Figure 103. Filtering Mechanism - example
Message Received
Identifier
Data
Ctrl
Identifier & Mask
Identifier List
Receive FIFO
Identifier
Identifier
Identifier
0
1
2
Identifier
n
Identifier
Mask
n+1
n+m
Identifier
Mask
No Match
Found
Message Discarded
Identifier #2 Match
n: number of single identifiers to receive
m: number of identifier groups to receive
n and m values depend on the configuration of the filters
The example above shows the filtering principle of
the beCAN. On reception of a message, the identifier is compared first with the filters configured in
identifier list mode. If there is a match, the message is stored in the FIFO and the index of the
matching filter is stored in the Filter Match Index.
As shown in the example, the identifier matches
with Identifier #2 thus the message content and
MFMI 2 is stored in the FIFO.
182/262
Message
Stored
If there is no match, the incoming identifier is then
compared with the filters configured in mask
mode.
If the identifier does not match any of the identifiers configured in the filters, the message is discarded by hardware without software intervention.
ST72561
beCAN CONTROLLER (Cont’d)
10.9.4.4 Message Storage
The interface between the software and the hardware for the CAN messages is implemented by
means of mailboxes. A mailbox contains all information related to a message; identifier, data, control and status information.
Transmit Mailbox
The software sets up the message to be transmitted in an empty transmit mailbox. The status of the
transmission is indicated by hardware in the
MCSR register.
Transmit Mailbox Mapping
Offset to Transmit
Mailbox base address (bytes)
Register Name
Receive Mailbox
When a message has been received, it is available
to the software in the FIFO output mailbox. Once
the software has handled the message (e.g. read
it) the software must release the FIFO output mailbox by means of the RFOM bit in the CRFR register to make the next incoming message available.
The filter match index is stored in the MFMI register.
Receive Mailbox Mapping
Offset to Receive
Mailbox base address (bytes)
Register Name
0
MFMI
MCSR
1
MDLC
1
MDLC
2
MIDR0
2
MIDR0
3
MIDR1
3
MIDR1
4
MIDR2
4
MIDR2
5
MIDR3
5
MIDR3
6
MDAR0
6
MDAR0
7
MDAR1
MDAR1
8
MDAR2
8
MDAR2
9
MDAR3
9
MDAR3
10
MDAR4
10
MDAR4
11
MDAR5
11
MDAR5
12
MDAR6
12
MDAR6
13
MDAR7
13
MDAR7
14
Reserved
14
Reserved
15
Reserved
15
Reserved
0
7
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beCAN CONTROLLER (Cont’d)
Figure 104. CAN Error State Diagram
When TEC or REC > 127
ERROR ACTIVE
ERROR PASSIVE
When TEC and REC < 128,
When 128 * 11 recessive bits occur:
When TEC > 255
BUS OFF
10.9.4.5 Error Management
The error management as described in the CAN
protocol is handled entirely by hardware using a
Transmit Error Counter (TECR register) and a Receive Error Counter (RECR register), which get incremented or decremented according to the error
condition. For detailed information about TEC and
REC management, please refer to the CAN standard.
Both of them may be read by software to determine the stability of the network. Furthermore, the
CAN hardware provides detailed information on
the current error status in CESR register. By
means of CEIER register and ERRIE bit in CIER
register, the software can configure the interrupt
generation on error detection in a very flexible
way.
184/262
Bus-Off Recovery
The Bus-Off state is reached when TECR is greater then 255, this state is indicated by BOFF bit in
CESR register. In Bus-Off state, the beCAN acts
as disconnected from the CAN bus, hence it is no
longer able to transmit and receive messages.
Depending on the ABOM bit in the CMCR register
beCAN will recover from Bus-Off (become error
active again) either automatically or on software
request. But in both cases the beCAN has to wait
at least for the recovery sequence specified in the
CAN standard (128 x 11 consecutive recessive
bits monitored on CANRX).
If ABOM is set, the beCAN will start the recovering
sequence automatically after it has entered BusOff state.
If ABOM is cleared, the software must initiate the
recovering sequence by requesting beCAN to enter initialization mode. Then beCAN starts monitoring the recovery sequence when the beCAN is requested to leave the initialisation mode.
Note: In initialization mode, beCAN does not monitor the CANRX signal, therefore it cannot complete the recovery sequence. To recover, beCAN
must be in normal mode.
ST72561
beCAN CONTROLLER (Cont’d)
10.9.4.6 Bit Timing
The bit timing logic monitors the serial bus-line and
performs sampling and adjustment of the sample
point by synchronizing on the start-bit edge and resynchronizing on the following edges.
Its operation may be explained simply by splitting
nominal bit time into three segments as follows:
– Synchronization segment (SYNC_SEG): a bit
change is expected to occur within this time segment. It has a fixed length of one time quantum
(1 x tCAN).
– Bit segment 1 (BS1): defines the location of the
sample point. It includes the PROP_SEG and
PHASE_SEG1 of the CAN standard. Its duration
is programmable between 1 and 16 time quanta
but may be automatically lengthened to compensate for positive phase drifts due to differences in
the frequency of the various nodes of the network.
– Bit segment 2 (BS2): defines the location of the
transmit point. It represents the PHASE_SEG2
of the CAN standard. Its duration is programmable between 1 and 8 time quanta but may also be
automatically shortened to compensate for negative phase drifts.
– Resynchronization Jump Width (RJW): defines an upper bound to the amount of lengthening or shortening of the bit segments. It is
programmable between 1 and 4 time quanta.
To guarantee the correct behaviour of the CAN
controller, SYNC_SEG + BS1 + BS2 must be
greater than or equal to 5 time quanta.
For a detailed description of the CAN resynchronization mechanism and other bit timing configuration constraints, please refer to the Bosch CAN
standard 2.0.
As a safeguard against programming errors, the
configuration of the Bit Timing Registers CBTR1
and CBTR0 is only possible while the device is in
Initialization mode.
Figure 105. Bit Timing
NOMINAL BIT TIME
SYNC_SEG
BIT SEGMENT 1 (BS1)
1 x tCAN
BIT SEGMENT 2 (BS2)
tBS1
tBS2
SAMPLE POINT
TRANSMIT POINT
Figure 106. CAN Frames (Part 1of 2)
Inter-Frame Space
Inter-Frame Space
or Overload Frame
Data Frame (Standard identifier)
44 + 8 * N
12
6
DLC
RTR
IDE
r0
SOF
ID
8*N
CRC Field
16
Ack Field
2
CRC
7
EOF
ACK
Arbitration Field Control Field Data Field
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beCAN CONTROLLER (Cont’d)
Figure 107. CAN Frames (Part 2 of 2)
Inter-Frame Space
or Overload Frame
Data Frame (Extended Identifier)
Inter-Frame Space
64 + 8 * N
Std Arbitr. Field
Ext Arbitr. Field
12
Ctrl Field
6
20
ID
Data Field
8*N
CRC
EOF
Inter-Frame Space
ACK
SRR
IDE
RTR
r1
r0
DLC
SOF
CRC Field Ack Field
2
16
7
Inter-Frame Space
or Overload Frame
Remote Frame
44
Arbitration Field Control Field
CRC Field
6
12
ID
16
End Of Frame
7
CRC
ACK
RTR
IDE
r0
DLC
SOF
Data Frame or
Remote Frame
Ack Field
2
Inter-Frame Space
or Overload Frame
Error Frame
Error Flag Flag Echo Error Delimiter
6
≤6
8
Notes:
Any Frame
Inter-Frame Space
Suspend
Intermission Transmission
3
8
Data Frame or
Remote Frame
• 0 <= N <= 8
• SOF = Start Of Frame
• ID = Identifier
Bus Idle
• RTR = Remote Transmission Request
• IDE = Identifier Extension Bit
• r0 = Reserved Bit
• DLC = Data Length Code
End Of Frame or
Error Delimiter or
Overload Delimiter
• CRC = Cyclic Redundancy Code
Overload Frame
Inter-Frame Space
or Error Frame
• Error flag: 6 dominant bits if node is error
active else 6 recessive bits.
Overload Flag Overload Delimiter
6
8
• Suspend transmission: applies to error
passive nodes only.
• EOF = End of Frame
• ACK = Acknowledge bit
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beCAN CONTROLLER (Cont’d)
10.9.5 Interrupts
Two interrupt vectors are dedicated to beCAN.
Each interrupt source can be independently ena-
bled or disabled by means of the CAN Interrupt
Enable Register (CIER) and CAN Error Interrupt
Enable register (CEIER).
Figure 108. Event flags and Interrupt Generation
FMPIE
FMP
&
FIFO
CRFR
INTERRUPT
FFIE
&
FOVIE
&
ERRIE
&
FULL
FOVR
EWGIE
&
EPVIE
&
EWGF
CESR
EPVF
BOFIE
BOFF
LECIE
LECIEF
+
&
TRANSMIT/
ERROR/
STATUS CHANGE
INTERRUPT
&
+
CMSR
MCSR
CIER
TXMB 0
TXMB 1
RQCP
RQCP
TMEIE
+
WKUIE
WKUI
+
&
&
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beCAN CONTROLLER (Cont’d)
– The FIFO interrupt can be generated by the following events:
– Reception of a new message, FMP bits in the
CRFR0 register incremented.
– FIFO0 full condition, FULL bit in the CRFR0
register set.
– FIFO0 overrun condition, FOVR bit in the
CRFR0 register set.
– The transmit, error and status change interrupt can be generated by the following events:
– Transmit mailbox 0 becomes empty, RQCP0
bit in the CTSR register set.
– Transmit mailbox 1 becomes empty, RQCP1
bit in the CTSR register set.
– Error condition, for more details on error conditions please refer to the CAN Error Status
register (CESR).
– Wake-up condition, SOF monitored on the
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CAN Rx signal.
10.9.6 Register Access Protection
Erroneous access to certain configuration registers can cause the hardware to temporarily disturb
the whole CAN network. Therefore the following
registers can be modified by software only while
the hardware is in initialization mode:
CBTR0, CBTR1, CFCR0, CFCR1, CFMR and
CDGR registers.
Although the transmission of incorrect data will not
cause problems at the CAN network level, it can
severely disturb the application. A transmit mailbox can be only modified by software while it is in
empty state, refer to Figure 100.Transmit Mailbox
States
The filters must be deactivated before their value
can be modified by software. The modification of
the filter configuration (scale or mode) can be
done by software only in initialization mode.
ST72561
beCAN CONTROLLER (Cont’d)
10.9.7 BeCAN Cell Limitations
10.9.7.1 FIFO Corruption
FIFO corruption occurs in the following case:
WHEN the beCAN RX FIFO already holds 2 messages (i.e. FMP==2)
AND the application releases the FIFO (with
the instruction CRFR=B_RFOM;)
WHILE the beCAN requests the transfer of a new
receive message into the FIFO (this lasts one CPU
cycle)
THEN the internal FIFO pointer is not updated
BUT the FMP bits are updated correctly
As the FIFO pointer is not updated correctly, this
causes the last message received to be overwritten by any incoming message. This means one
message is lost as shown in the example in Figure
109. The beCAN will not recover normal operation
until a device reset occurs.
Figure 109. FIFO Corruption.
FMP
Initial State
0
Receive Message A
1
Receive Message B
2
Receive Message C
3
Release Message A
2
Release Message B
2
and Receive Message D
Receive Message E
3
Release Message C
2
Release Message E
1
Release Message B
0
FIFO
*v
- - -
When the FIFO is empty, v and * point to the same location
v
A
v
A
v
A
* does not move because FIFO is full (normal operation)
*
- *
B -
*
B C
* v
A B C
* v
D B C
Normal operation
v
*
D B C * does not move, pointer corruption
* v
E B C D is overwritten by E
v *
E B C C released
v
*
E B C E released instead of B
* v
E B C * and v are not pointing to the same message
the FIFO is empty
* pointer to next receive location
v pointer to next message to be released
189/262
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beCAN CONTROLLER (Cont’d)
Workaround
To implement the workaround, use the following
sequence to release the CAN receive FIFO.
This sequence replaces any occurrence of
CRFR |= B_RFOM;.
Figure 110. Workaround 1
if ((CRFR & 0x03) == 0x02)
while
(( CMSR & 0x20) && ( CDGR & 0x08) )
CRFR |= B_RFOM;
Explanation of Workaround 1
First, we need to make sure no interrupt can occur
between the test and the release of the FIFO to
avoid any added delay.
The workaround checks if the first 2 FIFO levels
are already full (FMP = 2) as the problem happens
only in this case.
If FMP≠2 we release the FIFO immediately, if
FMP=2, we monitor the reception status of the
cell.
The reception status is available in the CMSR register bit 5 (REC bit). Note: The REC bit was called
RX in olders versions of the datasheet.
– If the cell is not receiving, then REC bit in CMSR
is at 0, the software can release the FIFO immediately: there is no risk.
– If the cell is receiving, it is important to make sure
the release of the mailbox will not happen at the
time when the received message is loaded into
the FIFO.
We could simply wait for the end of the reception,
but this could take a long time (200µs for a 100-bit
{ };
frame at 500kHz), so we also monitor the Rx pin of
the microcontroller to minimize the time the application may wait in the while loop.
We know the critical window is located at the end
of the frame, 6+ CAN bit times after the acknowledge bit (exactly six full bit times plus the time from
the beginning of the bit to the sample point). Those
bits represent the acknowledge delimiter + the end
of frame slot.
We know also that those 6+ bits are in recessive
state on the bus, therefore if the CAN Rx pin of the
device is at ‘0’, (reflecting a CAN dominant state
on the bus), this is early enough to be sure we can
release the FIFO before the critical time slot.
Therefore, if the device hardware pin Rx is at 0
and there is a reception on going, its message will
be transferred to the FIFO only 6+ CAN bit times
later at the earliest (if the dominant bit is the acknowledge) or later if the dominant bit is part of the
message.
Compiled with Cosmic C compiler, the workaround
generates the following assembly lines:
Cycles
if ((CRFR & 0x03) == 0x02)
ld
and
cp
jrne
a, CRFR
a,#3
a,#2
_RELEASE
3
2
2
3
test: 10 cycles
while
(( CMSR & 0x20) && ( CDGR & 0x08) ) { };
_WHILELOOP:
btjf
CMSR,#5,_RELEASE
5
btjt
CDGR,#3,_WHILELOOP 5 loop: 10 cycles
CRFR |= B_RFOM;
_RELEASE:
bset
190/262
CRFR,#5
5
release: 5 cycles
ST72561
beCAN CONTROLLER (Cont’d)
In the worst case configuration, if the CAN cell
speed is set to the maximum baud rate, one bit
time is 8 CPU cycle. In this case the minimum time
between the end of the acknowledge and the critical period is 52 CPU cycles (48 for the 6 bit times
+ 4 for the (PROP SEG + TSeg 1). According to the
previous code timing, we need less than 15 cycles
from the time we see the dominant state to the
time we perform the FIFO release (one full loop +
the actual release) therefore the application will
never release the FIFO at the critical time when
this workaround is implemented.
Timing analysis
- Time spent in the workaround
Inside a CAN frame, the longest period that the Rx
pin stays in recessive state is 5 bits. At the end of
the frame, the time between the acknowledge
dominant bit and the end of reception (signaled by
REC bit status) is 8TCANbit, therefore the maximum time spent in the workaround is:
8TCANbit+Tloop+Ttest+Trelease in this case or
8TCANbit+25TCPU.
At low speed, this time could represent a long delay for the application, therefore it makes sense to
evaluate how frequently this delay occurs.
In order to reach the critical FMP=2, the CAN node
needs to receive 2 messages without servicing
them. Then in order to reach the critical window,
the cell has to receive a third one and the application has to release the mailbox at the same time, at
the end of the reception.
In the application, messages are not processed
only if either the interrupt are disabled or higher
level interrupts are being serviced.
Therefore if:
TIT higher level + TIT disable + TIT CAN < 2 x T CAN frame
the application will never wait in the workaround
TIT higher level: This the sum of the duration of all the
interrupts with a level strictly higher than the CAN
interrupt level
TIT disable: This is the longest time the application
disables the CAN interrupt (or all interrupts)
TIT CAN: This is the maximum duration between
the beginning of the CAN interrupt and the actual
location of the workaround
TCAN frame: This is minimum CAN frame duration
Figure 111. Critical Window Timing Diagram
CAN Frame
Critical window: the received
message is placed in the FIFO
Acknowledge: last
dominant bit in the frame
A release is not
allowed at this time
Time to test RX pin and to
release the FIFO 4.5 µs@4MHz Time between the end of the
acknowledge and the critical windows
- 6 full CAN bit times+ time to the sample point
approx. 13µs @ 500kBd
Figure 112. Reception of a Sequence of Frames
FMP
0
BUS
TCAN frame 1
CPU
1
TCAN frame 2
TIT disable
2
2
TCAN frame 3
TIT higher level
TIT CAN
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beCAN CONTROLLER (Cont’d)
Side-effect of Workround 1
Because the while loop lasts 10 CPU cycles, at
high baud rate, it is possible to miss a dominant
state on the bus if it lasts just one CAN bit time and
the bus speed is high enough (see Table 28)
Table 28. While Loop Timing
fCPU
Software
timing:
8 MHz
4 MHz
fCPU
While loop
1.25 µs
2.5 µs
10/fCPU
Minimum baud rate for
possible missed
dominant bit
800 kBaud
400 kBaud
fCPU/10
If this happens, we will continue waiting in the
while loop instead of releasing the FIFO immediately. The workaround is still valid because we will
not release the FIFO during the critical period. But
the application may lose additional time waiting in
the while loop as we are no longer able to guarantee a maximum of 6 CAN bit times spent in the
workaround.
In this particular case the time the application can
spend in the workaround may increase up to a full
CAN frame, depending of the frame contents. This
case is very rare but happens when a specific sequence is present on in the CAN frame.
The example in Figure 113 shows reception at
maximum CAN baud rate: in this case TCAN is 8/
Fcpu and the sampling time is 10/Fcpu.
If the application is using the maximum baud rate
and the possible delay caused by the workaround
is not acceptable, there is another workaround
which reduces the Rx pin sampling time.
Workaround 2 (see Figure 114) first tests that
FMP=2 and the CAN cell is receiving, if not the
FIFO can be released immediately. If yes, the program goes through a sequence of test instructions
on the RX pin that last longer than the time between the acknowledge dominant bit and the critical time slot. If the Rx pin is in recessive state for
more than 8 CAN bit times, it means we are now
after the acknowledge and the critical slot. If a
dominant bit is read on the bus, we can release the
FIFO immediately. This workaround has to be written in assembly language to avoid the compiler
optimizing the test sequence.
The implementation shown here is for the CAN
bus maximum speed (1MBd @ 8MHz CPU clock).
Figure 113. Reception at maximum CAN baudrate
CAN Bus signal
Sampling of Rx pin
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R RR R D R RR R D R R R R D R RR R D R RR R D
ST72561
Figure 114. Workaround 2
Ld
And
Cp
Jrne
a, CRFR
a,#3
a,#2
_RELEASE
Btjf
CMSR,#5,_RELEASE ; test if reception on going.
; if not release
Btjf
Btjf
Btjf
btjf
btjf
btjf
btjf
btjf
btjf
btjf
btjf
btjf
btjf
btjf
CDGR,#3,_RELEASE ; sample RX pin for 8 CAN bit time
CDGR,#3,_RELEASE
CDGR,#3,_RELEASE
CDGR,#3,_RELEASE
CDGR,#3,_RELEASE
CDGR,#3,_RELEASE
CDGR,#3,_RELEASE
CDGR,#3,_RELEASE
CDGR,#3,_RELEASE
CDGR,#3,_RELEASE
CDGR,#3,_RELEASE
CDGR,#3,_RELEASE
CDGR,#3,_RELEASE
CDGR,#3,_RELEASE
_RELEASE:
bset
CRFR,#5
; test FMP=2 ?
; if not release
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beCAN CONTROLLER (Cont’d)
10.9.8 Register Description
10.9.8.1 Control and Status Registers
CAN MASTER CONTROL REGISTER (CMCR)
Reset Value: 0000 0010 (02h)
7
0
0
ABOM AWUM NART RFLM
TXFP SLEEP INRQ
Bit 7 = Reserved, must be kept cleared.
Bit 6 = ABOM Automatic Bus-Off Management
- Read/Set/Clear
This bit controls the behaviour of the CAN hardware on leaving the Bus-Off state.
0: The Bus-Off state is left on software request.
Refer to Section 10.9.4.5 "Error Management",
Bus-Off recovery.
1: The Bus-Off state is left automatically by hardware once 128 x 11 recessive bits have been
monitored.
For detailed information on the Bus-Off state
please refer to Section 10.9.4.5 "Error Management".
Bit 5 = AWUM Automatic Wake-Up Mode
- Read/Set/Clear
This bit controls the behaviour of the CAN hardware on message reception during sleep mode.
0: The sleep mode is left on software request by
clearing the SLEEP bit of the CMCR register.
1: The sleep mode is left automatically by hardware on CAN message detection. The SLEEP
bit of the CMCR register and the SLAK bit of the
CMSR register are cleared by hardware.
Bit 4 = NART No Automatic Retransmission
- Read/Set/Clear
0: The CAN hardware will automatically retransmit
the message until it has been successfully
transmitted according to the CAN standard.
1: A message will be transmitted only once, independently of the transmission result (successful,
error or arbitration lost).
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Bit 3 = RFLM Receive FIFO Locked Mode
- Read/Set/Clear
0: Receive FIFO not locked on overrun. Once a receive FIFO is full the next incoming message
will overwrite the previous one.
1: Receive FIFO locked against overrun. Once a
receive FIFO is full the next incoming message
will be discarded.
Bit 2 = TXFP Transmit FIFO Priority
- Read/Set/Clear
This bit controls the transmission order when several mailboxes are pending at the same time.
0: Priority driven by the identifier of the message
1: Priority driven by the request order (chronologically)
Bit 1 = SLEEP Sleep Mode Request
- Read/Set/Clear
This bit is set by software to request the CAN hardware to enter the sleep mode. Sleep mode will be
entered as soon as the current CAN activity (transmission or reception of a CAN frame) has been
completed.
This bit is cleared by software to exit sleep mode.
This bit is cleared by hardware when the AWUM
bit is set and a SOF bit is detected on the CAN Rx
signal.
Bit 0 = INRQ Initialization Request
- Read/Set/Clear
The software clears this bit to switch the hardware
into normal mode. Once 11 consecutive recessive
bits have been monitored on the Rx signal the
CAN hardware is synchronized and ready for
transmission and reception. Hardware signals this
event by clearing the INAK bit if the CMSR register.
Software sets this bit to request the CAN hardware
to enter initialization mode. Once software has set
the INRQ bit, the CAN hardware waits until the
current CAN activity (transmission or reception) is
completed before entering the initialization mode.
Hardware signals this event by setting the INAK bit
in the CMSR register.
ST72561
beCAN CONTROLLER (Cont’d)
CAN MASTER STATUS REGISTER (CMSR)
Reset Value: 0000 0010 (02h)
7
0
0
0
REC
TRAN
WKUI
ERRI
SLAK
INAK
Note: To clear a bit of this register the software
must write this bit with a one.
Bit 7:4 = Reserved. Forced to 0 by hardware.
Bit 5 = REC Receive
- Read
The CAN hardware is currently receiver.
Bit 4 = TRAN Transmit
- Read
The CAN hardware is currently transmitter.
Bit 3 = WKUI Wake-Up Interrupt
- Read/Clear
This bit is set by hardware to signal that a SOF bit
has been detected while the CAN hardware was in
sleep mode. Setting this bit generates a status
change interrupt if the WKUIE bit in the CIER register is set.
This bit is cleared by software.
Bit 2 = ERRI Error Interrupt
- Read/Clear
This bit is set by hardware when a bit of the CESR
has been set on error detection and the corresponding interrupt in the CEIER is enabled. Setting this bit generates a status change interrupt if
the ERRIE bit in the CIER register is set.
This bit is cleared by software.
Bit 1 = SLAK Sleep Acknowledge
- Read
This bit is set by hardware and indicates to the
software that the CAN hardware is now in sleep
mode. This bit acknowledges the sleep mode re-
quest from the software (set SLEEP bit in CMCR
register).
This bit is cleared by hardware when the CAN
hardware has left sleep mode. Sleep mode is left
when the SLEEP bit in the CMCR register is
cleared. Please refer to the AWUM bit of the
CMCR register description for detailed information
for clearing SLEEP bit.
Bit 0 = INAK Initialization Acknowledge
- Read
This bit is set by hardware and indicates to the
software that the CAN hardware is now in initialization mode. This bit acknowledges the initialization request from the software (set INRQ bit in
CMCR register).
This bit is cleared by hardware when the CAN
hardware has left the initialization mode and is
now synchronized on the CAN bus. To be synchronized the hardware has to monitor a sequence of 11 consecutive recessive bits on the
CAN RX signal.
CAN TRANSMIT STATUS REGISTER (CTSR)
Read / Write (
Reset Value: 0000 0000 (00h)
7
0
0
0
TXOK1 TXOK0
0
0
RQCP1 RQCP0
Note: To clear a bit of this register the software
must write this bit with a one.
Bit 7:6 = Reserved. Forced to 0 by hardware.
Bit 5 = TXOK1 Transmission OK for mailbox 1
- Read
This bit is set by hardware when the transmission
request on mailbox 1 has been completed successfully. Please refer to Figure 100.
This bit is cleared by hardware when mailbox 1 is
requested for transmission or when the software
clears the RQCP1 bit.
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beCAN CONTROLLER (Cont’d)
Bit 4 = TXOK0 Transmission OK for mailbox 0
- Read
This bit is set by hardware when the transmission
request on mailbox 0 has been completed successfully. Please refer to Figure 100.
This bit is cleared by hardware when mailbox 0 is
requested for transmission or when the software
clears the RQCP0 bit.
mailbox are pending for transmission and mailbox
1 has the lowest priority.
Bit 5 = LOW0 Lowest Priority Flag for Mailbox 0
- Read
This bit is set by hardware when more than one
mailbox are pending for transmission and mailbox
0 has the lowest priority.
Note: These bits are set to zero when only one
mailbox is pending.
Bit 3:2 = Reserved. Forced to 0 by hardware.
Bit 1 = RQCP1 Request Completed for Mailbox 1
- Read/Clear
This bit is set by hardware to signal that the last request for mailbox 1 has been completed. The request could be a transmit or an abort request.
This bit is cleared by software.
Bit 4 = Reserved. Forced to 0 by hardware.
Bit 0 = RQCP0 Request Completed for Mailbox 0
- Read/Clear
This bit is set by hardware to signal that the last request for mailbox 0 has been completed. The request could be a transmit or an abort request.
This bit is cleared by software.
Bit 2 = TME0 Transmit Mailbox 0 Empty
- Read
This bit is set by hardware when no transmit request is pending for mailbox 0.
CAN TRANSMIT PRIORITY REGISTER (CTPR)
All bits of this register are read only.
Reset Value: 0000 1100 (0Ch)
7
0
0
LOW1
LOW0
0
TME1
TME0
0
CODE
Bit 7 = Reserved. Forced to 0 by hardware.
Bit 6 = LOW1 Lowest Priority Flag for Mailbox 1
- Read
This bit is set by hardware when more than one
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Bit 3 = TME1 Transmit Mailbox 1 Empty
- Read
This bit is set by hardware when no transmit request is pending for mailbox 1.
Bit 1:0 = CODE Mailbox Code
- Read
In case at least one transmit mailbox is free, the
code value is equal to the number of the next
transmit mailbox free.
In case all transmit mailboxes are pending, the
code value is equal to the number of the transmit
mailbox with the lowest priority.
ST72561
beCAN CONTROLLER (Cont’d)
CAN RECEIVE FIFO REGISTERS (CRFR)
Read / Write
Reset Value: 0000 0000 (00h)
7
0
0
0
RFOM FOVR
FULL
0
FMP1
FMP0
Note: To clear a bit in this register, software must
write a “1” to the bit.
Bit 7:6 = Reserved. Forced to 0 by hardware.
Bit 5 = RFOM Release FIFO Output Mailbox
- Read/Set
Set by software to release the output mailbox of
the FIFO. The output mailbox can only be released
when at least one message is pending in the FIFO.
Setting this bit when the FIFO is empty has no effect. If more than one message are pending in the
FIFO, the software has to release the output mailbox to access the next message.
Cleared by hardware when the output mailbox has
been released.
Bit 4 = FOVR FIFO Overrun
- Read/Clear
This bit is set by hardware when a new message
has been received and passed the filter while the
FIFO was full.
This bit is cleared by software.
Bit 3 = FULL FIFO Full
- Read/Clear
Set by hardware when three messages are stored
in the FIFO.
This bit can be cleared by software writting a one
to this bit or releasing the FIFO by means of
RFOM.
Bit 2 = Reserved. Forced to 0 by hardware.
Bit 1:0 = FMP[1:0] FIFO Message Pending
- Read
These bits indicate how many messages are
pending in the receive FIFO.
FMP is increased each time the hardware stores a
new message in to the FIFO. FMP is decreased
each time the software releases the output mailbox by setting the RFOM bit.
CAN INTERRUPT ENABLE REGISTER (CIER)
All bits of this register are set and cleared by software.
Read / Write
Reset Value: 0000 0000 (00h)
7
WKUIE
0
0
0
0
FOVIE0
FFIE0
FMPIE0
TMEIE
Bit 7 = WKUIE Wake-Up Interrupt Enable
0: No interrupt when WKUI is set.
1: Interrupt generated when WKUI bit is set.
Bit 6:4 = Reserved. Forced to 0 by hardware.
Bit 3 = FOVIE FIFO Overrun Interrupt Enable
0: No interrupt when FOVR bit is set.
1: Interrupt generated when FOVR bit is set.
Bit 2 = FFIE FIFO Full Interrupt Enable
0: No interrupt when FULL bit is set.
1: Interrupt generated when FULL bit is set.
Bit 1 = FMPIE FIFO Message Pending Interrupt
Enable
0: No interrupt on FMP[1:0] bits transition from 00b
to 01b.
1: Interrupt generated on FMP[1:0] bits transition
from 00b to 01b.
Bit 0 = TMEIE Transmit Mailbox Empty Interrupt
Enable
0: No interrupt when RQCPx bit is set.
1: Interrupt generated when RQCPx bit is set.
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beCAN CONTROLLER (Cont’d)
CAN ERROR STATUS REGISTER (CESR)
Read / Write
Reset Value: 0000 0000 (00h)
7
0
0
LEC2
LEC1
LEC0
0
BOFF
EPVF EWGF
Bit 7 = Reserved. Forced to 0 by hardware.
Bit 6:4 = LEC[2:0] Last Error Code
- Read/Set/Clear
This field holds a code which indicates the type of
the last error detected on the CAN bus. If a message has been transferred (reception or transmission) without error, this field will be cleared to ‘0’.
The code 7 is unused and may be written by the
CPU to check for update
Table 29. LEC Error Types
Code
0
1
2
3
4
5
6
7
Error Type
No Error
Stuff Error
Form Error
Acknowledgment Error
Bit recessive Error
Bit dominant Error
CRC Error
Set by software
Bit 1 = EWGF Error Warning Flag
- Read
This bit is set by hardware when the warning limit
has been reached. Receive Error Counter or
Transmit Error Counter greater than 96.
CAN ERROR INTERRUPT ENABLE REGISTER
(CEIER)
All bits of this register are set and clear by software.
Read/Write
Reset Value: 0000 0000 (00h)
7
ERRIE
0
0
0
LECIE
0
BOFIE EPVIE EWGIE
Bit 7 = ERRIE Error Interrupt Enable
0: No interrupt will be generated when an error
condition is pending in the CESR.
1: An interrupt will be generation when an error
condition is pending in the CESR.
Bit 6:5 = Reserved. Forced to 0 by hardware.
Bit 4 = LECIE Last Error Code Interrupt Enable
0: ERRI bit will not be set when the error code in
LEC[2:0] is set by hardware on error detection.
1: ERRI bit will be set when the error code in
LEC[2:0] is set by hardware on error detection.
Bit 3 = Reserved. Forced to 0 by hardware.
Bit 3 = Reserved. Forced to 0 by hardware.
Bit 2 = BOFF Bus-Off Flag
- Read
This bit is set by hardware when it enters the busoff state. The bus-off state is entered on TECR
overrun, TEC greater than 255, refer to Section
10.9.4.5 on page 184.
Bit 1 = EPVF Error Passive Flag
- Read
This bit is set by hardware when the Error Passive
limit has been reached (Receive Error Counter or
Transmit Error Counter greater than 127).
198/262
Bit 2 = BOFIE Bus-Off Interrupt Enable
0: ERRI bit will not be set when BOFF is set.
1: ERRI bit will be set when BOFF is set.
Bit 1 = EPVIE Error Passive Interrupt Enable
0: ERRI bit will not be set when EPVF is set.
1: ERRI bit will be set when EPVF is set.
Bit 0 = EWGIE Error Warning Interrupt Enable
0: ERRI bit will not be set when EWGF is set.
1: ERRI bit will be set when EWGF is set.
ST72561
beCAN CONTROLLER (Cont’d)
TRANSMIT ERROR COUNTER REG. (TECR)
Read Only
Reset Value: 00h
7
TEC7
0
TEC6
TEC5
TEC4
TEC3
TEC2
TEC1
TEC0
TEC[7:0] is the least significant byte of the 9-bit
Transmit Error Counter implementing part of the
fault confinement mechanism of the CAN protocol.
0
7
REC0
SJW1
7
REC6
REC5 REC4
REC3
REC2
REC1
Bit 0 = LBKM Loop Back Mode
- Read/Set/Clear
0: Loop Back Mode disabled
1: Loop Back Mode enabled
CAN BIT TIMING REGISTER 0 (CBTR0)
This register can only be accessed by the software
when the CAN hardware is in configuration mode.
Read / Write
Reset Value: 0000 0000 (00h)
RECEIVE ERROR COUNTER REG. (RECR)
Page: 00h — Read Only
Reset Value: 00h
REC7
Bit 1 = SILM Silent Mode
- Read/Set/Clear
0: Normal operation
1: Silent Mode
REC[7:0] is the Receive Error Counter implementing part of the fault confinement mechanism of the
CAN protocol. In case of an error during reception,
this counter is incremented by 1 or by 8 depending
on the error condition as defined by the CAN standard. After every successful reception the counter is
decremented by 1 or reset to 120 if its value was
higher than 128. When the counter value exceeds
127, the CAN controller enters the error passive
state.
CAN DIAGNOSIS REGISTER (CDGR)
All bits of this register are set and clear by software.
Read / Write
Reset Value: 0000 1100 (0Ch)
7
SJW0
BRP5
BRP4
BRP3
BRP2
BRP1
BRP0
Bit 7:6 SJW[1:0] Resynchronization Jump Width
These bits define the maximum number of time
quanta the CAN hardware is allowed to lengthen
or shorten a bit to perform the resynchronization.
Resynchronization Jump Width = (SJW+1).
Bit 5:0 BRP[5:0] Baud Rate Prescaler
These bits define the length of a time quantum.
tq = (BRP+1)/fCPU
For more information on bit timing, please refer to
Section 10.9.4.6 "Bit Timing".
CAN BIT TIMING REGISTER 1 (CBTR1)
Read / Write
Reset Value: 0001 0011 (23h)
7
0
0
0
0
0
0
0
0
RX
SAMP
SILM
BS22
BS21
BS20
BS13
BS12
BS11
BS10
LBKM
Bit 7 = Reserved. Forced to 0 by hardware.
Bit 3 = RX CAN Rx Signal
- Read
Monitors the actual value of the CAN_RX Pin.
Bit 2 = SAMP Last Sample Point
- Read
The value of the last sample point.
Bit 6:4 BS2[2:0] Time Segment 2
These bits define the number of time quanta in
Time Segment 2.
Time Segment 2=(BS2+1)
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beCAN CONTROLLER (Cont’d)
Bit 3:0 BS1[3:0] Time Segment 1
These bits define the number of time quanta in
Time Segment 1
Time Segment 1=(BS1+1)
For more information on bit timing, please refer to
Section 10.9.4.6 "Bit Timing".
CAN FILTER PAGE SELECT REGISTER
(CPSR)
All bits of this register are set and cleared by software.
Read / Write
Reset Value: 0000 0000 (00h)
7
0
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0
0
0
0
0
FPS2
FPS1
FPS0
Bit 7:3 = Reserved. Forced to 0 by hardware.
Bit 2:0 = PS[2:0] Page Select
- Read/Write
This register contains the page number.
Table 30. Filter Page Selection
PS[2:0]
0
1
2
3
4
5
6
7
Page Selected
Tx Mailbox 0
Tx Mailbox 1
Acceptance Filter 0:1
Acceptance Filter 2:3
Acceptance Filter 4:5
Reserved
Configuration/Diagnosis
Receive FIFO
ST72561
beCAN CONTROLLER (Cont’d)
10.9.8.2 Mailbox Registers
This chapter describes the registers of the transmit
and receive mailboxes. Refer to Section 10.9.4.4
"Message Storage" for detailed register mapping.
Transmit and receive mailboxes have the same
registers except:
– MCSR register in a transmit mailbox is replaced
by MFMI register in a receive mailbox.
– A receive mailbox is always write protected.
– A transmit mailbox is write enable only while
empty, corresponding TME bit in the CTPR register set.
MAILBOX CONTROL STATUS REGISTER
(MCSR)
Read / Write
Reset Value: 0000 0000 (00h)
7
0
0
0
TERR
ALST
Bit 3 = TXOK Transmission OK
- Read
The hardware updates this bit after each transmission attempt.
0: The previous transmission failed
1: The previous transmission was successful
Note: This bit has the same value as the corresponding TXOKx bit in the CTSR register.
Bit 2 = RQCP Request Completed
- Read/Clear
Set by hardware when the last request (transmit or
abort) has been performed.
Cleared by software writing a “1” or by hardware
on transmission request.
Note: This bit has the same value as the corresponding RQCPx bit of the CTSR register.
Clearing this bit clears all the status bits (TXOK, ALST and TERR) in the MCSR register and
the RQCP and TXOK bits in the CTSR register.
TXOK RQCP ABRQ TXRQ
Bit 7:6 = Reserved. Forced to 0 by hardware.
Bit 5 = TERR Transmission Error
- Read
This bit is updated by hardware after each transmission attempt.
0: The previous transmission was successful
1: The previous transmission failed due to an error
Bit 4 = ALST Arbitration Lost
- Read
This bit is updated by hardware after each transmission attempt.
0: The previous transmission was successful
1: The previous transmission failed due to an arbitration lost
Bit 1 = ABRQ Abort Request for Mailbox
- Read/Set
Set by software to abort the transmission request
for the corresponding mailbox.
Cleared by hardware when the mailbox becomes
empty.
Setting this bit has no effect when the mailbox is
not pending for transmission.
Bit 0 = TXRQ Transmit Mailbox Request
- Read/Set
Set by software to request the transmission for the
corresponding mailbox.
Cleared by hardware when the mailbox becomes
empty.
Note: This register is implemented only in transmit
mailboxes. In receive mailboxes, the MFMI register is mapped at this location.
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beCAN CONTROLLER (Cont’d)
MAILBOX FILTER MATCH INDEX (MFMI)
This register is read only.
Reset Value: 0000 0000 (00h)
7
MIDR1
7
STID5
FMI7
0
0
FMI6
FMI5
FMI4
FMI3
FMI2
FMI1
STID4
STID3
STID2
STID1
STID0
EXID17 EXID16
FMI0
Bit 7:0 = FMI[7:0] Filter Match Index
This register contains the index of the filter the
message stored in the mailbox passed through.
For more details on identifier filtering please refer
to Section 10.9.4.3 - Filter Match Index paragraph.
Note: This register is implemented only in receive
mailboxes. In transmit mailboxes, the MCSR register is mapped at this location.
Bit 7:2 = STID[5:0] Standard Identifier
6 least significant bits of the standard part of the
identifier.
Bit 1:0 = EXID[17:16] Extended Identifier
2 most significant bits of the extended part of the
identifier.
MIDR2
MAILBOX IDENTIFIER REGISTERS
(MIDR[3:0])
Read / Write
Reset Value: Undefined
MIDR0
7
EXID15 EXID14 EXID13 EXID12 EXID11 EXID10
7
0
0
IDE
RTR
STID10
STID9
STID8
STID7
STID6
Bit 7 = Reserved. Forced to 0 by hardware.
Bit 5 = RTR Remote Transmission Request
0: Data frame
1: Remote frame
Bit 4:0 = STID[10:6] Standard Identifier
5 most significant bits of the standard part of the
identifier.
EXID9
EXID8
Bit 7:0 = EXID[15:8] Extended Identifier
Bit 15 to 8 of the extended part of the identifier.
MIDR3
7
EXID7
Bit 6 = IDE Extended Identifier
This bit defines the identifier type of message in
the mailbox.
0: Standard identifier.
1: Extended identifier.
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0
0
EXID6
EXID5
EXID4
EXID3
EXID2
EXID1
EXID0
Bit 7:1 = EXID[6:0] Extended Identifier
6 least significant bits of the extended part of the
identifier.
ST72561
beCAN CONTROLLER (Cont’d)
MAILBOX DATA LENGTH CONTROL REGISTER (MDLC)
All bits of this register is write protected when the
mailbox is not in empty state.
Read / Write
Reset Value: xxxx xxxx (xxh)
7
MAILBOX DATA REGISTERS (MDAR[7:0])
All bits of this register are write protected when the
mailbox is not in empty state.
Read / Write
Reset Value: Undefined
7
DATA7
0
0
0
0
0
0
DLC3
DLC2
DLC1
DATA6
DATA5
DATA4
DATA3
DATA2
DATA1
DATA0
DLC0
Bit 7 = Reserved, must be kept cleared.
6:4 = Reserved, forced to 0 by hardware.
Bit 7:0 = DATA[7:0] Data
A data byte of the message. A message can contain from 0 to 8 data bytes.
Bit 3:0 = DLC[3:0] Data Length Code
This field defines the number of data bytes a data
frame contains or a remote frame request.
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beCAN CONTROLLER (Cont’d)
10.9.8.3 CAN Filter Registers
CAN FILTER CONFIGURATION REG.0 (CFCR0)
All bits of this register are set and cleared by software.
Read / Write
Reset Value: 0000 0000 (00h)
7
0
0
FSC11 FSC10 FACT1
0
FSC01 FSC00 FACT0
Note: To modify the FFAx and FSCx bits, the beCAN must be in INIT mode.
Bit 7 = Reserved. Forced to 0 by hardware.
Bit 6:5 = FSC1[1:0] Filter Scale Configuration
These bits define the scale configuration of Filter
1.
Bit 4 = FACT1 Filter Active
The software sets this bit to activate Filter 1. To
modify the Filter 1 registers (CF1R[7:0]), the
FACT1 bit must be cleared.
0: Filter 1 is not active
1: Filter 1 is active
Bit 3 = Reserved. Forced to 0 by hardware.
Bit 2:1 = FSC0[1:0] Filter Scale Configuration
These bits define the scale configuration of Filter
0.
Bit 0 = FACT0 Filter Active
The software sets this bit to activate Filter 0. To
modify the Filter 0 registers (CF0R[0:7]), the
FACT0 bit must be cleared.
0: Filter 0 is not active
1: Filter 0 is active
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CAN FILTER CONFIGURATION REG.1 (CFCR1)
All bits of this register are set and cleared by software.
Read / Write
Reset Value: 0000 0000 (00h)
7
0
0
FSC31 FSC30 FACT3
0
FSC21 FSC20 FACT2
Bit 7 = Reserved. Forced to 0 by hardware.
Bit 6:5 = FSC3[1:0] Filter Scale Configuration
These bits define the scale configuration of Filter
3.
Bit 4 = FACT3 Filter Active
The software sets this bit to activate filter 3. To
modify the Filter 3 registers (CF3R[0:7]) the
FACT3 bit must be cleared.
0: Filter 3 is not active
1: Filter 3 is active
Bit 3 = Reserved. Forced to 0 by hardware.
Bit 2:1 = FSC2[1:0] Filter Scale Configuration
These bits define the scale configuration of Filter
2.
Bit 0 = FACT2 Filter Active
The software sets this bit to activate Filter 2. To
modify the Filter 2 registers (CF2R[0:7]), the
FACT2 bit must be cleared.
0: Filter 2 is not active
1: Filter 2 is active
ST72561
beCAN CONTROLLER (Cont’d)
CAN FILTER CONFIGURATION REG.1 (CFCR2)
All bits of this register are set and cleared by software.
Read / Write
Reset Value: 0000 0000 (00h)
7
0
0
FSC51 FSC50 FACT5
0
FSC41 FSC40 FACT4
Bit 7 = Reserved. Forced to 0 by hardware.
Bit 6:5 = FSC5[1:0] Filter Scale Configuration
These bits define the scale configuration of Filter
5.
Bit 4 = FACT5 Filter Active
The software sets this bit to activate filter 5. To
modify the Filter 5 registers (CF5R[0:7]) the
FACT5 bit must be cleared.
0: Filter 5 is not active
1: Filter 5 is active
Bit 3 = Reserved. Forced to 0 by hardware.
Bit 2:1 = FSC4[1:0] Filter Scale Configuration
These bits define the scale configuration of Filter
4.
Bit 0 = FACT4 Filter Active
The software sets this bit to activate Filter 4. To
modify the Filter 4 registers (CF4R[0:7]), the
FACT4 bit must be cleared.
0: Filter 4 is not active
1: Filter 4 is active
CAN FILTER MODE REGISTER (CFMR0)
All bits of this register are set and cleared by software.
Read / Write
Reset Value: 0000 0000 (00h)
7
FMH3
0
FML3
FMH2
FML2
FMH1
FML1
FMH0
FML0
Bit 7 = FMH3 Filter Mode High
Mode of the high registers of Filter 3.
0: High registers are in mask mode
1: High registers are in identifier list mode
Bit 6 = FML3 Filter Mode Low
Mode of the low registers of Filter 3.
0: Low registers are in mask mode
1: Low registers are in identifier list mode
Bit 5 = FMH2 Filter Mode High
Mode of the high registers of Filter 2.
0: High registers are in mask mode
1: High registers are in identifier list mode
Bit 4 = FML2 Filter Mode Low
Mode of the low registers of Filter 2.
0: Low registers are in mask mode
1: Low registers are in identifier list mode
Bit 3 = FMH1 Filter Mode High
Mode of the high registers of Filter 1.
0: High registers are in mask mode
1: High registers are in identifier list mode
Bit 2 = FML1 Filter Mode Low
Mode of the low registers of filter 1.
0: Low registers are in mask mode
1: Low registers are in identifier list mode
Bit 1 = FMH0 Filter Mode High
Mode of the high registers of filter 0.
0: High registers are in mask mode
1: High registers are in identifier list mode
Bit 0 = FML0 Filter Mode Low
Mode of the low registers of filter 0.
0: Low registers are in mask mode
1: Low registers are in identifier list mode
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ST72561
beCAN CONTROLLER (Cont’d)
CAN FILTER MODE REGISTER (CFMR1)
All bits of this register are set and cleared by software.
Read / Write
Reset Value: 0000 0000 (00h)
7
0
0
0
0
0
FMH5
FML5
FMH4
FML4
Bit 7:4 = Reserved. Forced to 0 by hardware.
Bit 3 = FMH5 Filter Mode High
Mode of the high registers of Filter 5.
0: High registers are in mask mode
1: High registers are in identifier list mode
Bit 2 = FML5 Filter Mode Low
Mode of the low registers of filter 5.
0: Low registers are in mask mode
1: Low registers are in identifier list mode
Bit 1 = FMH4 Filter Mode High
Mode of the high registers of filter 4.
0: High registers are in mask mode
1: High registers are in identifier list mode
Bit 0 = FML4 Filter Mode Low
Mode of the low registers of filter 4.
0: Low registers are in mask mode
1: Low registers are in identifier list mode
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FILTER x REGISTER[7:0] (CFxR[7:0])
Read / Write
Reset Value: Undefined
7
FB7
0
FB6
FB5
FB4
FB3
FB2
FB1
FB0
In all configurations:
Bit 7:0 = FB[7:0] Filter Bits
Identifier
Each bit of the register specifies the level of the
corresponding bit of the expected identifier.
0: Dominant bit is expected
1: Recessive bit is expected
Mask
Each bit of the register specifies whether the bit of
the associated identifier register must match with
the corresponding bit of the expected identifier or
not.
0: Don’t care, the bit is not used for the comparison
1: Must match, the bit of the incoming identifier
must have the same level has specified in the
corresponding identifier register of the filter.
Note: Each filter x is composed of 8 registers,
CFxR[7:0]. Depending on the scale and mode
configuration of the filter the function of each register can differ. For the filter mapping, functions
description and mask registers association, refer
to Section 10.9.4.3Identifier Filtering.
A Mask/Identifier register in mask mode has the
same bit mapping as in identifier list mode.
Note: To modify these registers, the corresponding FACT bit in the CFCR register must be
cleared.
ST72561
beCAN CONTROLLER (Cont’d)
Figure 115. CAN Register Mapping
68h
CAN MASTER CONTROL REGISTER
CMCR
69h
CAN MASTER STATUS REGISTER
CMSR
6Ah
CAN TRANSMIT STATUS REGISTER
CTSR
6Bh
CAN TRANSMIT PRIORITY REGISTER
CTPR
6Ch
CAN RECEIVE FIFO REGISTER
CRFR
6Dh
CAN INTERRUPT ENABLE REGISTER
CIER
6Eh
CAN DIAGNOSIS REGISTER
CDGR
6Fh
CAN PAGE SELECTION REGISTER
CPSR
PAGED REGISTER 0
PAGED REGISTER 1
PAGED REGISTER 2
PAGED REGISTER 3
PAGED REGISTER 4
PAGED REGISTER 5
PAGED REGISTER 6
PAGED REGISTER 7
PAGED REGISTER 8
PAGED REGISTER 9
PAGED REGISTER 10
PAGED REGISTER 11
PAGED REGISTER 12
PAGED REGISTER 13
XXh
PAGED REGISTER 14
PAGED REGISTER 15
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beCAN CONTROLLER (Cont’d)
10.9.8.4 Page Mapping for CAN
PAGE 0
PAGE 1
PAGE 2
PAGE 3
PAGE 4
70h
MCSR
MCSR
CF0R0
CF2R0
CF4R0
71h
MDLC
MDLC
CF0R1
CF2R1
CF4R1
72h
MIDR0
MIDR0
CF0R2
CF2R2
CF4R2
73h
MIDR1
MIDR1
CF0R3
CF2R3
CF4R3
74h
MIDR2
MIDR2
CF0R4
CF2R4
CF4R4
75h
MIDR3
MIDR3
CF0R5
CF2R5
CF4R5
76h
MDAR0
MDAR0
CF0R6
CF2R6
CF4R6
77h
MDAR1
MDAR1
CF0R7
CF2R7
CF4R7
78h
MDAR2
MDAR2
CF1R0
CF3R0
CF5R0
79h
MDAR3
MDAR3
CF1R1
CF3R1
CF5R1
7Ah
MDAR4
MDAR4
CF1R2
CF3R2
CF5R2
7Bh
MDAR5
MDAR5
CF1R3
CF3R3
CF5R3
7Ch
MDAR6
MDAR6
CF1R4
CF3R4
CF5R4
7Dh
MDAR7
MDAR7
CF1R5
CF3R5
CF5R5
7Eh
MTSLR
MTSLR
CF1R6
CF3R6
CF5R6
7Fh
MTSHR
MTSHR
CF1R7
CF3R7
CF5R7
Tx Mailbox 0
Tx Mailbox 1
Acceptance Filter 0:1
Acceptance Filter 2:3
Acceptance Filter 4:5
PAGE 6
PAGE 7
70h
CESR
MFMI
71h
CEIER
MDLC
72h
TECR
MIDR0
73h
RECR
MIDR1
74h
BTCR0
MIDR2
75h
BTCR1
MIDR3
76h
Reserved
MDAR0
77h
Reserved
MDAR1
78h
CFMR0
MDAR2
79h
CFMR1
MDAR3
7Ah
CFCR0
MDAR4
7Bh
CFCR1
MDAR5
7Ch
CFCR2
MDAR6
7Dh
Reserved
MDAR7
7Eh
Reserved
MTSLR
7Fh
Reserved
MTSHR
Configuration/Diagnosis
Receive FIFO
208/262
ST72561
beCAN CONTROLLER (Cont’d)
Table 31. beCAN Control & Status Page - Register Map and Reset Values
Address
(Hex.)
68h
69h
6Ah
6Bh
6Ch
6Dh
6Eh
6Fh
Register
Name
7
CMCR
6
5
4
3
2
1
0
ABOM
AWUM
NART
RFLM
TXFP
SLEEP
INRQ
0
0
0
0
0
0
1
0
REC
TRAN
WKUI
ERRI
SLAK
INAK
0
0
0
0
0
0
1
0
TXOK1
TXOK0
RQCP1
RQCP0
0
0
0
0
0
0
0
0
LOW1
LOW0
TME1
TME0
0
0
0
1
1
1
RFOM
FOVR
FULL
Reset Value
0
0
0
0
0
0
CIER
WKUIE
0
0
0
FOVIE0
Reset Value
0
0
0
0
0
0
0
0
0
0
Reset Value
CMSR
Reset Value
CTSR
Reset Value
CTPR
Reset Value
CRFR
CDGR
Reset Value
0
0
FMP1
FMP0
0
0
FFIE0
FMPIE0
TMEIE
0
0
0
0
RX
SAMP
SILM
LBKM
1
1
0
0
FPS2
FPS1
FPS0
0
0
0
CFPSR
Reset Value
CODE0
Table 32. beCAN Mailbox Pages - Register Map and Reset Values
Address
(Hex.)
Register
Name
7
6
5
4
3
2
1
0
70h
MFMI
FMI7
FMI6
FMI5
FMI4
FMI3
FMI2
FMI1
FMI0
Receive
Reset Value
0
0
0
0
0
0
0
0
70h
MCSR
TERR
ALST
TXOK
RQCP
ABRQ
TXRQ
Transmit
Reset Value
0
0
0
0
0
0
0
0
MDLC
0
DLC3
DLC2
DLC1
DLC0
Reset Value
x
x
x
x
x
x
x
x
71h
72h
73h
74h
75h
76h:7Dh
IDE
RTR
STID10
STID9
STID8
STID7
STID6
Reset Value
MIDR0
x
x
x
x
x
x
x
x
MIDR1
STID5
STID4
STID3
STID2
STID1
STID0
EXID17
EXID16
Reset Value
x
x
x
x
x
x
x
x
MIDR2
EXID15
EXID14
EXID13
EXID12
EXID11
EXID10
EXID9
EXID8
Reset Value
x
x
x
x
x
x
x
x
MIDR3
EXID7
EXID6
EXID5
EXID4
EXID3
EXID2
EXID1
EXID0
Reset Value
x
x
x
x
x
x
x
x
MDAR[0:7]
MDAR7
MDAR6
MDAR5
MDAR4
MDAR3
MDAR2
MDAR1
MDAR0
Reset Value
x
x
x
x
x
x
x
x
209/262
ST72561
Address
(Hex.)
7Eh
7Fh
Register
Name
7
6
5
4
3
2
1
0
MTSLR
TIME7
TIME6
TIME5
TIME4
TIME3
TIME2
TIME1
TIME0
Reset Value
x
x
x
x
x
x
x
x
MTSHR
TIME15
TIME14
TIME13
TIME12
TIME11
TIME10
TIME9
TIME8
Reset Value
x
x
x
x
x
x
x
x
2
1
0
BOFF
EPVF
EWGF
0
0
0
Table 33. beCAN Filter Configuration Page - Register Map and Reset Values
Address
(Hex.)
70h
71h
72h
73h
74h
75h
Register
Name
CESR
Reset Value
0
7Ch
210/262
LEC2
LEC1
LEC0
0
0
0
3
0
BOFIE
EPVIE
EWGIE
0
0
0
0
0
0
0
0
LECIE
TECR
TEC7
TEC6
TEC5
TEC4
TEC3
TEC2
TEC1
TEC0
Reset Value
0
0
0
0
0
0
0
0
RECR
REC7
REC6
REC5
REC4
REC3
REC2
REC1
REC0
Reset Value
0
0
0
0
0
0
0
0
CBTR0
SJW1
SJW0
BRP5
BRP4
BRP3
BRP2
BRP1
BRP0
Reset Value
0
0
0
0
0
0
0
0
CBTR1
BS22
BS21
BS20
BS13
BS12
BS11
BS10
0
0
1
0
0
0
1
1
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
CFMR0
FMH3
FML3
FMH2
FML2
FMH1
FML1
FMH0
FML0
Reset Value
0
0
0
0
0
0
0
0
0
0
0
0
FMH5
FML5
FMH4
FML4
0
0
0
0
Reset Value
Reserved
7Bh
4
ERRIE
77h
7Ah
5
CEIER
Reserved
79h
6
Reset Value
76h
78h
7
CFMR1
Reset Value
CFCR0
FFA1
FSC11
FSC10
FACT1
FFA0
FSC01
FSC00
FACT0
Reset Value
0
0
0
0
0
0
0
0
CFCR1
FFA3
FSC31
FSC30
FACT3
FFA2
FSC21
FSC20
FACT2
Reset Value
0
0
0
0
0
0
0
0
CFCR2
FFA5
FSC51
FSC50
FACT5
FFA4
FSC41
FSC40
FACT4
Reset Value
0
0
0
0
0
0
0
0
ST72561
10.10 10-BIT A/D CONVERTER (ADC)
10.10.1 Introduction
The on-chip Analog to Digital Converter (ADC) peripheral is a 10-bit, successive approximation converter with internal sample and hold circuitry. This
peripheral has up to 16 multiplexed analog input
channels (refer to device pin out description) that
allow the peripheral to convert the analog voltage
levels from up to 16 different sources.
The result of the conversion is stored in a 10-bit
Data Register. The A/D converter is controlled
through a Control/Status Register.
10.10.3 Functional Description
10.10.3.1 Digital A/D Conversion Result
The conversion is monotonic, meaning that the result never decreases if the analog input does not
and never increases if the analog input does not.
If the input voltage (VAIN) is greater than VDDA
(high-level voltage reference) then the conversion
result is FFh in the ADCDRH register and 03h in
the ADCDRL register (without overflow indication).
If the input voltage (VAIN) is lower than VSSA (lowlevel voltage reference) then the conversion result
in the ADCDRH and ADCDRL registers is 00 00h.
The A/D converter is linear and the digital result of
the conversion is stored in the ADCDRH and ADCDRL registers. The accuracy of the conversion is
described in the Electrical Characteristics Section.
RAIN is the maximum recommended impedance
for an analog input signal. If the impedance is too
high, this will result in a loss of accuracy due to
leakage and sampling not being completed in the
alloted time.
10.10.2 Main Features
■ 10-bit conversion
■ Up to 16 channels with multiplexed input
■ Linear successive approximation
■ Data register (DR) which contains the results
■ Conversion complete status flag
■ On/off bit (to reduce consumption)
The block diagram is shown in Figure 116.
Figure 116. ADC Block Diagram
fCPU
fADC
fCPU, fCPU/2, fCPU/4
EOC SPEEDADON SLOW CH3
CH2
CH1
CH0
ADCCSR
4
AIN0
AIN1
ANALOG TO DIGITAL
ANALOG
MUX
CONVERTER
AINx
ADCDRH
D9
D8
ADCDRL
D7
0
D6
0
D5
0
D4
0
D3
0
D2
0
D1
D0
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ST72561
10-BIT A/D CONVERTER (ADC) (Cont’d)
10.10.3.2 A/D Conversion
The analog input ports must be configured as input, no pull-up, no interrupt. Refer to the «I/O
ports» chapter. Using these pins as analog inputs
does not affect the ability of the port to be read as
a logic input.
In the ADCCSR register:
– Select the CS[3:0] bits to assign the analog
channel to convert.
in the ADCCSR register, the current conversion is
stopped, the EOC bit is cleared, and the A/D converter starts converting the newly selected channel.
10.10.3.4 ADCDR consistency
If an End Of Conversion event occurs after software has read the ADCDRLSB but before it has
read the ADCDRMSB, there would be a risk that
the two values read would belong to different samples.
ADC Conversion mode
In the ADCCSR register:
– Set the ADON bit to enable the A/D converter
and to start the conversion. From this time on,
the ADC performs a continuous conversion of
the selected channel.
To guarantee consistency:
– The ADCDRL and the ADCDRH registers are
locked when the ADCCRL is read
– The ADCDRL and the ADCDRH registers are
unlocked when the ADCDRH register is read
or when ADON is reset.
When a conversion is complete:
– The EOC bit is set by hardware.
– The result is in the ADCDR registers.
A read to the ADCDRH resets the EOC bit.
This is important, as the ADCDR register will not
be updated until the ADCDRH register is read.
10.10.4 Low Power Modes
Note: The A/D converter may be disabled by resetting the ADON bit. This feature allows reduced
power consumption when no conversion is needed and between single shot conversions.
To read the 10 bits, perform the following steps:
1. Poll EOC bit
2. Read the ADCDRL register
3. Read the ADCDRH register. This clears EOC
automatically.
Mode
WAIT
HALT
To read only 8 bits, perform the following steps:
1. Poll EOC bit
2. Read the ADCDRH register. This clears EOC
automatically.
10.10.3.3 Changing the conversion channel
The application can change channels during conversion. When software modifies the CH[3:0] bits
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Description
No effect on A/D Converter
A/D Converter disabled.
After wakeup from Halt mode, the A/D
Converter requires a stabilisation time
tSTAB (see Electrical Characteristics)
before accurate conversions can be
performed.
10.10.5 Interrupts
None.
ST72561
10-BIT A/D CONVERTER (ADC) (Cont’d)
10.10.6 Register Description
CONTROL/STATUS REGISTER (ADCCSR)
Read /Write (Except bit 7 read only)
Reset Value: 0000 0000 (00h)
7
0
EOC SPEED ADON SLOW
CH3
CH2
CH1
CH0
Bit 7 = EOC End of Conversion
This bit is set by hardware. It is cleared by software reading the ADCDRH register or writing to
any bit of the ADCCSR register.
0: Conversion is not complete
1: Conversion complete
Bit 6 = SPEED A/D clock selection
This bit is set and cleared by software.
Table 34. A/D Clock Selection
fADC
SLOW
SPEED
fCPU/2
fCPU (where fCPU <= 4 MHz)
fCPU/4
fCPU/2 (same frequency as
SLOW=0, SPEED=0)
0
0
1
0
1
0
1
1
Bit 5 = ADON A/D Converter on
This bit is set and cleared by software.
0: Disable ADC and stop conversion
1: Enable ADC and start conversion
Bit 4 = SLOW A/D Clock Selection
This bit is set and cleared by software. It works together with the SPEED bit. Refer to Table 34.
Channel Pin*
CH3
CH2
CH1
CH0
AIN0
AIN1
AIN2
AIN3
AIN4
AIN5
AIN6
AIN7
AIN8
AIN9
AIN10
AIN11
AIN12
AIN13
AIN14
AIN15
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
DATA REGISTER (ADCDRH)
Read Only
Reset Value: 0000 0000 (00h)
7
D9
0
D8
D7
D6
D5
D4
D3
D2
Bit 7:0 = D[9:2] MSB of Analog Converted Value
DATA REGISTER (ADCDRL)
Read Only
Reset Value: 0000 0000 (00h)
7
Bit 3:0 = CH[3:0] Channel Selection
These bits are set and cleared by software. They
select the analog input to convert.
*The number of channels is device dependent. Refer to
the device pinout description.
0
0
0
0
0
0
0
D1
D0
Bit 7:2 = Reserved. Forced by hardware to 0.
Bit 1:0 = D[1:0] LSB of Analog Converted Value
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ST72561
10-BIT A/D CONVERTER (ADC) (Cont’d)
Table 35. ADC Register Map and Reset Values
Address
(Hex.)
Register
Label
7
6
5
4
3
2
1
0
45h
ADCCSR
Reset Value
EOC
0
SPEED
0
ADON
0
SLOW
0
CH3
0
CH2
0
CH1
0
CH0
0
46h
ADCDRH
Reset Value
D9
0
D8
0
D7
0
D6
0
D5
0
D4
0
D3
0
D2
0
47h
ADCDRL
Reset Value
0
0
0
0
0
0
0
0
0
0
0
0
D1
0
D0
0
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ST72561
11 INSTRUCTION SET
11.1 CPU ADDRESSING MODES
The CPU features 17 different addressing modes
which can be classified in 7 main groups:
Addressing Mode
Example
Inherent
nop
Immediate
ld A,#$55
Direct
ld A,$55
Indexed
ld A,($55,X)
Indirect
ld A,([$55],X)
Relative
jrne loop
Bit operation
bset
byte,#5
The CPU Instruction set is designed to minimize
the number of bytes required per instruction: To do
so, most of the addressing modes may be subdivided in two sub-modes called long and short:
– Long addressing mode is more powerful because it can use the full 64 Kbyte address space,
however it uses more bytes and more CPU cycles.
– Short addressing mode is less powerful because
it can generally only access page zero (0000h 00FFh range), but the instruction size is more
compact, and faster. All memory to memory instructions use short addressing modes only
(CLR, CPL, NEG, BSET, BRES, BTJT, BTJF,
INC, DEC, RLC, RRC, SLL, SRL, SRA, SWAP)
The ST7 Assembler optimizes the use of long and
short addressing modes.
Table 36. CPU Addressing Mode Overview
Mode
Syntax
Destination
Pointer
Address
(Hex.)
Pointer Size
(Hex.)
Length
(Bytes)
Inherent
nop
+0
Immediate
ld A,#$55
+1
Short
Direct
ld A,$10
00..FF
+1
Long
Direct
ld A,$1000
0000..FFFF
+2
No Offset
Direct
Indexed
ld A,(X)
00..FF
+0
Short
Direct
Indexed
ld A,($10,X)
00..1FE
+1
Long
Direct
Indexed
ld A,($1000,X)
0000..FFFF
+2
Short
Indirect
ld A,[$10]
00..FF
00..FF
byte
+2
Long
Indirect
ld A,[$10.w]
0000..FFFF
00..FF
word
+2
Short
Indirect
Indexed
ld A,([$10],X)
00..1FE
00..FF
byte
+2
Long
Indirect
Indexed
ld A,([$10.w],X)
0000..FFFF
00..FF
word
+2
Relative
Direct
jrne loop
PC+/-127
Relative
Indirect
jrne [$10]
PC+/-127
Bit
Direct
bset $10,#7
00..FF
Bit
Indirect
bset [$10],#7
00..FF
Bit
Direct
Relative
btjt $10,#7,skip
00..FF
Bit
Indirect
Relative
btjt [$10],#7,skip
00..FF
+1
00..FF
byte
+2
+1
00..FF
byte
+2
+2
00..FF
byte
+3
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ST72561
INSTRUCTION SET OVERVIEW (Cont’d)
11.1.1 Inherent
All Inherent instructions consist of a single byte.
The opcode fully specifies all the required information for the CPU to process the operation.
Inherent Instruction
Function
NOP
No operation
TRAP
S/W Interrupt
WFI
Wait For Interrupt (Low Power Mode)
HALT
Halt Oscillator (Lowest Power
Mode)
RET
Sub-routine Return
IRET
Interrupt Sub-routine Return
SIM
Set Interrupt Mask (level 3)
RIM
Reset Interrupt Mask (level 0)
SCF
Set Carry Flag
RCF
Reset Carry Flag
RSP
Reset Stack Pointer
LD
Load
CLR
Clear
PUSH/POP
Push/Pop to/from the stack
INC/DEC
Increment/Decrement
TNZ
Test Negative or Zero
CPL, NEG
1 or 2 Complement
MUL
Byte Multiplication
SLL, SRL, SRA, RLC,
RRC
Shift and Rotate Operations
SWAP
Swap Nibbles
11.1.2 Immediate
Immediate instructions have two bytes, the first
byte contains the opcode, the second byte contains the operand value.
Immediate Instruction
Function
LD
Load
CP
Compare
BCP
Bit Compare
AND, OR, XOR
Logical Operations
ADC, ADD, SUB, SBC
Arithmetic Operations
216/262
11.1.3 Direct
In Direct instructions, the operands are referenced
by their memory address.
The direct addressing mode consists of two submodes:
Direct (short)
The address is a byte, thus requires only one byte
after the opcode, but only allows 00 - FF addressing space.
Direct (long)
The address is a word, thus allowing 64 Kbyte addressing space, but requires 2 bytes after the opcode.
11.1.4 Indexed (No Offset, Short, Long)
In this mode, the operand is referenced by its
memory address, which is defined by the unsigned
addition of an index register (X or Y) with an offset.
The indirect addressing mode consists of three
sub-modes:
Indexed (No Offset)
There is no offset, (no extra byte after the opcode),
and allows 00 - FF addressing space.
Indexed (Short)
The offset is a byte, thus requires only one byte after the opcode and allows 00 - 1FE addressing
space.
Indexed (long)
The offset is a word, thus allowing 64 Kbyte addressing space and requires 2 bytes after the opcode.
11.1.5 Indirect (Short, Long)
The required data byte to do the operation is found
by its memory address, located in memory (pointer).
The pointer address follows the opcode. The indirect addressing mode consists of two sub-modes:
Indirect (short)
The pointer address is a byte, the pointer size is a
byte, thus allowing 00 - FF addressing space, and
requires 1 byte after the opcode.
Indirect (long)
The pointer address is a byte, the pointer size is a
word, thus allowing 64 Kbyte addressing space,
and requires 1 byte after the opcode.
ST72561
INSTRUCTION SET OVERVIEW (Cont’d)
11.1.6 Indirect Indexed (Short, Long)
This is a combination of indirect and short indexed
addressing modes. The operand is referenced by
its memory address, which is defined by the unsigned addition of an index register value (X or Y)
with a pointer value located in memory. The pointer address follows the opcode.
The indirect indexed addressing mode consists of
two sub-modes:
Indirect Indexed (Short)
The pointer address is a byte, the pointer size is a
byte, thus allowing 00 - 1FE addressing space,
and requires 1 byte after the opcode.
Indirect Indexed (Long)
The pointer address is a byte, the pointer size is a
word, thus allowing 64 Kbyte addressing space,
and requires 1 byte after the opcode.
Table 37. Instructions Supporting Direct,
Indexed, Indirect and Indirect Indexed
Addressing Modes
Long and Short
Instructions
LD
11.1.7 Relative mode (Direct, Indirect)
This addressing mode is used to modify the PC
register value, by adding an 8-bit signed offset to
it.
Available Relative
Direct/Indirect
Instructions
Function
JRxx
Conditional Jump
CALLR
Call Relative
The relative addressing mode consists of two submodes:
Relative (Direct)
The offset is following the opcode.
Relative (Indirect)
The offset is defined in memory, which address
follows the opcode.
Function
Load
CP
Compare
AND, OR, XOR
Logical Operations
ADC, ADD, SUB, SBC
Arithmetic Additions/Substractions operations
BCP
Bit Compare
Short Instructions
Only
Function
CLR
Clear
INC, DEC
Increment/Decrement
TNZ
Test Negative or Zero
CPL, NEG
1 or 2 Complement
BSET, BRES
Bit Operations
BTJT, BTJF
Bit Test and Jump Operations
SLL, SRL, SRA, RLC,
RRC
Shift and Rotate Operations
SWAP
Swap Nibbles
CALL, JP
Call or Jump subroutine
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ST72561
INSTRUCTION SET OVERVIEW (Cont’d)
11.2 INSTRUCTION GROUPS
The ST7 family devices use an Instruction Set
consisting of 63 instructions. The instructions may
be subdivided into 13 main groups as illustrated in
the following table:
Load and Transfer
LD
CLR
Stack operation
PUSH
POP
Increment/Decrement
INC
DEC
Compare and Tests
CP
TNZ
BCP
Logical operations
AND
OR
XOR
CPL
NEG
Bit Operation
BSET
BRES
Conditional Bit Test and Branch
BTJT
BTJF
Arithmetic operations
ADC
ADD
SUB
SBC
MUL
Shift and Rotates
SLL
SRL
SRA
RLC
RRC
SWAP
SLA
Unconditional Jump or Call
JRA
JRT
JRF
JP
CALL
CALLR
NOP
Conditional Branch
JRxx
Interruption management
TRAP
WFI
HALT
IRET
Condition Code Flag modification
SIM
RIM
SCF
RCF
Using a pre-byte
The instructions are described with one to four opcodes.
In order to extend the number of available opcodes for an 8-bit CPU (256 opcodes), three different prebyte opcodes are defined. These prebytes
modify the meaning of the instruction they precede.
The whole instruction becomes:
PC-2
End of previous instruction
PC-1
Prebyte
PC
opcode
PC+1
Additional word (0 to 2) according
to the number of bytes required to compute the effective address
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RSP
RET
These prebytes enable instruction in Y as well as
indirect addressing modes to be implemented.
They precede the opcode of the instruction in X or
the instruction using direct addressing mode. The
prebytes are:
PDY 90
Replace an X based instruction
using immediate, direct, indexed, or inherent addressing mode by a Y one.
PIX 92
Replace an instruction using direct, direct bit, or direct relative addressing mode
to an instruction using the corresponding indirect
addressing mode.
It also changes an instruction using X indexed addressing mode to an instruction using indirect X indexed addressing mode.
PIY 91
Replace an instruction using X indirect indexed addressing mode by a Y one.
ST72561
INSTRUCTION SET OVERVIEW (Cont’d)
Mnemo
Description
Function/Example
Dst
Src
I1
H
I0
N
Z
C
ADC
Add with Carry
A=A+M+C
A
M
H
N
Z
C
ADD
Addition
A=A+M
A
M
H
N
Z
C
AND
Logical And
A=A.M
A
M
N
Z
BCP
Bit compare A, Memory
tst (A . M)
A
M
N
Z
BRES
Bit Reset
bres Byte, #3
M
BSET
Bit Set
bset Byte, #3
M
BTJF
Jump if bit is false (0)
btjf Byte, #3, Jmp1
M
C
BTJT
Jump if bit is true (1)
btjt Byte, #3, Jmp1
M
C
CALL
Call subroutine
CALLR
Call subroutine relative
CLR
Clear
CP
Arithmetic Compare
tst(Reg - M)
reg
CPL
One Complement
A = FFH-A
DEC
Decrement
dec Y
HALT
Halt
IRET
Interrupt routine return
Pop CC, A, X, PC
INC
Increment
inc X
JP
Absolute Jump
jp [TBL.w]
reg, M
0
1
N
Z
C
reg, M
N
Z
1
reg, M
N
Z
N
Z
N
Z
M
1
JRA
Jump relative always
JRT
Jump relative
JRF
Never jump
jrf *
JRIH
Jump if ext. INT pin = 1
(ext. INT pin high)
JRIL
Jump if ext. INT pin = 0
(ext. INT pin low)
JRH
Jump if H = 1
H=1?
JRNH
Jump if H = 0
H=0?
JRM
Jump if I1:0 = 11
I1:0 = 11 ?
JRNM
Jump if I1:0 <> 11
I1:0 <> 11 ?
JRMI
Jump if N = 1 (minus)
N=1?
JRPL
Jump if N = 0 (plus)
N=0?
JREQ
Jump if Z = 1 (equal)
Z=1?
JRNE
Jump if Z = 0 (not equal)
Z=0?
JRC
Jump if C = 1
C=1?
JRNC
Jump if C = 0
C=0?
JRULT
Jump if C = 1
Unsigned <
JRUGE
Jump if C = 0
Jmp if unsigned >=
JRUGT
Jump if (C + Z = 0)
Unsigned >
I1
reg, M
0
H
I0
C
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ST72561
INSTRUCTION SET OVERVIEW (Cont’d)
Mnemo
Description
Dst
Src
JRULE
Jump if (C + Z = 1)
Unsigned <=
LD
Load
dst <= src
reg, M
M, reg
MUL
Multiply
X,A = X * A
A, X, Y
X, Y, A
NEG
Negate (2's compl)
neg $10
reg, M
NOP
No Operation
OR
OR operation
A=A+M
A
M
POP
Pop from the Stack
pop reg
reg
M
pop CC
CC
M
PUSH
Push onto the Stack
push Y
M
reg, CC
RCF
Reset carry flag
C=0
RET
Subroutine Return
RIM
Enable Interrupts
I1:0 = 10 (level 0)
RLC
Rotate left true C
C <= A <= C
reg, M
N
Z
C
RRC
Rotate right true C
C => A => C
reg, M
N
Z
C
RSP
Reset Stack Pointer
S = Max allowed
SBC
Substract with Carry
A=A-M-C
N
Z
C
SCF
Set carry flag
C=1
SIM
Disable Interrupts
I1:0 = 11 (level 3)
SLA
Shift left Arithmetic
C <= A <= 0
reg, M
N
Z
C
SLL
Shift left Logic
C <= A <= 0
reg, M
N
Z
C
SRL
Shift right Logic
0 => A => C
reg, M
0
Z
C
SRA
Shift right Arithmetic
A7 => A => C
reg, M
N
Z
C
SUB
Substraction
A=A-M
A
N
Z
C
SWAP
SWAP nibbles
A7-A4 <=> A3-A0
reg, M
N
Z
TNZ
Test for Neg & Zero
tnz lbl1
N
Z
TRAP
S/W trap
S/W interrupt
WFI
Wait for Interrupt
XOR
Exclusive OR
N
Z
220/262
Function/Example
A = A XOR M
I1
H
I0
N
Z
N
Z
0
I1
H
C
0
I0
N
Z
N
Z
N
Z
C
C
0
1
A
0
M
1
1
A
1
M
M
1
1
1
0
ST72561
12 ELECTRICAL CHARACTERISTICS
12.1 PARAMETER CONDITIONS
Unless otherwise specified, all voltages are referred to VSS.
12.1.1 Minimum and Maximum values
Unless otherwise specified the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and
frequencies by tests in production on 100% of the
devices with an ambient temperature at TA=25°C
and TA=TAmax (given by the selected temperature
range).
Data based on characterization results, design
simulation and/or technology characteristics are
indicated in the table footnotes and are not tested
in production. Based on characterization, the minimum and maximum values refer to sample tests
and represent the mean value plus or minus three
times the standard deviation (mean±3Σ).
12.1.2 Typical values
Unless otherwise specified, typical data are based
on TA=25°C, VDD=5V (for the 4.5V≤VDD≤5.5V
voltage range). They are given only as design
guidelines and are not tested.
Typical ADC accuracy values are determined by
characterization of a batch of samples from a
standard diffusion lot over the full temperature
range, where 95% of the devices have an error
less than or equal to the value indicated
(mean±2Σ).
12.1.3 Typical curves
Unless otherwise specified, all typical curves are
given only as design guidelines and are not tested.
12.1.4 Loading capacitor
The loading conditions used for pin parameter
measurement are shown in Figure 117.
12.1.5 Pin input voltage
The input voltage measurement on a pin of the device is described in Figure 118.
Figure 118. Pin input voltage
ST7 PIN
VIN
Figure 117. Pin loading conditions
ST7 PIN
CL
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ST72561
12.2 ABSOLUTE MAXIMUM RATINGS
Stresses above those listed as “absolute maximum ratings” may cause permanent damage to
the device. This is a stress rating only and functional operation of the device under these condi12.2.1 Voltage Characteristics
Symbol
Ratings
VDD - VSS
Supply voltage
VPP - VSS
Programming Voltage
VIN
|∆VDDx| and |∆VSSx|
|VSSA - VSSx|
tions is not implied. Exposure to maximum rating
conditions for extended periods may affect device
reliability.
Maximum value
Unit
6.5
13
Input voltage on any pin 1) & 2)
V
VSS-0.3 to VDD+0.3
Variations between different digital power pins
50
Variations between digital and analog ground pins
50
VESD(HBM)
Electro-static discharge voltage (Human Body Model)
VESD(MM)
Electro-static discharge voltage (Machine Model)
mV
see Section 12.8.3 on page 235
12.2.2 Current Characteristics
Symbol
IVDD
IVSS
Ratings
Maximum value
Total current into VDD power lines (source)
3)
150
Total current out of VSS ground lines (sink)
3)
150
Output current sunk by any standard I/O and control pin
IIO
IINJ(PIN) 2) & 4)
ΣIINJ(PIN) 2)
Output current sunk by any high sink I/O pin
Unit
25
50
Output current source by any I/Os and control pin
- 25
Injected current on VPP pin
±5
Injected current on RESET pin
±5
Injected current on OSC1 and OSC2 pins
±5
Injected current on PB3
+5
Injected current on any other pin 5) & 6)
±5
Total injected current (sum of all I/O and control pins) 5)
± 25
mA
12.2.3 Thermal Characteristics
Symbol
TSTG
TJ
Ratings
Storage temperature range
Value
Unit
-65 to +150
°C
Maximum junction temperature (see Section 13.2 "THERMAL CHARACTERISTICS")
Notes:
1. Directly connecting the RESET and I/O pins to VDD or VSS could damage the device if an unintentional internal reset
is generated or an unexpected change of the I/O configuration occurs (for example, due to a corrupted program counter).
To guarantee safe operation, this connection has to be done through a pull-up or pull-down resistor (typical: 4.7kΩ for
RESET, 10kΩ for I/Os). Unused I/O pins must be tied in the same way to VDD or VSS according to their reset configuration.
2. IINJ(PIN) must never be exceeded. This is implicitly insured if VIN maximum is respected. If VIN maximum cannot be
respected, the injection current must be limited externally to the IINJ(PIN) value. A positive injection is induced by VIN>VDD
while a negative injection is induced by VIN<VSS. For true open-drain pads, there is no positive injection current, and the
corresponding VIN maximum must always be respected
3. All power (VDD) and ground (VSS) lines must always be connected to the external supply.
4. Negative injection disturbs the analog performance of the device. See note in “10-BIT ADC CHARACTERISTICS” on
page 246.
5. When several inputs are submitted to a current injection, the maximum ΣIINJ(PIN) is the absolute sum of the positive
and negative injected currents (instantaneous values). These results are based on characterisation with ΣIINJ(PIN) maximum current injection on four I/O port pins of the device.
222/262
ST72561
12.3 OPERATING CONDITIONS
12.3.1 General Operating Conditions
Symbol
fCPU
VDD
Parameter
Conditions
Internal clock frequency
No Flash Write/Erase. Analog
parameters not guaranteed.
Extended Operating voltage
Standard Operating Voltage
TA
Min
Max
Unit
0
8
MHz
3.8
4.5
V
4.5
5.5
Operating Voltage for Flash Write/Erase
VPP = 11.4 to 12.6V
4.5
5.5
Ambient temperature range
C Suffix Version
-40
125
°C
Figure 119. fCPU Max Versus VDD
fCPU [MHz]
FUNCTIONALITY GUARANTEED IN THIS AREA
UNLESS OTHERWISE SPECIFIED IN THE TABLES OF
PARAMETRIC DATA
FUNCTIONALITY
GUARANTEED
IN THIS AREA
8
FUNCTIONALITY
NOT GUARANTEED
IN THIS AREA
6
4
2
1
0
3.5
3.8 4.0
4.5
5.0
5.5
SUPPLY VOLTAGE [V]
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ST72561
12.3.2 Operating Conditions with Low Voltage Detector (LVD)
Subject to general operating conditions for TA.
Symbol
Parameter
Conditions
VIT+(LVD)
Reset release threshold (VDD rise)
VIT-(LVD)
Reset generation threshold (VDD fall)
Vhys(LVD)
LVD voltage threshold hysteresis1)
VIT+(LVD)-VIT-(LVD)
Min
Typ
Max
4.0 1)
4.2
4.5
3.8
4.0
4.25
150
200
250
VDD rise time rate 1)
tg(VDD)
Width of filtered glitches on VDD
(which are not detected by the LVD)1)
V
mV
µs/V
6
VtPOR
Unit
100
ms/V
40
ns
Unit
Notes:
1. Data based on characterization results, not tested in production.
12.3.3 Auxiliary Voltage Detector (AVD) Thresholds
Subject to general operating conditions for TA.
Symbol
Parameter
Conditions
Min
Typ
Max
VIT+(AVD)
1⇒0 AVDF flag toggle threshold
(VDD rise)
4.4 1)
4.6
4.9
VIT-(AVD)
0⇒1 AVDF flag toggle threshold
(VDD fall)
4.2
4.4
4.651)
Vhys(AVD)
AVD voltage threshold hysteresis
VIT+(AVD)-VIT-(AVD)
250
mV
∆VIT-
Voltage drop between AVD flag set
and LVD reset activated
VIT-(AVD)-VIT-(LVD)
450
mV
V
1. Data based on characterization results, not tested in production.
Figure 120. LVD Startup Behaviour
5V
LVD RESET
VIT+
VD
D
2V
Reset state
not defined
in this area
t
Note: When the LVD is enabled, the MCU reaches its authorized operating voltage from a reset state.
However, in some devices, the reset signal may be undefined until VDD is approximately 2V. As a consequence, the I/Os may toggle when VDD is below this voltage.
Because Flash write access is impossible below this voltage, the Flash memory contents will not be corrupted.
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ST72561
12.4 SUPPLY CURRENT CHARACTERISTICS
The following current consumption specified for the ST7 functional operating modes over temperature
range does not take into account the clock source current consumption. To get the total device consumption, the two current values must be added (except for HALT mode for which the clock is stopped).
12.4.1 RUN and SLOW Modes (Flash devices)
Parameter
Supply current in RUN mode 3)
(see Figure 121)
IDD
Supply current in SLOW mode
(see Figure 122)
3)
Figure 121. Typical IDD in RUN mode
12
8
7
6
fcpu
1MHz
fcpu
4MHz
fcpu
2MHz
fcpu
8MHz
Max 2)
fOSC=2MHz, fCPU=1MHz
fOSC=4MHz, fCPU=2MHz
fOSC=8MHz, fCPU=4MHz
fOSC=16MHz, fCPU=8MHz
1.5
2.6
4.8
9.0
3.0
5.0
8.0
15.0
fOSC=2MHz, fCPU=62.5kHz
fOSC=4MHz, fCPU=125kHz
fOSC=8MHz, fCPU=250kHz
fOSC=16MHz, fCPU=500kHz
0.5
0.6
0.85
1.25
2.7
3.0
3.6
4.0
Unit
mA
Figure 122. Typical IDD in SLOW mode
7
fcpu
1MHz
fcpu
4MHz
fcpu
2MHz
fcpu
8MHz
6
5
Idd (mA)
Idd (mA)
11
10
9
Typ 1)
Conditions
3.8V≤VDD≤5.5V
Symbol
5
4
3
4
3
2
2
1
0
1
0
3.5
4
4.5
Vdd (V)
5
5.5
3.5
4
4.5
5
5.5
Vdd (V)
Notes:
1. Typical data are based on TA=25°C, VDD=5V (4.5V≤VDD≤5.5V range) .
2. Data based on characterization results, tested in production at VDD max. and fCPU max.
3. Measurements are done in the following conditions:
- Progam executed from RAM, CPU running with RAM access. The increase in consumption when running in Flash is
30%. There is no increase when running in ROM.
- All I/O pins in input mode with a static value at VDD or VSS (no load)
- All peripherals in reset state.
- LVD disabled.
- Clock input (OSC1) driven by external square wave.
- In SLOW and SLOW WAIT mode, fCPU is based on fOSC divided by 32.
To obtain the total current consumption of the device, add the clock source (Section 12.5.3 and Section 12.5.4) and the
peripheral power consumption (Section 12.4.5).
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ST72561
SUPPLY CURRENT CHARACTERISTICS (Cont’d)
12.4.2 WAIT and SLOW WAIT Modes (Flash devices)
Parameter
Supply current in WAIT mode 3)
(see Figure 123)
IDD
Supply current in SLOW WAIT mode
(see Figure 124)
3)
Figure 123. Typical IDD in WAIT mode
7
Max 2)
fOSC=2MHz, fCPU=1MHz
fOSC=4MHz, fCPU=2MHz
fOSC=8MHz, fCPU=4MHz
fOSC=16MHz, fCPU=8MHz
1
1.45
3
5.6
3.0
4.0
5.0
7.0
fOSC=2MHz, fCPU=62.5kHz
fOSC=4MHz, fCPU=125kHz
fOSC=8MHz, fCPU=250kHz
fOSC=16MHz, fCPU=500MHz
0.4
0.5
0.6
0.8
1.2
1.3
1.8
2.0
1
fcpu 4MHz
0.9
fcpu 2MHz
Unit
mA
Figure 124. Typical IDD in SLOW-WAIT vs. fOSC
fcpu 8MHz
fcpu 1MHz
fcpu 4MHz
fcpu 2MHz
fcpu 8MHz
0.8
5
0.7
4
0.6
Idd (mA)
Idd (mA)
6
fcpu 1MHz
Typ 1)
Conditions
3.8V≤VDD≤5.5V
Symbol
3
0.5
0.4
0.3
2
0.2
1
0.1
0
0
3.5
4
4.5
Vdd (V)
5
5.5
3.5
4
4.5
5
5.5
Vdd (V)
Notes:
1. Typical data are based on TA=25°C, VDD=5V (4.5V≤VDD≤5.5V range) .
2. Data based on characterization results, tested in production at VDD max. and fCPU max.
3. Measurements are done in the following conditions:
- Progam executed from RAM, CPU running with RAM access. The increase in consumption when running in Flash is
30%. There is no increase when running in ROM.
- All I/O pins in input mode with a static value at VDD or VSS (no load)
- All peripherals in reset state.
- LVD disabled.
- Clock input (OSC1) driven by external square wave.
- In SLOW and SLOW WAIT mode, fCPU is based on fOSC divided by 32.
To obtain the total current consumption of the device, add the clock source (Section 12.5.3 ) and the peripheral power
consumption (Section 12.4.5).
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ST72561
SUPPLY CURRENT CHARACTERISTICS (Cont’d)
12.4.3 HALT and ACTIVE-HALT Modes
Symbol
Parameter
IDD
Supply current in HALT mode 1)
IDD
Supply current in ACTIVE-HALT mode 1)2)
IDD
Supply current in AWUFH mode 1)2)
Conditions
VDD=5.5V
-40°C≤TA≤+85°C
-40°C≤TA≤+125°C
Typ
0
1
VDD=5.5V
-40°C≤TA≤+85°C
-40°C≤TA≤+125°C
25
Max
Unit
10
µA
50
1.2
mA
30
µA
70
1. All I/O pins in input mode with a static value at VDD or VSS (no load). Data tested in production at VDD max. and fCPU
max.
2. This consumption refers to the Halt period only and not the associated run period which is software dependent.
12.4.4 Supply and Clock Managers
The previous current consumption specified for the ST7 functional operating modes over temperature
range does not take into account the clock source current consumption. To get the total device consumption, the two current values must be added (except for HALT mode).
Symbol
Parameter
Conditions
Typ
IDD(RES)
Supply current of resonator oscillator 2) & 3)
IDD(PLL)
PLL supply current
VDD= 5V
360
IDD(LVD)
LVD supply current
HALT mode, VDD= 5V
150
Max1)
See Section
12.5.3 on page
230
Unit
µA
300
Notes:
1. Data based on characterization results, not tested in production.
2. Data based on characterization results done with the external components specified in Section 12.5.3 , not tested in
production.
3. As the oscillator is based on a current source, the consumption does not depend on the voltage.
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ST72561
12.4.5 On-Chip Peripherals
TA= 25°C, fCPU=8 Mhz.
Symbol
Parameter
Conditions
Typ
IDD(TIM)
16-bit Timer supply current 1)
VDD=5.0V
50
IDD(TIM8)
8-bit Timer supply current 1)
VDD=5.0V
50
IDD(ART)
ART PWM supply current2)
VDD=5.0V
75
IDD(SPI)
SPI supply current 3)
VDD=5.0V
400
IDD(SCI)
SCI supply current 4)
VDD=5.0V
400
IDD(CAN
IDD(ADC)
CAN supply current 5)
VDD=5.0V
800
ADC supply current when converting 6)
VDD=5.0V
400
Unit
µA
Notes:
1. Data based on a differential IDD measurement between reset configuration (timer counter running at fCPU/4) and timer
counter stopped (only TIMD bit set). Data valid for one timer.
2. Data based on a differential IDD measurement between reset configuration (timer stopped) and timer counter enabled
(only TCE bit set).
3. Data based on a differential IDD measurement between reset configuration (SPI disabled) and a permanent SPI master
communication at maximum speed (data sent equal to 55h).This measurement includes the pad toggling consumption.
4. Data based on a differential IDD measurement between SCI low power state (SCID=1) and a permanent SCI data transmit sequence. Data valid for one SCI.
5. Data based on a differential IDD measurement between reset configuration (CAN disabled) and a permanent CAN data
transmit sequence with RX and TX connected together. This measurement include the pad toggling consumption.
6. Data based on a differential IDD measurement between reset configuration and continuous A/D conversions.
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ST72561
12.5 CLOCK AND TIMING CHARACTERISTICS
Subject to general operating conditions for VDD, fOSC, and TA.
12.5.1 General Timings
Symbol
tc(INST)
tv(IT)
Parameter
Conditions
Instruction cycle time
Interrupt reaction time
tv(IT) = ∆tc(INST) + 10
fCPU=8MHz
2)
fCPU=8MHz
Min
Typ 1)
Max
Unit
2
3
12
tCPU
250
375
1500
ns
10
22
tCPU
1.25
2.75
µs
12.5.2 External Clock Source
Symbol
Parameter
Conditions
Min
Typ
Max
VOSC1H
OSC1 input pin high level voltage
0.7xVDD
VDD
VOSC1L
OSC1 input pin low level voltage
VSS
0.3xVDD
tw(OSC1H)
tw(OSC1L)
tr(OSC1)
tf(OSC1)
IL
OSC1 high or low time 3)
see Figure 125
Unit
V
25
ns
OSC1 rise or fall time 3)
5
VSS≤VIN≤VDD
OSCx Input leakage current
±1
µA
Figure 125. Typical Application with an External Clock Source
90%
VOSC1H
10%
VOSC1L
tr(OSC1)
tf(OSC1)
OSC2
tw(OSC1H)
tw(OSC1L)
Not connected internally
fOSC
EXTERNAL
CLOCK SOURCE
OSC1
IL
ST72XXX
Notes:
1. Data based on typical application software.
2. Time measured between interrupt event and interrupt vector fetch. ∆tc(INST) is the number of tCPU cycles needed to finish
the current instruction execution.
3. Data based on design simulation and/or technology characteristics, not tested in production.
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ST72561
CLOCK AND TIMING CHARACTERISTICS (Cont’d)
12.5.3 Crystal and Ceramic Resonator Oscillators
The ST7 internal clock can be supplied with four
different Crystal/Ceramic resonator oscillators. All
the information given in this paragraph are based
on characterization results with specified typical
external components. In the application, the resonator and the load capacitors have to be placed as
Symbol
Parameter
fOSC
Oscillator Frequency 3)
RF
Feedback resistor
CL1
CL2
i2
close as possible to the oscillator pins in order to
minimize output distortion and start-up stabilization time. Refer to the crystal/ceramic resonator
manufacturer for more details (frequency, package, accuracy...).
Conditions
LP: Low power oscillator
MP: Medium power oscillator
MS: Medium speed oscillator
HS: High speed oscillator
R =200Ω
Recommended load capacitatance ver- S
RS=200Ω
sus equivalent serial resistance of the
RS=200Ω
crystal or ceramic resonator (RS)
RS=100Ω
VDD=5V
VIN=VSS
OSC2 driving current
Min
Max
Unit
1
>2
>4
>8
2
4
8
16
MHz
20
40
kΩ
LP oscillator
MP oscillator
MS oscillator
HS oscillator
22
22
18
15
56
46
33
33
pF
LP oscillator
MP oscillator
MS oscillator
HS oscillator
80
160
310
610
150
250
460
910
µA
Figure 126. Typical Application with a Crystal or Ceramic Resonator
WHEN RESONATOR WITH
INTEGRATED CAPACITORS
i2
fOSC
CL1
OSC1
RESONATOR
CL2
RF
OSC2
ST72XXX
Notes:
1. Resonator characteristics given by the crystal/ceramic resonator manufacturer.
2. tSU(OSC) is the typical oscillator start-up time measured between VDD=2.8V and the fetch of the first instruction (with a
quick VDD ramp-up from 0 to 5V (<50µs).
3. The oscillator selection can be optimized in terms of supply current using an high quality resonator with small RS value.
Refer to crystal/ceramic resonator manufacturer for more details.
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ST72561
CLOCK CHARACTERISTICS (Cont’d)
12.5.4 PLL Characteristics
Operating conditions: VDD 3.8 to 5.5V @ TA 0 to 70°C1) or VDD 4.5 to 5.5V @ TA -40 to 125°C
Symbol
Parameter
VDD(PLL)
PLL Voltage Range
fOSC
PLL input frequency range
∆ fCPU/fCPU
PLL jitter 1)
Conditions
Min
Typ
Max
TA 0 to 70°C
3.8
5.5
TA -40 to +125°C
4.5
5.5
2
Unit
4
MHz
fOSC = 4 MHz. VDD= 4.5 to 5.5V
TBD
TBD
%
fOSC = 2 MHz. VDD= 4.5 to 5.5V
TBD
TBD
%
Note:
1. Data characterized but not tested.
Figure 127. PLL Jitter vs. Signal frequency1
0.8
+/-Jitter (%)
0.7
0.6
PLL ON
0.5
PLL OFF
0.4
0.3
0.2
0.1
0
2000
The user must take the PLL jitter into account in
the application (for example in serial communication or sampling of high frequency signals). The
PLL jitter is a periodic effect, which is integrated
over several CPU cycles. Therefore the longer the
period of the application signal, the less it will be
impacted by the PLL jitter.
Figure 87 shows the PLL jitter integrated on application signals in the range 125kHz to 2MHz. At frequencies of less than 125KHz, the jitter is negligible.
1000
500
250
125
Application Signal Frequency (KHz)
Note 1: Measurement conditions: fCPU = 4MHz, TA= 25°C
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ST72561
CLOCK CHARACTERISTICS (Cont’d)
12.6 Auto Wakeup from Halt Oscillator (AWU)
Symbol
fAWU
Parameter
Conditions
AWU Oscillator Frequency
AWU Oscillator startup time
tRCSRT
Figure 128. AWU Oscillator Freq @ TA 25C
Freq(KHz)
200
150
100
Ta=25C
50
4.4
232/262
5
Vdd
5.6
Min
Typ
Max
Unit
50
100
250
50
kHz
µs
ST72561
12.7 MEMORY CHARACTERISTICS
12.7.1 RAM and Hardware Registers
Symbol
VRM
Parameter
Data retention mode
1)
Conditions
HALT mode (or RESET)
Min
Typ
Max
1.6
Unit
V
12.7.2 FLASH Memory
DUAL VOLTAGE HDFLASH MEMORY
Symbol
Parameter
fCPU
Operating frequency
VPP
Programming voltage 3)
IPP
VPP current4)5)
tVPP
tRET
NRW
TPROG
TERASE
Internal VPP stabilization time
Data retention
Write erase cycles
Programming or erasing temperature range
Conditions
Read mode
Write / Erase mode
4.5V ≤ VDD ≤ 5.5V
Read (VPP=12V)
Write / Erase
Min 2)
0
1
11.4
Typ
Max 2)
8
8
12.6
200
30
10
TA=55°C
TA=25°C
20
100
-40
25
85
Unit
MHz
V
µA
mA
µs
years
cycles
°C
Notes:
1. Minimum VDD supply voltage without losing data stored in RAM (in HALT mode or under RESET) or in hardware registers (only in HALT mode). Not tested in production.
2. Data based on characterization results, not tested in production.
3. VPP must be applied only during the programming or erasing operation and not permanently for reliability reasons.
4. Data based on simulation results, not tested in production.
5. In Write / erase mode the IDD supply current consumption is the same as in Run mode (see Section 12.4.1)
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ST72561
12.8 EMC CHARACTERISTICS
Susceptibility tests are performed on a sample basis during product characterization.
12.8.1 Functional EMS (Electro Magnetic
Susceptibility)
Based on a simple running application on the
product (toggling 2 LEDs through I/O ports), the
product is stressed by two electro magnetic events
until a failure occurs (indicated by the LEDs).
■ ESD: Electro-Static Discharge (positive and
negative) is applied on all pins of the device until
a functional disturbance occurs. This test
conforms with the IEC 1000-4-2 standard.
■ FTB: A Burst of Fast Transient voltage (positive
and negative) is applied to VDD and VSS through
a 100pF capacitor, until a functional disturbance
occurs. This test conforms with the IEC 1000-44 standard.
A device reset allows normal operations to be resumed. The test results are given in the table below based on the EMS levels and classes defined
in application note AN1709.
12.8.1.1 Designing hardened software to avoid
noise problems
EMC characterization and optimization are performed at component level with a typical applicaSymbol
tion environment and simplified MCU software. It
should be noted that good EMC performance is
highly dependent on the user application and the
software in particular.
Therefore it is recommended that the user applies
EMC software optimization and prequalification
tests in relation with the EMC level requested for
his application.
Software recommendations:
The software flowchart must include the management of runaway conditions such as:
– Corrupted program counter
– Unexpected reset
– Critical Data corruption (control registers...)
Prequalification trials:
Most of the common failures (unexpected reset
and program counter corruption) can be reproduced by manually forcing a low state on the RESET pin or the Oscillator pins for 1 second.
To complete these trials, ESD stress can be applied directly on the device, over the range of
specification values. When unexpected behaviour
is detected, the software can be hardened to prevent unrecoverable errors occurring (see application note AN1015).
Parameter
Level/
Class
Conditions
VFESD
Voltage limits to be applied on any I/O pin to induce a VDD=5V, TA=+25°C, fOSC=8MHz
functional disturbance
conforms to IEC 1000-4-2
3B
VFFTB
Fast transient voltage burst limits to be applied
V =5V, TA=+25°C, fOSC=8MHz
through 100pF on VDD and VDD pins to induce a func- DD
conforms to IEC 1000-4-4
tional disturbance
3B
12.8.2 Electro Magnetic Interference (EMI)
Based on a simple application running on the
product (toggling 2 LEDs through the I/O ports),
the product is monitored in terms of emission. This
emission test is in line with the norm SAE J 1752/
3 which specifies the board and the loading of
each pin.
Symbol
SEMI
Parameter
Peak level
Conditions
0.1MHz to 30MHz
VDD=5V, TA=+25°C,
30MHz to 130MHz
TQFP64 package
conforming to SAE J 1752/3 130MHz to 1GHz
SAE EMI Level
Notes:
1. Data based on characterization results, not tested in production.
234/262
Monitored
Frequency Band
Max vs. [fOSC/fCPU]
8/4MHz
Unit
16/8MHz
31
32
32
11
37
16
dBµV
3.0
3.5
-
ST72561
EMC CHARACTERISTICS (Cont’d)
12.8.3 Absolute Maximum Ratings (Electrical
Sensitivity)
Based on three different tests (ESD, LU and DLU)
using specific measurement methods, the product
is stressed in order to determine its performance in
terms of electrical sensitivity. For more details, refer to the application note AN1181.
12.8.3.1 Electro-Static Discharge (ESD)
Electro-Static Discharges (a positive then a negative pulse separated by 1 second) are applied to
the pins of each sample according to each pin
combination. The sample size depends on the
number of supply pins in the device (3 parts*(n+1)
supply pin). Two models can be simulated: Human
Body Model and Machine Model. This test conforms to the JESD22-A114A/A115A standard.
Absolute Maximum Ratings
Symbol
Ratings
Conditions
Maximum value 1) Unit
VESD(HBM)
Electro-static discharge voltage
(Human Body Model)
TA=+25°C
2000
VESD(MM)
Electro-static discharge voltage
(Machine Model)
TA=+25°C
200
V
Notes:
1. Data based on characterization results, not tested in production.
12.8.3.2 Static and Dynamic Latch-Up
■ LU: 3 complementary static tests are required
on 10 parts to assess the latch-up performance.
A supply overvoltage (applied to each power
supply pin) and a current injection (applied to
each input, output and configurable I/O pin) are
performed on each sample. This test conforms
to the EIA/JESD 78 IC latch-up standard. For
more details, refer to the application note
AN1181.
■
DLU: Electro-Static Discharges (one positive
then one negative test) are applied to each pin
of 3 samples when the micro is running to
assess the latch-up performance in dynamic
mode. Power supplies are set to the typical
values, the oscillator is connected as near as
possible to the pins of the micro and the
component is put in reset mode. This test
conforms to the IEC1000-4-2 and SAEJ1752/3
standards. For more details, refer to the
application note AN1181.
Electrical Sensitivities
Symbol
LU
DLU
Parameter
Conditions
Class 1)
Static latch-up class
TA=+25°C
TA=+85°C
TA=+125°C
A
A
A
Dynamic latch-up class
VDD=5.5V, fOSC=4MHz, TA=+25°C
A
Notes:
1. Class description: A Class is an STMicroelectronics internal specification. All its limits are higher than the JEDEC specifications, that means when a device belongs to Class A it exceeds the JEDEC standard. B Class strictly covers all the
JEDEC criteria (international standard).
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ST72561
12.9 I/O PORT PIN CHARACTERISTICS
12.9.1 General Characteristics
Subject to general operating conditions for VDD, fOSC, and TA unless otherwise specified.
Symbol
Parameter
Conditions
VIL
Input low level voltage
VIH
Input high level voltage 1)
Vhys
Schmitt trigger voltage hysteresis 2)
VIL
Input low level voltage 1)
VIH
Input high level voltage 1)
Vhys
Schmitt trigger voltage hysteresis 2)
IINJ(PIN)
Typ
Max
0.7xVDD
1
V
0.8
TTL ports
2
400
Injected Current on PB3
mV
+4
Injected Current on any other I/O pin
±4
VDD=5V
Input leakage current on robust pins See “10-BIT ADC CHARACTERISTICS” on page 246
VSS≤VIN≤VDD
±1
Static current consumption 4)
Floating input mode
200
RPU
Weak pull-up equivalent resistor 5)
VIN=VSS
CIO
I/O pin capacitance
tf(IO)out
mA
± 25
Input leakage current
IS
Unit
0.3xVDD
CMOS ports
Total injected current (sum of all I/O
ΣIINJ(PIN)3)
and control pins) 7)
Ilkg
Min
1)
Output high to low level fall time
VDD=5V
50
90
5
6)
tr(IO)out
CL=50pF
Output low to high level rise time 6) Between 10% and 90%
tw(IT)in
External interrupt pulse time 7)
25
25
1
250
µA
kΩ
pF
ns
tCPU
Notes:
1. Data based on characterization results, not tested in production.
2. Hysteresis voltage between Schmitt trigger switching levels. Based on characterization results, not tested.
3. When the current limitation is not possible, the VIN absolute maximum rating must be respected, otherwise refer to
IINJ(PIN) specification. A positive injection is induced by VIN>VDD while a negative injection is induced by VIN<VSS. Refer
to Section 12.2 on page 222 for more details.
4. Configuration not recommended, all unused pins must be kept at a fixed voltage: using the output mode of the I/O for
example or an external pull-up or pull-down resistor (see Figure 129). Data based on design simulation and/or technology
characteristics, not tested in production.
5. The RPU pull-up equivalent resistor is based on a resistive transistor (corresponding IPU current characteristics described in Figure 130).
6. Data based on characterization results, not tested in production.
7. To generate an external interrupt, a minimum pulse width has to be applied on an I/O port pin configured as an external
interrupt source.
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ST72561
I/O PORT PIN CHARACTERISTICS (Cont’d)
Figure 129. Connecting unused I/O pins
VDD
Figure 131. IPU vs. VDD with VIN=VSS
ST72XXX
10kΩ
UNUSED I/O PORT
Ta=-45C
Ta=25C
Ta=130C
UNUSED I/O PORT
10kΩ
Ipu (µA)
100
80
60
40
20
ST72XXX
0
3.5
4
4.5
Vdd
5
5.5
Figure 130. RPU vs. VDD with VIN=VSS
200
Ta=-45C
Ta=25C
Ta=130C
Rpu (Ko)
150
100
50
0
3.5
4
4.5
5
5.5
Vdd
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ST72561
I/O PORT PIN CHARACTERISTICS (Cont’d)
12.9.2 Output Driving Current
Subject to general operating conditions for VDD, fOSC, and TA unless otherwise specified.
Symbol
Parameter
Conditions
VOL 1)
Output low level voltage for a high sink I/O pin
when 4 pins are sunk at same time
(see Figure 133 and Figure 136)
VDD=5V
Output low level voltage for a standard I/O pin
when 8 pins are sunk at same time
(see Figure 132 )
Output high level voltage for an I/O pin
when 4 pins are sourced at same time
(see Figure 134 and Figure 137)
VOH 2)
Min
IIO=+5mA
1.2
IIO=+2mA
0.5
IIO=+20mA, TA≤85°C
TA≥85°C
1.3
1.5
IIO=+8mA
IIO=-5mA, TA≤85°C VDD-1.4
TA≥85°C VDD-1.6
0.6
IIO=-2mA
Figure 132. Typical VOL at VDD=5V (standard)
Max
Unit
V
VDD-0.7
Figure 134. Typical VOH at VDD=5V
0.8
4.9
0.7
4.8
-45°C
4.7
0.6
0.5
4.6
130°C
Voh(V)
Voh(V)
25°C
0.4
4.5
4.4
0.3
-45°C
4.3
130°C
25°C
0.2
4.2
0.1
4.1
2
5
-2
Iio(mA)
-5
Iio(mA)
Figure 133. Typical VOL at VDD=5V (high-sink)
0.8
0.7
-45°C
0.6
25°C
130°C
Vol (V)
0.5
0.4
0.3
0.2
0.1
0
2
5
8
20
Iol (mA)
Notes:
1. The IIO current sunk must always respect the absolute maximum rating specified in Section 12.2.2 and the sum of IIO
(I/O ports and control pins) must not exceed IVSS.
2. The IIO current sourced must always respect the absolute maximum rating specified in Section 12.2.2 and the sum of
IIO (I/O ports and control pins) must not exceed IVDD. True open drain I/O pins does not have VOH.
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ST72561
I/O PORT PIN CHARACTERISTICS (Cont’d)
Figure 135. Typical VOL vs. VDD (Standard I/Os)
1.1
0.4
-45°C
1
25°C
0.9
25°C
130°C
Vol(V) Iio=2mA
Vol(V) Iio=5mA
-45°C
0.35
0.8
0.7
0.6
0.3
130°C
0.25
0.2
0.5
0.15
0.4
0.3
0.1
3
4
5
6
3
4
Vdd(V)
5
6
Vdd(V)
Figure 136. Typical VOL vs. VDD (high-sink I/Os)
0.4
1.3
0.3
1.2
25°C
1.1
25°C
130°C
1
130°C
Vol(V) Iio=20mA
Vol(V) Iio=8mA
0.35
-45°C
0.25
0.2
-45°C
0.9
0.8
0.7
0.6
0.5
0.15
0.4
0.1
0.3
3
4
5
Vdd(V)
6
3
4
5
6
Vdd(V)
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ST72561
I/O PORT PIN CHARACTERISTICS (Cont’d)
Figure 137. Typical VOH vs. VDD
6
6
-45°C
25°C
5
130°C
Voh(V) Iio=5mA
Voh(V) Iio=2mA
5
-45°C
4
25°C
4
3
130°C
3
2
2
1
3
4
5
Vdd(V)
240/262
6
3
4
5
Vdd(V)
6
ST72561
12.10 CONTROL PIN CHARACTERISTICS
12.10.1 Asynchronous RESET Pin
Subject to general operating conditions for VDD, fOSC, and TA unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ 1)
1)
VIL
Input low level voltage
VIH
Input high level voltage 1)
Vhys
Schmitt trigger voltage hysteresis 2)
Max
0.3xVDD
0.7xVDD
VDD=5V
VOL
Output low level voltage 3)
VDD=5V
RON
Weak pull-up equivalent resistor 4)
VIN=VSS
tw(RSTL)out Generated reset pulse duration
th(RSTL)in
External reset pulse hold time
tg(RSTL)in
Filtered glitch duration 6)
1.5
0.68
0.95
IIO=+2mA
0.28
0.45
40
80
20
5)
30
V
V
IIO=+5mA
Internal reset source
Unit
V
kΩ
µs
µs
2.5
200
ns
Figure 138. Typical Application with RESET pin 7)8)9)
Recommended
if LVD is disabled
VDD
USER
EXTERNAL
RESET
CIRCUIT 6)
VDD
ST72XXX
VDD
0.01µF
4.7kΩ
RON
INTERNAL
RESET
Filter
0.01µF
PULSE
GENERATOR
WATCHDOG
LVD RESET
Required if LVD is disabled
Notes:
1. Data based on characterization results, not tested in production.
2. Hysteresis voltage between Schmitt trigger switching levels.
3. Not tested in production. The IIO current sunk must always respect the absolute maximum rating specified in Section
12.2.2 and the sum of IIO (I/O ports and control pins) must not exceed IVSS.
4. The RON pull-up equivalent resistor is based on a resistive transistor.
5. To guarantee the reset of the device, a minimum pulse has to be applied to the RESET pin. All short pulses applied on
RESET pin with a duration below th(RSTL)in can be ignored.
6. The reset network (the resistor and two capacitors) protects the device against parasitic resets, especially in a noisy
environments.
7. The output of the external reset circuit must have an open-drain output to drive the ST7 reset pad. Otherwise the device
can be damaged when the ST7 generates an internal reset (watchdog).
8. Whatever the reset source is (internal or external), the user must ensure that the level on the RESET pin can go below
the VIL max. level specified in Section 12.10.1 . Otherwise the reset will not be taken into account internally.
9. Because the reset circuit is designed to allow the internal RESET to be output in the RESET pin, the user must ensure
that the current sunk on the RESET pin (by an external pull-p for example) is less than the absolute maximum value specified for IINJ(RESET) in Section 12.2.2 on page 222.
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ST72561
CONTROL PIN CHARACTERISTICS (Cont’d)
Rpu (kOhm)
Figure 139. RESET RPU vs. VDD
100
Ta=-45C
80
Ta=25C
Ta=130C
60
40
20
0
3.5
4
4.5
Vdd
5
5.5
12.10.2 ICCSEL/VPP Pin
Subject to general operating conditions for VDD, fOSC, and TA unless otherwise specified.
Symbol
VIL
VIH
IL
Parameter
Input low level voltage 1)
Input high level voltage 1)
Input leakage current
Conditions
Min
Max
VSS
VDD-0.1
0.2
12.6
±1
VIN=VSS
Unit
V
µA
Figure 140. Two typical Applications with ICCSEL/VPP Pin 2)
ICCSEL/V PP
ST72XXX
VPP
PROGRAMMING
TOOL
10kΩ
Notes:
1. Data based on design simulation and/or technology characteristics, not tested in production.
2. When ICC mode is not required by the application ICCSEL/VPP pin must be tied to VSS.
242/262
ST72XXX
ST72561
12.11 TIMER PERIPHERAL CHARACTERISTICS
Subject to general operating conditions for VDD,
fOSC, and TA unless otherwise specified.
Refer to I/O port characteristics for more details on
the input/output alternate function characteristics
(output compare, input capture, external clock,
PWM output...).
12.11.1 8-Bit PWM-ART Autoreload Timer
Symbol
Parameter
tres(PWM) PWM resolution time
Conditions
fCPU=8MHz
Min
Typ
Max
tCPU
125
ns
fEXT
ART external clock frequency
0
fCPU/2
fPWM
PWM repetition rate
0
fCPU/2
ResPWM
VOS
tCOUNTER
PWM resolution
8
PWM/DAC output step voltage
VDD=5V, Res=8-bits
Timer clock period when internal
clock is selected
fCPU=8MHz
Unit
1
20
MHz
bit
mV
1
128
tCPU
0.125
16
µs
Max
Unit
12.11.2 8-Bit Timer
Symbol
Parameter
Conditions
tw(ICAP)in Input capture pulse time
tres(PWM) PWM resolution time
fPWM
ResPWM
fCPU=8MHz
PWM repetition rate
Min
Typ
1
tCPU
2
tCPU
250
ns
0
fCPU/4
MHz
8
bit
2
8000
tCPU
0.250
1000
µs
Max
Unit
PWM resolution
tCOUNTER Timer clock period
fCPU=8MHz
12.11.3 16-Bit Timer
Symbol
Parameter
Conditions
tw(ICAP)in Input capture pulse time
tres(PWM) PWM resolution time
fCPU=8MHz
Min
Typ
1
tCPU
2
tCPU
250
ns
fEXT
Timer external clock frequency
0
fCPU/4
MHz
fPWM
PWM repetition rate
0
fCPU/4
MHz
16
bit
2
8
tCPU
0.250
1
µs
ResPWM
PWM resolution
tCOUNTER
Timer clock period when internal
clock is selected
fCPU=8MHz
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ST72561
12.12 COMMUNICATION INTERFACE CHARACTERISTICS
Refer to I/O port characteristics for more details on
the input/output alternate function characteristics
(SS, SCK, MOSI, MISO).
12.12.1 SPI - Serial Peripheral Interface
Subject to general operating conditions for VDD,
fOSC, and TA unless otherwise specified.
Symbol
Parameter
Conditions
Master
fSCK
1/tc(SCK)
fCPU=8MHz
SPI clock frequency
Slave
fCPU=8MHz
Min
Max
fCPU/128
0.0625
fCPU/4
2
0
fCPU/2
4
tr(SCK)
tf(SCK)
SPI clock rise and fall time
tsu(SS)
th(SS)
SS setup time
SS hold time
Slave
Slave
120
120
SCK high and low time
Master
Slave
100
90
Data input setup time
Master
Slave
100
100
Data input hold time
Master
Slave
100
100
0
tw(SCKH)
tw(SCKL)
tsu(MI)
tsu(SI)
th(MI)
th(SI)
ta(SO)
Data output access time
Slave
Data output disable time
Data output valid time
Slave
Data output hold time
tv(MO)
th(MO)
Data output valid time
Data output hold time
MHz
see I/O port pin description
tdis(SO)
tv(SO)
th(SO)
Unit
ns
120
240
90
Slave (after enable edge)
0
Master (before capture edge)
0.25
0.25
tCPU
Figure 141. SPI Slave Timing Diagram with CPHA=0 3)
SS INPUT
SCK INPUT
tsu(SS)
tc(SCK)
th(SS)
CPHA=0
CPOL=0
CPHA=0
CPOL=1
ta(SO)
MISO OUTPUT
tw(SCKH)
tw(SCKL)
MSB OUT
see note 2
tsu(SI)
MOSI INPUT
tv(SO)
th(SO)
BIT6 OUT
tdis(SO)
tr(SCK)
tf(SCK)
LSB OUT
see
note 2
th(SI)
MSB IN
BIT1 IN
LSB IN
Notes:
1. Data based on design simulation and/or characterisation results, not tested in production.
2. When no communication is on-going the data output line of the SPI (MOSI in master mode, MISO in slave mode) has
its alternate function capability released. In this case, the pin status depends on the I/O port configuration.
3. Measurement points are done at CMOS levels: 0.3xVDD and 0.7xVDD.
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ST72561
COMMUNICATION INTERFACE CHARACTERISTICS (Cont’d)
Figure 142. SPI Slave Timing Diagram with CPHA=11)
SS INPUT
SCK INPUT
tsu(SS)
tc(SCK)
th(SS)
CPHA=0
CPOL=0
CPHA=0
CPOL=1
tw(SCKH)
tw(SCKL)
ta(SO)
MISO OUTPUT
see
note 2
tv(SO)
th(SO)
MSB OUT
HZ
tsu(SI)
BIT6 OUT
LSB OUT
see
note 2
th(SI)
MSB IN
MOSI INPUT
tdis(SO)
tr(SCK)
tf(SCK)
Figure 143. SPI Master Timing Diagram
BIT1 IN
LSB IN
1)
SS INPUT
tc(SCK)
SCK INPUT
CPHA=0
CPOL=0
CPHA=0
CPOL=1
CPHA=1
CPOL=0
CPHA=1
CPOL=1
tw(SCKH)
tw(SCKL)
tsu(MI)
MISO INPUT
MOSI OUTPUT see note 2
th(MI)
MSB IN
tv(MO)
tr(SCK)
tf(SCK)
BIT6 IN
LSB IN
th(MO)
MSB OUT
BIT6 OUT
LSB OUT
see note 2
Notes:
1. Measurement points are done at CMOS levels: 0.3xVDD and 0.7xVDD.
2. When no communication is on-going the data output line of the SPI (MOSI in master mode, MISO in slave mode) has
its alternate function capability released. In this case, the pin status depends of the I/O port configuration.
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ST72561
COMMUNICATIONS INTERFACE CHARACTERISTICS (Cont’d)
12.12.2 CAN - Controller Area Network Interface
Subject to general operating condition for VDD, fOSC, and TA unless otherwise specified.
Refer to I/O port characteristics for more details on
Symbol
tp(RX:TX)
Parameter
the input/output alternate function characteristics
(CANTX and CANRX).
Conditions
Min
Typ
Max
Unit
60
ns
CAN controller propagation time
12.13 10-BIT ADC CHARACTERISTICS
Subject to general operating conditions for VDD, fCPU, and TA unless otherwise specified.
Symbol
fADC
Parameter
Conditions
ADC clock frequency
VAIN
Conversion voltage
range 2)
Min
Typ 1)
Max
Unit
0.4
4
MHz
VSSA
VDDA
V
see
Figure
144 and
Figure
1453)4)5)
kΩ
6
µA
RAIN
External input impedance
CAIN
External capacitor on analog input
fAIN
Variation frequency of analog input
signal
Ilkg
Negative input leakage current on
VIN<VSS, | IIN |< 400µA on
robust analog pins (refer to Table 1
adjacent robust analog pin
on page 9)
5
CADC
Internal sample and hold capacitor
6
tCONV
Conversion time
IADC
246/262
fADC=4MHz
pF
Hz
pF
3.5
µs
14
1/fADC
Analog Part
Sunk on VDDA2)
3.6
Digital Part
Sunk on VDD
0.2
mA
ST72561
ADC CHARACTERISTICS (Cont’d)
Figure 144. RAIN max. vs f ADC with CAIN=0pF4)
Figure 145. Recommended CAIN/RAIN values5)
45
1000
40
Cain 10 nF
4 MHz
2 MHz
30
1 MHz
25
Cain 22 nF
100
Max. R AIN (Kohm)
Max. R AIN (Kohm)
35
20
15
10
Cain 47 nF
10
1
5
0
0.1
0
10
30
70
0.01
0.1
CPARASITIC (pF)
1
10
f AIN(KHz)
Figure 146. Typical Application with ADC
VDD
ST72XXX
VT
0.6V
RAIN
2kΩ(max)
AINx
VAIN
CAIN
VT
0.6V
IL
±1µA
10-Bit A/D
Conversion
CADC
6pF
Notes:
1. Unless otherwise specified, typical data are based on TA=25°C and VDD-VSS=5V. They are given only as design guidelines and are not tested.
2. When VDDA and VSSA pins are not available on the pinout, the ADC refers to VDD and VSS.
3. Any added external serial resistor will downgrade the ADC accuracy (especially for resistance greater than 10kΩ). Data
based on characterization results, not tested in production.
4. CPARASITIC represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the pad capacitance (3pF). A high CPARASITIC value will downgrade conversion accuracy. To remedy this, fADC should be reduced.
5. This graph shows that depending on the input signal variation (fAIN), CAIN can be increased for stabilization time and
reduced to allow the use of a larger serial resistor (RAIN). It is valid for all fADC frequencies ≤ 4MHz.
247/262
ST72561
ADC CHARACTERISTICS (Cont’d)
12.13.0.1 Analog Power Supply and Reference
Pins
Depending on the MCU pin count, the package
may feature separate VDDA and VSSA analog power supply pins. These pins supply power to the A/D
converter cell and function as the high and low reference voltages for the conversion. In smaller
packages VDDA and VSSA pins are not available
and the analog supply and reference pads are internally bonded to the VDD and VSS pins.
Separation of the digital and analog power pins allow board designers to improve A/D performance.
Conversion accuracy can be impacted by voltage
drops and noise in the event of heavily loaded or
badly decoupled power supply lines (see Section
12.13.0.2 "General PCB Design Guidelines").
12.13.0.2 General PCB Design Guidelines
To obtain best results, some general design and
layout rules should be followed when designing
the application PCB to shield the the noise-sensitive, analog physical interface from noise-generating CMOS logic signals.
– Use separate digital and analog planes. The analog ground plane should be connected to the
digital ground plane via a single point on the
PCB.
– Filter power to the analog power planes. It is recommended to connect capacitors, with good high
frequency characteristics, between the power
and ground lines, placing 0.1µF and optionally, if
needed 10pF capacitors as close as possible to
the ST7 power supply pins and a 1 to 10µF capacitor close to the power source (see Figure
147).
– The analog and digital power supplies should be
connected in a star nework. Do not use a resistor, as VDDA is used as a reference voltage by the
A/D converter and any resistance would cause a
voltage drop and a loss of accuracy.
– Properly place components and route the signal
traces on the PCB to shield the analog inputs.
Analog signals paths should run over the analog
ground plane and be as short as possible. Isolate
analog signals from digital signals that may
switch while the analog inputs are being sampled
by the A/D converter. Do not toggle digital outputs on the same I/O port as the A/D input being
converted.
12.13.0.3 Software Filtering of Spurious
Conversion Results
For EMC performance reasons, it is recommended to filter A/D conversion outliers using software
filtering techniques.
Figure 147. Power Supply Filtering
ST72XXX
1 to 10µF
0.1µF
ST7
DIGITAL NOISE
FILTERING
VSS
VDD
VDD
POWER
SUPPLY
SOURCE
0.1µF
EXTERNAL
NOISE
FILTERING
248/262
VDDA
VSSA
ST72561
ADC CHARACTERISTICS (Cont’d)
ADC Accuracy with fCPU=8 MHz, fADC=4 MHz RAIN< 10kΩ, VDD= 5V
Symbol
Parameter
|ET|
Total unadjusted
|EO|
Offset error 1)
Conditions
error 1)
Typ
Max
Unit
4
1)
2.5
4
|EG|
Gain Error
3
4
|ED|
Differential linearity error1)
1.5
2
|EL|
Integral linearity error 1)
1.5
2
LSB
Figure 148. ADC Accuracy Characteristics
Digital Result ADCDR
EG
1023
1022
1021
1LSB
IDEA L
V
–V
DDA
SSA
= -----------------------------------------
1024
(2)
ET
(3)
7
(1)
6
5
4
(1) Example of an actual transfer curve
(2) The ideal transfer curve
(3) End point correlation line
EO
EL
3
ED
2
ET=Total Unadjusted Error: maximum deviation
between the actual and the ideal transfer curves.
EO=Offset Error: deviation between the first actual
transition and the first ideal one.
EG=Gain Error: deviation between the last ideal
transition and the last actual one.
ED=Differential Linearity Error: maximum deviation
between actual steps and the ideal one.
EL=Integral Linearity Error: maximum deviation
between any actual transition and the end point
correlation line.
1 LSBIDEAL
1
0
1
VSSA
Vin (LSBIDEAL)
2
3
4
5
6
7
1021 1022 1023 1024
VDDA
Notes:
1) ADC Accuracy vs. Negative Injection Current: Injecting negative current on any of the standard (non-robust) analog
input pins should be avoided as this significantly reduces the accuracy of the conversion being performed on another
analog input. It is recommended to add a Schottky diode (pin to ground) to standard analog pins which may potentially
inject negative current. The effect of negative injection current on robust pins is specified in Section 12.9.
Any positive injection current within the limits specified for IINJ(PIN) and ΣIINJ(PIN) in Section 12.9 does not affect the ADC
accuracy.
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ST72561
13 PACKAGE CHARACTERISTICS
13.1 PACKAGE MECHANICAL DATA
Figure 149. 64-Pin Thin Quad Flat Package (14x14)
D
A
D1
A2
Dim.
mm
Min
Typ
A
A1
b
e
E1 E
L
Min
Typ
Max
1.60
0.063
0.15 0.002
0.006
A1
0.05
A2
1.35
1.40
1.45 0.053 0.055 0.057
b
0.30
0.37
0.45 0.012 0.015 0.018
c
0.09
0.20 0.004
0.008
D
16.00
0.630
D1
14.00
0.551
E
16.00
0.630
E1
14.00
0.551
e
0.80
0.031
θ
0°
3.5°
L
0.45
0.60
L1
7°
0°
3.5°
7°
0.75 0.018 0.024 0.030
1.00
L1
0.039
Number of Pins
c
h
inches
Max
N
64
Figure 150. 64-Pin Thin Quad Flat Package (10 x10)
Dim.
D
A
D1
A2
b
E
e
c
L1
h
L
Typ
A
A1
E1
mm
Min
inches
Max
Min
Typ
0.063
0.15 0.002
0.006
A1
0.05
A2
1.35
1.40
1.45 0.053 0.055 0.057
b
0.17
0.22
0.27 0.007 0.009 0.011
c
0.09
0.20 0.004
0.008
D
12.00
0.472
D1
10.00
0.394
E
12.00
0.472
E1
10.00
0.394
e
0.50
0.020
θ
0°
3.5°
L
0.45
0.60
L1
7°
0°
3.5°
N
7°
0.75 0.018 0.024 0.030
1.00
0.039
Number of Pins
250/262
Max
1.60
64
ST72561
Figure 151. 44-Pin Thin Quad Flat Package
Dim.
A
A2
D
D1
b
e
c
L1
inches
Max
Min
Typ
Max
1.60
0.063
0.15 0.002
0.006
A1
0.05
A2
1.35
1.40
1.45 0.053 0.055 0.057
b
0.30
0.37
0.45 0.012 0.015 0.018
C
0.09
0.20 0.004 0.000 0.008
D
12.00
0.472
D1
10.00
0.394
E
12.00
0.472
E1
10.00
0.394
e
0.80
0.031
θ
0°
3.5°
L
0.45
0.60
L1
L
Typ
A
A1
E1 E
mm
Min
h
7°
0°
3.5°
7°
0.75 0.018 0.024 0.030
1.00
0.039
Number of Pins
N
44
251/262
ST72561
PACKAGE CHARACTERISTICS (Cont’d)
Figure 152. 32-Pin Thin Quad Flat Package
Dim.
mm
Min
Typ
inches
Max
Min
Typ
Max
D
A
A
D1
A2
A1
0.05
A2
1.35
1.40
1.45 0.053 0.055 0.057
b
0.30
0.37
0.45 0.012 0.015 0.018
C
0.09
A1
e
E1 E
b
c
L1
L
h
1.60
0.063
0.15 0.002
0.006
0.20 0.004
0.008
D
9.00
0.354
D1
7.00
0.276
E
9.00
0.354
E1
7.00
0.276
e
0.80
θ
0°
3.5°
L
0.45
0.60
L1
0.031
7°
0°
3.5°
7°
0.75 0.018 0.024 0.030
1.00
0.039
Number of Pins
N
32
13.2 THERMAL CHARACTERISTICS
Symbol
Ratings
Value
Unit
RthJA
Package thermal resistance (junction to ambient)
TQFP64
TQFP44
TQFP32
60
52
70
°C/W
Power dissipation 1)
500
mW
150
°C
PD
TJmax
Maximum junction
temperature 2)
Notes:
1. The power dissipation is obtained from the formula PD=PINT+PPORT where PINT is the chip internal power (IDDxVDD)
and PPORT is the port power dissipation determined by the user.
2. The average chip-junction temperature can be obtained from the formula TJ = TA + PD x RthJA.
252/262
ST72561
13.3 SOLDERING AND GLUEABILITY INFORMATION
Recommended soldering information given only as design guidelines.
Figure 153. Recommended Wave Soldering Profile (with 37% Sn and 63% Pb)
250
150
SOLDERING
PHASE
80°C
Temp. [°C]
100
50
COOLING PHASE
(ROOM TEMPERATURE)
5 sec
200
PREHEATING
PHASE
Time [sec]
0
20
40
60
80
100
120
140
160
Figure 154. Recommended Reflow Soldering Oven Profile (MID JEDEC)
250
Tmax=220+/-5°C
for 25 sec
200
150
90 sec at 125°C
150 sec above 183°C
Temp. [°C]
100
50
ramp down natural
2°C/sec max
ramp up
2°C/sec for 50sec
Time [sec]
0
100
200
300
400
Recommended glue for SMD plastic packages dedicated to molding compound with silicone:
■ Heraeus: PD945, PD955
■ Loctite: 3615, 3298
253/262
ST72561
14 DEVICE CONFIGURATION AND ORDERING INFORMATION
Each device is available for production in user programmable versions (FLASH) as well as in factory
coded versions (ROM/FASTROM).
ST72561 devices are ROM versions. ST72P561
devices are Factory Advanced Service Technique
ROM (FASTROM) versions: they are factory-programmed HDFlash devices.
ST72F561 FLASH devices are shipped to customers with a default content (FFh), while ROM factory coded parts contain the code supplied by the
customer. This implies that FLASH devices have
to be configured by the customer using the Option
Bytes while the ROM devices are factory-configured.
active.
0: No Reset generation when entering Halt mode
1: Reset generation when entering Halt mode
OPT6= WDGSW Hardware or software watchdog
This option bit selects the watchdog type.
0: Hardware (watchdog always enabled)
1: Software (watchdog to be enabled by software)
OPT5 = Reserved, must be kept at derfault value.
OPT4= LVD Voltage detection
This option bit enables the voltage detection block
(LVD).
14.1 FLASH OPTION BYTES
The option bytes allows the hardware configuration of the microcontroller to be selected. They
have no address in the memory map and can be
accessed only in programming mode (for example
using a standard ST7 programming tool). The default content of the FLASH is fixed to FFh. To program directly the FLASH devices using ICP,
FLASH devices are shipped to customers with a
reserved internal clock source enabled. In masked
ROM devices, the option bytes are fixed in hardware by the ROM code (see option list).
OPTION BYTE 0
OPT7= WDGHALT Watchdog reset on HALT
This option bit determines if a RESET is generated
when entering HALT mode while the Watchdog is
Selected Low Voltage Detector
VD
LVD Off
LVD On
1
0
OPT3 = PLL OFF PLL activation
This option bit activates the PLL which allows multiplication by two of the main input clock frequency.
The PLL is guaranteed only with an input frequency between 2 and 4MHz.
0: PLL x2 enabled
1: PLL x2 disabled
Caution: the PLL can be enabled only if the “OSC
RANGE” (OPT11:10) bits are configured to “MP 2~4MHz”. Otherwise, the device functionality is
not guaranteed.
STATIC OPTION BYTE 0
STATIC OPTION BYTE 1
1
1
0
1
1
1
(*) : Option bit values programmed by ST
254/262
AFI_MAP
1
0
1
0
1
0
RSTC
1
1
0
Reserved
Default(*)
PKG
7
FMP_R
1
WDG
PLLOFF
Reserved
LVD
SW
0
HALT
7
1
1
1
1
0
1
1
1
1
OSCTYPE OSCRANGE
ST72561
FLASH OPTION BYTES (Cont’d)
OPT2:1= PKG[1:0] Package selection
These option bits select the device package.
AFI Mapping 1
AFI_MAP(1)
T16_ICAP2 is mapped on PC1
PKG
1
Selected Package
1
0
TQFP 64
1
x
TQFP 44
0
1
TQFP 32
0
0
Note: Pads that are not bonded to external pins
are in input pull-up configuration when the package selection option bits have been properly programmed. The configuration of these pads must
be kept in reset state to avoid added current consumption.
OPT0= FMP_R Flash memory read-out protection
Readout protection, when selected provides a protection against program memory content extraction and against write access to Flash memory.
Erasing the option bytes when the FMP_R option
is selected causes the whole user memory to be
erased first, and the device can be reprogrammed.
Refer to Section 4.3.1 and the ST7 Flash Programming Reference Manual for more details.
0: Read-out protection enabled
1: Read-out protection disabled
OPT5:4 = OSCTYPE[1:0] Oscillator Type
These option bits select the ST7 main clock
source type.
OSCTYPE
Clock Source
1
0
Resonator Oscillator
0
0
Reserved
0
1
Reserved internal clock source
(used only in ICC mode)
1
0
External Source
1
1
OPT3:2 = OSCRANGE[1:0] Oscillator range
If the resonator oscillator type is selected, these
option bits select the resonator oscillator. This selection corresponds to the frequency range of the
resonator used. If external source is selected with
the OSCTYPE option, then the OSCRANGE option must be selected with the corresponding
range.
OSCRANGE
Typ. Freq. Range
OPTION BYTE 1
OPT7:6 = AFI_MAP[1:0] AFI Mapping
These option bits allow the mapping of some of the
Alternate Functions to be changed.
AFI Mapping 1
AFI_MAP(1)
1
0
LP
1~2MHz
0
0
MP
2~4MHz
0
1
MS
4~8MHz
1
0
HS
8~16MHz
1
1
T16_OCMP1 on PD3
T16_OCMP2 on PD5
T16_ICAP1 on PD4
LINSCI2_SCK not available
LINSCI2_TDO not available
LINSCI2_RDI not available
0
OPT1 = Reserved
T16_OCMP1 on PB6
T16_OCMP2 on PB7
T16_ICAP1 on PC0
LINSCI2_SCK on PD3
LINSCI2_TDO on PD5
LINSCI2_RDI on PD4
1
OPT0 = RSTC RESET clock cycle selection
This option bit selects the number of CPU cycles
inserted during the RESET phase and when exiting HALT mode. For resonator oscillators, it is advised to select 4096 due to the long crystal stabilization time.
0: Reset phase with 4096 CPU cycles
1: Reset phase with 256 CPU cycles
AFI Mapping 0
T16_ICAP2 is mapped on PD1
AFI_MAP(0)
0
255/262
ST72561
14.2 DEVICE ORDERING INFORMATION AND
TRANSFER OF CUSTOMER CODE
Customer code is made up of the ROM/FASTROM contents and the list of the selected options
(if any). The ROM/FASTROM contents are to be
sent on diskette, or by electronic means, with the
S19 hexadecimal file generated by the development tool. All unused bytes must be set to FFh.
The selected options are communicated to
STMicroelectronics using the correctly completed
OPTION LIST appended.
Refer to application note AN1635 for information
on the counter listing returned by ST after code
has been transferred.
The STMicroelectronics Sales Organization will be
pleased to provide detailed information on contractual points.
14.2.1 Version-Specific Sales Conditions
To satisfy the different customer requirements and
to ensure that ST Standard Microcontrollers will
consistently meet or exceed the expectations of
each Market Segment, the Codification System for
Standard Microcontrollers clearly distinguishes
products intended for use in automotive environments, from products intended for use in non-automotive environments.
It is the responsibility of the Customer to select the
appropriate product for his application.
Figure 155. ROM Factory Coded Device Types
DEVICE PACKAGE VERSION / XXX
Code name (defined by STMicroelectronics)
C = Automotive -40 to +125 °C
T= Plastic Thin Quad Flat Pack
ST72561AR9, ST72561AR6,
ST72561R9, ST72561R6,
ST72561J9,ST72561J6
ST72561K9,ST72561K6
Figure 156. FASTROM Factory Coded Device Types
DEVICE PACKAGE VERSION / XXX
Code name (defined by STMicroelectronics)
C = Automotive -40 to +125 °C
T= Plastic Thin Quad Flat Pack
ST72P561AR9, ST72P561AR6,
ST72P561R9, ST72P561R6,
ST72P561J9,ST72P561J6
ST72P561K9,ST72P561K6
Figure 157. FLASH User Programmable Device Types
DEVICE PACKAGE VERSION
C = Automotive -40 to +125 °C
T= Plastic Thin Quad Flat Pack
ST72F561AR9, ST72F561AR6,
ST72F561R9, ST72F561R6,
ST72F561J9,ST72F561J6
ST72F561K9,ST72F561K6
256/262
ST72561
TRANSFER OF CUSTOMER CODE (Cont’d)
ST72561 MICROCONTROLLER OPTION LIST
...................................................................
...................................................................
...................................................................
Contact
...................................................................
Phone No
...................................................................
Reference/ROM Code* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
*The ROM/FASTROM code name is assigned by STMicroelectronics.
ROM/FASTROM code must be sent in .S19 format. .Hex extension cannot be processed.
Customer
Address
Device Type/Memory Size/Package (check only one option)
| --------------------------------- | ------------------------------------ |
ROM:
60K
Package
|
| -----------------------------------| --------------------------------|
TQFP64 10x10: |
[ ] ST72561AR9T
|
|
TQFP64 14x14: |
[ ] ST72561R9T
|
|
TQFP44:
|
[ ] ST72561J9T
|
|
TQFP32:
|
[ ] ST72561K6T
|
-------------------------------------------------------------------|
|
|
FASTROM:
60K
Package
|
| -----------------------------------| --------------------------------|
TQFP64 10x10: |
[ ] ST72P561AR9T
|
|
TQFP64 14x14: |
[ ] ST72P561R9T
|
|
TQFP44:
|
[ ] ST72P561J9T
|
|
TQFP32:
|
[ ] ST72P561K6T
|
....
....
....
....
....
....
...
...
...
...
...
...
------------------------------------ |
32K
------------------------------------ |
[ ] ST72561AR6T
|
[ ] ST72561R6T
|
[ ] ST72561J6T
|
[ ] ST72561K6T
|
------------------------------------ |
32K
|
-----------------------------------[ ] ST72P561AR6T
|
[ ] ST72P561R6T
|
[ ] ST72P561J6T
|
[ ] ST72P561K6T
|
Conditioning:
[ ] Tray
[ ] Tape & Reel
Special Marking:
[ ] No
[ ] Yes "_ _ _ _ _ _ _ _ _ _ " (10 char. max)
Authorized characters are letters, digits, '.', '-', '/' and spaces only.
Clock Source Selection:
[ ] Resonator:
[ ] External Source
Oscillator/External source range:
[ ] LP: Low power (1 to 2 MHz)
[ ] MP: Medium power (2 to 4 MHz)
[ ] MS: Medium speed (4 to 8 MHz)
[ ] HS: High speed (8 to 16 MHz)
LVD
[ ] Disabled
[ ] Enabled
[ ] Disabled
[ ] Enabled
PLL1
Watchdog Selection
[ ] Software Activation
[ ] Hardware Activation
Watchdog Reset on Halt
[ ] Reset
[ ] No Reset
Readout Protection
[ ] Disabled
[ ] Enabled
Reset Delay
[ ] 256 Cycles
LINSCI2 Mapping
T16_ICAP2 Mapping
[ ] Not available (AFIMAP[1] = 0)
[ ] On PD1 (AFIMAP[0] = 0)
[ ] 4096 Cycles
[ ] Mapped (AFIMAP[1] = 1)
[ ] On PC1 (AFIMAP[0] = 1)
Comments:
Supply Operating Range in the application: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Notes
Signature
Date
1If
..........................................................................
..........................................................................
..........................................................................
PLL is enabled, medium power (2 to 4 MHz range) has to be selected (MP)
257/262
ST72561
14.3 DEVELOPMENT TOOLS
Full details of tools available for the ST7 from third
party manufacturers can be obtained from the
STMicroelectronics Internet site:
➟ http://mcu.st.com.
Tools from iSystem and Hitex include C compliers,
emulators and gang programmers.
Note: Before designing the board layout, it is recommended to check the overall dimensions of the
socket as they may be greater than the dimensions of the device.
258/262
For footprint and other mechanical information
about these sockets and adapters, refer to the
manufacturer’s datasheet.
ST Programming Tools
■ ST7MDT25-EPB:
for in-socket or ICC
programming
■ ST7-STICK: for ICC programming
ST72561
15 IMPORTANT NOTES
15.1
CLEARING
ACTIVE
INTERRUPTS
OUTSIDE INTERRUPT ROUTINE
When an active interrupt request occurs at the
same time as the related flag or interrupt mask is
being cleared, the CC register may be corrupted.
Concurrent interrupt context
The symptom does not occur when the interrupts
are handled normally, i.e. when:
– The interrupt request is cleared (flag reset or interrupt mask) within its own interrupt routine
– The interrupt request is cleared (flag reset or interrupt mask) within any interrupt routine
– The interrupt request is cleared (flag reset or interrupt mask) in any part of the code while this interrupt is disabled
If these conditions are not met, the symptom can
be avoided by implementing the following sequence:
Perform SIM and RIM operation before and after
resetting an active interrupt request
Ex:
SIM
reset flag or interrupt mask
RIM
Nested interrupt context
The symptom does not occur when the interrupts
are handled normally, i.e. when:
– The interrupt request is cleared (flag reset or interrupt mask) within its own interrupt routine
– The interrupt request is cleared (flag reset or interrupt mask) within any interrupt routine with
higher or identical priority level
– The interrupt request is cleared (flag reset or interrupt mask) in any part of the code while this interrupt is disabled
If these conditions are not met, the symptom can
be avoided by implementing the following sequence:
PUSH CC
SIM
reset flag or interrupt mask
POP CC
15.2 CAN FIFO CORRUPTION
The beCAN FIFO gets corrupted when a message
is received and simultaneously a message is released while FMP=2. For details and a description
of the workaround refer to Section 10.9.7.1 on
page 189.
15.3 FLASH/FASTROM DEVICES ONLY
15.3.1 LINSCI wrong break duration
SCI Mode
A single break character is sent by setting and resetting the SBK bit in the SCICR2 register. In
some cases, the break character may have a longer duration than expected:
- 20 bits instead of 10 bits if M=0
- 22 bits instead of 11 bits if M=1.
In the same way, as long as the SBK bit is set,
break characters are sent to the TDO pin. This
may lead to generate one break more than expected.
Occurrence
The occurrence of the problem is random and proportional to the baudrate. With a transmit frequency of 19200 baud (fCPU=8MHz and SCIBRR=0xC9), the wrong break duration occurrence
is around 1%.
Workaround
If this wrong duration is not compliant with the
communication protocol in the application, software can request that an Idle line be generated
before the break character. In this case, the break
duration is always correct assuming the application is not doing anything between the idle and the
break. This can be ensured by temporarily disabling interrupts.
The exact sequence is:
- Disable interrupts
- Reset and Set TE (IDLE request)
- Set and Reset SBK (Break Request)
- Re-enable interrupts
LIN mode
If the LINE bit in the SCICR3 is set and the M bit in
the SCICR1 register is reset, the LINSCI is in LIN
master mode. A single break character is sent by
setting and resetting the SBK bit in the SCICR2
register. In some cases, the break character may
have a longer duration than expected:
259/262
ST72561
- 24 bits instead of 13 bits
Occurrence
The occurrence of the problem is random and proportional to the baudrate. With a transmit frequency of 19200 baud (fCPU=8MHz and SCIBRR=0xC9), the wrong break duration occurrence
is around 1%.
Analysis
The LIN protocol specifies a minimum of 13 bits for
the break duration, but there is no maximum value.
Nevertheless, the maximum length of the header
is specified as (14+10+10+1)x1.4=49 bits. This is
composed of:
- the synch break field (14 bits),
- the synch field (10 bits),
- the identifier field (10 bits).
Every LIN frame starts with a break character.
Adding an idle character increases the length of
each header by 10 bits. When the problem occurs, the header length is increased by 11 bits and
becomes ((14+11)+10+10+1)=45 bits.
To conclude, the problem is not always critical for
LIN communication if the software keeps the time
260/262
between the sync field and the ID smaller than 4
bits, i.e. 208us at 19200 baud.
The workaround is the same as for SCI mode but
considering the low probability of occurrence (1%),
it may be better to keep the break generation sequence as it is.
15.3.2 16-bit and 8-bit Timer PWM Mode
In PWM mode, the first PWM pulse is missed after
writing the value FFFCh in the OC1R or OC2R
register.
15.4 ROM DEVICES ONLY
15.4.1 16-bit Timer PWM Mode Buffering
Feature Change
In all devices, the frequency and period of the
PWM signal are controlled by comparing the counter with a 16-bit buffer updated by the OCiHR and
OCiLR registers. In ROM devices, contrary to the
description in Section 10.5.3.5 on page 105, the
output compare function is not inhibited after a
write instruction to the OCiHR register. Instead the
buffer update at the end of the PWM period is inhibited until OCiLR is written. This improved buffer
handling is fully compatible with applications written for Flash devices.
ST72561
16 REVISION HISTORY
Date
Revision
Main changes
Added TQFP 10x10 package
Removed internal RC
Updated Figure 11 on page 22
Added note on monotonous VDD ramp on “Low Voltage Detector (LVD)” on page 26
Added caution ART Ext clock not avalaible in HALT see Section 10.3 on page 64
Added note “Once the OCIE bit is set both output compare features may trigger...” and
“Once the ICIE bit is set both input capture features may trigger...” in 8-bit timer Section 10.5.
Changed clock from fcpu/8000 to fosc2/8000 in Section 10.5 on page 94
Changed description of CSR register to read only except bit 2 R/W Section 10.5 on page 94
03-May 04
1.9
Added note to SPI slave freq. and updated Master mode procedure in Section 10.6 on page
112
Changed description of NF bit in Section 10.7.10
Removed “Configurable timer resolution” under "Time triggered communication option" from
Section 10.9 on page 172
Added Clearing interrupts limitation and SCI wrong break duration to “IMPORTANT
NOTES” on page 259
Removed beCAN Time triggered mode feature from Section 10.9 on page 172
Renamed CMSR RX and TX bits to REC and TRAN in Section 10.9 on page 172
Added beCAN FIFO corruption limitation Section 10.9.7.1 on page 189
Modified IINJ for Port B3 in Section 12.9.1 on page 236
11-May 04
2.0
Modified Clearing interrupts limitation in “IMPORTANT NOTES” on page 259
261/262
ST72561
Notes:
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
The ST logo is a registered trademark of STMicroelectronics.
All other names are the property of their respective owners
© 2004 STMicroelectronics - All rights reserved
STMicroelectronics GROUP OF COMPANIES
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www.st.com
LINSCI is a trademark of STMicroelectronics.
262/262