ST7263B LOW SPEED USB 8-BIT MCU FAMILY WITH FLASH/ROM, UP TO 512 BYTES RAM, 8-BIT ADC, WDG, TIMER, SCI & I²C ■ ■ ■ ■ ■ Memories – 4, 8 or 16 Kbytes Program Memory: High Density Flash (HDFlash) or ROM with Readout and Write Protection – In-Application Programming (IAP) and In-Circuit programming (ICP) for HDFlash devices – 384 or 512 bytes RAM memory (128-byte stack) Clock, Reset and Supply Management – Run, Wait, Slow and Halt CPU modes – 12 or 24 MHz Oscillator – RAM Retention mode – Optional Low Voltage Detector (LVD) USB (Universal Serial Bus) Interface – DMA for low speed applications compliant with USB 1.5 Mbs (version 1.1) and HID specifications (version 1.0) – Integrated 3.3 V voltage regulator and transceivers – Suspend and Resume operations – 3 Endpoints with programmable In/Out configuration 19 I/O Ports – 8 high sink I/Os (10 mA at 1.3 V) – 2 very high sink true open drain I/Os (25 mA at 1.5 V) – 8 lines individually programmable as interrupt inputs 2 Timers – Programmable Watchdog – 16-bit Timer with 2 Input Captures, 2 Output Compares, PWM output and clock input PSDIP32 SO34 (Shrink) ■ ■ ■ ■ 2 Communication Interfaces – Asynchronous Serial Communications Interface (on K4 and K2 versions only) – I²C Multi Master Interface up to 400 kHz (on K4 versions only) 1 Analog Peripheral – 8-bit A/D Converter (ADC) with 8 channels Instruction Set – 63 basic instructions – 17 main addressing modes – 8 x 8 unsigned multiply instruction – True bit manipulation Development Tools – Versatile Development Tools (under Windows) including assembler, linker, C-compiler, archiver, source level debugger, software library, hardware emulator, programming boards and gang programmers Table 1. Device Summary Features Program Memory -bytesRAM (stack) - bytes Peripherals Operating Supply CPU frequency ST72F63BK4 16K (Flash or FASTROM) ST7263BK2 8K (Flash, ROM or FASTROM) 512 (128) Watchdog timer, 16-bit timer, SCI, I²C, ADC, USB ST7263BK1 4K (Flash, ROM or FASTROM) 384 (128) Watchdog timer, 16-bit timer, SCI, ADC, USB Watchdog, 16-bit timer, ADC, USB 4.0 V to 5.5 V 8 MHz (with 24 MHz oscillator) or 4 MHz (with 12 MHz oscillator) Operating temperature 0 °C to +70 °C Packages SO34/SDIP32 Rev. 1.5 April 2003 1/132 1 Table of Contents 1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2 PIN DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3 REGISTER & MEMORY MAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 4 FLASH PROGRAM MEMORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4.2 MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4.3 STRUCTURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4.4 ICC INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4.5 ICP (IN-CIRCUIT PROGRAMMING) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.6 IAP (IN-APPLICATION PROGRAMMING) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5 CENTRAL PROCESSING UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5.2 MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5.3 CPU REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 6 RESET AND CLOCK MANAGEMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 6.1 RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 6.2 CLOCK SYSTEM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 7 INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 7.1 INTERRUPT REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 8 POWER SAVING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 8.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 8.2 HALT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 8.3 SLOW MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 8.4 WAIT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 9 I/O PORTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 9.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 9.2 FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 9.3 I/O PORT IMPLEMENTATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 10 MISCELLANEOUS REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 11 ON-CHIP PERIPHERALS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 11.1 WATCHDOG TIMER (WDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 11.2 16-BIT TIMER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 11.3 SERIAL COMMUNICATIONS INTERFACE (SCI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 11.4 USB INTERFACE (USB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 11.5 I²C BUS INTERFACE (I²C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 11.6 8-BIT A/D CONVERTER (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 12 INSTRUCTION SET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 12.1 ST7 ADDRESSING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 12.2 INSTRUCTION GROUPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 13 ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 13.1 PARAMETER CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 . . . . 96 13.2 ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 2/132 Table of Contents 13.3 OPERATING CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 13.4 SUPPLY CURRENT CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 13.5 CLOCK AND TIMING CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 13.6 MEMORY CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 13.7 EMC CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 13.8 I/O PORT PIN CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 13.9 CONTROL PIN CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 13.10COMMUNICATION INTERFACE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . 116 13.118-BIT ADC CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 14 PACKAGE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 14.1 PACKAGE MECHANICAL DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 14.2 THERMAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 14.3 SOLDERING AND GLUEABILITY INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 15 DEVICE CONFIGURATION AND ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . 124 15.1 OPTION BYTE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 15.2 DEVICE ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 15.3 DEVELOPMENT TOOLS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 15.4 ST7 APPLICATION NOTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 16 KNOWN LIMITATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 16.1 UNEXPECTED RESET FETCH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 16.2 HALT MODE POWER CONSUMPTION WITH ADC ON . . . . . . . . . . . . . . . . . . . . . . . . . 130 17 SUMMARY OF CHANGES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 To obtain the most recent version of this datasheet, please check at www.st.com>products>technical literature>datasheet Please also pay special attention to the Section “IMPORTANT NOTES” on page 130. 3/132 ST7263B 1 INTRODUCTION The ST7263B Microcontrollers form a sub-family of the ST7 MCUs dedicated to USB applications. The devices are based on an industry-standard 8bit core and feature an enhanced instruction set. They operate at a 24 MHz or 12 MHz oscillator frequency. Under software control, the ST7263B MCUs may be placed in either Wait or Halt modes, thus reducing power consumption. The enhanced instruction set and addressing modes afford real programming potential. In addition to standard 8bit data management, the ST7263B MCUs feature true bit manipulation, 8x8 unsigned multiplication and indirect addressing modes. The devices include an ST7 Core, up to 16 Kbytes of program memory, up to 512 bytes of RAM, 19 I/O lines and the following on-chip peripherals: – USB low speed interface with 3 endpoints with programmable in/out configuration using the DMA architecture with embedded 3.3V voltage regulator and transceivers (no external components are needed). – 8-bit Analog-to-Digital converter (ADC) with 8 multiplexed analog inputs – Industry standard asynchronous SCI serial interface (not on all products - see Table 1 Device Summary) – Watchdog – 16-bit Timer featuring an External clock input, 2 Input Captures, 2 Output Compares with Pulse Generator capabilities – Fast I²C Multi Master interface (not on all products - see device summary) – Low voltage reset (LVD) ensuring proper poweron or power-off of the device The ST7263B devices are ROM versions. The ST72P63B devices are Factory Advanced Service Technique ROM (FASTROM) versions: they are factory-programmed and are not reprogrammable. The ST72F63B devices are Flash versions. They support programming in IAP mode (In-application programming) via the on-chip USB interface. Figure 1. General Block Diagram INTERNAL CLOCK OSC/3 OSCIN OSCOUT OSCILLATOR I²C* OSC/4 or OSC/2 (for USB) VDD VSS PORT A POWER SUPPLY PA[7:0] (8 bits) 16-BIT TIMER WATCHDOG CONTROL 8-BIT CORE ALU LVD USB DMA VPP/TEST VDDA VSSA PROGRAM MEMORY (4K/8K/16K Bytes) RAM (384/512 Bytes) * Not on all products (refer to Table 1: Device Summary) 4/132 ADDRESS AND DATA BUS RESET PORT B ADC PB[7:0] (8 bits) PORT C SCI* (UART) USB SIE PC[2:0] (3 bits) USBDP USBDM USBVCC ST7263B 2 PIN DESCRIPTION Figure 2. 34-Pin SO Package Pinout VDD 1 34 VDDA OSCOUT 2 33 USBVCC OSCIN 3 32 USBDM VSS 4 31 USBDP PC2/USBOE 5 30 VSSA PC1/TDO 6 29 PA0/MCO PC0/RDI 7 28 PA1(25mA)/SDA/ICCDATA RESET 8 27 NC NC 9 26 NC AIN7/IT8PB7(10mA) 10 25 NC AIN6/PB6/IT7(10mA) 11 24 PA2(25mA)/SCL/ICCCLK VPP/TEST 12 23 PA3/EXTCLK AIN5/IT6/PB5(10mA) 13 22 PA4/ICAP1/IT1 AIN4/IT5/PB4(10mA) 14 21 PA5/ICAP2/IT2 AIN3/PB3(10mA) 15 20 PA6/OCMP1/IT3 AIN2/PB2(10mA) 16 19 PA7/OCMP2/IT4 18 PB0(10mA)/AIN0 AIN1/PB1(10mA) 17 * VPP on Flash versions only Figure 3. 32-Pin SDIP Package Pinout VDD 1 32 VDDA OSCOUT 2 31 USBVCC OSCIN 3 30 USBDM VSS 4 29 USBDP PC2/USBOE 5 28 VSSA PC1/TDO 6 27 PA0/MCO PC0/RDI 7 26 PA1(25mA)/SDA/ICCDATA RESET 8 25 NC AIN7/IT8/PB7(10mA) 9 24 NC AIN6/IT7/PB6(10mA) 10 23 PA2(25mA)/SCL/ICCCLK VPP /TEST* 11 22 PA3/EXTCLK AIN5/IT6/PB5(10mA) 12 21 PA4/ICAP1/IT1 AIN4/IT5/PB4(10mA) 13 20 PA5/ICAP2/IT2 AIN3/PB3(10mA) 14 19 PA6/COMP1/IT3 AIN2/PB2(10mA) 15 18 PA7/COMP2/IT4 AIN1/PB1/(10mA) 16 17 PB0(10mA)/AIN0 * VPP on Flash versions only 5/132 ST7263B PIN DESCRIPTION (Cont’d) RESET (see Note 1): Bidirectional. This active low signal forces the initialization of the MCU. This event is the top priority non maskable interrupt. This pin is switched low when the Watchdog is triggered or the V DD is low. It can be used to reset external peripherals. OSCIN/OSCOUT: Input/Output Oscillator pin. These pins connect a parallel-resonant crystal, or an external source, to the on-chip oscillator. VDD/VSS (see Note 2): Main Power Supply and Ground voltages. VDDA/VSSA (see Note 2): Power Supply and Ground voltages for analog peripherals. Alternate Functions: Several pins of the I/O ports assume software programmable alternate functions as shown in the pin description. Note 1: Adding two 100 nF decoupling capacitors on the Reset pin (respectively connected to VDD and VSS) will significantly improve product electromagnetic susceptibility performance. Note 2: To enhance the reliability of operation, it is recommended that VDDA and VDD be connected together on the application board. This also applies to VSSA and VSS. Table 2. Device Pin Description Level Port / Control Output Main Function (after reset) OSCOUT O Oscillator output 3 3 OSCIN I Oscillator input 4 4 VSS S Digital ground 5 5 PC2/USBOE I/O CT X X Port C2 USB Output Enable 6 6 PC1/TDO I/O CT X X Port C1 SCI Transmit Data Output* 7 7 PC0/RDI I/O CT X X Port C0 SCI Receive Data Input* 8 8 RESET I/O -- 9 NC 9 10 PB7/AIN7/IT8 I/O CT 10mA X X X X Port B7 ADC analog input 7 10 11 PB6/AIN6/IT7 I/O CT 10mA X X X X Port B6 ADC analog input 6 11 12 VPP/TEST X PP 2 OD 2 ana Power supply voltage (4V - 5.5V) int S wpu VDD float 1 Output 1 Pin Name Input SO34 Input SDIP32 Type Pin n° X Alternate Function Reset -- Not connected S Programming supply 12 13 PB5/AIN5/IT6 I/O CT 10mA X X X X Port B5 ADC analog input 5 13 14 PB4/AIN4/IT5 I/O CT 10mA X X X X Port B4 ADC analog input 4 14 15 PB3/AIN3 I/O CT 10mA X X X Port B3 ADC analog input 3 15 16 PB2/AIN2 I/O CT 10mA X X X Port B2 ADC analog input 2 16 17 PB1/AIN1 I/O CT 10mA X X X Port B1 ADC analog input 1 17 18 PB0/AIN0 I/O CT 10mA X X X Port B0 ADC Analog Input 0 18 19 PA7/OCMP2/IT4 I/O CT X X X Port A7 Timer Output Compare 2 19 20 PA6/OCMP1/IT3 I/O CT X X X Port A6 Timer Output Compare 1 20 21 PA5/ICAP2/IT2 I/O CT X X X Port A5 Timer Input Capture 2 21 22 PA4/ICAP1/IT1 I/O CT X X X Port A4 Timer Input Capture 1 6/132 ST7263B Port / Control 22 23 PA3/EXTCLK I/O CT 23 24 PA2/SCL/ICCCLK I/O CT 25mA X X PP OD Output ana int wpu Input float Output Pin Name Input Level Type SO34 SDIP32 Pin n° X T Main Function (after reset) Port A3 Timer External Clock Port A2 I²C serial clock*, ICC Clock -- 25 NC -- Not connected 24 26 NC -- Not connected 25 27 NC -- Not connected 26 28 PA1/SDA/ICCDATA I/O CT 25mA X 27 29 PA0/MCO I/O 28 30 VSSA S CT T X X Alternate Function Port A1 I²C serial data*, ICC Data Port A0 Main Clock Output Analog ground 29 31 USBDP I/O USB bidirectional data (data +) 30 32 USBDM I/O USB bidirectional data (data -) 31 33 USBVCC O USB power supply 32 34 VDDA S Analog supply voltage Note (*): if the peripheral is present on the device (see Table 1, "Device Summary") Legend / Abbreviations for Figure 2 and Table 2: Type: I = input, O = output, S = supply In/Output level: CT = CMOS 0.3VDD/0.7VDD with input trigger Output level: 10mA = 10mA high sink (on N-buffer only) 25mA = 25mA very high sink (on N-buffer only) Port and control configuration: – Input: float = floating, wpu = weak pull-up, int = interrupt, ana = analog – Output: OD = open drain, PP = push-pull, T = True open drain Refer to “I/O PORTS” on page 25 for more details on the software configuration of the I/O ports. The RESET configuration of each pin is shown in bold. This configuration is kept as long as the device is under reset state. 7/132 ST7263B 3 REGISTER & MEMORY MAP As shown in Figure 4, the MCU is capable of addressing 64 Kbytes of memories and I/O registers. The available memory locations consist of up to 512 bytes of RAM including 64 bytes of register locations, and up to 16K bytes of user program memory in which the upper 32 bytes are reserved for interrupt vectors. The RAM space includes up to 128 bytes for the stack from 0100h to 017Fh. The highest address bytes contain the user reset and interrupt vectors. IMPORTANT: Memory locations noted “Reserved” must never be accessed. Accessing a reserved area can have unpredictable effects on the device. Figure 4. Memory Map 0000h 003Fh 0040h 0040h HW Registers (See Table 4) 00FFh 0100h RAM (384/512 Bytes) Short Addressing RAM (192 bytes) Stack (128 Bytes) 017Fh 0180h 01BF/023Fh 01C0/0240h 16-bit Addressing RAM Reserved BFFFh C000h 01BF/023Fh C000h Program Memory* (4/8/16 KBytes) FFDFh FFE0h FFFFh 16 KBytes Interrupt & Reset Vectors (See Table 3) E000h 8 KBytes F000h 4 KBytes FFDFh * Program memory and RAM sizes are product dependent (see Table 1, "Device Summary") Table 3. Interrupt Vector Map Vector Address Description FFE0h-FFEDh Reserved Area Masked by Remarks Exit from Halt Mode FFEEh-FFEFh FFF0h-FFF1h USB Interrupt Vector I- bit Internal Interrupt No SCI Interrupt Vector I- bit Internal Interrupt FFF2h-FFF3h No I²C Interrupt Vector I- bit Internal Interrupt No FFF4h-FFF5h TIMER Interrupt Vector I- bit Internal Interrupt No FFF6h-FFF7h IT1 to IT8 Interrupt Vector I- bit External Interrupt Yes FFF8h-FFF9h USB End Suspend Mode Interrupt Vector I- bit External Interrupts Yes Yes FFFAh-FFFBh Flash Start Programming Interrupt Vector I- bit Internal Interrupt FFFCh-FFFDh TRAP (software) Interrupt Vector None CPU Interrupt FFFEh-FFFFh RESET Vector None 8/132 No Yes ST7263B Table 4. Hardware Register Memory Map Address 0000h 0001h 0002h 0003h 0004h 0005h Block Port A Port B Port C Register Label Register name Reset Status Remarks PADR Port A Data Register 00h R/W PADDR Port A Data Direction Register 00h R/W PBDR Port B Data Register 00h R/W PBDDR Port B Data Direction Register 00h R/W PCDR Port C Data Register 1111 x000b R/W PCDDR Port C Data Direction Register 1111 x000b R/W 0006h Reserved (2 Bytes) 0007h 0008h ITC ITIFRE Interrupt Register 00h R/W 0009h MISC MISCR Miscellaneous Register 00h R/W ADCDR ADC Data Register 00h Read only ADCCSR ADC control Status register 00h R/W WDGCR Watchdog Control Register 7Fh R/W 000Ah 000Bh 000Ch ADC WDG 000Dh to Reserved (4 bytes) 0010h 0011h TCR2 Timer Control Register 2 00h R/W 0012h TCR1 Timer Control Register 1 00h R/W 0013h TSR Timer Status Register 00h Read only 0014h TIC1HR Timer Input Capture High Register 1 xxh Read only 0015h TIC1LR Timer Input Capture Low Register 1 xxh Read only 0016h TOC1HR Timer Output Compare High Register 1 80h R/W 0017h TOC1LR Timer Output Compare Low Register 1 00h R/W TCHR Timer Counter High Register FFh Read only 0019h TCLR Timer Counter Low Register FCh R/W 001Ah TACHR Timer Alternate Counter High Register FFh Read only 001Bh TACLR Timer Alternate Counter Low Register FCh R/W 001Ch TIC2HR Timer Input Capture High Register 2 xxh Read only 001Dh TIC2LR Timer Input Capture Low Register 2 xxh Read only 001Eh TOC2HR Timer Output Compare High Register 2 80h R/W 001Fh TOC2LR Timer Output Compare Low Register 2 00h R/W 0020h SCISR SCI Status Register C0h Read only 0021h SCIDR SCI Data Register xxh R/W SCIBRR SCI Baud Rate Register 00h R/W 0023h SCICR1 SCI Control Register 1 x000 0000b R/W 0024h SCICR2 SCI Control Register 2 00h R/W 0018h 0022h TIM SCI 1) 9/132 ST7263B Address Block Register Label Register name Reset Status Remarks 0025h USBPIDR USB PID Register x0h Read only 0026h USBDMAR USB DMA address Register xxh R/W 0027h USBIDR USB Interrupt/DMA Register x0h R/W 0028h USBISTR USB Interrupt Status Register 00h R/W 0029h USBIMR USB Interrupt Mask Register 00h R/W 002Ah USBCTLR USB Control Register 06h R/W USBDADDR USB Device Address Register 00h R/W 002Ch USBEP0RA USB Endpoint 0 Register A 0000 xxxxb R/W 002Dh USBEP0RB USB Endpoint 0 Register B 80h R/W 002Eh USBEP1RA USB Endpoint 1 Register A 0000 xxxxb R/W 002Fh USBEP1RB USB Endpoint 1 Register B 0000 xxxxb R/W 0030h USBEP2RA USB Endpoint 2 Register A 0000 xxxxb R/W 0031h USBEP2RB USB Endpoint 2 Register B 0000 xxxxb R/W 00h R/W I²C Data Register 00h R/W Reserved - I2COAR I²C (7 Bits) Slave Address Register 00h R/W 002Bh USB 0032h to Reserved (5 bytes) 0036h 0032h Reserved (5 Bytes) 0036h 0037h Flash FCSR Flash Control /Status Register 0038h Reserved (1 byte) I2CDR 0039h 003Ah 003Bh I²C1) I2CCCR I²C Clock Control Register 00h R/W 003Dh I2CSR2 I²C 2nd Status Register 00h Read only 003Eh I2CSR1 I²C 1st Status Register 00h Read only 003Fh I2CCR I²C Control Register 00h R/W 003Ch Note 1. If the peripheral is present on the device (see Table 1, "Device Summary") 10/132 ST7263B 4 FLASH PROGRAM MEMORY 4.1 Introduction The ST7 dual voltage High Density Flash (HDFlash) is a non-volatile memory that can be electrically erased as a single block or by individual sectors and programmed on a Byte-by-Byte basis using an external VPP supply. The HDFlash devices can be programmed and erased off-board (plugged in a programming tool) or on-board using ICP (In-Circuit Programming) or IAP (In-Application Programming). The array matrix organisation allows each sector to be erased and reprogrammed without affecting other sectors. Depending on the overall Flash memory size in the microcontroller device, there are up to three user sectors (see Table 5). Each of these sectors can be erased independently to avoid unnecessary erasing of the whole Flash memory when only a partial erasing is required. The first two sectors have a fixed size of 4 Kbytes (see Figure 5). They are mapped in the upper part of the ST7 addressing space so the reset and interrupt vectors are located in Sector 0 (F000hFFFFh). Table 5. Sectors available in Flash devices Flash Size (bytes) Available Sectors 4K Sector 0 4.2 Main Features ■ ■ ■ ■ Three Flash programming modes: – Insertion in a programming tool. In this mode, all sectors including option bytes can be programmed or erased. – ICP (In-Circuit Programming). In this mode, all sectors including option bytes can be programmed or erased without removing the device from the application board. – IAP (In-Application Programming) In this mode, all sectors except Sector 0, can be programmed or erased without removing the device from the application board and while the application is running. ICT (In-Circuit Testing) for downloading and executing user application test patterns in RAM Read-out protection against piracy Register Access Security System (RASS) to prevent accidental programming or erasing 8K Sectors 0,1 > 8K Sectors 0,1, 2 4.3.1 Read-out Protection Read-out protection, when selected, makes it impossible to extract the memory content from the microcontroller, thus preventing piracy. Even ST cannot access the user code. In flash devices, this protection is removed by reprogramming the option. In this case, the entire program memory is first automatically erased. Read-out protection selection depends on the device type: – In Flash devices it is enabled and removed through the FMP_R bit in the option byte. – In ROM devices it is enabled by mask option specified in the Option List. 4.3 Structure The Flash memory is organised in sectors and can be used for both code and data storage. Figure 5. Memory Map and Sector Address 4K 8K 10K 16K 24K 32K 48K 60K 1000h FLASH MEMORY SIZE 3FFFh 7FFFh 9FFFh SECTOR 2 BFFFh D7FFh DFFFh EFFFh FFFFh 2 Kbytes 8 Kbytes 16 Kbytes 24 Kbytes 40 Kbytes 52 Kbytes 4 Kbytes SECTOR 1 4 Kbytes SECTOR 0 11/132 ST7263B FLASH PROGRAM MEMORY (Cont’d) – – – – ICCCLK: ICC output serial clock pin ICCDATA: ICC input/output serial data pin ICCSEL/VPP: programming voltage OSC1(or OSCIN): main clock input for external source (optional) – VDD: application board power supply (optional, see Figure 6, Note 3) 4.4 ICC Interface ICC needs a minimum of 4 and up to 6 pins to be connected to the programming tool (see Figure 6). These pins are: – RESET: device reset – VSS: device power supply ground Figure 6. Typical ICC Interface PROGRAMMING TOOL ICC CONNECTOR ICC Cable APPLICATION BOARD OPTIONAL (See Note 3) ICC CONNECTOR HE10 CONNECTOR TYPE OPTIONAL (See Note 4) 9 7 5 3 1 10 8 6 4 2 APPLICATION RESET SOURCE See Note 2 10kΩ APPLICATION POWER SUPPLY CL2 CL1 See Notes 1 and 5 Notes: 1. If the ICCCLK or ICCDATA pins are only used as outputs in the application, no signal isolation is necessary. As soon as the Programming Tool is plugged to the board, even if an ICC session is not in progress, the ICCCLK and ICCDATA pins are not available for the application. If they are used as inputs by the application, isolation such as a serial resistor has to implemented in case another device forces the signal. Refer to the Programming Tool documentation for recommended resistor values. 2. During the ICC session, the programming tool must control the RESET pin. This can lead to conflicts between the programming tool and the application reset circuit if it drives more than 5mA at high level (push pull output or pull-up resistor<1K). A schottky diode can be used to isolate the application RESET circuit in this case. When using a classical RC network with R>1K or a reset management IC with open drain output and pull-up resistor>1K, no additional components are needed. 12/132 ICCDATA ICCCLK RESET ST7 ICCSEL/VPP VSS OSC1 OSC2 VDD See Note 1 APPLICATION I/O In all cases the user must ensure that no external reset is generated by the application during the ICC session. 3. The use of Pin 7 of the ICC connector depends on the Programming Tool architecture. This pin must be connected when using most ST Programming Tools (it is used to monitor the application power supply). Please refer to the Programming Tool manual. 4. Pin 9 has to be connected to the OSC1 or OSCIN pin of the ST7 when the clock is not available in the application or if the selected clock option is not programmed in the option byte. ST7 devices with multi-oscillator capability need to have OSC2 grounded in this case. 5. During normal operation, the ICCCLK pin must be pulled-up, internally or externally, to avoid entering ICC mode unexpectedly during a reset. ST7263B FLASH PROGRAM MEMORY (Cont’d) 4.5 ICP (In-Circuit Programming) To perform ICP the microcontroller must be switched to ICC (In-Circuit Communication) mode by an external controller or programming tool. Depending on the ICP code downloaded in RAM, Flash memory programming can be fully customized (number of bytes to program, program locations, or selection serial communication interface for downloading). When using an STMicroelectronics or third-party programming tool that supports ICP and the specific microcontroller device, the user needs only to implement the ICP hardware interface on the application board (see Figure 6). For more details on the pin locations, refer to the device pinout description. mode, choice of communications protocol used to fetch the data to be stored, etc.). For example, it is possible to download code from the SPI, SCI, USB or CAN interface and program it in the Flash. IAP mode can be used to program any of the Flash sectors except Sector 0, which is write/erase protected to allow recovery in case errors occur during the programming operation. 4.6.1 Register Description FLASH CONTROL/STATUS REGISTER (FCSR) Read /Write Reset Value: 0000 0000 (00h) 7 0 0 0 0 0 0 0 0 0 4.6 IAP (In-Application Programming) This mode uses a BootLoader program previously stored in Sector 0 by the user (in ICP mode or by plugging the device in a programming tool). This mode is fully controlled by user software. This allows it to be adapted to the user application, (user-defined strategy for entering programming This register is reserved for use by Programming Tool software. It controls the Flash programming and erasing operations. For details on customizing Flash programming methods and In-Circuit Testing, refer to the ST7 Flash Programming Reference Manual. 13/132 ST7263B 5 CENTRAL PROCESSING UNIT 5.1 INTRODUCTION This CPU has a full 8-bit architecture and contains six internal registers allowing efficient 8-bit data manipulation. 5.2 MAIN FEATURES ■ ■ ■ ■ ■ ■ ■ ■ 63 basic instructions Fast 8-bit by 8-bit multiply 17 main addressing modes Two 8-bit index registers 16-bit stack pointer Low power modes Maskable hardware interrupts Non-maskable software interrupt 5.3 CPU REGISTERS The 6 CPU registers shown in Figure 7 are not present in the memory mapping and are accessed by specific instructions. Accumulator (A) The Accumulator is an 8-bit general purpose register used to hold operands and the results of the arithmetic and logic calculations and to manipulate data. Index Registers (X and Y) In indexed addressing modes, these 8-bit registers are used to create either effective addresses or temporary storage areas for data manipulation. (The Cross-Assembler generates a precede instruction (PRE) to indicate that the following instruction refers to the Y register.) The Y register is not affected by the interrupt automatic procedures (not pushed to and popped from the stack). Program Counter (PC) The program counter is a 16-bit register containing the address of the next instruction to be executed by the CPU. It is made of two 8-bit registers PCL (Program Counter Low which is the LSB) and PCH (Program Counter High which is the MSB). Figure 7. CPU Registers 7 0 ACCUMULATOR RESET VALUE = XXh 7 0 X INDEX REGISTER RESET VALUE = XXh 7 0 Y INDEX REGISTER RESET VALUE = XXh 15 PCH 8 7 PCL 0 PROGRAM COUNTER RESET VALUE = RESET VECTOR @ FFFEh-FFFFh 7 1 1 1 H I 0 N Z C CONDITION CODE REGISTER RESET VALUE = 1 1 1 X 1 X X X 15 8 7 0 STACK POINTER RESET VALUE = STACK HIGHER ADDRESS X = Undefined Value 14/132 ST7263B CPU REGISTERS (Cont’d) CONDITION CODE REGISTER (CC) Read/Write Reset Value: 111x1xxx 7 1 0 1 1 H I N Z because the I bit is set by hardware at the start of the routine and reset by the IRET instruction at the end of the routine. If the I bit is cleared by software in the interrupt routine, pending interrupts are serviced regardless of the priority level of the current interrupt routine. C The 8-bit Condition Code register contains the interrupt mask and four flags representative of the result of the instruction just executed. This register can also be handled by the PUSH and POP instructions. These bits can be individually tested and/or controlled by specific instructions. Bit 4 = H Half carry. This bit is set by hardware when a carry occurs between bits 3 and 4 of the ALU during an ADD or ADC instruction. It is reset by hardware during the same instructions. 0: No half carry has occurred. 1: A half carry has occurred. This bit is tested using the JRH or JRNH instruction. The H bit is useful in BCD arithmetic subroutines. Bit 2 = N Negative. This bit is set and cleared by hardware. It is representative of the result sign of the last arithmetic, logical or data manipulation. It is a copy of the 7th bit of the result. 0: The result of the last operation is positive or null. 1: The result of the last operation is negative (i.e. the most significant bit is a logic 1). This bit is accessed by the JRMI and JRPL instructions. Bit 1 = Z Zero. This bit is set and cleared by hardware. This bit indicates that the result of the last arithmetic, logical or data manipulation is zero. 0: The result of the last operation is different from zero. 1: The result of the last operation is zero. This bit is accessed by the JREQ and JRNE test instructions. Bit 3 = I Interrupt mask. This bit is set by hardware when entering in interrupt or by software to disable all interrupts except the TRAP software interrupt. This bit is cleared by software. 0: Interrupts are enabled. 1: Interrupts are disabled. This bit is controlled by the RIM, SIM and IRET instructions and is tested by the JRM and JRNM instructions. Note: Interrupts requested while I is set are latched and can be processed when I is cleared. By default an interrupt routine is not interruptable Bit 0 = C Carry/borrow. This bit is set and cleared by hardware and software. It indicates an overflow or an underflow has occurred during the last arithmetic operation. 0: No overflow or underflow has occurred. 1: An overflow or underflow has occurred. This bit is driven by the SCF and RCF instructions and tested by the JRC and JRNC instructions. It is also affected by the “bit test and branch”, shift and rotate instructions. 15/132 ST7263B CPU REGISTERS (Cont’d) STACK POINTER (SP) Read/Write Reset Value: 017Fh 15 0 8 0 0 0 0 0 0 7 0 1 0 SP6 SP5 SP4 SP3 SP2 SP1 SP0 The Stack Pointer is a 16-bit register which is always pointing to the next free location in the stack. It is then decremented after data has been pushed onto the stack and incremented before data is popped from the stack (see Figure 8). Since the stack is 128 bytes deep, the 9 most significant bits are forced by hardware. Following an MCU Reset, or after a Reset Stack Pointer instruction (RSP), the Stack Pointer contains its reset value (the SP6 to SP0 bits are set) which is the stack higher address. The least significant byte of the Stack Pointer (called S) can be directly accessed by a LD instruction. Note: When the lower limit is exceeded, the Stack Pointer wraps around to the stack upper limit, without indicating the stack overflow. The previously stored information is then overwritten and therefore lost. The stack also wraps in case of an underflow. The stack is used to save the return address during a subroutine call and the CPU context during an interrupt. The user may also directly manipulate the stack by means of the PUSH and POP instructions. In the case of an interrupt, the PCL is stored at the first location pointed to by the SP. Then the other registers are stored in the next locations as shown in Figure 8. – When an interrupt is received, the SP is decremented and the context is pushed on the stack. – On return from interrupt, the SP is incremented and the context is popped from the stack. A subroutine call occupies two locations and an interrupt five locations in the stack area. Figure 8. Stack Manipulation Example CALL Subroutine PUSH Y Interrupt Event POP Y RET or RSP IRET @ 0100h SP SP CC A CC A X X X PCH PCH PCL PCL PCL PCH PCH PCH PCH PCH PCL PCL PCL PCL PCL Stack Higher Address = 017Fh Stack Lower Address = 0100h 16/132 SP PCH SP @ 017Fh Y CC A SP SP ST7263B 6 RESET AND CLOCK MANAGEMENT 6.1 RESET The Reset procedure is used to provide an orderly software start-up or to exit low power modes. Three reset modes are provided: a low voltage (LVD) reset, a watchdog reset and an external reset at the RESET pin. A reset causes the reset vector to be fetched from addresses FFFEh and FFFFh in order to be loaded into the PC and with program execution starting from this point. An internal circuitry provides a 4096 CPU clock cycle delay from the time that the oscillator becomes active. 6.1.3 External Reset The external reset is an active low input signal applied to the RESET pin of the MCU. As shown in Figure 12, the RESET signal must stay low for a minimum of one and a half CPU clock cycles. An internal Schmitt trigger at the RESET pin is provided to improve noise immunity. Figure 9. Low Voltage Detector functional Diagram RESET VDD 6.1.1 Low Voltage Detector (LVD) Low voltage reset circuitry generates a reset when VDD is: ■ below VIT+ when VDD is rising, ■ below VIT- when VDD is falling. LOW VOLTAGE DETECTOR INTERNAL RESET FROM WATCHDOG RESET Figure 10. Low Voltage Reset Signal Output During low voltage reset, the RESET pin is held low, thus permitting the MCU to reset other devices. The Low Voltage Detector can be disabled by setting bit 3 of the option byte. VIT+ VIT- VDD 6.1.2 Watchdog Reset When a watchdog reset occurs, the RESET pin is pulled low permitting the MCU to reset other devices in the same way as the low voltage reset (Figure 9). RESET Note: Hysteresis (VIT+-VIT-) = Vhys Figure 11. Temporization timing diagram after an internal Reset VDD VIT+ Temporization (4096 CPU clock cycles) Addresses $FFFE 17/132 ST7263B RESET (Cont’d) Figure 12. Reset Timing Diagram tDDR VDD OSCIN tOXOV fCPU PC RESET WATCHDOG RESET FFFE FFFF 4096 CPU CLOCK CYCLES DELAY Note: Refer to Electrical Characteristics for values of tDDR, tOXOV, VIT+, VIT- and Vhys 18/132 ST7263B 6.2 CLOCK SYSTEM 6.2.1 General Description The MCU accepts either a Crystal or Ceramic resonator, or an external clock signal to drive the internal oscillator. The internal clock (fCPU) is derived from the external oscillator frequency (fOSC), which is divided by 3 (and by 2 or 4 for USB, depending on the external clock used). The internal clock is further divided by 2 by setting the SMS bit in the Miscellaneous Register. Using the OSC24/12 bit in the option byte, a 12 MHz or a 24 MHz external clock can be used to provide an internal frequency of either 2, 4 or 8 MHz while maintaining a 6 MHz for the USB (refer to Figure 15). The internal clock signal (fCPU) is also routed to the on-chip peripherals. The CPU clock signal consists of a square wave with a duty cycle of 50%. The internal oscillator is designed to operate with an AT-cut parallel resonant quartz or ceramic resonator in the frequency range specified for fosc. The circuit shown in Figure 14 is recommended when using a crystal, and Table 6, "Recommended Values for 24 MHz Crystal Resonator" lists the recommended capacitance. The crystal and associated components should be mounted as close as possible to the input pins in order to minimize output distortion and start-up stabilisation time. source should be used instead of tOXOV (see Section 6.5 CONTROL TIMING). Figure 13. External Clock Source Connections OSCOUT OSCIN NC EXTERNAL CLOCK Figure 14. Crystal/Ceramic Resonator OSCIN OSCOUT RP COSCIN COSCOUT Table 6. Recommended Values for 24 MHz Crystal Resonator RSMAX 20 Ω 25 Ω 70 Ω COSCIN 56pF 47pF 22pF COSCOUT 56pF 47pF 22pF RP 1-10 MΩ 1-10 MΩ 1-10 MΩ Note: RSMAX is the equivalent serial resistor of the crystal (see crystal specification). 6.2.2 External Clock An external clock may be applied to the OSCIN input with the OSCOUT pin not connected, as shown on Figure 13. The tOXOV specifications do not apply when using an external clock input. The equivalent specification of the external clock Figure 15. Clock Block Diagram 0 %2 %3 8, 4 or 2 MHz CPU and peripherals) 1 SMS 1 24 or 12 MHz Crystal 6 MHz (USB) %2 %2 %2 0 OSC24/12 19/132 ST7263B 7 INTERRUPTS The ST7 core may be interrupted by one of two different methods: maskable hardware interrupts as listed in Table 7, "Interrupt Mapping" and a nonmaskable software interrupt (TRAP). The Interrupt processing flowchart is shown in Figure 16. The maskable interrupts must be enabled clearing the I bit in order to be serviced. However, disabled interrupts may be latched and processed when they are enabled (see external interrupts subsection). When an interrupt has to be serviced: – Normal processing is suspended at the end of the current instruction execution. – The PC, X, A and CC registers are saved onto the stack. – The I bit of the CC register is set to prevent additional interrupts. – The PC is then loaded with the interrupt vector of the interrupt to service and the first instruction of the interrupt service routine is fetched (refer to Table 7, "Interrupt Mapping" for vector addresses). The interrupt service routine should finish with the IRET instruction which causes the contents of the saved registers to be recovered from the stack. Note: As a consequence of the IRET instruction, the I bit will be cleared and the main program will resume. Priority Management By default, a servicing interrupt cannot be interrupted because the I bit is set by hardware entering in interrupt routine. In the case several interrupts are simultaneously pending, a hardware priority defines which one will be serviced first (see Table 7, "Interrupt Mapping"). Non-maskable Software Interrupts This interrupt is entered when the TRAP instruction is executed regardless of the state of the I bit. It will be serviced according to the flowchart on Figure 16. 20/132 Interrupts and Low Power Mode All interrupts allow the processor to leave the Wait low power mode. Only external and specific mentioned interrupts allow the processor to leave the Halt low power mode (refer to the “Exit from HALT“ column in Table 7, "Interrupt Mapping"). External Interrupts The pins ITi/PAk and ITj/PBk (i=1,2; j= 5,6; k=4,5) can generate an interrupt when a rising edge occurs on this pin. Conversely, the ITl/PAn and ITm/ PBn pins (l=3,4; m= 7,8; n=6,7) can generate an interrupt when a falling edge occurs on this pin. Interrupt generation will occur if it is enabled with the ITiE bit (i=1 to 8) in the ITRFRE register and if the I bit of the CCR is reset. Peripheral Interrupts Different peripheral interrupt flags in the status register are able to cause an interrupt when they are active if both: – The I bit of the CC register is cleared. – The corresponding enable bit is set in the control register. If any of these two conditions is false, the interrupt is latched and thus remains pending. Clearing an interrupt request is done by one of the two following operations: – Writing “0” to the corresponding bit in the status register. – Accessing the status register while the flag is set followed by a read or write of an associated register. Notes: 1. The clearing sequence resets the internal latch. A pending interrupt (i.e. waiting to be enabled) will therefore be lost if the clear sequence is executed. 2. All interrupts allow the processor to leave the Wait low power mode. 3. Exit from Halt mode may only be triggered by an External Interrupt on one of the ITi ports (PA4-PA7 and PB4-PB7), an end suspend mode Interrupt coming from USB peripheral, or a reset. ST7263B INTERRUPTS (Cont’d) Figure 16. Interrupt Processing Flowchart FROM RESET BIT I SET N N Y Y FETCH NEXT INSTRUCTION N INTERRUPT IRET STACK PC, X, A, CC SET I BIT LOAD PC FROM INTERRUPT VECTOR Y EXECUTE INSTRUCTION RESTORE PC, X, A, CC FROM STACK THIS CLEARS I BIT BY DEFAULT Table 7. Interrupt Mapping N° Source Block RESET TRAP FLASH USB 1 ITi 2 TIMER 3 I²C Description Reset Software Interrupt Register Label Priority Order N/A Highest Priority Flash Start Programming Interrupt End Suspend Mode ISTR External Interrupts ITRFRE Timer Peripheral Interrupts TIMSR I²C Peripheral Interrupts Address yes FFFEh-FFFFh no FFFCh-FFFDh yes FFFAh-FFFBh yes 4 SCI SCI Peripheral Interrupts SCISR 5 USB USB Peripheral Interrupts ISTR FFF8h-FFF9h FFF6h-FFF7h FFF4h-FFF5h I²CSR1 I²CSR2 Vector Exit from HALT Lowest Priority no FFF2h-FFF3h FFF0h-FFF1h FFEEh-FFEFh 21/132 ST7263B INTERRUPTS (Cont’d) 7.1 Interrupt Register INTERRUPTS REGISTER (ITRFRE) Address: 0008h — Read/Write Reset Value: 0000 0000 (00h) 7 IT8E 0 IT7E IT6E IT5E IT4E IT3E IT2E IT1E Bit 7:0 = ITiE (i=1 to 8). Interrupt Enable Control Bits . 22/132 If an ITiE bit is set, the corresponding interrupt is generated when – a rising edge occurs on the pin PA4/IT1 or PA5/ IT2 or PB4/IT5 or PB5/IT6 or – a falling edge occurs on the pin PA6/IT3 or PA7/ IT4 or PB6/IT7 or PB7/IT8 No interrupt is generated elsewhere. Note: Analog input must be disabled for interrupts coming from port B. ST7263B 8 POWER SAVING MODES 8.1 Introduction To give a large measure of flexibility to the application in terms of power consumption, two main power saving modes are implemented in the ST7. After a RESET, the normal operating mode is selected by default (RUN mode). This mode drives the device (CPU and embedded peripherals) by means of a master clock which is based on the main oscillator frequency divided by 3 (f CPU). From Run mode, the different power saving modes may be selected by setting the relevant register bits or by calling the specific ST7 software instruction whose action depends on the oscillator status. Figure 17. HALT Mode Flow Chart HALT INSTRUCTION OSCILLATOR PERIPH. CLOCK CPU CLOCK I-BIT 8.2 HALT Mode The MCU consumes the least amount of power in HALT mode. The HALT mode is entered by executing the HALT instruction. The internal oscillator is then turned off, causing all internal processing to be stopped, including the operation of the on-chip peripherals. When entering HALT mode, the I bit in the Condition Code Register is cleared. Thus, all external interrupts (ITi or USB end suspend mode) are allowed and if an interrupt occurs, the CPU clock becomes active. The MCU can exit HALT mode on reception of either an external interrupt on ITi, an end suspend mode interrupt coming from USB peripheral, or a reset. The oscillator is then turned on and a stabilization time is provided before releasing CPU operation. The stabilization time is 4096 CPU clock cycles. After the start up delay, the CPU continues operation by servicing the interrupt which wakes it up or by fetching the reset vector if a reset wakes it up. OFF OFF OFF CLEARED N RESET N EXTERNAL INTERRUPT* Y Y OSCILLATOR PERIPH. CLOCK CPU CLOCK I-BIT ON ON ON SET 4096 CPU CLOCK CYCLES DELAY FETCH RESET VECTOR OR SERVICE INTERRUPT Note: Before servicing an interrupt, the CC register is pushed on the stack. The I-Bit is set during the interrupt routine and cleared when the CC register is popped. 23/132 ST7263B POWER SAVING MODES (Cont’d) 8.3 SLOW Mode In Slow mode, the oscillator frequency can be divided by 2 as selected by the SMS bit in the Miscellaneous Register. The CPU and peripherals are clocked at this lower frequency. Slow mode is used to reduce power consumption, and enables the user to adapt the clock frequency to the available supply voltage. Figure 18. WAIT Mode Flow Chart WFI INSTRUCTION OSCILLATOR PERIPH. CLOCK CPU CLOCK 8.4 WAIT Mode WAIT mode places the MCU in a low power consumption mode by stopping the CPU. This power saving mode is selected by calling the “WFI” ST7 software instruction. All peripherals remain active. During WAIT mode, the I bit of the CC register is forced to 0 to enable all interrupts. All other registers and memory remain unchanged. The MCU remains in WAIT mode until an interrupt or Reset occurs, whereupon the Program Counter branches to the starting address of the interrupt or Reset service routine. The MCU will remain in WAIT mode until a Reset or an Interrupt occurs, causing it to wake up. Refer to Figure 18. I-BIT ON ON OFF CLEARED N RESET N Y INTERRUPT Y OSCILLATOR PERIPH. CLOCK CPU CLOCK I-BIT ON ON ON SET IF RESET 4096 CPU CLOCK CYCLES DELAY FETCH RESET VECTOR OR SERVICE INTERRUPT Note: Before servicing an interrupt, the CC register is pushed on the stack. The I-Bit is set during the interrupt routine and cleared when the CC register is popped. 24/132 ST7263B 9 I/O PORTS 9.1 Introduction The I/O ports offer different functional modes: – Transfer of data through digital inputs and outputs and for specific pins – Analog signal input (ADC) – Alternate signal input/output for the on-chip peripherals – External interrupt generation An I/O port consists of up to 8 pins. Each pin can be programmed independently as a digital input (with or without interrupt generation) or a digital output. 9.2 Functional description Each port is associated to 2 main registers: – Data Register (DR) – Data Direction Register (DDR) Each I/O pin may be programmed using the corresponding register bits in DDR register: bit X corresponding to pin X of the port. The same correspondence is used for the DR register. Table 8. I/O Pin Functions DDR MODE 0 Input 1 Output Input Modes The input configuration is selected by clearing the corresponding DDR register bit. In this case, reading the DR register returns the digital value applied to the external I/O pin. Note 1: All the inputs are triggered by a Schmitt trigger. Note 2: When switching from input mode to output mode, the DR register should be written first to output the correct value as soon as the port is configured as an output. Interrupt function When an I/O is configured as an Input with Interrupt, an event on this I/O can generate an external Interrupt request to the CPU. The interrupt sensi- tivity is given independently according to the description mentioned in the ITRFRE interrupt register. Each pin can independently generate an Interrupt request. Each external interrupt vector is linked to a dedicated group of I/O port pins (see Interrupts section). If more than one input pin is selected simultaneously as an interrupt source, this is logically ORed. For this reason if one of the interrupt pins is tied low, the other ones are masked. Output Mode The pin is configured in output mode by setting the corresponding DDR register bit (see Table 7). In this mode, writing “0” or “1” to the DR register applies this digital value to the I/O pin through the latch. Therefore, the previously saved value is restored when the DR register is read. Note: The interrupt function is disabled in this mode. Digital Alternate Function When an on-chip peripheral is configured to use a pin, the alternate function is automatically selected. This alternate function takes priority over standard I/O programming. When the signal is coming from an on-chip peripheral, the I/O pin is automatically configured in output mode (push-pull or open drain according to the peripheral). When the signal is going to an on-chip peripheral, the I/O pin has to be configured in input mode. In this case, the pin’s state is also digitally readable by addressing the DR register. Notes: 1. Input pull-up configuration can cause an unexpected value at the input of the alternate peripheral input. 2. When the on-chip peripheral uses a pin as input and output, this pin must be configured as an input (DDR = 0). Warning: The alternate function must not be activated as long as the pin is configured as an input with interrupt in order to avoid generating spurious interrupts. 25/132 ST7263B I/O PORTS (Cont’d) Analog Alternate Function When the pin is used as an ADC input the I/O must be configured as a floating input. The analog multiplexer (controlled by the ADC registers) switches the analog voltage present on the selected pin to the common analog rail which is connected to the ADC input. It is recommended not to change the voltage level or loading on any port pin while conversion is in progress. Furthermore it is recommended not to 26/132 have clocking pins located close to a selected analog pin. Warning: The analog input voltage level must be within the limits stated in the Absolute Maximum Ratings. 9.3 I/O Port Implementation The hardware implementation on each I/O port depends on the settings in the DDR register and specific feature of the I/O port such as ADC Input or true open drain. ST7263B I/O PORTS (Cont’d) 9.3.1 Port A Table 9. Port A0, A3, A4, A5, A6, A7 Description I/O PORT A Alternate Function Input* Output Signal Condition PA0 with pull-up push-pull MCO (Main Clock Output) PA3 with pull-up push-pull Timer EXTCLK PA4 with pull-up PA5 with pull-up PA6 with pull-up PA7 with pull-up MCO = 1 (MISCR) CC1 =1 CC0 = 1 (Timer CR2) Timer ICAP1 push-pull IT1 Schmitt triggered input IT1E = 1 (ITIFRE) Timer ICAP2 push-pull push-pull push-pull IT2 Schmitt triggered input IT2E = 1 (ITIFRE) Timer OCMP1 OC1E = 1 IT3 Schmitt triggered input IT3E = 1 (ITIFRE) Timer OCMP2 OC2E = 1 IT4 Schmitt triggered input IT4E = 1 (ITIFRE) *Reset State Figure 19. PA0, PA3, PA4, PA5, PA6, PA7 Configuration ALTERNATE ENABLE VDD ALTERNATE 1 OUTPUT 0 P-BUFFER VDD DR PULL-UP DATA BUS LATCH ALTERNATE ENABLE DDR LATCH PAD DDR SEL N-BUFFER DR SEL ALTERNATE INPUT 1 0 DIODES ALTERNATE ENABLE VSS CMOS SCHMITT TRIGGER 27/132 ST7263B I/O PORTS (Cont’d) Table 10. PA1, PA2 Description PORT A I/O Alternate Function Input* Output Signal Condition PA1 without pull-up Very High Current open drain SDA (I²C data) I²C enable PA2 without pull-up Very High Current open drain SCL (I²C clock) I²C enable *Reset State Figure 20. PA1, PA2 Configuration ALTERNATE ENABLE ALTERNATE 1 OUTPUT 0 DR LATCH DDR LATCH DATA BUS PAD DDR SEL N-BUFFER DR SEL 1 ALTERNATE ENABLE VSS 0 CMOS SCHMITT TRIGGER 28/132 ST7263B I/O PORTS (Cont’d) 9.3.2 Port B Table 11. Port B Description PORT B I/O Alternate Function Input* Output Signal Condition PB0 without pull-up push-pull Analog input (ADC) CH[2:0] = 000 (ADCCSR) PB1 without pull-up push-pull Analog input (ADC) CH[2:0] = 001 (ADCCSR) PB2 without pull-up push-pull Analog input (ADC) CH[2:0]= 010 (ADCCSR) PB3 without pull-up push-pull Analog input (ADC) CH[2:0]= 011 (ADCCSR) Analog input (ADC) CH[2:0]= 100 (ADCCSR) PB4 without pull-up push-pull IT5 Schmitt triggered input IT4E = 1 (ITIFRE) Analog input (ADC) CH[2:0]= 101 (ADCCSR) IT6 Schmitt triggered input IT5E = 1 (ITIFRE) Analog input (ADC) CH[2:0]= 110 (ADCCSR) IT7 Schmitt triggered input IT6E = 1 (ITIFRE) Analog input (ADC) CH[2:0]= 111 (ADCCSR) IT8 Schmitt triggered input IT7E = 1 (ITIFRE) PB5 without pull-up PB6 push-pull without pull-up PB7 push-pull without pull-up push-pull *Reset State Figure 21. Port B Configuration ALTERNATE ENABLE ALTERNATE OUTPUT V DD 1 0 P-BUFFER DR LATCH VDD ALTERNATE ENABLE DDR PAD LATCH DATA BUS COMMON ANALOG RAIL ANALOG ENABLE (ADC) DDR SEL ANALOG SWITCH DIODES N-BUFFER DR SEL 1 ALTERNATE ENABLE 0 DIGITAL ENABLE V SS ALTERNATE INPUT 29/132 ST7263B I/O PORTS (Cont’d) 9.3.3 Port C Table 12. Port C Description I/O Alternate Function PORT C Input* Output Signal Condition PC0 with pull-up push-pull RDI (SCI input) PC1 with pull-up push-pull TDO (SCI output) SCI enable PC2 with pull-up push-pull USBOE (USB output enable) USBOE =1 (MISCR) *Reset State Figure 22. Port C Configuration ALTERNATE ENABLE VDD ALTERNATE 1 OUTPUT 0 P-BUFFER VDD DR PULL-UP LATCH ALTERNATE ENABLE DATA BUS DDR PAD LATCH DDR SEL N-BUFFER DR SEL 1 0 DIODES ALTERNATE ENABLE VSS ALTERNATE INPUT CMOS SCHMITT TRIGGER 30/132 ST7263B I/O PORTS (Cont’d) 9.3.4 Register Description DATA REGISTERS (PxDR) Port A Data Register (PADR): 0000h Port B Data Register (PBDR): 0002h Port C Data Register (PCDR): 0004h Read /Write Reset Value Port A: 0000 0000 (00h) Reset Value Port B: 0000 0000 (00h) Reset Value Port C: 1111 x000 (FXh) Note: For Port C, unused bits (7-3) are not accessible. DATA DIRECTION REGISTER (PxDDR) Port A Data Direction Register (PADDR): 0001h Port B Data Direction Register (PBDDR): 0003h Port C Data Direction Register (PCDDR): 0005h Read/Write Reset Value Port A: 0000 0000 (00h) Reset Value Port B: 0000 0000 (00h) Reset Value Port C: 1111 x000 (FXh) Note: For Port C, unused bits (7-3) are not accessible 7 7 0 0 DD7 D7 D6 D5 D4 D3 D2 D1 DD6 DD5 DD4 DD3 DD2 DD1 DD0 D0 Bit 7:0 = D[7:0] Data Register 8 bits. The DR register has a specific behaviour according to the selected input/output configuration. Writing the DR register is always taken into account even if the pin is configured as an input. Reading the DR register returns either the DR register latch content (pin configured as output) or the digital value applied to the I/O pin (pin configured as input). Bit 7:0 = DD[7:0] Data Direction Register 8 bits. The DDR register gives the input/output direction configuration of the pins. Each bit is set and cleared by software. 0: Input mode 1: Output mode Table 13. I/O Ports Register Map Address (Hex.) 00 01 02 03 04 05 Register Label 7 PADR PADDR PBDR PBDDR PCDR PCDDR MSB MSB MSB MSB MSB MSB 6 5 4 3 2 1 0 LSB LSB LSB LSB LSB LSB 31/132 ST7263B 10 MISCELLANEOUS REGISTER Address: 0009h — Read/Write Reset Value: 0000 0000 (00h) 7 - 0 - - - - SMS USBOE MCO Bit 7:3 = Reserved Bit 2 = SMS Slow Mode Select. This bit is set by software and only cleared by hardware after a reset. If this bit is set, it enables the use of an internal divide-by-2 clock divider (refer to Figure 15 on page 19). The SMS bit has no effect on the USB frequency. 0: Divide-by-2 disabled and CPU clock frequency is standard 1: Divide-by-2 enabled and CPU clock frequency is halved. 32/132 Bit 1 = USBOE USB enable. If this bit is set, the port PC2 outputs the USB output enable signal (at “1” when the ST7 USB is transmitting data). Unused bits 7-4 are set. Bit 0 = MCO Main Clock Out selection This bit enables the MCO alternate function on the PA0 I/O port. It is set and cleared by software. 0: MCO alternate function disabled (I/O pin free for general-purpose I/O) 1: MCO alternate function enabled (fCPU on I/O port) ST7263B 11 ON-CHIP PERIPHERALS 11.1 WATCHDOG TIMER (WDG) 11.1.1 Introduction The Watchdog timer is used to detect the occurrence of a software fault, usually generated by external interference or by unforeseen logical conditions, which causes the application program to abandon its normal sequence. The Watchdog circuit generates an MCU reset on expiry of a programmed time period, unless the program refreshes the counter’s contents before the T6 bit becomes cleared. 11.1.2 Main Features ■ Programmable timer (64 increments of 49,152 CPU cycles) ■ Programmable reset ■ Reset (if watchdog activated) when the T6 bit reaches zero ■ Optional reset on HALT instruction (configurable by option byte) ■ Hardware Watchdog selectable by option byte. 11.1.3 Functional Description The counter value stored in the CR register (bits T6:T0), is decremented every 49,152 machine cy- cles, and the length of the timeout period can be programmed by the user in 64 increments. If the watchdog is activated (the WDGA bit is set) and when the 7-bit timer (bits T6:T0) rolls over from 40h to 3Fh (T6 becomes cleared), it initiates a reset cycle pulling low the reset pin for typically 500ns. The application program must write in the CR register at regular intervals during normal operation to prevent an MCU reset. The value to be stored in the CR register must be between FFh and C0h (see Table 14, ". Watchdog Timing (fCPU = 8 MHz)"): – The WDGA bit is set (watchdog enabled) – The T6 bit is set to prevent generating an immediate reset – The T5:T0 bits contain the number of increments which represents the time delay before the watchdog produces a reset. Figure 23. Watchdog Block Diagram RESET WATCHDOG CONTROL REGISTER (CR) WDGA T6 T5 T4 T3 T2 T1 T0 7-BIT DOWNCOUNTER fCPU CLOCK DIVIDER ÷49152 33/132 ST7263B WATCHDOG TIMER (Cont’d) Table 14. Watchdog Timing (fCPU = 8 MHz) CR Register initial value WDG timeout period (ms) Max FFh 393.216 Min C0h 6.144 Notes: Following a reset, the watchdog is disabled. Once activated it cannot be disabled, except by a reset. The T6 bit can be used to generate a software reset (the WDGA bit is set and the T6 bit is cleared). 11.1.4 Software Watchdog Option If Software Watchdog is selected by option byte, the watchdog is disabled following a reset. Once activated it cannot be disabled, except by a reset. The T6 bit can be used to generate a software reset (the WDGA bit is set and the T6 bit is cleared). 11.1.5 Hardware Watchdog Option If Hardware Watchdog is selected by option byte, the watchdog is always active and the WDGA bit in the CR is not used. 11.1.6 Low Power Modes WAIT Instruction No effect on Watchdog. HALT Instruction If the Watchdog reset on HALT option is selected by option byte, a HALT instruction causes an immediate reset generation if the Watchdog is activated (WDGA bit is set). 11.1.6.1 Using Halt Mode with the WDG (option) If the Watchdog reset on HALT option is not selected by option byte, the Halt mode can be used when the watchdog is enabled. 34/132 In this case, the HALT instruction stops the oscillator. When the oscillator is stopped, the WDG stops counting and is no longer able to generate a reset until the microcontroller receives an external interrupt or a reset. If an external interrupt is received, the WDG restarts counting after 4096 CPU clocks. If a reset is generated, the WDG is disabled (reset state). Recommendations – Make sure that an external event is available to wake up the microcontroller from Halt mode. – Before executing the HALT instruction, refresh the WDG counter, to avoid an unexpected WDG reset immediately after waking up the microcontroller. – When using an external interrupt to wake up the microcontroller, reinitialize the corresponding I/O as “Input Pull-up with Interrupt” before executing the HALT instruction. The main reason for this is that the I/O may be wrongly configured due to external interference or by an unforeseen logical condition. – For the same reason, reinitialize the level sensitiveness of each external interrupt as a precautionary measure. – The opcode for the HALT instruction is 0x8E. To avoid an unexpected HALT instruction due to a program counter failure, it is advised to clear all occurrences of the data value 0x8E from memory. For example, avoid defining a constant in ROM with the value 0x8E. – As the HALT instruction clears the I bit in the CC register to allow interrupts, the user may choose to clear all pending interrupt bits before executing the HALT instruction. This avoids entering other peripheral interrupt routines after executing the external interrupt routine corresponding to the wake-up event (reset or external interrupt). 11.1.7 Interrupts None. ST7263B WATCHDOG TIMER (Cont’d) 11.1.8 Register Description CONTROL REGISTER (CR) Read /Write Reset Value: 0111 1111 (7Fh) hardware after a reset. When WDGA = 1, the watchdog can generate a reset. 0: Watchdog disabled 1: Watchdog enabled 7 WDGA Bit 6:0 = T[6:0] 7-bit timer (MSB to LSB). These bits contain the decremented value. A reset is produced when it rolls over from 40h to 3Fh (T6 becomes cleared). 0 T6 T5 T4 T3 T2 T1 T0 Bit 7 = WDGA Activation bit. This bit is set by software and only cleared by Table 15. Watchdog Timer Register Map and Reset Values Address (Hex.) 0Ch Register Label 7 6 5 4 3 2 1 0 WDGCR WDGA T6 T5 T4 T3 T2 T1 T0 Reset Value 0 1 1 1 1 1 1 1 35/132 ST7263B 11.2 16-BIT TIMER 11.2.1 Introduction The timer consists of a 16-bit free-running counter driven by a programmable prescaler. It may be used for a variety of purposes, including pulse length measurement of up to two input signals ( input capture) or generation of up to two output waveforms (output compare and PWM). Pulse lengths and waveform periods can be modulated from a few microseconds to several milliseconds using the timer prescaler and the CPU clock prescaler. Some ST7 devices have two on-chip 16-bit timers. They are completely independent, and do not share any resources. They are synchronized after a MCU reset as long as the timer clock frequencies are not modified. This description covers one or two 16-bit timers. In ST7 devices with two timers, register names are prefixed with TA (Timer A) or TB (Timer B). 11.2.2 Main Features ■ Programmable prescaler: fCPU divided by 2, 4 or 8. ■ Overflow status flag and maskable interrupt ■ External clock input (must be at least 4 times slower than the CPU clock speed) with the choice of active edge ■ 1 or 2 Output Compare functions each with: – 2 dedicated 16-bit registers – 2 dedicated programmable signals – 2 dedicated status flags – 1 dedicated maskable interrupt ■ 1 or 2 Input Capture functions each with: – 2 dedicated 16-bit registers – 2 dedicated active edge selection signals – 2 dedicated status flags – 1 dedicated maskable interrupt ■ Pulse width modulation mode (PWM) ■ One pulse mode ■ Reduced Power Mode ■ 5 alternate functions on I/O ports (ICAP1, ICAP2, OCMP1, OCMP2, EXTCLK)* The Block Diagram is shown in Figure 24. *Note: Some timer pins may not available (not bonded) in some ST7 devices. Refer to the device pin out description. 36/132 When reading an input signal on a non-bonded pin, the value will always be ‘1’. 11.2.3 Functional Description 11.2.3.1 Counter The main block of the Programmable Timer is a 16-bit free running upcounter and its associated 16-bit registers. The 16-bit registers are made up of two 8-bit registers called high & low. Counter Register (CR): – Counter High Register (CHR) is the most significant byte (MS Byte). – Counter Low Register (CLR) is the least significant byte (LS Byte). Alternate Counter Register (ACR) – Alternate Counter High Register (ACHR) is the most significant byte (MS Byte). – Alternate Counter Low Register (ACLR) is the least significant byte (LS Byte). These two read-only 16-bit registers contain the same value but with the difference that reading the ACLR register does not clear the TOF bit (Timer overflow flag), located in the Status register, (SR), (see note at the end of paragraph titled 16-bit read sequence). Writing in the CLR register or ACLR register resets the free running counter to the FFFCh value. Both counters have a reset value of FFFCh (this is the only value which is reloaded in the 16-bit timer). The reset value of both counters is also FFFCh in One Pulse mode and PWM mode. The timer clock depends on the clock control bits of the CR2 register, as illustrated in Table 16, "Clock Control Bits". The value in the counter register repeats every 131072, 262144 or 524288 CPU clock cycles depending on the CC[1:0] bits. The timer frequency can be fCPU/2, fCPU/4, fCPU/8 or an external frequency. ST7263B 16-BIT TIMER (Cont’d) Figure 24. Timer Block Diagram ST7 INTERNAL BUS fCPU MCU-PERIPHERAL INTERFACE 8 low 8 8 8 low 8 high 8 low 8 high EXEDG 8 low high 8 high 8-bit buffer low 8 high 16 1/2 1/4 1/8 OUTPUT COMPARE REGISTER 2 OUTPUT COMPARE REGISTER 1 COUNTER REGISTER ALTERNATE COUNTER REGISTER EXTCLK pin INPUT CAPTURE REGISTER 1 INPUT CAPTURE REGISTER 2 16 16 16 CC[1:0] TIMER INTERNAL BUS 16 16 OVERFLOW DETECT CIRCUIT OUTPUT COMPARE CIRCUIT 6 ICF1 OCF1 TOF ICF2 OCF2 TIMD 0 EDGE DETECT CIRCUIT1 ICAP1 pin EDGE DETECT CIRCUIT2 ICAP2 pin LATCH1 OCMP1 pin LATCH2 OCMP2 pin 0 (Control/Status Register) CSR ICIE OCIE TOIE FOLV2 FOLV1OLVL2 IEDG1 OLVL1 (Control Register 1) CR1 OC1E OC2E OPM PWM CC1 CC0 IEDG2 EXEDG (Control Register 2) CR2 (See note) TIMER INTERRUPT Note: If IC, OC and TO interrupt requests have separate vectors then the last OR is not present (See device Interrupt Vector Table) 37/132 ST7263B 16-BIT TIMER (Cont’d) 16-bit read sequence: (from either the Counter Register or the Alternate Counter Register). Beginning of the sequence At t0 Read MS Byte LS Byte is buffered Other instructions Read At t0 +∆t LS Byte Returns the buffered LS Byte value at t0 Sequence completed The user must read the MS Byte first, then the LS Byte value is buffered automatically. This buffered value remains unchanged until the 16-bit read sequence is completed, even if the user reads the MS Byte several times. After a complete reading sequence, if only the CLR register or ACLR register are read, they return the LS Byte of the count value at the time of the read. Whatever the timer mode used (input capture, output compare, one pulse mode or PWM mode) an overflow occurs when the counter rolls over from FFFFh to 0000h then: – The TOF bit of the SR register is set. – A timer interrupt is generated if: – TOIE bit of the CR1 register is set and – I bit of the CC register is cleared. If one of these conditions is false, the interrupt remains pending to be issued as soon as they are both true. 38/132 Clearing the overflow interrupt request is done in two steps: 1. Reading the SR register while the TOF bit is set. 2. An access (read or write) to the CLR register. Notes: The TOF bit is not cleared by accesses to ACLR register. The advantage of accessing the ACLR register rather than the CLR register is that it allows simultaneous use of the overflow function and reading the free running counter at random times (for example, to measure elapsed time) without the risk of clearing the TOF bit erroneously. The timer is not affected by WAIT mode. In HALT mode, the counter stops counting until the mode is exited. Counting then resumes from the previous count (MCU awakened by an interrupt) or from the reset count (MCU awakened by a Reset). 11.2.3.2 External Clock The external clock (where available) is selected if CC0=1 and CC1=1 in the CR2 register. The status of the EXEDG bit in the CR2 register determines the type of level transition on the external clock pin EXTCLK that will trigger the free running counter. The counter is synchronized with the falling edge of the internal CPU clock. A minimum of four falling edges of the CPU clock must occur between two consecutive active edges of the external clock; thus the external clock frequency must be less than a quarter of the CPU clock frequency. ST7263B 16-BIT TIMER (Cont’d) Figure 25. Counter Timing Diagram, internal clock divided by 2 CPU CLOCK INTERNAL RESET TIMER CLOCK FFFD FFFE FFFF 0000 COUNTER REGISTER 0001 0002 0003 TIMER OVERFLOW FLAG (TOF) Figure 26. Counter Timing Diagram, internal clock divided by 4 CPU CLOCK INTERNAL RESET TIMER CLOCK COUNTER REGISTER FFFC FFFD 0000 0001 TIMER OVERFLOW FLAG (TOF) Figure 27. Counter Timing Diagram, internal clock divided by 8 CPU CLOCK INTERNAL RESET TIMER CLOCK COUNTER REGISTER FFFC FFFD 0000 TIMER OVERFLOW FLAG (TOF) Note: The MCU is in reset state when the internal reset signal is high, when it is low the MCU is running. 39/132 ST7263B 16-BIT TIMER (Cont’d) 11.2.3.3 Input Capture In this section, the index, i, may be 1 or 2 because there are 2 input capture functions in the 16-bit timer. The two 16-bit input capture registers (IC1R and IC2R) are used to latch the value of the free running counter after a transition is detected on the ICAP i pin (see figure 5). ICiR MS Byte ICiHR LS Byte ICiLR IC iR register is a read-only register. The active transition is software programmable through the IEDGi bit of Control Registers (CRi). Timing resolution is one count of the free running counter: (fCPU/CC[1:0]). Procedure: To use the input capture function select the following in the CR2 register: – Select the timer clock (CC[1:0]) (see Table 16, "Clock Control Bits"). – Select the edge of the active transition on the ICAP2 pin with the IEDG2 bit (the ICAP2 pin must be configured as floating input or input with pull-up without interrupt if this configuration is available). And select the following in the CR1 register: – Set the ICIE bit to generate an interrupt after an input capture coming from either the ICAP1 pin or the ICAP2 pin – Select the edge of the active transition on the ICAP1 pin with the IEDG1 bit (the ICAP1pin must be configured as floating input or input with pullup without interrupt if this configuration is available). 40/132 When an input capture occurs: – ICFi bit is set. – The ICiR register contains the value of the free running counter on the active transition on the ICAPi pin (see Figure 29). – A timer interrupt is generated if the ICIE bit is set and the I bit is cleared in the CC register. Otherwise, the interrupt remains pending until both conditions become true. Clearing the Input Capture interrupt request (i.e. clearing the ICFi bit) is done in two steps: 1. Reading the SR register while the ICFi bit is set. 2. An access (read or write) to the ICiLR register. Notes: 1. After reading the ICiHR register, transfer of input capture data is inhibited and ICFi will never be set until the ICiLR register is also read. 2. The ICiR register contains the free running counter value which corresponds to the most recent input capture. 3. The 2 input capture functions can be used together even if the timer also uses the 2 output compare functions. 4. In One pulse Mode and PWM mode only Input Capture 2 can be used. 5. The alternate inputs (ICAP1 & ICAP2) are always directly connected to the timer. So any transitions on these pins activates the input capture function. Moreover if one of the ICAPi pins is configured as an input and the second one as an output, an interrupt can be generated if the user toggles the output pin and if the ICIE bit is set. This can be avoided if the input capture function i is disabled by reading the IC iHR (see note 1). 6. The TOF bit can be used with interrupt generation in order to measure events that go beyond the timer range (FFFFh). ST7263B 16-BIT TIMER (Cont’d) Figure 28. Input Capture Block Diagram ICAP1 pin ICAP2 pin (Control Register 1) CR1 EDGE DETECT CIRCUIT2 EDGE DETECT CIRCUIT1 ICIE IEDG1 (Status Register) SR IC1R Register IC2R Register ICF1 ICF2 0 0 0 (Control Register 2) CR2 16-BIT 16-BIT FREE RUNNING COUNTER CC1 CC0 IEDG2 Figure 29. Input Capture Timing Diagram TIMER CLOCK COUNTER REGISTER FF01 FF02 FF03 ICAPi PIN ICAPi FLAG ICAPi REGISTER FF03 Note: The rising edge is the active edge. 41/132 ST7263B 16-BIT TIMER (Cont’d) 11.2.3.4 Output Compare In this section, the index, i, may be 1 or 2 because there are 2 output compare functions in the 16-bit timer. This function can be used to control an output waveform or indicate when a period of time has elapsed. When a match is found between the Output Compare register and the free running counter, the output compare function: – Assigns pins with a programmable value if the OCiE bit is set – Sets a flag in the status register – Generates an interrupt if enabled Two 16-bit registers Output Compare Register 1 (OC1R) and Output Compare Register 2 (OC2R) contain the value to be compared to the counter register each timer clock cycle. OCiR MS Byte OCiHR LS Byte OCiLR These registers are readable and writable and are not affected by the timer hardware. A reset event changes the OCiR value to 8000h. Timing resolution is one count of the free running counter: (fCPU/CC[1:0]). Procedure: To use the output compare function, select the following in the CR2 register: – Set the OCiE bit if an output is needed then the OCMPi pin is dedicated to the output compare i signal. – Select the timer clock (CC[1:0]) (see Table 16, "Clock Control Bits"). And select the following in the CR1 register: – Select the OLVLi bit to applied to the OCMP i pins after the match occurs. – Set the OCIE bit to generate an interrupt if it is needed. When a match is found between OCRi register and CR register: – OCFi bit is set. 42/132 – The OCMP i pin takes OLVLi bit value (OCMPi pin latch is forced low during reset). – A timer interrupt is generated if the OCIE bit is set in the CR1 register and the I bit is cleared in the CC register (CC). The OCiR register value required for a specific timing application can be calculated using the following formula: ∆ OCiR = ∆t * fCPU PRESC Where: ∆t = Output compare period (in seconds) fCPU = CPU clock frequency (in hertz) PRESC = Timer prescaler factor (2, 4 or 8 depending on CC[1:0] bits, see Table 16, "Clock Control Bits") If the timer clock is an external clock, the formula is: ∆ OCiR = ∆t * fEXT Where: ∆t = Output compare period (in seconds) fEXT = External timer clock frequency (in hertz) Clearing the output compare interrupt request (i.e. clearing the OCFi bit) is done by: 1. Reading the SR register while the OCFi bit is set. 2. An access (read or write) to the OCiLR register. The following procedure is recommended to prevent the OCFi bit from being set between the time it is read and the write to the OCiR register: – Write to the OCiHR register (further compares are inhibited). – Read the SR register (first step of the clearance of the OCFi bit, which may be already set). – Write to the OCiLR register (enables the output compare function and clears the OCFi bit). ST7263B 16-BIT TIMER (Cont’d) Notes: 1. After a processor write cycle to the OCiHR register, the output compare function is inhibited until the OCiLR register is also written. 2. If the OCiE bit is not set, the OCMPi pin is a general I/O port and the OLVLi bit will not appear when a match is found but an interrupt could be generated if the OCIE bit is set. 3. When the timer clock is fCPU/2, OCFi and OCMPi are set while the counter value equals the OCiR register value (see Figure 31 on page 44). This behaviour is the same in OPM or PWM mode. When the timer clock is fCPU/4, fCPU/8 or in external clock mode, OCFi and OCMPi are set while the counter value equals the OCiR register value plus 1 (see Figure 32 on page 44). 4. The output compare functions can be used both for generating external events on the OCMPi pins even if the input capture mode is also used. 5. The value in the 16-bit OCiR register and the OLVi bit should be changed after each successful comparison in order to control an output waveform or establish a new elapsed timeout. Forced Compare Output capability When the FOLVi bit is set by software, the OLVLi bit is copied to the OCMPi pin. The OLVi bit has to be toggled in order to toggle the OCMPi pin when it is enabled (OCiE bit=1). The OCFi bit is then not set by hardware, and thus no interrupt request is generated. The FOLVLi bits have no effect in both one pulse mode and PWM mode. Figure 30. Output Compare Block Diagram 16 BIT FREE RUNNING COUNTER OC1E OC2E CC1 CC0 (Control Register 2) CR2 16-bit (Control Register 1) CR1 OUTPUT COMPARE CIRCUIT 16-bit OCIE FOLV2 FOLV1 OLVL2 OLVL1 16-bit Latch 1 Latch 2 OC1R Register OCF1 OCF2 0 0 OCMP1 Pin OCMP2 Pin 0 OC2R Register (Status Register) SR 43/132 ST7263B 16-BIT TIMER (Cont’d) Figure 31. Output Compare Timing Diagram, fTIMER =fCPU/2 INTERNAL CPU CLOCK TIMER CLOCK COUNTER REGISTER 2ECF 2ED0 2ED1 2ED2 2ED3 2ED4 OUTPUT COMPARE REGISTER i (OCRi) 2ED3 OUTPUT COMPARE FLAG i (OCFi) OCMPi PIN (OLVLi=1) Figure 32. Output Compare Timing Diagram, fTIMER =fCPU/4 INTERNAL CPU CLOCK TIMER CLOCK COUNTER REGISTER OUTPUT COMPARE REGISTER i (OCRi) COMPARE REGISTER i LATCH OUTPUT COMPARE FLAG i (OCFi) OCMPi PIN (OLVLi=1) 44/132 2ECF 2ED0 2ED1 2ED2 2ED3 2ED4 2ED3 ST7263B 16-BIT TIMER (Cont’d) 11.2.3.5 One Pulse Mode One Pulse mode enables the generation of a pulse when an external event occurs. This mode is selected via the OPM bit in the CR2 register. The one pulse mode uses the Input Capture1 function and the Output Compare1 function. Procedure: To use one pulse mode: 1. Load the OC1R register with the value corresponding to the length of the pulse (see the formula in the opposite column). 2. Select the following in the CR1 register: – Using the OLVL1 bit, select the level to be applied to the OCMP1 pin after the pulse. – Using the OLVL2 bit, select the level to be applied to the OCMP1 pin during the pulse. – Select the edge of the active transition on the ICAP1 pin with the IEDG1 bit (the ICAP1 pin must be configured as floating input). 3. Select the following in the CR2 register: – Set the OC1E bit, the OCMP1 pin is then dedicated to the Output Compare 1 function. – Set the OPM bit. – Select the timer clock CC[1:0] (see Table 16, "Clock Control Bits"). One pulse mode cycle When event occurs on ICAP1 ICR1 = Counter OCMP1 = OLVL2 Counter is reset to FFFCh ICF1 bit is set When Counter = OC1R OCMP1 = OLVL1 Then, on a valid event on the ICAP1 pin, the counter is initialized to FFFCh and OLVL2 bit is loaded on the OCMP1 pin, the ICF1 bit is set and the value FFFDh is loaded in the IC1R register. Because the ICF1 bit is set when an active edge occurs, an interrupt can be generated if the ICIE bit is set. Clearing the Input Capture interrupt request (i.e. clearing the ICFi bit) is done in two steps: 1. Reading the SR register while the ICFi bit is set. 2. An access (read or write) to the ICiLR register. The OC1R register value required for a specific timing application can be calculated using the following formula: OCiR Value = t * fCPU -5 PRESC Where: t = Pulse period (in seconds) fCPU = CPU clock frequency (in hertz) PRESC = Timer prescaler factor (2, 4 or 8 depending on the CC[1:0] bits, see Table 16, "Clock Control Bits") If the timer clock is an external clock the formula is: OCiR = t * fEXT -5 Where: t = Pulse period (in seconds) fEXT = External timer clock frequency (in hertz) When the value of the counter is equal to the value of the contents of the OC1R register, the OLVL1 bit is output on the OCMP1 pin, (See Figure 33). Notes: 1. The OCF1 bit cannot be set by hardware in one pulse mode but the OCF2 bit can generate an Output Compare interrupt. 2. When the Pulse Width Modulation (PWM) and One Pulse Mode (OPM) bits are both set, the PWM mode is the only active one. 3. If OLVL1=OLVL2 a continuous signal will be seen on the OCMP1 pin. 4. The ICAP1 pin can not be used to perform input capture. The ICAP2 pin can be used to perform input capture (ICF2 can be set and IC2R can be loaded) but the user must take care that the counter is reset each time a valid edge occurs on the ICAP1 pin and ICF1 can also generates interrupt if ICIE is set. 5. When one pulse mode is used OC1R is dedicated to this mode. Nevertheless OC2R and OCF2 can be used to indicate a period of time has been elapsed but cannot generate an output waveform because the level OLVL2 is dedicated to the one pulse mode. 45/132 ST7263B 16-BIT TIMER (Cont’d) Figure 33. One Pulse Mode Timing Example COUNTER 2ED3 01F8 IC1R 01F8 FFFC FFFD FFFE 2ED0 2ED1 2ED2 FFFC FFFD 2ED3 ICAP1 OLVL2 OCMP1 OLVL1 OLVL2 compare1 Note: IEDG1=1, OC1R=2ED0h, OLVL1=0, OLVL2=1 Figure 34. Pulse Width Modulation Mode Timing Example with 2 Output Compare Functions COUNTER 34E2 FFFC FFFD FFFE 2ED0 2ED1 2ED2 OLVL2 OCMP1 compare2 OLVL1 compare1 34E2 FFFC OLVL2 compare2 Note: OC1R=2ED0h, OC2R=34E2, OLVL1=0, OLVL2= 1 Note: On timers with only 1 Output Compare register, a fixed frequency PWM signal can be generated using the output compare and the counter overflow to define the pulse length. 46/132 ST7263B 16-BIT TIMER (Cont’d) 11.2.3.6 Pulse Width Modulation Mode Pulse Width Modulation (PWM) mode enables the generation of a signal with a frequency and pulse length determined by the value of the OC1R and OC2R registers. Pulse Width Modulation mode uses the complete Output Compare 1 function plus the OC2R register, and so this functionality can not be used when PWM mode is activated. In PWM mode, double buffering is implemented on the output compare registers. Any new values written in the OC1R and OC2R registers are taken into account only at the end of the PWM period (OC2) to avoid spikes on the PWM output pin (OCMP1). Procedure To use pulse width modulation mode: 1. Load the OC2R register with the value corresponding to the period of the signal using the formula in the opposite column. 2. Load the OC1R register with the value corresponding to the period of the pulse if (OLVL1=0 and OLVL2=1) using the formula in the opposite column. 3. Select the following in the CR1 register: – Using the OLVL1 bit, select the level to be applied to the OCMP1 pin after a successful comparison with the OC1R register. – Using the OLVL2 bit, select the level to be applied to the OCMP1 pin after a successful comparison with the OC2R register. 4. Select the following in the CR2 register: – Set OC1E bit: the OCMP1 pin is then dedicated to the output compare 1 function. – Set the PWM bit. – Select the timer clock (CC[1:0]) (see Table 16, "Clock Control Bits"). Pulse Width Modulation cycle When Counter = OC1R When Counter = OC2R OCMP1 = OLVL1 OCMP1 = OLVL2 Counter is reset to FFFCh If OLVL1=1 and OLVL2=0 the length of the positive pulse is the difference between the OC2R and OC1R registers. If OLVL1=OLVL2 a continuous signal will be seen on the OCMP1 pin. The OCiR register value required for a specific timing application can be calculated using the following formula: OCiR Value = t * fCPU -5 PRESC Where: t = Signal or pulse period (in seconds) fCPU = CPU clock frequency (in hertz) PRESC = Timer prescaler factor (2, 4 or 8 depending on CC[1:0] bits, see Table 16, "Clock Control Bits") If the timer clock is an external clock the formula is: OCiR = t * fEXT -5 Where: t = Signal or pulse period (in seconds) fEXT = External timer clock frequency (in hertz) The Output Compare 2 event causes the counter to be initialized to FFFCh (See Figure 34) Notes: 1. After a write instruction to the OCiHR register, the output compare function is inhibited until the OCiLR register is also written. 2. The OCF1 and OCF2 bits cannot be set by hardware in PWM mode therefore the Output Compare interrupt is inhibited. 3. The ICF1 bit is set by hardware when the counter reaches the OC2R value and can produce a timer interrupt if the ICIE bit is set and the I bit is cleared. 4. In PWM mode the ICAP1 pin can not be used to perform input capture because it is disconnected to the timer. The ICAP2 pin can be used to perform input capture (ICF2 can be set and IC2R can be loaded) but the user must take care that the counter is reset each period and ICF1 can also generates interrupt if ICIE is set. 5. When the Pulse Width Modulation (PWM) and One Pulse Mode (OPM) bits are both set, the PWM mode is the only active one. ICF1 bit is set 47/132 ST7263B 16-BIT TIMER (Cont’d) 11.2.4 Low Power Modes Mode WAIT HALT Description No effect on 16-bit Timer. Timer interrupts cause the device to exit from WAIT mode. 16-bit Timer registers are frozen. In HALT mode, the counter stops counting until Halt mode is exited. Counting resumes from the previous count when the MCU is woken up by an interrupt with “exit from HALT mode” capability or from the counter reset value when the MCU is woken up by a RESET. If an input capture event occurs on the ICAPi pin, the input capture detection circuitry is armed. Consequently, when the MCU is woken up by an interrupt with “exit from HALT mode” capability, the ICFi bit is set, and the counter value present when exiting from HALT mode is captured into the ICiR register. 11.2.5 Interrupts Event Flag Interrupt Event Input Capture 1 event/Counter reset in PWM mode Input Capture 2 event Output Compare 1 event (not available in PWM mode) Output Compare 2 event (not available in PWM mode) Timer Overflow event ICF1 ICF2 OCF1 OCF2 TOF Enable Control Bit ICIE OCIE TOIE Exit from Wait Yes Yes Yes Yes Yes Exit from Halt No No No No No Note: The 16-bit Timer interrupt events are connected to the same interrupt vector (see Interrupts chapter). These events generate an interrupt if the corresponding Enable Control Bit is set and the interrupt mask in the CC register is reset (RIM instruction). 11.2.6 Summary of Timer modes MODES Input Capture (1 and/or 2) Output Compare (1 and/or 2) One Pulse Mode PWM Mode Input Capture 1 Yes Yes No No TIMER RESOURCES Input Capture 2 Output Compare 1 Output Compare 2 Yes Yes Yes Yes Yes Yes 1) No Partially 2) Not Recommended 3) Not Recommended No No 1) See note 4 in Section 11.2.3.5, "One Pulse Mode" 2) See note 5 in Section 11.2.3.5, "One Pulse Mode" 3) See note 4 in Section 11.2.3.6, "Pulse Width Modulation Mode" 48/132 ST7263B 16-BIT TIMER (Cont’d) 11.2.7 Register Description Each Timer is associated with three control and status registers, and with six pairs of data registers (16-bit values) relating to the two input captures, the two output compares, the counter and the alternate counter. CONTROL REGISTER 1 (CR1) Read/Write Reset Value: 0000 0000 (00h) 7 0 Bit 4 = FOLV2 Forced Output Compare 2. This bit is set and cleared by software. 0: No effect on the OCMP2 pin. 1: Forces the OLVL2 bit to be copied to the OCMP2 pin, if the OC2E bit is set and even if there is no successful comparison. Bit 3 = FOLV1 Forced Output Compare 1. This bit is set and cleared by software. 0: No effect on the OCMP1 pin. 1: Forces OLVL1 to be copied to the OCMP1 pin, if the OC1E bit is set and even if there is no successful comparison. ICIE OCIE TOIE FOLV2 FOLV1 OLVL2 IEDG1 OLVL1 Bit 7 = ICIE Input Capture Interrupt Enable. 0: Interrupt is inhibited. 1: A timer interrupt is generated whenever the ICF1 or ICF2 bit of the SR register is set. Bit 6 = OCIE Output Compare Interrupt Enable. 0: Interrupt is inhibited. 1: A timer interrupt is generated whenever the OCF1 or OCF2 bit of the SR register is set. Bit 5 = TOIE Timer Overflow Interrupt Enable. 0: Interrupt is inhibited. 1: A timer interrupt is enabled whenever the TOF bit of the SR register is set. Bit 2 = OLVL2 Output Level 2. This bit is copied to the OCMP2 pin whenever a successful comparison occurs with the OC2R register and OCxE is set in the CR2 register. This value is copied to the OCMP1 pin in One Pulse Mode and Pulse Width Modulation mode. Bit 1 = IEDG1 Input Edge 1. This bit determines which type of level transition on the ICAP1 pin will trigger the capture. 0: A falling edge triggers the capture. 1: A rising edge triggers the capture. Bit 0 = OLVL1 Output Level 1. The OLVL1 bit is copied to the OCMP1 pin whenever a successful comparison occurs with the OC1R register and the OC1E bit is set in the CR2 register. 49/132 ST7263B 16-BIT TIMER (Cont’d) CONTROL REGISTER 2 (CR2) Read/Write Reset Value: 0000 0000 (00h) 7 0 OC1E OC2E OPM PWM CC1 CC0 IEDG2 EXEDG Bit 7 = OC1E Output Compare 1 Pin Enable. This bit is used only to output the signal from the timer on the OCMP1 pin (OLV1 in Output Compare mode, both OLV1 and OLV2 in PWM and one-pulse mode). Whatever the value of the OC1E bit, the Output Compare 1 function of the timer remains active. 0: OCMP1 pin alternate function disabled (I/O pin free for general-purpose I/O). 1: OCMP1 pin alternate function enabled. Bit 6 = OC2E Output Compare 2 Pin Enable. This bit is used only to output the signal from the timer on the OCMP2 pin (OLV2 in Output Compare mode). Whatever the value of the OC2E bit, the Output Compare 2 function of the timer remains active. 0: OCMP2 pin alternate function disabled (I/O pin free for general-purpose I/O). 1: OCMP2 pin alternate function enabled. Bit 5 = OPM One Pulse Mode. 0: One Pulse Mode is not active. 1: One Pulse Mode is active, the ICAP1 pin can be used to trigger one pulse on the OCMP1 pin; the active transition is given by the IEDG1 bit. The length of the generated pulse depends on the contents of the OC1R register. 50/132 Bit 4 = PWM Pulse Width Modulation. 0: PWM mode is not active. 1: PWM mode is active, the OCMP1 pin outputs a programmable cyclic signal; the length of the pulse depends on the value of OC1R register; the period depends on the value of OC2R register. Bit 3, 2 = CC[1:0] Clock Control. The timer clock mode depends on these bits: Table 16. Clock Control Bits Timer Clock fCPU / 4 fCPU / 2 fCPU / 8 External Clock (where available) CC1 0 0 1 CC0 0 1 0 1 1 Note: If the external clock pin is not available, programming the external clock configuration stops the counter. Bit 1 = IEDG2 Input Edge 2. This bit determines which type of level transition on the ICAP2 pin will trigger the capture. 0: A falling edge triggers the capture. 1: A rising edge triggers the capture. Bit 0 = EXEDG External Clock Edge. This bit determines which type of level transition on the external clock pin EXTCLK will trigger the counter register. 0: A falling edge triggers the counter register. 1: A rising edge triggers the counter register. ST7263B 16-BIT TIMER (Cont’d) CONTROL/STATUS REGISTER (CSR) Read Only (except bit 2 R/W) Reset Value: xxxx x0xx (xxh) Note: Reading or writing the ACLR register does not clear TOF. 7 ICF1 0 OCF1 TOF ICF2 OCF2 TIMD 0 0 Bit 7 = ICF1 Input Capture Flag 1. 0: No input capture (reset value). 1: An input capture has occurred on the ICAP1 pin or the counter has reached the OC2R value in PWM mode. To clear this bit, first read the SR register, then read or write the low byte of the IC1R (IC1LR) register. Bit 6 = OCF1 Output Compare Flag 1. 0: No match (reset value). 1: The content of the free running counter has matched the content of the OC1R register. To clear this bit, first read the SR register, then read or write the low byte of the OC1R (OC1LR) register. Bit 5 = TOF Timer Overflow Flag. 0: No timer overflow (reset value). 1: The free running counter rolled over from FFFFh to 0000h. To clear this bit, first read the SR register, then read or write the low byte of the CR (CLR) register. Bit 4 = ICF2 Input Capture Flag 2. 0: No input capture (reset value). 1: An input capture has occurred on the ICAP2 pin. To clear this bit, first read the SR register, then read or write the low byte of the IC2R (IC2LR) register. Bit 3 = OCF2 Output Compare Flag 2. 0: No match (reset value). 1: The content of the free running counter has matched the content of the OC2R register. To clear this bit, first read the SR register, then read or write the low byte of the OC2R (OC2LR) register. Bit 2 = TIMD Timer disable. This bit is set and cleared by software. When set, it freezes the timer prescaler and counter and disabled the output functions (OCMP1 and OCMP2 pins) to reduce power consumption. Access to the timer registers is still available, allowing the timer configuration to be changed, or the counter reset, while it is disabled. 0: Timer enabled 1: Timer prescaler, counter and outputs disabled Bits 1:0 = Reserved, must be kept cleared. 51/132 ST7263B 16-BIT TIMER (Cont’d) INPUT CAPTURE 1 HIGH REGISTER (IC1HR) Read Only Reset Value: Undefined This is an 8-bit read only register that contains the high part of the counter value (transferred by the input capture 1 event). OUTPUT COMPARE 1 HIGH REGISTER (OC1HR) Read/Write Reset Value: 1000 0000 (80h) This is an 8-bit register that contains the high part of the value to be compared to the CHR register. 7 0 7 0 MSB LSB MSB LSB INPUT CAPTURE 1 LOW REGISTER (IC1LR) Read Only Reset Value: Undefined This is an 8-bit read only register that contains the low part of the counter value (transferred by the input capture 1 event). OUTPUT COMPARE 1 LOW REGISTER (OC1LR) Read/Write Reset Value: 0000 0000 (00h) This is an 8-bit register that contains the low part of the value to be compared to the CLR register. 7 0 7 0 MSB LSB MSB LSB 52/132 ST7263B 16-BIT TIMER (Cont’d) OUTPUT COMPARE 2 HIGH REGISTER (OC2HR) Read/Write Reset Value: 1000 0000 (80h) This is an 8-bit register that contains the high part of the value to be compared to the CHR register. ALTERNATE COUNTER HIGH REGISTER (ACHR) Read Only Reset Value: 1111 1111 (FFh) This is an 8-bit register that contains the high part of the counter value. 7 0 7 0 MSB LSB MSB LSB OUTPUT COMPARE 2 LOW REGISTER (OC2LR) Read/Write Reset Value: 0000 0000 (00h) This is an 8-bit register that contains the low part of the value to be compared to the CLR register. 7 0 MSB LSB COUNTER HIGH REGISTER (CHR) Read Only Reset Value: 1111 1111 (FFh) This is an 8-bit register that contains the high part of the counter value. 7 0 MSB LSB COUNTER LOW REGISTER (CLR) Read Only Reset Value: 1111 1100 (FCh) This is an 8-bit register that contains the low part of the counter value. A write to this register resets the counter. An access to this register after accessing the CSR register clears the TOF bit. 7 0 MSB LSB ALTERNATE COUNTER LOW REGISTER (ACLR) Read Only Reset Value: 1111 1100 (FCh) This is an 8-bit register that contains the low part of the counter value. A write to this register resets the counter. An access to this register after an access to CSR register does not clear the TOF bit in the CSR register. 7 0 MSB LSB INPUT CAPTURE 2 HIGH REGISTER (IC2HR) Read Only Reset Value: Undefined This is an 8-bit read only register that contains the high part of the counter value (transferred by the Input Capture 2 event). 7 0 MSB LSB INPUT CAPTURE 2 LOW REGISTER (IC2LR) Read Only Reset Value: Undefined This is an 8-bit read only register that contains the low part of the counter value (transferred by the Input Capture 2 event). 7 0 MSB LSB 53/132 ST7263B 16-BIT TIMER (Cont’d) Table 17. 16-Bit Timer Register Map and Reset Values Address (Hex.) 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 54/132 Register Label 7 6 5 4 3 2 1 0 OC1E OC2E OPM PWM CC1 CC0 IEDG2 EXEDG Reset Value CR1 0 ICIE 0 OCIE 0 TOIE 0 FOLV2 0 FOLV1 0 OLVL2 0 IEDG1 0 OLVL1 Reset Value SR 0 ICF1 0 OCF1 0 TOF 0 ICF2 0 OCF2 0 TIMD 0 0 0 0 Reset Value IC1HR 0 0 0 0 0 0 0 0 CR2 Reset Value IC1LR Reset Value OC1HR Reset Value OC1LR Reset Value CHR Reset Value CLR Reset Value ACHR Reset Value ACLR Reset Value IC2HR Reset Value IC2LR Reset Value OC2HR Reset Value OC2LR Reset Value MSB LSB MSB LSB MSB 1 0 0 0 0 0 0 LSB 0 MSB 0 0 0 0 0 0 0 LSB 0 MSB 1 1 1 1 1 1 1 LSB 1 MSB 1 1 1 1 1 1 0 LSB 0 MSB 1 1 1 1 1 1 1 LSB 1 MSB 1 1 1 1 1 1 0 LSB 0 MSB LSB MSB LSB MSB 1 0 0 0 0 0 0 LSB 0 MSB 0 0 0 0 0 0 0 LSB 0 ST7263B 11.3 SERIAL COMMUNICATIONS INTERFACE (SCI) 11.3.1 Introduction The Serial Communications Interface (SCI) offers a flexible means of full-duplex data exchange with external equipment requiring an industry standard NRZ asynchronous serial data format. 11.3.2 Main Features ■ Full duplex, asynchronous communications ■ NRZ standard format (Mark/Space) ■ Independently programmable transmit and receive baud rates up to 250K baud. ■ Programmable data word length (8 or 9 bits) ■ Receive buffer full, Transmit buffer empty and End of Transmission flags ■ Two receiver wake-up modes: – Address bit (MSB) – Idle line ■ Muting function for multiprocessor configurations ■ Separate enable bits for Transmitter and Receiver ■ Four error detection flags: – Overrun error – Noise error – Frame error – Parity error ■ Five interrupt sources with flags: – Transmit data register empty – Transmission complete – Receive data register full – Idle line received – Overrun error detected ■ Parity control: – Transmits parity bit – Checks parity of received data byte ■ Reduced power consumption mode 11.3.3 General Description The interface is externally connected to another device by two pins (see Figure 36): – TDO: Transmit Data Output. When the transmitter and the receiver are disabled, the output pin returns to its I/O port configuration. When the transmitter is enabled and nothing is to be transmitted, the TDO pin is at high level. – RDI: Receive Data Input is the serial data input. Oversampling techniques are used for data recovery by discriminating between valid incoming data and noise. Through these pins, serial data is transmitted and received as frames comprising: – An Idle Line prior to transmission or reception – A start bit – A data word (8 or 9 bits) least significant bit first – A Stop bit indicating that the frame is complete. 55/132 ST7263B SERIAL COMMUNICATIONS INTERFACE (Cont’d) Figure 35. SCI Block Diagram Write Read (DATA REGISTER) DR Received Data Register (RDR) Transmit Data Register (TDR) TDO Received Shift Register Transmit Shift Register RDI CR1 R8 TRANSMIT WAKE UP CONTROL UNIT T8 SCID M WAKE PCE PS PIE RECEIVER CLOCK RECEIVER CONTROL CR2 SR TIE TCIE RIE ILIE TE RE RWU SBK TDRE TC RDRF IDLE OR NF FE SCI INTERRUPT CONTROL TRANSMITTER CLOCK TRANSMITTER RATE fCPU CONTROL /16 /PR BRR SCP1 SCP0 SCT2 SCT1 SCT0 SCR2 SCR1SCR0 RECEIVER RATE CONTROL BAUD RATE GENERATOR 56/132 PE ST7263B SERIAL COMMUNICATIONS INTERFACE (Cont’d) 11.3.4 Functional Description The block diagram of the Serial Control Interface, is shown in Figure 35. It contains 6 dedicated registers: – Two control registers (SCICR1 & SCICR2) – A status register (SCISR) – A baud rate register (SCIBRR) Refer to the register descriptions in Section 11.3.7for the definitions of each bit. 11.3.4.1 Serial Data Format Word length may be selected as being either 8 or 9 bits by programming the M bit in the SCICR1 register (see Figure 35). The TDO pin is in low state during the start bit. The TDO pin is in high state during the stop bit. An Idle character is interpreted as an entire frame of “1”s followed by the start bit of the next frame which contains data. A Break character is interpreted on receiving “0”s for some multiple of the frame period. At the end of the last break frame the transmitter inserts an extra “1” bit to acknowledge the start bit. Figure 36. Word Length Programming 9-bit Word length (M bit is set) Possible Parity Bit Data Frame Start Bit Bit0 Bit2 Bit1 Bit3 Bit4 Bit5 Bit6 Start Bit Break Frame Extra ’1’ Possible Parity Bit Data Frame Bit0 Bit8 Next Stop Start Bit Bit Idle Frame 8-bit Word length (M bit is reset) Start Bit Bit7 Next Data Frame Bit1 Bit2 Bit3 Bit4 Bit5 Bit6 Bit7 Start Bit Next Data Frame Stop Bit Next Start Bit Idle Frame Start Bit Break Frame Extra Start Bit ’1’ 57/132 ST7263B SERIAL COMMUNICATIONS INTERFACE (Cont’d) 11.3.4.2 Transmitter The transmitter can send data words of either 8 or 9 bits depending on the M bit status. When the M bit is set, word length is 9 bits and the 9th bit (the MSB) has to be stored in the T8 bit in the SCICR1 register. Character Transmission During an SCI transmission, data shifts out least significant bit first on the TDO pin. In this mode, the SCIDR register consists of a buffer (TDR) between the internal bus and the transmit shift register (see Figure 35). Procedure – Select the M bit to define the word length. – Select the desired baud rate using the SCIBRR register. – Set the TE bit to assign the TDO pin to the alternate function and to send a idle frame as first transmission. – Access the SCISR register and write the data to send in the SCIDR register (this sequence clears the TDRE bit). Repeat this sequence for each data to be transmitted. Clearing the TDRE bit is always performed by the following software sequence: 1. An access to the SCISR register 2. A write to the SCIDR register The TDRE bit is set by hardware and it indicates: – The TDR register is empty. – The data transfer is beginning. – The next data can be written in the SCIDR register without overwriting the previous data. This flag generates an interrupt if the TIE bit is set and the I bit is cleared in the CCR register. When a transmission is taking place, a write instruction to the SCIDR register stores the data in the TDR register and which is copied in the shift register at the end of the current transmission. When no transmission is taking place, a write instruction to the SCIDR register places the data directly in the shift register, the data transmission starts, and the TDRE bit is immediately set. 58/132 When a frame transmission is complete (after the stop bit or after the break frame) the TC bit is set and an interrupt is generated if the TCIE is set and the I bit is cleared in the CCR register. Clearing the TC bit is performed by the following software sequence: 1. An access to the SCISR register 2. A write to the SCIDR register Note: The TDRE and TC bits are cleared by the same software sequence. Break Characters Setting the SBK bit loads the shift register with a break character. The break frame length depends on the M bit (see Figure 36). As long as the SBK bit is set, the SCI send break frames to the TDO pin. After clearing this bit by software the SCI insert a logic 1 bit at the end of the last break frame to guarantee the recognition of the start bit of the next frame. Idle Characters Setting the TE bit drives the SCI to send an idle frame before the first data frame. Clearing and then setting the TE bit during a transmission sends an idle frame after the current word. Note: Resetting and setting the TE bit causes the data in the TDR register to be lost. Therefore the best time to toggle the TE bit is when the TDRE bit is set i.e. before writing the next byte in the SCIDR. ST7263B SERIAL COMMUNICATIONS INTERFACE (Cont’d) 11.3.4.3 Receiver The SCI can receive data words of either 8 or 9 bits. When the M bit is set, word length is 9 bits and the MSB is stored in the R8 bit in the SCICR1 register. Character Reception During a SCI reception, data shifts in least significant bit first through the RDI pin. In this mode, the SCIDR register consists or a buffer (RDR) between the internal bus and the received shift register (see Figure 35). Procedure – Select the M bit to define the word length. – Select the desired baud rate using the SCIBRR register. – Set the RE bit, this enables the receiver which begins searching for a start bit. When a character is received: – The RDRF bit is set. It indicates that the content of the shift register is transferred to the RDR. – An interrupt is generated if the RIE bit is set and the I bit is cleared in the CCR register. – The error flags can be set if a frame error, noise or an overrun error has been detected during reception. Clearing the RDRF bit is performed by the following software sequence done by: 1. An access to the SCISR register 2. A read to the SCIDR register. The RDRF bit must be cleared before the end of the reception of the next character to avoid an overrun error. Break Character When a break character is received, the SPI handles it as a framing error. Idle Character When a idle frame is detected, there is the same procedure as a data received character plus an interrupt if the ILIE bit is set and the I bit is cleared in the CCR register. Overrun Error An overrun error occurs when a character is received when RDRF has not been reset. Data can not be transferred from the shift register to the RDR register as long as the RDRF bit is not cleared. When a overrun error occurs: – The OR bit is set. – The RDR content will not be lost. – The shift register will be overwritten. – An interrupt is generated if the RIE bit is set and the I bit is cleared in the CCR register. The OR bit is reset by an access to the SCISR register followed by a SCIDR register read operation. Noise Error Oversampling techniques are used for data recovery by discriminating between valid incoming data and noise. When noise is detected in a frame: – The NF is set at the rising edge of the RDRF bit. – Data is transferred from the Shift register to the SCIDR register. – No interrupt is generated. However this bit rises at the same time as the RDRF bit which itself generates an interrupt. The NF bit is reset by a SCISR register read operation followed by a SCIDR register read operation. Framing Error A framing error is detected when: – The stop bit is not recognized on reception at the expected time, following either a de-synchronization or excessive noise. – A break is received. When the framing error is detected: – the FE bit is set by hardware – Data is transferred from the Shift register to the SCIDR register. – No interrupt is generated. However this bit rises at the same time as the RDRF bit which itself generates an interrupt. The FE bit is reset by a SCISR register read operation followed by a SCIDR register read operation. 59/132 ST7263B SERIAL COMMUNICATIONS INTERFACE (Cont’d) 11.3.4.4 Baud Rate Generation The baud rate for the receiver and transmitter (Rx and Tx) are set independently and calculated as follows: Tx = fCPU (16*PR)*TR Rx = fCPU (16*PR)*RR with: PR = 1, 3, 4 or 13 (see SCP[1:0] bits) TR = 1, 2, 4, 8, 16, 32, 64,128 (see SCT[2:0] bits) RR = 1, 2, 4, 8, 16, 32, 64,128 (see SCR[2:0] bits) All these bits are in the SCIBRR register. Example: If fCPU is 8 MHz (normal mode) and if PR=13 and TR=RR=1, the transmit and receive baud rates are 38400 baud. Note: The baud rate registers MUST NOT be changed while the transmitter or the receiver is enabled. 11.3.4.5 Receiver Muting and Wake-up Feature In multiprocessor configurations it is often desirable that only the intended message recipient should actively receive the full message contents, thus reducing redundant SCI service overhead for all non addressed receivers. 60/132 The non addressed devices may be placed in sleep mode by means of the muting function. Setting the RWU bit by software puts the SCI in Sleep mode: All the reception status bits can not be set. All the receive interrupts are inhibited. A muted receiver may be awakened by one of the following two ways: – by Idle Line detection if the WAKE bit is reset, – by Address Mark detection if the WAKE bit is set. Receiver wakes-up by Idle Line detection when the Receive line has recognised an Idle Frame. Then the RWU bit is reset by hardware but the IDLE bit is not set. Receiver wakes-up by Address Mark detection when it received a “1” as the most significant bit of a word, thus indicating that the message is an address. The reception of this particular word wakes up the receiver, resets the RWU bit and sets the RDRF bit, which allows the receiver to receive this word normally and to use it as an address word. Caution: In Mute mode, do not write to the SCICR2 register. If the SCI is in Mute mode during the read operation (RWU=1) and a address mark wake up event occurs (RWU is reset) before the write operation, the RWU bit will be set again by this write operation. Consequently the address byte is lost and the SCI is not woken up from Mute mode. ST7263B SERIAL COMMUNICATIONS INTERFACE (Cont’d) 11.3.4.6 Parity Control Parity control (generation of parity bit in trasmission and and parity checking in reception) can be enabled by setting the PCE bit in the SCICR1 register. Depending on the frame length defined by the M bit, the possible SCI frame formats are as listed in Table 18. Table 18. Frame Formats M bit 0 0 1 1 PCE bit 0 1 0 1 SCI Frame | SB | 8 bit data | STB | | SB | 7-bit data | PB | STB | | SB | 9-bit data | STB | | SB | 8-bit data PB | STB | Legend: SB = Start Bit, STB = Stop Bit, PB = Parity Bit Note: In case of wake up by an address mark, the MSB bit of the data is taken into account and not the parity bit Even parity: the parity bit is calculated to obtain an even number of “1s” inside the frame made of the 7 or 8 LSB bits (depending on whether M is equal to 0 or 1) and the parity bit. Ex: data=00110101; 4 bits set => parity bit will be 0 if even parity is selected (PS bit = 0). Odd parity: the parity bit is calculated to obtain an odd number of “1s” inside the frame made of the 7 or 8 LSB bits (depending on whether M is equal to 0 or 1) and the parity bit. Ex: data=00110101; 4 bits set => parity bit will be 1 if odd parity is selected (PS bit = 1). Transmission mode: If the PCE bit is set then the MSB bit of the data written in the data register is not transmitted but is changed by the parity bit. Reception mode: If the PCE bit is set then the interface checks if the received data byte has an even number of “1s” if even parity is selected (PS=0) or an odd number of “1s” if odd parity is selected (PS=1). If the parity check fails, the PE flag is set in the SCISR register and an interrupt is generated if PIE is set in the SCICR1 register. 11.3.5 Low Power Modes Mode Description No effect on SCI. WAIT SCI interrupts cause the device to exit from Wait mode. SCI registers are frozen. HALT In Halt mode, the SCI stops transmitting/receiving until Halt mode is exited. 11.3.6 Interrupts Interrupt Event Enable Exit Event Control from Flag Wait Bit Transmit Data Register TDRE Empty Transmission ComTC plete Received Data Ready RDRF to be Read Overrun Error Detected OR Idle Line Detected IDLE Parity Error PE Exit from Halt TIE Yes No TCIE Yes No Yes No Yes Yes Yes No No No RIE ILIE PIE The SCI interrupt events are connected to the same interrupt vector. These events generate an interrupt if the corresponding Enable Control Bit is set and the interrupt mask in the CC register is reset (RIM instruction). 61/132 ST7263B SERIAL COMMUNICATIONS INTERFACE (Cont’d) curs). This bit is not set by an idle line when the re11.3.7 Register Description ceiver wakes up from wake-up mode. STATUS REGISTER (SCISR) Read Only Reset Value: 1100 0000 (C0h) Bit 3 = OR Overrun error. This bit is set by hardware when the word currently 7 0 being received in the shift register is ready to be transferred into the RDR register while RDRF=1. TDRE TC RDRF IDLE OR NF FE PE An interrupt is generated if RIE=1 in the SCICR2 register. It is cleared by a software sequence (an access to the SCISR register followed by a read to Bit 7 = TDRE Transmit data register empty. the SCIDR register). This bit is set by hardware when the content of the 0: No Overrun error TDR register has been transferred into the shift 1: Overrun error is detected register. An interrupt is generated if the TIE bit=1 in the SCICR2 register. It is cleared by a software Note: When this bit is set RDR register content will sequence (an access to the SCISR register folnot be lost but the shift register will be overwritten. lowed by a write to the SCIDR register). 0: Data is not transferred to the shift register 1: Data is transferred to the shift register Bit 2 = NF Noise flag. This bit is set by hardware when noise is detected Note: Data will not be transferred to the shift regon a received frame. It is cleared by a software seister unless the TDRE bit is cleared. quence (an access to the SCISR register followed by a read to the SCIDR register). 0: No noise is detected Bit 6 = TC Transmission complete. 1: Noise is detected This bit is set by hardware when transmission of a frame containing Data, a Preamble or a Break is Note: This bit does not generate interrupt as it apcomplete. An interrupt is generated if TCIE=1 in pears at the same time as the RDRF bit which itthe SCICR2 register. It is cleared by a software seself generates an interrupt. quence (an access to the SCISR register followed by a write to the SCIDR register). 0: Transmission is not complete Bit 1 = FE Framing error. 1: Transmission is complete This bit is set by hardware when a de-synchronization, excessive noise or a break character is detected. It is cleared by a software sequence (an Bit 5 = RDRF Received data ready flag. access to the SCISR register followed by a read to This bit is set by hardware when the content of the the SCIDR register). RDR register has been transferred to the SCIDR 0: No Framing error is detected register. An interrupt is generated if RIE=1 in the 1: Framing error or break character is detected SCICR2 register. It is cleared by a software sequence (an access to the SCISR register followed Note: This bit does not generate interrupt as it apby a read to the SCIDR register). pears at the same time as the RDRF bit which it0: Data is not received self generates an interrupt. If the word currently 1: Received data is ready to be read being transferred causes both frame error and overrun error, it will be transferred and only the OR bit will be set. Bit 4 = IDLE Idle line detect. This bit is set by hardware when a Idle Line is detected. An interrupt is generated if the ILIE=1 in Bit 0 = PE Parity error. the SCICR2 register. It is cleared by a software seThis bit is set by hardware when a parity error ocquence (an access to the SCISR register followed curs in receiver mode. It is cleared by a software by a read to the SCIDR register). sequence (a read to the status register followed by 0: No Idle Line is detected an access to the SCIDR data register). An inter1: Idle Line is detected rupt is generated if PIE=1 in the SCICR1 register. Note: The IDLE bit will not be set again until the 0: No parity error RDRF bit has been set itself (i.e. a new idle line oc1: Parity error 62/132 ST7263B SERIAL COMMUNICATIONS INTERFACE (Cont’d) CONTROL REGISTER 1 (SCICR1) Read/Write Reset Value: x000 0000 (x0h) 7 R8 0 T8 SCID M WAKE PCE PS PIE Bit 7 = R8 Receive data bit 8. This bit is used to store the 9th bit of the received word when M=1. Bit 6 = T8 Transmit data bit 8. This bit is used to store the 9th bit of the transmitted word when M=1. Bit 5 = SCID Disabled for low power consumption When this bit is set the SCI prescalers and outputs are stopped and the end of the current byte transfer in order to reduce power consumption.This bit is set and cleared by software. 0: SCI enabled 1: SCI prescaler and outputs disabled Bit 4 = M Word length. This bit determines the word length. It is set or cleared by software. 0: 1 Start bit, 8 Data bits, 1 Stop bit 1: 1 Start bit, 9 Data bits, 1 Stop bit Note: The M bit must not be modified during a data transfer (both transmission and reception). Bit 3 = WAKE Wake-Up method. This bit determines the SCI Wake-Up method, it is set or cleared by software. 0: Idle Line 1: Address Mark Bit 2 = PCE Parity control enable. This bit selects the hardware parity control (generation and detection). When the parity control is enabled, the computed parity is inserted at the MSB position (9th bit if M=1; 8th bit if M=0) and parity is checked on the received data. This bit is set and cleared by software. Once it is set, PCE is active after the current byte (in reception and in transmission). 0: Parity control disabled 1: Parity control enabled Bit 1 = PS Parity selection. This bit selects the odd or even parity when the parity generation/detection is enabled (PCE bit set). It is set and cleared by software. The parity will be selected after the current byte. 0: Even parity 1: Odd parity Bit 0 = PIE Parity interrupt enable. This bit enables the interrupt capability of the hardware parity control when a parity error is detected (PE bit set). It is set and cleared by software. 0: Parity error interrupt disabled 1: Parity error interrupt enabled. 63/132 ST7263B SERIAL COMMUNICATIONS INTERFACE (Cont’d) 0: Transmitter is disabled CONTROL REGISTER 2 (SCICR2) 1: Transmitter is enabled Read/Write Note: During transmission, a “0” pulse on the TE Reset Value: 0000 0000 (00 h) bit (“0” followed by “1”) sends a preamble after the current word. 7 0 Caution: The TDO pin is free for general purpose TIE TCIE RIE ILIE TE RE RWU SBK I/O only when the TE and RE bits are both cleared (or if TE is never set). Bit 7 = TIE Transmitter interrupt enable. This bit is set and cleared by software. Bit 2 = RE Receiver enable. 0: Interrupt is inhibited This bit enables the receiver. It is set and cleared 1: An SCI interrupt is generated whenever by software. TDRE=1 in the SCISR register 0: Receiver is disabled 1: Receiver is enabled and begins searching for a start bit Bit 6 = TCIE Transmission complete interrupt enable This bit is set and cleared by software. Bit 1 = RWU Receiver wake-up. 0: Interrupt is inhibited This bit determines if the SCI is in mute mode or 1: An SCI interrupt is generated whenever TC=1 in not. It is set and cleared by software and can be the SCISR register cleared by hardware when a wake-up sequence is recognized. 0: Receiver in active mode Bit 5 = RIE Receiver interrupt enable. 1: Receiver in mute mode This bit is set and cleared by software. 0: Interrupt is inhibited Note: Before selecting mute mode (setting the 1: An SCI interrupt is generated whenever OR=1 RWU bit), the SCI must receive some data first, or RDRF=1 in the SCISR register otherwise it cannot function in mute mode with wakeup by idle line detection. Bit 4 = ILIE Idle line interrupt enable. This bit is set and cleared by software. Bit 0 = SBK Send break. 0: Interrupt is inhibited This bit set is used to send break characters. It is 1: An SCI interrupt is generated whenever IDLE=1 set and cleared by software. in the SCISR register. 0: No break character is transmitted 1: Break characters are transmitted Bit 3 = TE Transmitter enable. Note: If the SBK bit is set to “1” and then to “0”, the This bit enables the transmitter and assigns the transmitter will send a BREAK word at the end of TDO pin to the alternate function. It is set and the current word. cleared by software. 64/132 ST7263B SERIAL COMMUNICATIONS INTERFACE (Cont’d) DATA REGISTER (SCIDR) PR Prescaling factor SCP1 SCP0 Read/Write 4 1 0 Reset Value: Undefined 13 1 1 Contains the Received or Transmitted data character, depending on whether it is read from or writBits 5:3 = SCT[2:0] SCI Transmitter rate divisor ten to. These 3 bits, in conjunction with the SCP1 & SCP0 bits define the total division applied to the bus 7 0 clock to yield the transmit rate clock. DR7 DR6 DR5 DR4 DR3 DR2 DR1 DR0 The Data register performs a double function (read and write) since it is composed of two registers, one for transmission (TDR) and one for reception (RDR). The TDR register provides the parallel interface between the internal bus and the output shift register (see Figure 35). The RDR register provides the parallel interface between the input shift register and the internal bus (see Figure 35). 7 0 SCP0 SCT2 SCT1 SCT0 SCR2 SCR1 SCR0 Bits 7:6= SCP[1:0] First SCI Prescaler These 2 prescaling bits allow several standard clock division ranges: PR Prescaling factor SCP1 SCT2 SCT1 SCT0 1 0 0 0 2 0 0 1 4 0 1 0 8 0 1 1 16 1 0 0 32 1 0 1 64 1 1 0 128 1 1 1 Bits 2:0 = SCR[2:0] SCI Receiver rate divisor. These 3 bits, in conjunction with the SCP[1:0] bits define the total division applied to the bus clock to yield the receive rate clock. BAUD RATE REGISTER (SCIBRR) Read/Write Reset Value: 0000 0000 (00h) SCP1 TR dividing factor SCP0 1 0 0 3 0 1 RR dividing factor SCR2 SCR1 SCR0 1 0 0 0 2 0 0 1 4 0 1 0 8 0 1 1 16 1 0 0 32 1 0 1 64 1 1 0 128 1 1 1 65/132 ST7263B SERIAL COMMUNICATIONS INTERFACE (Cont’d) Table 19. SCI Register Map and Reset Values Address (Hex.) Register Label 7 6 5 4 3 2 1 0 20 SCISR Reset Value TDRE 1 TC 1 RDRF 0 IDLE 0 OR 0 NF 0 FE 0 PE 0 21 SCIDR Reset Value DR7 x DR6 x DR5 x DR4 x DR3 x DR2 x DR1 x DR0 x 22 SCIBRR Reset Value SCP1 0 SCP0 0 SCT2 x SCT1 x SCT0 x SCR2 x SCR1 x SCR0 x 23 SCICR1 Reset Value R8 x T8 x SCID 0 M x WAKE x PCE 0 PS 0 PIE 0 24 SCICR2 Reset Value TIE 0 TCIE 0 RIE 0 ILIE 0 TE 0 RE 0 RWU 0 SBK 0 66/132 ST7263B 11.4 USB INTERFACE (USB) 11.4.1 Introduction The USB Interface implements a low-speed function interface between the USB and the ST7 microcontroller. It is a highly integrated circuit which includes the transceiver, 3.3 voltage regulator, SIE and DMA. No external components are needed apart from the external pull-up on USBDM for low speed recognition by the USB host. The use of DMA architecture allows the endpoint definition to be completely flexible. Endpoints can be configured by software as in or out. 11.4.2 Main Features ■ USB Specification Version 1.1 Compliant ■ Supports Low-Speed USB Protocol ■ Two or Three Endpoints (including default one) depending on the device (see device feature list and register map) ■ CRC generation/checking, NRZI encoding/ decoding and bit-stuffing ■ USB Suspend/Resume operations ■ DMA Data transfers ■ On-Chip 3.3V Regulator ■ On-Chip USB Transceiver 11.4.3 Functional Description The block diagram in Figure 37, gives an overview of the USB interface hardware. For general information on the USB, refer to the “Universal Serial Bus Specifications” document available at http//:www.usb.org. Serial Interface Engine The SIE (Serial Interface Engine) interfaces with the USB, via the transceiver. The SIE processes tokens, handles data transmission/reception, and handshaking as required by the USB standard. It also performs frame formatting, including CRC generation and checking. Endpoints The Endpoint registers indicate if the microcontroller is ready to transmit/receive, and how many bytes need to be transmitted. DMA When a token for a valid Endpoint is recognized by the USB interface, the related data transfer takes place, using DMA. At the end of the transaction, an interrupt is generated. Interrupts By reading the Interrupt Status register, application software can know which USB event has occurred. Figure 37. USB Block Diagram 6 MHz ENDPOINT REGISTERS USBDM Transceiver SIE DMA USBDP CPU Address, data buses and interrupts USBVCC 3.3V Voltage Regulator INTERRUPT REGISTERS MEMORY USBGND 67/132 ST7263B USB INTERFACE (Cont’d) 11.4.4 Register Description DMA ADDRESS REGISTER (DMAR) Read / Write Reset Value: Undefined INTERRUPT/DMA REGISTER (IDR) Read / Write Reset Value: xxxx 0000 (x0h) 7 7 DA7 DA15 0 0 DA14 DA13 DA12 DA11 DA10 DA9 DA6 EP1 EP0 CNT3 CNT2 CNT1 CNT0 DA8 Bits 7:0=DA[15:8] DMA address bits 15-8. Software must write the start address of the DMA memory area whose most significant bits are given by DA15-DA6. The remaining 6 address bits are set by hardware. See the description of the IDR register and Figure 38. Bits 7:6 = DA[7:6] DMA address bits 7-6. Software must reset these bits. See the description of the DMAR register and Figure 38. Bits 5:4 = EP[1:0] Endpoint number (read-only). These bits identify the endpoint which required attention. 00: Endpoint 0 01: Endpoint 1 10: Endpoint 2 When a CTR interrupt occurs (see register ISTR) the software should read the EP bits to identify the endpoint which has sent or received a packet. Bits 3:0 = CNT[3:0] Byte count (read only). This field shows how many data bytes have been received during the last data reception. Note: Not valid for data transmission. Figure 38. DMA Buffers 101111 Endpoint 2 TX 101000 100111 Endpoint 2 RX 100000 011111 011000 010111 010000 001111 Endpoint 1 TX Endpoint 1 RX Endpoint 0 TX 001000 000111 Endpoint 0 RX DA15-6,000000 68/132 000000 ST7263B USB INTERFACE (Cont’d) PID REGISTER (PIDR) Read only Reset Value: xx00 0000 (x0h) INTERRUPT STATUS REGISTER (ISTR) Read / Write Reset Value: 0000 0000 (00h) 7 TP3 0 TP2 0 0 0 RX_ SEZ RXD 0 Bits 7:6 = TP[3:2] Token PID bits 3 & 2. USB token PIDs are encoded in four bits. TP[3:2] correspond to the variable token PID bits 3 & 2. Note: PID bits 1 & 0 have a fixed value of 01. When a CTR interrupt occurs (see register ISTR) the software should read the TP3 and TP2 bits to retrieve the PID name of the token received. The USB standard defines TP bits as: TP3 0 1 1 TP2 0 0 1 PID Name OUT IN SETUP 7 SUSP 0 DOVR CTR ERR IOVR ESUSP RESET SOF When an interrupt occurs these bits are set by hardware. Software must read them to determine the interrupt type and clear them after servicing. Note: These bits cannot be set by software. Bit 7 = SUSP Suspend mode request. This bit is set by hardware when a constant idle state is present on the bus line for more than 3 ms, indicating a suspend mode request from the USB bus. The suspend request check is active immediately after each USB reset event and its disabled by hardware when suspend mode is forced (FSUSP bit of CTLR register) until the end of resume sequence. Bits 5:3 Reserved. Forced by hardware to 0. Bit 2 = RX_SEZ Received single-ended zero This bit indicates the status of the RX_SEZ transceiver output. 0: No SE0 (single-ended zero) state 1: USB lines are in SE0 (single-ended zero) state Bit 1 = RXD Received data 0: No K-state 1: USB lines are in K-state This bit indicates the status of the RXD transceiver output (differential receiver output). Note: If the environment is noisy, the RX_SEZ and RXD bits can be used to secure the application. By interpreting the status, software can distinguish a valid End Suspend event from a spurious wake-up due to noise on the external USB line. A valid End Suspend is followed by a Resume or Reset sequence. A Resume is indicated by RXD=1, a Reset is indicated by RX_SEZ=1. Bit 0 = Reserved. Forced by hardware to 0. Bit 6 = DOVR DMA over/underrun. This bit is set by hardware if the ST7 processor can’t answer a DMA request in time. 0: No over/underrun detected 1: Over/underrun detected Bit 5 = CTR Correct Transfer. This bit is set by hardware when a correct transfer operation is performed. The type of transfer can be determined by looking at bits TP3-TP2 in register PIDR. The Endpoint on which the transfer was made is identified by bits EP1-EP0 in register IDR. 0: No Correct Transfer detected 1: Correct Transfer detected Note: A transfer where the device sent a NAK or STALL handshake is considered not correct (the host only sends ACK handshakes). A transfer is considered correct if there are no errors in the PID and CRC fields, if the DATA0/DATA1 PID is sent as expected, if there were no data overruns, bit stuffing or framing errors. Bit 4 = ERR Error. This bit is set by hardware whenever one of the errors listed below has occurred: 0: No error detected 1: Timeout, CRC, bit stuffing or nonstandard framing error detected 69/132 ST7263B USB INTERFACE (Cont’d) Bit 3 = IOVR Interrupt overrun. This bit is set when hardware tries to set ERR, or SOF before they have been cleared by software. 0: No overrun detected 1: Overrun detected Bit 2 = ESUSP End suspend mode. This bit is set by hardware when, during suspend mode, activity is detected that wakes the USB interface up from suspend mode. This interrupt is serviced by a specific vector, in order to wake up the ST7 from HALT mode. 0: No End Suspend detected 1: End Suspend detected Bit 1 = RESET USB reset. This bit is set by hardware when the USB reset sequence is detected on the bus. 0: No USB reset signal detected 1: USB reset signal detected Note: The DADDR, EP0RA, EP0RB, EP1RA, EP1RB, EP2RA and EP2RB registers are reset by a USB reset. Bit 0 = SOF Start of frame. This bit is set by hardware when a low-speed SOF indication (keep-alive strobe) is seen on the USB bus. It is also issued at the end of a resume sequence. 0: No SOF signal detected 1: SOF signal detected Note: To avoid spurious clearing of some bits, it is recommended to clear them using a load instruction where all bits which must not be altered are set, and all bits to be cleared are reset. Avoid readmodify-write instructions like AND , XOR.. INTERRUPT MASK REGISTER (IMR) Read / Write Reset Value: 0000 0000 (00h) 7 SUS PM 0 DOV RM CTR M ERR M IOVR M ESU SPM RES ETM SOF M Bits 7:0 = These bits are mask bits for all interrupt condition bits included in the ISTR. Whenever one of the IMR bits is set, if the corresponding ISTR bit is set, and the I bit in the CC register is cleared, an interrupt request is generated. For an explanation 70/132 of each bit, please refer to the corresponding bit description in ISTR. CONTROL REGISTER (CTLR) Read / Write Reset Value: 0000 0110 (06h) 7 0 0 0 0 0 RESUME PDWN FSUSP FRES Bits 7:4 = Reserved. Forced by hardware to 0. Bit 3 = RESUME Resume. This bit is set by software to wake-up the Host when the ST7 is in suspend mode. 0: Resume signal not forced 1: Resume signal forced on the USB bus. Software should clear this bit after the appropriate delay. Bit 2 = PDWN Power down. This bit is set by software to turn off the 3.3V onchip voltage regulator that supplies the external pull-up resistor and the transceiver. 0: Voltage regulator on 1: Voltage regulator off Note: After turning on the voltage regulator, software should allow at least 3 µs for stabilisation of the power supply before using the USB interface. Bit 1 = FSUSP Force suspend mode. This bit is set by software to enter Suspend mode. The ST7 should also be halted allowing at least 600 ns before issuing the HALT instruction. 0: Suspend mode inactive 1: Suspend mode active When the hardware detects USB activity, it resets this bit (it can also be reset by software). Bit 0 = FRES Force reset. This bit is set by software to force a reset of the USB interface, just as if a RESET sequence came from the USB. 0: Reset not forced 1: USB interface reset forced. The USB is held in RESET state until software clears this bit, at which point a “USB-RESET” interrupt will be generated if enabled. ST7263B USB INTERFACE (Cont’d) DEVICE ADDRESS REGISTER (DADDR) Read / Write Reset Value: 0000 0000 (00h) 7 0 0 ADD6 ADD5 ADD4 ADD3 ADD2 ADD1 ADD0 Bit 7 = Reserved. Forced by hardware to 0. Bits 6:0 = ADD[6:0] Device address, 7 bits. Software must write into this register the address sent by the host during enumeration. Note: This register is also reset when a USB reset is received from the USB bus or forced through bit FRES in the CTLR register. ENDPOINT n REGISTER A (EPnRA) Read / Write Reset Value: 0000 xxxx (0xh) 7 ST_ OUT 0 DTOG _TX STAT _TX1 STAT _TX0 TBC 3 TBC 2 TBC 1 TBC 0 These registers (EP0RA, EP1RA and EP2RA) are used for controlling data transmission. They are also reset by the USB bus reset. Note: Endpoint 2 and the EP2RA register are not available on some devices (see device feature list and register map). Bit 7 = ST_OUT Status out. This bit is set by software to indicate that a status out packet is expected: in this case, all nonzero OUT data transfers on the endpoint are STALLed instead of being ACKed. When ST_OUT is reset, OUT transactions can have any number of bytes, as needed. Bit 6 = DTOG_TX Data Toggle, for transmission transfers. It contains the required value of the toggle bit (0=DATA0, 1=DATA1) for the next transmitted data packet. This bit is set by hardware at the reception of a SETUP PID. DTOG_TX toggles only when the transmitter has received the ACK signal from the USB host. DTOG_TX and also DTOG_RX (see EPnRB) are normally updated by hardware, at the receipt of a relevant PID. They can be also written by software. Bits 5:4 = STAT_TX[1:0] Status bits, for transmission transfers. These bits contain the information about the endpoint status, which are listed below: STAT_TX1 STAT_TX0 Meaning DISABLED: transmission 0 0 transfers cannot be executed. STALL: the endpoint is stalled 0 1 and all transmission requests result in a STALL handshake. NAK: the endpoint is naked 1 0 and all transmission requests result in a NAK handshake. VALID: this endpoint is ena1 1 bled for transmission. These bits are written by software. Hardware sets the STAT_TX bits to NAK when a correct transfer has occurred (CTR=1) related to a IN or SETUP transaction addressed to this endpoint; this allows the software to prepare the next set of data to be transmitted. Bits 3:0 = TBC[3:0] Transmit byte count for Endpoint n. Before transmission, after filling the transmit buffer, software must write in the TBC field the transmit packet size expressed in bytes (in the range 08). Warning: Any value outside the range 0-8 willinduce undesired effects (such as continuous data transmission). 71/132 ST7263B USB INTERFACE (Cont’d) ENDPOINT n REGISTER B (EPnRB) Read / Write Reset Value: 0000 xxxx (0xh) STAT_RX1 7 CTRL 1 0 1 1 NAK: the endpoint is naked and all reception requests result in a NAK handshake. VALID: this endpoint is enabled for reception. 0 DTOG _RX STAT _RX1 STAT _RX0 EA3 EA2 EA1 EA0 These registers (EP1RB and EP2RB) are used for controlling data reception on Endpoints 1 and 2. They are also reset by the USB bus reset. Note: Endpoint 2 and the EP2RB register are not available on some devices (see device feature list and register map). Bit 7 = CTRL Control. This bit should be 0. Note: If this bit is 1, the Endpoint is a control endpoint. (Endpoint 0 is always a control Endpoint, but it is possible to have more than one control Endpoint). Bit 6 = DTOG_RX Data toggle, for reception transfers . It contains the expected value of the toggle bit (0=DATA0, 1=DATA1) for the next data packet. This bit is cleared by hardware in the first stage (Setup Stage) of a control transfer (SETUP transactions start always with DATA0 PID). The receiver toggles DTOG_RX only if it receives a correct data packet and the packet’s data PID matches the receiver sequence bit. Bits 5:4 = STAT_RX [1:0] Status bits, for reception transfers. These bits contain the information about the endpoint status, which are listed below: STAT_RX1 STAT_RX0 Meaning 0 0 0 1 72/132 STAT_RX0 Meaning DISABLED: reception transfers cannot be executed. STALL: the endpoint is stalled and all reception requests result in a STALL handshake. These bits are written by software. Hardware sets the STAT_RX bits to NAK when a correct transfer has occurred (CTR=1) related to an OUT or SETUP transaction addressed to this endpoint, so the software has the time to elaborate the received data before acknowledging a new transaction. Bits 3:0 = EA[3:0] Endpoint address. Software must write in this field the 4-bit address used to identify the transactions directed to this endpoint. Usually EP1RB contains “0001” and EP2RB contains “0010”. ENDPOINT 0 REGISTER B (EP0RB) Read / Write Reset Value: 1000 0000 (80h) 7 1 0 DTOG RX STAT RX1 STAT RX0 0 0 0 0 This register is used for controlling data reception on Endpoint 0. It is also reset by the USB bus reset. Bit 7 = Forced by hardware to 1. Bits 6:4 = Refer to the EPnRB register for a description of these bits. Bits 3:0 = Forced by hardware to 0. ST7263B USB INTERFACE (Cont’d) 11.4.5 Programming Considerations The interaction between the USB interface and the application program is described below. Apart from system reset, action is always initiated by the USB interface, driven by one of the USB events associated with the Interrupt Status Register (ISTR) bits. 11.4.5.1 Initializing the Registers At system reset, the software must initialize all registers to enable the USB interface to properly generate interrupts and DMA requests. 1. Initialize the DMAR, IDR, and IMR registers (choice of enabled interrupts, address of DMA buffers). Refer the paragraph titled initializing the DMA Buffers. 2. Initialize the EP0RA and EP0RB registers to enable accesses to address 0 and endpoint 0 to support USB enumeration. Refer to the paragraph titled Endpoint Initialization. 3. When addresses are received through this channel, update the content of the DADDR. 4. If needed, write the endpoint numbers in the EA fields in the EP1RB and EP2RB register. 11.4.5.2 Initializing DMA buffers The DMA buffers are a contiguous zone of memory whose maximum size is 48 bytes. They can be placed anywhere in the memory space to enable the reception of messages. The 10 most significant bits of the start of this memory area are specified by bits DA15-DA6 in registers DMAR and IDR, the remaining bits are 0. The memory map is shown in Figure 38. Each buffer is filled starting from the bottom (last 3 address bits=000) up. 11.4.5.3 Endpoint Initialization To be ready to receive: Set STAT_RX to VALID (11b) in EP0RB to enable reception. To be ready to transmit: 1. Write the data in the DMA transmit buffer. 2. In register EPnRA, specify the number of bytes to be transmitted in the TBC field 3. Enable the endpoint by setting the STAT_TX bits to VALID (11b) in EPnRA. Note: Once transmission and/or reception are enabled, registers EPnRA and/or EPnRB (respec- tively) must not be modified by software, as the hardware can change their value on the fly. When the operation is completed, they can be accessed again to enable a new operation. 11.4.5.4 Interrupt Handling Start of Frame (SOF) The interrupt service routine may monitor the SOF events for a 1 ms synchronization event to the USB bus. This interrupt is generated at the end of a resume sequence and can also be used to detect this event. USB Reset (RESET) When this event occurs, the DADDR register is reset, and communication is disabled in all endpoint registers (the USB interface will not respond to any packet). Software is responsible for reenabling endpoint 0 within 10 ms of the end of reset. To do this, set the STAT_RX bits in the EP0RB register to VALID. Suspend (SUSP) The CPU is warned about the lack of bus activity for more than 3 ms, which is a suspend request. The software should set the USB interface to suspend mode and execute an ST7 HALT instruction to meet the USB-specified power constraints. End Suspend (ESUSP) The CPU is alerted by activity on the USB, which causes an ESUSP interrupt. The ST7 automatically terminates HALT mode. Correct Transfer (CTR) 1. When this event occurs, the hardware automatically sets the STAT_TX or STAT_RX to NAK. Note: Every valid endpoint is NAKed until software clears the CTR bit in the ISTR register, independently of the endpoint number addressed by the transfer which generated the CTR interrupt. Note: If the event triggering the CTR interrupt is a SETUP transaction, both STAT_TX and STAT_RX are set to NAK. 2. Read the PIDR to obtain the token and the IDR to get the endpoint number related to the last transfer. Note: When a CTR interrupt occurs, the TP3TP2 bits in the PIDR register and EP1-EP0 bits in the IDR register stay unchanged until the CTR bit in the ISTR register is cleared. 3. Clear the CTR bit in the ISTR register. 73/132 ST7263B USB INTERFACE (Cont’d) Table 20. USB Register Map and Reset Values Address (Hex.) 25 26 27 28 29 2A 2B 2C 2D 2E 2F 30 31 74/132 Register Name 7 6 5 4 3 2 1 0 TP3 TP2 0 0 0 RX_SEZ RXD 0 Reset Value DMAR x DA15 x DA14 0 DA13 0 DA12 0 DA11 0 DA10 0 DA9 0 DA8 Reset Value IDR x DA7 x DA6 x EP1 x EP0 x CNT3 x CNT2 x CNT1 x CNT0 Reset Value ISTR x SUSP x DOVR x CTR x ERR 0 IOVR 0 ESUSP 0 RESET 0 SOF Reset Value IMR 0 SUSPM 0 DOVRM 0 CTRM 0 ERRM 0 IOVRM Reset Value CTLR 0 0 0 0 0 0 0 0 0 RESUME 0 PDWN 0 FSUSP 0 FRES Reset Value DADDR 0 0 0 ADD6 0 ADD5 0 ADD4 0 ADD3 1 ADD2 1 ADD1 0 ADD0 Reset Value EP0RA 0 ST_OUT 0 0 TBC3 0 TBC2 0 TBC1 0 TBC0 Reset Value EP0RB 0 1 0 0 STAT_TX1 STAT_TX0 DTOG_TX 0 0 0 DTOG_RX STAT_RX1 STAT_RX0 x 0 x 0 x 0 x 0 Reset Value EP1RA 1 ST_OUT 0 0 0 DTOG_TX STAT_TX1 STAT_TX0 0 TBC3 0 TBC2 0 TBC1 0 TBC0 Reset Value EP1RB 0 CTRL 0 0 0 DTOG_RX STAT_RX1 STAT_RX0 x EA3 x EA2 x EA1 x EA0 Reset Value EP2RA 0 ST_OUT 0 0 0 DTOG_TX STAT_TX1 STAT_TX0 x TBC3 x TBC2 x TBC1 x TBC0 Reset Value EP2RB 0 CTRL 0 0 0 DTOG_RX STAT_RX1 STAT_RX0 x EA3 x EA2 x EA1 x EA0 Reset Value 0 x x x x PIDR 0 0 0 0 0 ESUSPM RESETM 0 SOFM ST7263B 11.5 I²C BUS INTERFACE (I²C) 11.5.1 Introduction The I²C Bus Interface serves as an interface between the microcontroller and the serial I²C bus. It provides both multimaster and slave functions, and controls all I²C bus-specific sequencing, protocol, arbitration and timing. It supports fast I²C mode (400 kHz). 11.5.2 Main Features ■ Parallel-bus/I²C protocol converter ■ Multi-master capability ■ 7-bit Addressing ■ Transmitter/Receiver flag ■ End-of-byte transmission flag ■ Transfer problem detection I²C Master Features: ■ Clock generation ■ I²C bus busy flag ■ Arbitration Lost Flag ■ End of byte transmission flag ■ Transmitter/Receiver Flag ■ Start bit detection flag ■ Start and Stop generation I²C Slave Features: ■ Stop bit detection ■ I²C bus busy flag ■ Detection of misplaced start or stop condition ■ Programmable I²C Address detection ■ Transfer problem detection ■ End-of-byte transmission flag ■ Transmitter/Receiver flag 11.5.3 General Description In addition to receiving and transmitting data, this interface converts it from serial to parallel format and vice versa, using either an interrupt or polled handshake. The interrupts are enabled or disabled by software. The interface is connected to the I²C bus by a data pin (SDAI) and by a clock pin (SCLI). It can be connected both with a standard I²C bus and a Fast I²C bus. This selection is made by software. Mode Selection The interface can operate in the four following modes: – Slave transmitter/receiver – Master transmitter/receiver By default, it operates in slave mode. The interface automatically switches from slave to master after it generates a START condition and from master to slave in case of arbitration loss or a STOP generation, this allows Multi-Master capability. Communication Flow In Master mode, it initiates a data transfer and generates the clock signal. A serial data transfer always begins with a start condition and ends with a stop condition. Both start and stop conditions are generated in master mode by software. In Slave mode, the interface is capable of recognising its own address (7-bit), and the General Call address. The General Call address detection may be enabled or disabled by software. Data and addresses are transferred as 8-bit bytes, MSB first. The first byte following the start condition is the address byte; it is always transmitted in Master mode. A 9th clock pulse follows the 8 clock cycles of a byte transfer, during which the receiver must send an acknowledge bit to the transmitter. Refer to Figure 39. Figure 39. I²C BUS Protocol SDA ACK MSB SCL 1 START CONDITION 2 8 9 STOP CONDITION VR02119B 75/132 ST7263B I²C BUS INTERFACE (Cont’d) The Acknowledge function may be enabled and disabled by software. The I²C interface address and/or general call address can be selected by software. The speed of the I²C interface may be selected between Standard (0-100 kHz) and Fast I²C (100400 kHz). SDA/SCL Line Control Transmitter mode: the interface holds the clock line low before transmission to wait for the microcontroller to write the byte in the Data Register. Receiver mode: the interface holds the clock line low after reception to wait for the microcontroller to read the byte in the Data Register. The SCL frequency (FSCL) is controlled by a programmable clock divider which depends on the I²C bus mode. When the I²C cell is enabled, the SDA and SCL ports must be configured as floating open-drain output or floating input. In this case, the value of the external pull-up resistor used depends on the application. When the I²C cell is disabled, the SDA and SCL ports revert to being standard I/O port pins. Figure 40. I²C Interface Block Diagram DATA REGISTER (DR) SDAI DATA CONTROL SDA DATA SHIFT REGISTER COMPARATOR OWN ADDRESS REGISTER (OAR) SCLI SCL CLOCK CONTROL CLOCK CONTROL REGISTER (CCR) CONTROL REGISTER (CR) STATUS REGISTER 1 (SR1) CONTROL LOGIC STATUS REGISTER 2 (SR2) INTERRUPT 76/132 ST7263B I²C BUS INTERFACE (Cont’d) 11.5.4 Functional Description Refer to the CR, SR1 and SR2 registers in Section 11.5.7. for the bit definitions. By default the I²C interface operates in Slave mode (M/SL bit is cleared) except when it initiates a transmit or receive sequence. 11.5.4.1 Slave Mode As soon as a start condition is detected, the address is received from the SDA line and sent to the shift register; then it is compared with the address of the interface or the General Call address (if selected by software). Address not matched: the interface ignores it and waits for another Start condition. Address matched: the interface generates in sequence: – An Acknowledge pulse is generated if the ACK bit is set. – EVF and ADSL bits are set with an interrupt if the ITE bit is set. Then the interface waits for a read of the SR1 register, holding the SCL line low (see Figure 41 Transfer sequencing EV1). Next, software must read the DR register to determine from the least significant bit if the slave must enter Receiver or Transmitter mode. Slave Receiver Following the address reception and after SR1 register has been read, the slave receives bytes from the SDA line into the DR register via the internal shift register. After each byte the interface generates in sequence: – An Acknowledge pulse is generated if the ACK bit is set – EVF and BTF bits are set with an interrupt if the ITE bit is set. Then the interface waits for a read of the SR1 register followed by a read of the DR register, holding the SCL line low (see Figure 41 Transfer sequencing EV2). The slave waits for a read of the SR1 register followed by a write in the DR register, holding the SCL line low (see Figure 41 Transfer sequencing EV3). When the acknowledge pulse is received: – The EVF and BTF bits are set by hardware with an interrupt if the ITE bit is set. Closing Slave Communication After the last data byte is transferred a Stop Condition is generated by the master. The interface detects this condition and sets: – EVF and STOPF bits with an interrupt if the ITE bit is set. Then the interface waits for a read of the SR2 register (see Figure 41 Transfer sequencing EV4). Error Cases – BERR: Detection of a Stop or a Start condition during a byte transfer. In this case, the EVF and BERR bits are set with an interrupt if the ITE bit is set. If it is a Stop condition, then the interface discards the data, released the lines and waits for another Start condition. If it is a Start condition, then the interface discards the data and waits for the next slave address on the bus. – AF: Detection of a non-acknowledge bit. In this case, the EVF and AF bits are set with an interrupt if the ITE bit is set. Note: In both cases, the SCL line is not held low; however, the SDA line can remain low due to possible “0” bits transmitted last. It is then necessary to release both lines by software. How to Release the SDA / SCL lines Set and subsequently clear the STOP bit while BTF is set. The SDA/SCL lines are released after the transfer of the current byte. Slave Transmitter Following the address reception and after the SR1 register has been read, the slave sends bytes from the DR register to the SDA line via the internal shift register. 77/132 ST7263B I²C BUS INTERFACE (Cont’d) 11.5.4.2 Master Mode To switch from default Slave mode to Master mode, a Start condition generation is needed. Start Condition and Transmit Slave Address Setting the START bit while the BUSY bit is cleared causes the interface to switch to Master mode (M/SL bit set) and generates a Start condition. Once the Start condition is sent: – The EVF and SB bits are set by hardware with an interrupt if the ITE bit is set. Then the master waits for a read of the SR1 register followed by a write in the DR register with the Slave address byte, holding the SCL line low (see Figure 41 Transfer sequencing EV5). Then the slave address byte is sent to the SDA line via the internal shift register. After completion of this transfer (and acknowledge from the slave if the ACK bit is set): – The EVF bit is set by hardware with interrupt generation if the ITE bit is set. Then the master waits for a read of the SR1 register followed by a write in the CR register (for example set PE bit), holding the SCL line low (see Figure 41 Transfer sequencing EV6). Next the master must enter Receiver or Transmitter mode. Master Receiver Following the address transmission and after the SR1 and CR registers have been accessed, the master receives bytes from the SDA line into the DR register via the internal shift register. After each byte the interface generates in sequence: – An Acknowledge pulse is generated if if the ACK bit is set – EVF and BTF bits are set by hardware with an interrupt if the ITE bit is set. Then the interface waits for a read of the SR1 register followed by a read of the DR register, holding the SCL line low (see Figure 41 Transfer sequencing EV7). 78/132 To close the communication: before reading the last byte from the DR register, set the STOP bit to generate the Stop condition. The interface returns automatically to slave mode (M/SL bit cleared). Note: In order to generate the non-acknowledge pulse after the last received data byte, the ACK bit must be cleared just before reading the second last data byte. Master Transmitter Following the address transmission and after SR1 register has been read, the master sends bytes from the DR register to the SDA line via the internal shift register. The master waits for a read of the SR1 register followed by a write in the DR register, holding the SCL line low (see Figure 41 Transfer sequencing EV8). When the acknowledge bit is received, the interface sets: – EVF and BTF bits with an interrupt if the ITE bit is set. To close the communication: after writing the last byte to the DR register, set the STOP bit to generate the Stop condition. The interface goes automatically back to slave mode (M/SL bit cleared). Error Cases – BERR: Detection of a Stop or a Start condition during a byte transfer. In this case, the EVF and BERR bits are set by hardware with an interrupt if the ITE bit is set. – AF: Detection of a non-acknowledge bit. In this case, the EVF and AF bits are set by hardware with an interrupt if the ITE bit is set. To resume, set the START or STOP bit. – ARLO: Detection of an arbitration lost condition. In this case the ARLO bit is set by hardware (with an interrupt if the ITE bit is set and the interface goes automatically back to slave mode (the M/SL bit is cleared). Note: In all these cases, the SCL line is not held low; however, the SDA line can remain low due to possible “0” bits transmitted last. It is then necessary to release both lines by software. ST7263B I²C BUS INTERFACE (Cont’d) Figure 41. Transfer Sequencing Slave Receiver S Address A Data1 A EV1 Data2 A EV2 EV2 ..... DataN A P EV2 EV4 Slave Transmitter S Address A Data1 A EV1 EV3 Data2 A EV3 EV3 ..... DataN NA P EV3-1 EV4 Master Receiver S Address A EV5 Data1 A EV6 Data2 A EV7 EV7 ..... DataN NA P EV7 Master Transmitter S Address EV5 A Data1 EV6 EV8 A Data2 EV8 A EV8 ..... DataN A P EV8 Legend: S=Start, P=Stop, A=Acknowledge, NA=Non-acknowledge EVx=Event (with interrupt if ITE=1) EV1: EVF=1, ADSL=1, cleared by reading the SR1 register. EV2: EVF=1, BTF=1, cleared by reading the SR1 register followed by reading the DR register. EV3: EVF=1, BTF=1, cleared by reading the SR1 register followed by writing the DR register. EV3-1: EVF=1, AF=1, BTF=1; AF is cleared by reading the SR1 register. The BTF is cleared by releasing the lines (STOP=1, STOP=0) or by writing the DR register (DR=FFh). Note: If lines are released by STOP=1, STOP=0, the subsequent EV4 is not seen. EV4: EVF=1, STOPF=1, cleared by reading the SR2 register. EV5: EVF=1, SB=1, cleared by reading the SR1 register followed by writing the DR register. EV6: EVF=1, cleared by reading the SR1 register followed by writing the CR register (for example PE=1). EV7: EVF=1, BTF=1, cleared by reading the SR1 register followed by reading the DR register. EV8: EVF=1, BTF=1, cleared by reading the SR1 register followed by writing the DR register. 79/132 ST7263B I²C BUS INTERFACE (Cont’d) 11.5.5 Low Power Modes Mode WAIT HALT Description No effect on I²C interface. I²C interrupts exit from Wait mode. I²C registers are frozen. In Halt mode, the I²C interface is inactive and does not acknowledge data on the bus. The I²C interface resumes operation when the MCU is woken up by an interrupt with “exit from Halt mode” capability. 11.5.6 Interrupts Figure 42. Event Flags and Interrupt Generation BTF ADSL SB AF STOPF ARLO BERR ITE INTERRUPT EVF * * EVF can also be set by EV6 or an error from the SR2 register. Interrupt Event End of Byte Transfer Event Address Matched Event (Slave mode) Start Bit Generation Event (Master mode) Acknowledge Failure Event Stop Detection Event (Slave mode) Arbitration Lost Event (Multimaster configuration) Bus Error Event The I²C interrupt events are connected to the same interrupt vector (see Interrupts chapter). 80/132 Event Flag Enable Control Bit BTF ADSEL SB AF STOPF ARLO BERR ITE Exit from Wait Yes Yes Yes Yes Yes Yes Yes Exit from Halt No No No No No No No They generate an interrupt if the corresponding Enable Control Bit is set and the I-bit in the CC register is reset (RIM instruction). ST7263B I²C BUS INTERFACE (Cont’d) 11.5.7 Register Description I²C CONTROL REGISTER (CR) Read / Write Reset Value: 0000 0000 (00h) 7 0 0 0 PE ENGC START ACK STOP ITE Bits 7:6 = Reserved. Forced to 0 by hardware. Bit 5 = PE Peripheral enable. This bit is set and cleared by software. 0: Peripheral disabled 1: Master/Slave capability Notes: – When PE=0, all the bits of the CR register and the SR register except the Stop bit are reset. All outputs are released while PE=0 – When PE=1, the corresponding I/O pins are selected by hardware as alternate functions. – To enable the I²C interface, write the CR register TWICE with PE=1 as the first write only activates the interface (only PE is set). Bit 4 = ENGC Enable General Call. This bit is set and cleared by software. It is also cleared by hardware when the interface is disabled (PE=0). The 00h General Call address is acknowledged (01h ignored). 0: General Call disabled 1: General Call enabled Bit 3 = START Generation of a Start condition . This bit is set and cleared by software. It is also cleared by hardware when the interface is disabled (PE=0) or when the Start condition is sent (with interrupt generation if ITE=1). – In master mode: 0: No start generation 1: Repeated start generation – In slave mode: 0: No start generation 1: Start generation when the bus is free Bit 2 = ACK Acknowledge enable. This bit is set and cleared by software. It is also cleared by hardware when the interface is disabled (PE=0). 0: No acknowledge returned 1: Acknowledge returned after an address byte or a data byte is received Bit 1 = STOP Generation of a Stop condition. This bit is set and cleared by software. It is also cleared by hardware in master mode. Note: This bit is not cleared when the interface is disabled (PE=0). – In Master mode: 0: No stop generation 1: Stop generation after the current byte transfer or after the current Start condition is sent. The STOP bit is cleared by hardware when the Stop condition is sent. – In Slave mode: 0: No stop generation 1: Release the SCL and SDA lines after the current byte transfer (BTF=1). In this mode the STOP bit has to be cleared by software. Bit 0 = ITE Interrupt enable. This bit is set and cleared by software and cleared by hardware when the interface is disabled (PE=0). 0: Interrupts disabled 1: Interrupts enabled Refer to Figure 42 for the relationship between the events and the interrupt. SCL is held low when the SB, BTF or ADSL flags or an EV6 event (See Figure 41) is detected. 81/132 ST7263B I²C BUS INTERFACE (Cont’d) I²C STATUS REGISTER 1 (SR1) Read Only Reset Value: 0000 0000 (00h) 7 EVF 0 0 TRA BUSY BTF ADSL M/SL SB Bit 7 = EVF Event flag. This bit is set by hardware as soon as an event occurs. It is cleared by software reading SR2 register in case of error event or as described in Figure 41. It is also cleared by hardware when the interface is disabled (PE=0). 0: No event 1: One of the following events has occurred: – BTF=1 (Byte received or transmitted) – ADSL=1 (Address matched in Slave mode while ACK=1) – SB=1 (Start condition generated in Master mode) – AF=1 (No acknowledge received after byte transmission) – STOPF=1 (Stop condition detected in Slave mode) – ARLO=1 (Arbitration lost in Master mode) – BERR=1 (Bus error, misplaced Start or Stop condition detected) – Address byte successfully transmitted in Master mode. Bit 6 = Reserved. Forced to 0 by hardware. Bit 5 = TRA Transmitter/Receiver. When BTF is set, TRA=1 if a data byte has been transmitted. It is cleared automatically when BTF is cleared. It is also cleared by hardware after detection of Stop condition (STOPF=1), loss of bus arbitration (ARLO=1) or when the interface is disabled (PE=0). 0: Data byte received (if BTF=1) 1: Data byte transmitted Bit 4 = BUSY Bus busy . This bit is set by hardware on detection of a Start condition and cleared by hardware on detection of a Stop condition. It indicates a communication in progress on the bus. This information is still updated when the interface is disabled (PE=0). 0: No communication on the bus 1: Communication ongoing on the bus 82/132 Bit 3 = BTF Byte transfer finished. This bit is set by hardware as soon as a byte is correctly received or transmitted with interrupt generation if ITE=1. It is cleared by software reading SR1 register followed by a read or write of DR register. It is also cleared by hardware when the interface is disabled (PE=0). – Following a byte transmission, this bit is set after reception of the acknowledge clock pulse. In case an address byte is sent, this bit is set only after the EV6 event (See Figure 41). BTF is cleared by reading SR1 register followed by writing the next byte in DR register. – Following a byte reception, this bit is set after transmission of the acknowledge clock pulse if ACK=1. BTF is cleared by reading SR1 register followed by reading the byte from DR register. The SCL line is held low while BTF=1. 0: Byte transfer not done 1: Byte transfer succeeded Bit 2 = ADSL Address matched (Slave mode). This bit is set by hardware as soon as the received slave address matched with the OAR register content or a general call is recognized. An interrupt is generated if ITE=1. It is cleared by software reading SR1 register or by hardware when the interface is disabled (PE=0). The SCL line is held low while ADSL=1. 0: Address mismatched or not received 1: Received address matched Bit 1 = M/SL Master/Slave. This bit is set by hardware as soon as the interface is in Master mode (writing START=1). It is cleared by hardware after detecting a Stop condition on the bus or a loss of arbitration (ARLO=1). It is also cleared when the interface is disabled (PE=0). 0: Slave mode 1: Master mode Bit 0 = SB Start bit (Master mode). This bit is set by hardware as soon as the Start condition is generated (following a write START=1). An interrupt is generated if ITE=1. It is cleared by software reading SR1 register followed by writing the address byte in DR register. It is also cleared by hardware when the interface is disabled (PE=0). 0: No Start condition 1: Start condition generated ST7263B I²C BUS INTERFACE (Cont’d) I²C STATUS REGISTER 2 (SR2) Read Only Reset Value: 0000 0000 (00h) 7 0 0 0 0 AF STOPF ARLO BERR GCAL Bits 7:5 = Reserved. Forced to 0 by hardware. es the arbitration of the bus to another master. An interrupt is generated if ITE=1. It is cleared by software reading SR2 register or by hardware when the interface is disabled (PE=0). After an ARLO event the interface switches back automatically to Slave mode (M/SL=0). The SCL line is not held low while ARLO=1. 0: No arbitration lost detected 1: Arbitration lost detected Bit 4 = AF Acknowledge failure. This bit is set by hardware when no acknowledge is returned. An interrupt is generated if ITE=1. It is cleared by software reading SR2 register or by hardware when the interface is disabled (PE=0). The SCL line is not held low while AF=1. 0: No acknowledge failure 1: Acknowledge failure Bit 1 = BERR Bus error. This bit is set by hardware when the interface detects a misplaced Start or Stop condition. An interrupt is generated if ITE=1. It is cleared by software reading SR2 register or by hardware when the interface is disabled (PE=0). The SCL line is not held low while BERR=1. 0: No misplaced Start or Stop condition 1: Misplaced Start or Stop condition Bit 3 = STOPF Stop detection (Slave mode). This bit is set by hardware when a Stop condition is detected on the bus after an acknowledge (if ACK=1). An interrupt is generated if ITE=1. It is cleared by software reading SR2 register or by hardware when the interface is disabled (PE=0). The SCL line is not held low while STOPF=1. 0: No Stop condition detected 1: Stop condition detected Bit 0 = GCAL General Call (Slave mode). This bit is set by hardware when a general call address is detected on the bus while ENGC=1. It is cleared by hardware detecting a Stop condition (STOPF=1) or when the interface is disabled (PE=0). 0: No general call address detected on bus 1: general call address detected on bus Bit 2 = ARLO Arbitration lost. This bit is set by hardware when the interface los- 83/132 ST7263B I²C BUS INTERFACE (Cont’d) I²C CLOCK CONTROL REGISTER (CCR) Read / Write Reset Value: 0000 0000 (00h) 7 FM/SM CC6 CC5 CC4 CC3 CC2 CC1 I²C OWN ADDRESS REGISTER (OAR) Read / Write Reset Value: 0000 0000 (00h) 0 7 CC0 ADD7 Bit 7 = FM/SM Fast/Standard I²C mode. This bit is set and cleared by software. It is not cleared when the interface is disabled (PE=0). 0: Standard I²C mode 1: Fast I²C mode Bits 6:0 = CC6-CC0 7-bit clock divider. These bits select the speed of the bus (FSCL) depending on the I²C mode. They are not cleared when the interface is disabled (PE=0). – Standard mode (FM/SM=0): FSCL <= 100kHz FSCL = fCPU/(2x([CC6..CC0]+2)) – Fast mode (FM/SM=1): FSCL > 100kHz FSCL = fCPU/(3x([CC6..CC0]+2)) Note: The programmed FSCL assumes no load on SCL and SDA lines. I²C DATA REGISTER (DR) Read / Write Reset Value: 0000 0000 (00h) 7 D7 0 D6 D5 D4 D3 D2 D1 D0 Bits 7:0 = D7-D0 8-bit Data Register. These bits contains the byte to be received or transmitted on the bus. – Transmitter mode: Byte transmission start automatically when the software writes in the DR register. – Receiver mode: the first data byte is received automatically in the DR register using the least significant bit of the address. Then, the next data bytes are received one by one after reading the DR register. 84/132 0 ADD6 ADD5 ADD4 ADD3 ADD2 ADD1 ADD0 Bits 7:1 = ADD7-ADD1 Interface address . These bits define the I²C bus address of the interface. They are not cleared when the interface is disabled (PE=0). Bit 0 = ADD0 Address direction bit. This bit is don’t care, the interface acknowledges either 0 or 1. It is not cleared when the interface is disabled (PE=0). Note: Address 01h is always ignored. ST7263B Table 21. I²C Register Map Address (Hex.) 39 3B 3C 3D 3E 3F Register Name DR OAR CCR SR2 SR1 CR 7 6 5 FM/SM EVF TRA PE 4 3 DR7 .. DR0 ADD7 .. ADD0 CC6 .. CC0 AF STOPF BUSY BTF ENGC START 2 1 0 ARLO ADSL ACK BERR M/SL STOP GCAL SB ITE 85/132 ST7263B 11.6 8-BIT A/D CONVERTER (ADC) 11.6.1 Introduction The on-chip Analog to Digital Converter (ADC) peripheral is a 8-bit, successive approximation converter with internal sample and hold circuitry. This peripheral has up to 16 multiplexed analog input channels (refer to device pin out description) that allow the peripheral to convert the analog voltage levels from up to 16 different sources. The result of the conversion is stored in a 8-bit Data Register. The A/D converter is controlled through a Control/Status Register. 11.6.3 Functional Description 11.6.3.1 Analog Power Supply VDDA and VSSA are the high and low level reference voltage pins. In some devices (refer to device pin out description) they are internally connected to the VDD and V SS pins. Conversion accuracy may therefore be impacted by voltage drops and noise in the event of heavily loaded or badly decoupled power supply lines. See electrical characteristics section for more details. 11.6.2 Main Features ■ 8-bit conversion ■ Up to 16 channels with multiplexed input ■ Linear successive approximation ■ Data register (DR) which contains the results ■ Conversion complete status flag ■ On/off bit (to reduce consumption) The block diagram is shown in Figure 43. Figure 43. ADC Block Diagram fCPU COCO 0 ADON 0 fADC DIV 4 CH3 CH2 CH1 CH0 ADCCSR 4 AIN0 HOLD CONTROL RADC AIN1 ANALOG TO DIGITAL ANALOG MUX CONVERTER CADC AINx ADCDR 86/132 D7 D6 D5 D4 D3 D2 D1 D0 ST7263B 8-BIT A/D CONVERTER (ADC) (Cont’d) 11.6.3.2 Digital A/D Conversion Result The conversion is monotonic, meaning that the result never decreases if the analog input does not and never increases if the analog input does not. If the input voltage (VAIN) is greater than or equal to V DDA (high-level voltage reference) then the conversion result in the DR register is FFh (full scale) without overflow indication. If input voltage (VAIN) is lower than or equal to VSSA (low-level voltage reference) then the conversion result in the DR register is 00h. The A/D converter is linear and the digital result of the conversion is stored in the ADCDR register. The accuracy of the conversion is described in the parametric section. RAIN is the maximum recommended impedance for an analog input signal. If the impedance is too high, this will result in a loss of accuracy due to leakage and sampling not being completed in the alloted time. 11.6.3.3 A/D Conversion Phases The A/D conversion is based on two conversion phases as shown in Figure 44: ■ Sample capacitor loading [duration: tLOAD] During this phase, the VAIN input voltage to be measured is loaded into the CADC sample capacitor. ■ A/D conversion [duration: tCONV] During this phase, the A/D conversion is computed (8 successive approximations cycles) and the CADC sample capacitor is disconnected from the analog input pin to get the optimum analog to digital conversion accuracy. While the ADC is on, these two phases are continuously repeated. At the end of each conversion, the sample capacitor is kept loaded with the previous measurement load. The advantage of this behaviour is that it minimizes the current consumption on the analog pin in case of single input channel measurement. 11.6.3.4 Software Procedure Refer to the control/status register (CSR) and data register (DR) in Section 11.6.6 for the bit definitions and to Figure 44 for the timings. ADC Configuration The total duration of the A/D conversion is 12 ADC clock periods (1/fADC=4/fCPU). The analog input ports must be configured as input, no pull-up, no interrupt. Refer to the «I/O ports» chapter. Using these pins as analog inputs does not affect the ability of the port to be read as a logic input. In the CSR register: – Select the CH[3:0] bits to assign the analog channel to be converted. ADC Conversion In the CSR register: – Set the ADON bit to enable the A/D converter and to start the first conversion. From this time on, the ADC performs a continuous conversion of the selected channel. When a conversion is complete – The COCO bit is set by hardware. – No interrupt is generated. – The result is in the DR register and remains valid until the next conversion has ended. A write to the CSR register (with ADON set) aborts the current conversion, resets the COCO bit and starts a new conversion. Figure 44. ADC Conversion Timings ADON ADCCSR WRITE OPERATION tCONV HOLD CONTROL tLOAD COCO BIT SET 11.6.4 Low Power Modes Mode WAIT HALT Description No effect on A/D Converter A/D Converter disabled. After wakeup from Halt mode, the A/D Converter requires a stabilisation time before accurate conversions can be performed. Note: The A/D converter may be disabled by resetting the ADON bit. This feature allows reduced power consumption when no conversion is needed and between single shot conversions. 11.6.5 Interrupts None 87/132 ST7263B 8-BIT A/D CONVERTER (ADC) (Cont’d) 11.6.6 Register Description DATA REGISTER (DR) Read Only Reset Value: 0000 0000 (00h) CONTROL/STATUS REGISTER (CSR) Read /Write Reset Value: 0000 0000 (00h) 7 COCO 0 ADON 0 CH3 CH2 CH1 0 7 CH0 D7 Bit 7 = COCO Conversion Complete This bit is set by hardware. It is cleared by software reading the result in the DR register or writing to the CSR register. 0: Conversion is not complete 1: Conversion can be read from the DR register Bit 6 = Reserved. must always be cleared. Bit 5 = ADON A/D Converter On This bit is set and cleared by software. 0: A/D converter is switched off 1: A/D converter is switched on Bit 4 = Reserved. must always be cleared. Bits 3:0 = CH[3:0] Channel Selection These bits are set and cleared by software. They select the analog input to convert. Channel Pin* CH3 CH2 CH1 CH0 AIN0 AIN1 AIN2 AIN3 AIN4 AIN5 AIN6 AIN7 AIN8 AIN9 AIN10 AIN11 AIN12 AIN13 AIN14 AIN15 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 *Note: The number of pins AND the channel selection varies according to the device. Refer to the device pinout. 88/132 0 D6 D5 D4 D3 D2 D1 D0 Bits 7:0 = D[7:0] Analog Converted Value This register contains the converted analog value in the range 00h to FFh. Note: Reading this register reset the COCO flag. ST7263B 8-BIT A/D CONVERTER (ADC) (Cont’d) Table 22. ADC Register Map Address (Hex.) Register Name 0Ah DR 0Bh CSR 7 6 5 4 3 2 1 0 CH2 CH1 CH0 AD7 .. AD0 COCO 0 ADON 0 0 89/132 ST7263B 12 INSTRUCTION SET 12.1 ST7 ADDRESSING MODES The ST7 Core features 17 different addressing modes which can be classified in 7 main groups: Addressing Mode Example Inherent nop Immediate ld A,#$55 Direct ld A,$55 Indexed ld A,($55,X) Indirect ld A,([$55],X) Relative jrne loop Bit operation bset byte,#5 The ST7 Instruction set is designed to minimize the number of bytes required per instruction: To do so, most of the addressing modes may be subdivided in two sub-modes called long and short: – Long addressing mode is more powerful because it can use the full 64 Kbyte address space, however it uses more bytes and more CPU cycles. – Short addressing mode is less powerful because it can generally only access page zero (0000h 00FFh range), but the instruction size is more compact, and faster. All memory to memory instructions use short addressing modes only (CLR, CPL, NEG, BSET, BRES, BTJT, BTJF, INC, DEC, RLC, RRC, SLL, SRL, SRA, SWAP) The ST7 Assembler optimizes the use of long and short addressing modes. Table 23. ST7 Addressing Mode Overview Mode Syntax Pointer Address (Hex.) Destination/ Source Pointer Size (Hex.) Length (Bytes) Inherent nop +0 Immediate ld A,#$55 +1 Short Direct ld A,$10 00..FF +1 Long Direct ld A,$1000 0000..FFFF +2 No Offset Direct Indexed ld A,(X) 00..FF + 0 (with X register) + 1 (with Y register) Short Direct Indexed ld A,($10,X) 00..1FE +1 Long Direct Indexed Short Indirect ld A,($1000,X) 0000..FFFF ld A,[$10] 00..FF +2 00..FF byte +2 Long Indirect ld A,[$10.w] 0000..FFFF 00..FF word +2 Short Indirect Indexed ld A,([$10],X) 00..1FE 00..FF byte +2 Long Indirect Indexed ld A,([$10.w],X) 0000..FFFF 00..FF word +2 00..FF byte 00..FF byte 1) Relative Direct jrne loop PC-128/PC+127 Relative Indirect jrne [$10] PC-128/PC+1271) Bit Direct bset $10,#7 00..FF Bit Indirect bset [$10],#7 00..FF Bit Direct Relative btjt $10,#7,skip 00..FF Bit Indirect Relative btjt [$10],#7,skip 00..FF +1 +2 +1 +2 +2 00..FF byte +3 Note 1. At the time the instruction is executed, the Program Counter (PC) points to the instruction following JRxx. 90/132 ST7263B ST7 ADDRESSING MODES (Cont’d) 12.1.1 Inherent All Inherent instructions consist of a single byte. The opcode fully specifies all the required information for the CPU to process the operation. Inherent Instruction Function NOP No operation TRAP S/W Interrupt WFI Wait For Interrupt (Low Power Mode) HALT Halt Oscillator (Lowest Power Mode) RET Sub-routine Return IRET Interrupt Sub-routine Return SIM Set Interrupt Mask RIM Reset Interrupt Mask SCF Set Carry Flag RCF Reset Carry Flag RSP Reset Stack Pointer LD Load CLR Clear PUSH/POP Push/Pop to/from the stack INC/DEC Increment/Decrement TNZ Test Negative or Zero CPL, NEG 1 or 2 Complement MUL Byte Multiplication SLL, SRL, SRA, RLC, RRC Shift and Rotate Operations SWAP Swap Nibbles 12.1.2 Immediate Immediate instructions have two bytes, the first byte contains the opcode, the second byte contains the operand value. Immediate Instruction Function LD Load CP Compare BCP Bit Compare AND, OR, XOR Logical Operations ADC, ADD, SUB, SBC Arithmetic Operations 12.1.3 Direct In Direct instructions, the operands are referenced by their memory address. The direct addressing mode consists of two submodes: Direct (short) The address is a byte, thus requires only one byte after the opcode, but only allows 00 - FF addressing space. Direct (long) The address is a word, thus allowing 64 Kbyte addressing space, but requires 2 bytes after the opcode. 12.1.4 Indexed (No Offset, Short, Long) In this mode, the operand is referenced by its memory address, which is defined by the unsigned addition of an index register (X or Y) with an offset. The indirect addressing mode consists of three sub-modes: Indexed (No Offset) There is no offset, (no extra byte after the opcode), and allows 00 - FF addressing space. Indexed (Short) The offset is a byte, thus requires only one byte after the opcode and allows 00 - 1FE addressing space. Indexed (long) The offset is a word, thus allowing 64 Kbyte addressing space and requires 2 bytes after the opcode. 12.1.5 Indirect (Short, Long) The required data byte to do the operation is found by its memory address, located in memory (pointer). The pointer address follows the opcode. The indirect addressing mode consists of two sub-modes: Indirect (short) The pointer address is a byte, the pointer size is a byte, thus allowing 00 - FF addressing space, and requires 1 byte after the opcode. Indirect (long) The pointer address is a byte, the pointer size is a word, thus allowing 64 Kbyte addressing space, and requires 1 byte after the opcode. 91/132 ST7263B ST7 ADDRESSING MODES (Cont’d) 12.1.6 Indirect Indexed (Short, Long) This is a combination of indirect and short indexed addressing modes. The operand is referenced by its memory address, which is defined by the unsigned addition of an index register value (X or Y) with a pointer value located in memory. The pointer address follows the opcode. The indirect indexed addressing mode consists of two sub-modes: Indirect Indexed (Short) The pointer address is a byte, the pointer size is a byte, thus allowing 00 - 1FE addressing space, and requires 1 byte after the opcode. Indirect Indexed (Long) The pointer address is a byte, the pointer size is a word, thus allowing 64 Kbyte addressing space, and requires 1 byte after the opcode. Table 24. Instructions Supporting Direct, Indexed, Indirect and Indirect Indexed Addressing Modes Long and Short Instructions Function LD Load CP Compare AND, OR, XOR Logical Operations ADC, ADD, SUB, SBC Arithmetic Addition/subtraction operations BCP Bit Compare Short Instructions Only Function CLR Clear INC, DEC Increment/Decrement TNZ Test Negative or Zero CPL, NEG 1 or 2 Complement BSET, BRES Bit Operations BTJT, BTJF Bit Test and Jump Operations SLL, SRL, SRA, RLC, RRC Shift and Rotate Operations 92/132 SWAP Swap Nibbles CALL, JP Call or Jump subroutine 12.1.7 Relative Mode (Direct, Indirect) This addressing mode is used to modify the PC register value by adding an 8-bit signed offset to it. Available Relative Direct/ Indirect Instructions Function JRxx Conditional Jump CALLR Call Relative The relative addressing mode consists of two submodes: Relative (Direct) The offset follows the opcode. Relative (Indirect) The offset is defined in memory, of which the address follows the opcode. ST7263B 12.2 INSTRUCTION GROUPS The ST7 family devices use an Instruction Set consisting of 63 instructions. The instructions may be subdivided into 13 main groups as illustrated in the following table: Load and Transfer LD CLR Stack operation PUSH POP Increment/Decrement INC DEC Compare and Tests CP TNZ BCP Logical operations AND OR XOR CPL NEG Bit Operation BSET BRES Conditional Bit Test and Branch BTJT BTJF Arithmetic operations ADC ADD SUB SBC MUL Shift and Rotates SLL SRL SRA RLC RRC SWAP SLA Unconditional Jump or Call JRA JRT JRF JP CALL CALLR NOP Conditional Branch JRxx Interruption management TRAP WFI HALT IRET Condition Code Flag modification SIM RIM SCF RCF Using a pre-byte The instructions are described with one to four bytes. In order to extend the number of available opcodes for an 8-bit CPU (256 opcodes), three different prebyte opcodes are defined. These prebytes modify the meaning of the instruction they precede. The whole instruction becomes: PC-2 End of previous instruction PC-1 Prebyte PC Opcode PC+1 Additional word (0 to 2) according to the number of bytes required to compute the effective address RSP RET These prebytes enable instruction in Y as well as indirect addressing modes to be implemented. They precede the opcode of the instruction in X or the instruction using direct addressing mode. The prebytes are: PDY 90 Replace an X based instruction using immediate, direct, indexed, or inherent addressing mode by a Y one. PIX 92 Replace an instruction using direct, direct bit, or direct relative addressing mode to an instruction using the corresponding indirect addressing mode. It also changes an instruction using X indexed addressing mode to an instruction using indirect X indexed addressing mode. PIY 91 Replace an instruction using X indirect indexed addressing mode by a Y one. 93/132 ST7263B INSTRUCTION GROUPS (Cont’d) Mnemo Description Function/Example Dst Src H I N Z C ADC Add with Carry A=A+M+C A M H N Z C ADD Addition A=A+M A M H N Z C AND Logical And A=A.M A M N Z BCP Bit compare A, Memory tst (A . M) A M N Z BRES Bit Reset bres Byte, #3 M BSET Bit Set bset Byte, #3 M BTJF Jump if bit is false (0) btjf Byte, #3, Jmp1 M C BTJT Jump if bit is true (1) btjt Byte, #3, Jmp1 M C CALL Call subroutine CALLR Call subroutine relative CLR Clear CP Arithmetic Compare tst(Reg - M) reg reg, M CPL One Complement A = FFH-A DEC Decrement dec Y HALT Halt IRET Interrupt routine return Pop CC, A, X, PC INC Increment inc X JP Absolute Jump jp [TBL.w] JRA Jump relative always JRT Jump relative JRF Never jump JRIH Jump if ext. interrupt = 1 JRIL Jump if ext. interrupt = 0 JRH Jump if H = 1 H=1? JRNH Jump if H = 0 H=0? JRM Jump if I = 1 I=1? JRNM Jump if I = 0 I=0? JRMI Jump if N = 1 (minus) N=1? JRPL Jump if N = 0 (plus) N=0? JREQ Jump if Z = 1 (equal) Z=1? JRNE Jump if Z = 0 (not equal) Z=0? JRC Jump if C = 1 C=1? JRNC Jump if C = 0 C=0? JRULT Jump if C = 1 Unsigned < JRUGE Jump if C = 0 Jmp if unsigned >= JRUGT Jump if (C + Z = 0) Unsigned > 94/132 0 1 N Z C reg, M N Z 1 reg, M N Z N Z N Z M 0 jrf * H reg, M I C ST7263B INSTRUCTION GROUPS (Cont’d) Mnemo Description Function/Example Dst Src JRULE Jump if (C + Z = 1) Unsigned <= LD Load dst <= src reg, M M, reg MUL Multiply X,A = X * A A, X, Y X, Y, A NEG Negate (2’s compl) neg $10 reg, M NOP No Operation OR OR operation A=A+M A M POP Pop from the Stack pop reg reg M pop CC CC M M reg, CC H I N Z N Z 0 H C 0 I N Z N Z N Z C C PUSH Push onto the Stack push Y RCF Reset carry flag C=0 RET Subroutine Return RIM Enable Interrupts I=0 RLC Rotate left true C C <= Dst <= C reg, M N Z C RRC Rotate right true C C => Dst => C reg, M N Z C RSP Reset Stack Pointer S = Max allowed SBC Subtract with Carry A=A-M-C N Z C SCF Set carry flag C=1 SIM Disable Interrupts I=1 SLA Shift left Arithmetic C <= Dst <= 0 reg, M N Z C SLL Shift left Logic C <= Dst <= 0 reg, M N Z C SRL Shift right Logic 0 => Dst => C reg, M 0 Z C SRA Shift right Arithmetic Dst7 => Dst => C reg, M N Z C SUB Subtraction A=A-M A N Z C SWAP SWAP nibbles Dst[7..4] <=> Dst[3..0] reg, M N Z TNZ Test for Neg & Zero tnz lbl1 N Z TRAP S/W trap S/W interrupt WFI Wait for Interrupt XOR Exclusive OR N Z 0 0 A M 1 1 M 1 0 A = A XOR M A M 95/132 ST7263B 13 ELECTRICAL CHARACTERISTICS 13.1 PARAMETER CONDITIONS Unless otherwise specified, all voltages are referred to V SS. 13.1.1 Minimum and Maximum values Unless otherwise specified the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on 100% of the devices with an ambient temperature at TA=25°C and TA=TAmax (given by the selected temperature range). Data based on characterization results, design simulation and/or technology characteristics are indicated in the table footnotes and are not tested in production. Based on characterization, the minimum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation (mean±3Σ). 13.1.2 Typical values Unless otherwise specified, typical data are based on TA=25°C, VDD=5V. They are given only as design guidelines and are not tested. 13.1.3 Typical curves Unless otherwise specified, all typical curves are given only as design guidelines and are not tested. 13.1.4 Loading capacitor The loading conditions used for pin parameter measurement are shown in Figure 45. Figure 45. Pin loading conditions ST7 PIN CL 13.1.5 Pin input voltage The input voltage measurement on a pin of the device is described in Figure 46. 96/132 Figure 46. Pin input voltage ST7 PIN VIN ST7263B 13.2 ABSOLUTE MAXIMUM RATINGS Stresses above those listed as “absolute maximum ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device under these condi13.2.1 Voltage Characteristics Symbol VDD - VSS VIN1) & 2) VESD(HBM) tions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. Ratings Maximum value Supply voltage Unit 6.0 Input voltage on true open drain pins VSS -0.3 to 6.0 Input voltage on any other pin V VSS-0.3 to VDD+0.3 Electro-static discharge voltage (Human Body Model) See “Absolute Electrical Sensitivity” on page 105. 13.2.2 Current Characteristics Symbol Ratings Maximum value 3) IVDD Total current into VDD power lines (source) IVSS Total current out of VSS ground lines (sink) 3) Output current sunk by any standard I/O and control pin 80 Output current sunk by any high sink I/O pin 50 IIO IINJ(PIN) 2) & 4) ΣIINJ(PIN) 2) 80 25 Output current source by any I/Os and control pin - 25 Injected current on VPP pin TBD Injected current on RESET pin Injected current on OSCIN and OSCOUT pins Unit mA ±5 ±5 Injected current on any other pin 5) & 6) TBD Total injected current (sum of all I/O and control pins) 5) ± 20 Notes: 1. Directly connecting the RESET and I/O pins to VDD or VSS could damage the device if an unintentional internal reset is generated or an unexpected change of the I/O configuration occurs (for example, due to a corrupted program counter). To guarantee safe operation, this connection has to be done through a pull-up or pull-down resistor (typical: 4.7kΩ for RESET, 10kΩ for I/Os). Unused I/O pins must be tied in the same way to VDD or VSS according to their reset configuration. 2. When the current limitation is not possible, the VIN absolute maximum rating must be respected, otherwise refer to IINJ(PIN) specification. A positive injection is induced by VIN>VDD while a negative injection is induced by VIN<VSS. 3. All power (VDD) and ground (VSS) lines must always be connected to the external supply. 4. Negative injection disturbs the analog performance of the device. In particular, it induces leakage currents throughout the device including the analog inputs. To avoid undesirable effects on the analog functions, care must be taken: - Analog input pins must have a negative injection less than 0.8 mA (assuming that the impedance of the analog voltage is lower than the specified limits) - Pure digital pins must have a negative injection less than 1.6mA. In addition, it is recommended to inject the current as far as possible from the analog input pins. 5. When several inputs are submitted to a current injection, the maximum ΣIINJ(PIN) is the absolute sum of the positive and negative injected currents (instantaneous values). These results are based on characterisation with ΣIINJ(PIN) maximum current injection on four I/O port pins of the device. 6. True open drain I/O port pins do not accept positive injection. 13.2.3 Thermal Characteristics Symbol TSTG TJ Ratings Storage temperature range Maximum junction temperature Value Unit -65 to +150 °C TBD 97/132 ST7263B 13.3 OPERATING CONDITIONS 13.3.1 General Operating Conditions Symbol Parameter Conditions Min Typ Max 4 5 5.5 VDD Operating Supply Voltage (No USB) VDDA Analog reference voltage VDD VDD VSSA Analog reference voltage VSS VSS fCPU Operating frequency TA fCPU = 8 MHz fOSC = 24 MHz 8 fOSC = 12 MHz 4 Ambient temperature range 0 70 Unit V MHz °C Figure 47. fCPU Maximum Operating Frequency Versus VDD Supply Voltage fCPU [MHz] 8 FUNCTIONALITY GUARANTEED FROM 4 TO 5.5 V 4 FUNCTIONALITY NOT GUARANTEED IN THIS AREA 2 0 2.5 98/132 3.0 3.5 4 4.5 5 5.5 SUPPLY VOLTAGE [V] ST7263B OPERATING CONDITIONS (Cont’d) 13.3.2 Operating Conditions with Low Voltage Detector (LVD) Subject to general operating conditions for V DD, fCPU, and TA. Refer to Figure 9 on page 17. Parameter Conditions Min Typ 1) Max Unit VIT+ Low Voltage Reset Threshold (VDD rising) VDD Max. Variation 50V/ms 3.6 3.7 3.8 V VIT- Low Voltage Reset Threshold (VDD falling) VDD Max. Variation 50V/ms 3.3 3.5 3.7 V 200 220 mV 50 V/ms Symbol Vhyst Hysteresis (VIT+ - VIT-) 180 VtPOR VDD rise time rate 2) 0.5 Notes: 1. Not tested, guaranteed by design. 2. The VDD rise time rate condition is needed to insure a correct device power-on and LVD reset. Not tested in production. 99/132 ST7263B 13.4 SUPPLY CURRENT CHARACTERISTICS The following current consumption specified for the ST7 functional operating modes over temperature range does not take into account the clock source current consumption. To get the total device consumption, the two current values must be Symbol added (except for HALT mode for which the clock is stopped). Parameter Conditions Typ 1) Max Unit 10 9 2) 13.5 2) 7.5 9.52) 150 3) 30 3) 150 % 7.5 12 6 8.5 120 20 120 ∆IDD(∆Ta) Supply current variation vs. temperature Constant VDD and fCPU CPU RUN mode I/Os in input mode CPU WAIT mode IDD fCPU fCPU fCPU fCPU =4 =8 =4 =8 MHz MHz MHz MHz with LVD without LVD CPU HALT mode USB Suspend mode4) Note 1: Typical data are based on TA=25°C and not tested in production Note 2: Oscillator and watchdog running. All others peripherals disabled. Note 3: USB Transceiver and ADC are powered down. Note 4: Low voltage reset function enabled. CPU in HALT mode. Current consumption of external pull-up (1.5Kohms to USBVCC) and pull-down (15Kohms to VSSA) not included. Figure 48. Typ. IDD in RUN at 4 and 8 MHz fCPU mA mA µA µA Figure 49. Typ. IDD in WAIT at 4 and 8 MHz fCPU 10 14 9 12 8 7 Idd wait (mA) Idd run ( mA ) 10 8 6 6 5 4 3 4 4 mHz 8 mHz 2 4 mHz 2 8 mHz 1 0 0 4 4.5 5 Vdd (V) 100/132 5.5 4 4.5 Vdd (V) 5 5.5 ST7263B 13.5 CLOCK AND TIMING CHARACTERISTICS Subject to general operating conditions for V DD, fCPU, and TA. 13.5.1 General Timings Symbol tc(INST) Parameter Instruction cycle time Conditions fCPU=8MHz 2) tv(IT) Interrupt reaction time tv(IT) = ∆tc(INST) + 10 tCPU fCPU=8MHz Min Typ 1) Max Unit 2 3 12 tCPU 250 375 1500 ns 10 22 tCPU 1.25 2.75 µs 1. Data based on typical application software. 2. Time measured between interrupt event and interrupt vector fetch. ∆tc(INST) is the number of tCPU cycles needed to finish the current instruction execution. 13.5.2 CONTROL TIMING CHARACTERISTICS CONTROL TIMINGS Symbol Parameter Conditions Value Min Typ. Max Unit fOSC Oscillator Frequency 24 MHz fCPU Operating Frequency 8 MHz tRL External RESET Input pulse Width 1.5 tCPU tPORL Internal Power Reset Duration 514 tCPU TDOGL Watchdog or Low Voltage Reset Output Pulse Width 200 ns tDOG tOXOV tDDR Watchdog Time-out fcpu = 8MHz Crystal Oscillator Start-up Time Power up rise time 49152 3145728 tCPU 6.144 393.216 ms 40 ms 100 ms 20 from VDD = 0 to 4V 30 Note 1: The minimum period t ILIL should not be less than the number of cycle times it takes to execute the interrupt service routine plus 21 cycles. 101/132 ST7263B CLOCK AND TIMING CHARACTERISTICS (Cont’d) 13.5.3 External Clock Source Symbol Parameter VOSCINH OSCIN input pin high level voltage Conditions 0.7xVDD VDD VOSCINL OSCIN input pin low level voltage VSS 0.3xVDD tw(OSCINH) OSCIN high or low time 1) tw(OSCINL) tr(OSCIN) tf(OSCIN) IL Min see Figure 50 Typ Max ns 15 OSCx Input leakage current VSS≤VIN≤VDD ±1 Figure 50. Typical Application with an External Clock Source 90% VOSCINH 10% VOSCINL tf(OSCIN) tw(OSCINH) OSCOUT tw(OSCINL) Not connected internally fOSC EXTERNAL CLOCK SOURCE IL OSCIN ST72XXX Notes: 1. Data based on design simulation and/or technology characteristics, not tested in production. Figure 51. Typical Application with a Crystal Resonator i2 fOSC CL1 OSCIN RESONATOR CL2 RF OSCOUT ST72XXX 102/132 V 15 OSCIN rise or fall time1) tr(OSCIN) Unit µA ST7263B 13.6 MEMORY CHARACTERISTICS Subject to general operating conditions for f CPU, and TA unless otherwise specified. 13.6.1 RAM and Hardware Registers Symbol VRM Parameter Data retention mode 1) Conditions HALT mode (or RESET) Min Typ Max 2.0 Unit V Note 1: Guaranteed by design. Not tested in production. 13.6.2 Flash Memory Operating Conditions: fCPU = 8 MHz. DUAL VOLTAGE FLASH MEMORY Symbol Parameter fCPU Operating Frequency VPP IPP Programming Voltage VPP Current Byte Programming Time Block Programming Time (16KB) Sector Erasing Time (sector 0 ; 4KB) Sector Erasing Time (sector 1 ; 4KB) Sector Erasing Time (sector 2 ; 8KB) Internal VPP Stabilization Time Data Retention Write Erase Cycles tPROG tERASE tVPP tRET NRW Conditions Read mode Write / Erase mode, TA=25°C 4.0V ≤VDD ≤ 5.5V Write / Erase Min Max 8 8 11.4 12.6 30 330 0.8 2 2 2.5 10 TA=25°C TA ≤ 55°C TA=25°C Typ Unit MHz V mA µs s µs years cycles 20 100 Figure 52. Two typical Applications with VPP Pin1) VPP VPP PROGRAMMING TOOL ST72XXX 10kΩ ST72XXX Note 1: When the ICP mode is not required by the application, VPP pin must be tied to VSS. 103/132 ST7263B 13.7 EMC CHARACTERISTICS Susceptibility tests are performed on a sample basis during product characterization. 13.7.1 Functional EMS (Electro Magnetic Susceptibility) Based on a simple running application on the product (toggling 2 LEDs through I/O ports), the product is stressed by two electro magnetic events until a failure occurs (indicated by the LEDs). ESD: Electro-Static Discharge (positive and negative) is applied on all pins of the device until a functional disturbance occurs. This test conforms with the IEC 1000-4-2 standard. ■ FTB: A Burst of Fast Transient voltage (positive and negative) is applied to V DD and VSS through a 100pF capacitor, until a functional disturbance occurs. This test conforms with the IEC 1000-44 standard. A device reset allows normal operations to be resumed. ■ Symbol Parameter Conditions Neg 1) Pos 1) VFESD Voltage limits to be applied on any I/O pin to induce a functional disturbance VDD=5V, TA=+25°C, fOSC=8MHz conforms to IEC 1000-4-2 1.5 1 VFFTB Fast transient voltage burst limits to be apVDD=5V, TA=+25°C, fOSC=8MHz plied through 100pF on VDD and VDD pins conforms to IEC 1000-4-4 to induce a functional disturbance 1.8 1.8 Unit kV Figure 53. EMC Recommended star network power supply connection 2) ST72XXX 10µF 0.1µF ST7 DIGITAL NOISE FILTERING VDD VSS VDD POWER SUPPLY SOURCE VSSA EXTERNAL NOISE FILTERING VDDA 0.1µF Notes: 1. Data based on characterization results, not tested in production. 2. The suggested 10µF and 0.1µF decoupling capacitors on the power supply lines are proposed as a good price vs. EMC performance trade-off. They have to be put as close as possible to the device power supply pins. Other EMC recommendations are given in other sections (I/Os, RESET, OSCx pin characteristics). 104/132 ST7263B EMC CHARACTERISTICS (Cont’d) 13.7.2 Absolute Electrical Sensitivity Based on three different tests (ESD, LU and DLU) using specific measurement methods, the product is stressed in order to determine its performance in terms of electrical sensitivity. For more details, refer to the AN1181 ST7 application note. 13.7.2.1 Electro-Static Discharge (ESD) Electro-Static Discharges (1 positive then 1 negative pulse separated by 1 second) are applied to the pins of each sample according to each pin combination. The sample size depends of the number of supply pins of the device (3 parts*(n+1) supply pin). The Human Body Model is simulated. This test conforms to the JESD22-A114A standard. See Figure 54 and the following test sequences. – A discharge from CL through R (body resistance) to the ST7 occurs. – S2 must be closed 10 to 100ms after the pulse delivery period to ensure the ST7 is not left in charge state. S2 must be opened at least 10ms prior to the delivery of the next pulse. Human Body Model Test Sequence – C L is loaded through S1 by the HV pulse generator. – S1 switches position from generator to R. Absolute Maximum Ratings Symbol VESD(HBM) Ratings Maximum value 1) Unit Conditions Electro-static discharge voltage (Human Body Model) TA=+25°C 2000 V Figure 54. Typical Equivalent ESD Circuits S1 HIGH VOLTAGE PULSE GENERATOR R=1500Ω CL=100pF ST7 S2 HUMAN BODY MODEL Notes: 1. Data based on characterization results, not tested in production. 105/132 ST7263B EMC CHARACTERISTICS (Cont’d) 13.7.2.2 Static and Dynamic Latch-Up ■ LU: 3 complementary static tests are required on 10 parts to assess the latch-up performance. A supply overvoltage (applied to each power supply pin), a current injection (applied to each input, output and configurable I/O pin) and a power supply switch sequence are performed on each sample. This test conforms to the EIA/ JESD 78 IC latch-up standard. For more details, refer to the AN1181 ST7 application note. ■ DLU: Electro-Static Discharges (one positive then one negative test) are applied to each pin of 3 samples when the micro is running to assess the latch-up performance in dynamic mode. Power supplies are set to the typical values, the oscillator is connected as near as possible to the pins of the micro and the component is put in reset mode. This test conforms to the IEC1000-4-2 and SAEJ1752/3 standards and is described in Figure 55. For more details, refer to the AN1181 ST7 application note. Electrical Sensitivities Symbol LU DLU Parameter Class 1) Conditions Static latch-up class TA=+25°C TA=+85°C A A Dynamic latch-up class VDD=5.5V, fOSC=4MHz, TA=+25°C A Figure 55. Simplified Diagram of the ESD Generator for DLU RCH=50MΩ RD=330Ω DISCHARGE TIP VDD VSS CS=150pF ESD GENERATOR 2) HV RELAY ST7 DISCHARGE RETURN CONNECTION Notes: 1. Class description: A Class is an STMicroelectronics internal specification. All its limits are higher than the JEDEC specifications, that means when a device belongs to Class A it exceeds the JEDEC standard. B Class strictly covers all the JEDEC criteria (international standard). 2. Schaffner NSG435 with a pointed test finger. 106/132 ST7263B EMC CHARACTERISTICS (Cont’d) 13.7.3 ESD Pin Protection Strategy To protect an integrated circuit against ElectroStatic Discharge the stress must be controlled to prevent degradation or destruction of the circuit elements. The stress generally affects the circuit elements which are connected to the pads but can also affect the internal devices when the supply pads receive the stress. The elements to be protected must not receive excessive current, voltage or heating within their structure. An ESD network combines the different input and output ESD protections. This network works, by allowing safe discharge paths for the pins subjected to ESD stress. Two critical ESD stress cases are presented in Figure 56 and Figure 57 for standard pins and in Figure 58 and Figure 59 for true open drain pins. Standard Pin Protection To protect the output structure the following elements are added: – A diode to VDD (3a) and a diode from VSS (3b) – A protection device between VDD and V SS (4) To protect the input structure the following elements are added: – A resistor in series with the pad (1) – A diode to VDD (2a) and a diode from VSS (2b) – A protection device between VDD and V SS (4) Figure 56. Positive Stress on a Standard Pad vs. VSS VDD VDD (3a) (2a) (1) OUT (4) IN Main path (3b) Path to avoid (2b) VSS VSS Figure 57. Negative Stress on a Standard Pad vs. VDD VDD VDD (3a) (2a) (1) OUT (4) IN Main path (3b) VSS (2b) VSS 107/132 ST7263B EMC CHARACTERISTICS (Cont’d) True Open Drain Pin Protection The centralized protection (4) is not involved in the discharge of the ESD stresses applied to true open drain pads due to the fact that a P-Buffer and diode to V DD are not implemented. An additional local protection between the pad and V SS (5a & 5b) is implemented to completely absorb the positive ESD discharge. Multisupply Configuration When several types of ground (VSS, V SSA, ...) and power supply (VDD, VDDA, ...) are available for any reason (better noise immunity...), the structure shown in Figure 60 is implemented to protect the device against ESD. Figure 58. Positive Stress on a True Open Drain Pad vs. VSS VDD VDD Main path (1) Path to avoid OUT (5a) (4) IN (3b) (5b) (2b) VSS VSS Figure 59. Negative Stress on a True Open Drain Pad vs. VDD VDD VDD Main path (1) OUT (3b) (4) IN (3b) (2b) (3b) VSS VSS Figure 60. Multisupply Configuration VDD VDDA VDDA VSS BACK TO BACK DIODE BETWEEN GROUNDS VSSA 108/132 VSSA ST7263B 13.8 I/O PORT PIN CHARACTERISTICS 13.8.1 General Characteristics Subject to general operating conditions for V DD, fCPU, and TA unless otherwise specified. Symbol Parameter Conditions VIL Input low level voltage VIH Input high level voltage VIN Input voltage Vhys Schmitt trigger voltage hysteresis Typ 1) Min Max Unit 0.3xVDD V 0.7xVDD True open drain I/O pins 6.0 VSS Other I/O pins V VDD 400 mV IL Input leakage current VSS≤VIN≤VDD ±1 IS Static current consumption 2) Floating input mode 200 RPU Weak pull-up equivalent resistor 3) VIN=VSS CIO I/O pin capacitance VDD=5V 50 90 µA 120 kΩ 5 tf(IO)out Output high to low level fall time tr(IO)out Output low to high level rise time tw(IT)in External interrupt pulse time 4) pF 25 CL=50pF Between 10% and 90% ns 25 1 tCPU Figure 61. Two typical Applications with unused I/O Pin VDD ST72XXX 10kΩ 10kΩ UNUSED I/O PORT UNUSED I/O PORT ST72XXX Figure 62. Typical IPU vs. VDD with V IN=VSS Figure 63. Typical RPU vs. VDD with VIN=VSS 100 Vdd (V) 6.00 5.75 5.50 75°C 5.25 6.00 5.75 5.50 5.25 5.00 4.75 4.50 4.25 4.00 3.75 0 3.50 10 25°C 5.00 20 -45°C 4.75 75°C 30 4.50 25°C 40 4.25 -45°C 50 4.00 Ipu (µA) 60 R (kohms) 70 170 160 150 140 130 120 110 100 90 80 70 60 3.75 80 3.50 90 Vdd (V) Notes: 1. Unless otherwise specified, typical data are based on TA=25°C and VDD=5V, not tested in production. 2. Configuration not recommended, all unused pins must be kept at a fixed voltage: using the output mode of the I/O for example or an external pull-up or pull-down resistor (see Figure 61). Data based on design simulation and/or technology characteristics, not tested in production. 3. The RPU pull-up equivalent resistor is based on a resistive transistor (corresponding IPU current characteristics described in Figure 62). This data is based on characterization results. 4. To generate an external interrupt, a minimum pulse width has to be applied on an I/O port pin configured as an external interrupt source. 109/132 ST7263B I/O PORT PIN CHARACTERISTICS (Cont’d) 13.8.2 Output Driving Current Subject to general operating condition for VDD, fCPU, and TA unless otherwise specified. Symbol Parameter Conditions Output low level voltage for a standard I/O pin when up to 8 pins are sunk at the same time, Port A0, Port A(3:7), Port C(0:2) (see Figure 64) VDD=5V Output low level voltage for a high sink I/O pin when up to 4 pins are sunk at the same time, Port B(0:7) (see Figure 65) VOL 1) Output low level voltage for a very high sink I/O pin when up to 2 pins are sunk at the same time, Port A1, Port A2 VOH 2) Min Max IIO=+1.6mA 0.4 IIO=+10mA 1.3 Unit V IIO=+25mA Output high level voltage for an I/O pin when up to 8 pins are sourced at same time (see Figure 66) 1.5 IIO=-10mA VDD-1.3 IIO=-1.6mA VDD-0.8 Notes: 1. The IIO current sunk must always respect the absolute maximum rating specified in Section 13.2 and the sum of IIO (I/ O ports and control pins) must not exceed IVSS. 2. The IIO current sourced must always respect the absolute maximum rating specified in Section 13.2 and the sum of IIO (I/O ports and control pins) must not exceed IVDD. True open drain I/O pins does not have VOH. Figure 65. Typical VOL at VDD=5V (high-sink) 0.3 3 0.25 2.5 0.2 2 0.15 1.5 Vol Vol (V) Figure 64. Typical VOL at VDD=5V (standard) 0.1 1 0.05 0.5 0 0 1.5 2 2.5 3 3.5 4 5 10 15 Iio (mA) Iio (mA) 110/132 20 25 ST7263B Figure 66. Typical VOL at VDD=5V (very high-sink) 2 Vol 1.5 1 0.5 0 15 20 25 30 35 40 Iio (mA) 111/132 ST7263B I/O PORT PIN CHARACTERISTICS (Cont’d) Figure 67. Typical VDD-VOH at VDD= 5V Vdd - Voh (V) at Vdd=5V (standard) 0.35 2.5 Vdd-Voh (V) at Vdd=5V (high-sink) 0.3 0.25 0.2 0.15 0.1 0.05 0 2 1.5 1 0.5 0 -4 -3.5 -3 -2.5 Iio (mA) -2 -1.5 -1 -25 -20 -15 -10 -5 Iio (mA) Figure 68. Typical VOL vs. VDD (standard I/Os) Figure 69. Typical VOL vs. VDD (high-sink I/Os) 0.134 0.75 0.132 Vol (V) at lio=10mA Vol (V) vs Vdd at lio=1.6mA 0.7 0.130 0.128 0.126 0.124 0.65 0.6 0.55 0.122 0.5 4 0.120 4 4.25 4.5 4.75 5 5.25 Figure 70. Typical VOL vs. VDD (very high-sink I/Os) 0.95 0.9 Vol (V) at Vdd=25mA 0.85 0.8 0.75 0.7 0.65 0.6 0.55 0.5 4.25 4.5 4.75 Vdd ( V ) 112/132 4.5 4.75 Vdd (V ) Vdd ( V ) 4 4.25 5.5 5 5.25 5.5 5 5.25 5.5 ST7263B I/O PORT PIN CHARACTERISTICS (Cont’d) Figure 71. Typical VDD-VOH vs. VDD 0.9 0.85 0.16 Vdd - Voh (V) at lio=-10mA Vdd - Voh ( V ) at lio=-1.6mA 0.165 0.155 0.15 0.145 0.14 0.8 0.75 0.7 0.65 0.6 0.55 0.5 0.135 4 4.25 4.5 4.75 Vdd ( V ) 5 5.25 5.5 4 4.25 4.5 4.75 5 5.25 5.5 Vdd ( V ) 113/132 ST7263B 13.9 CONTROL PIN CHARACTERISTICS 13.9.1 Asynchronous RESET Pin Subject to general operating conditions for V DD, fCPÜ, and TA unless otherwise specified. Symbol Parameter VIH Input High Level Voltage VIL Input Low Voltage Conditions Vhys Schmitt trigger voltage hysteresis 3) VOL Output low level voltage 4) (see Figure 74, Figure 75) VDD=5V RON Weak pull-up equivalent resistor 5) VIN=VSS tw(RSTL)out Generated reset pulse duration Typ 1) Max Unit 0.7xVDD VDD V VSS 0.3xVDD Min V 400 mV IIO=5mA 0.8 IIO=7.5mA 1.3 VDD=5V 50 External pin or internal reset sources th(RSTL)in External reset pulse hold time 6) 80 V 100 6 30 kΩ 1/fSFOSC µs µs 5 Figure 72. Typical Application with RESET pin 7) L NA IO VDD O PT VDD RON USER EXTERNAL RESET CIRCUIT 8) 0.1µF ST72XXX VDD 4.7kΩ INTERNAL RESET CONTROL RESET 0.1µF WATCHDOG RESET LVD RESET Notes: 1. Unless otherwise specified, typical data are based on TA=25°C and VDD=5V, not tested in production. 2. Data based on characterization results, not tested in production. 3. Hysteresis voltage between Schmitt trigger switching levels. Based on characterization results, not tested. 4. The IIO current sunk must always respect the absolute maximum rating specified in Section 13.2 and the sum of IIO (I/ O ports and control pins) must not exceed IVSS. 5. The RON pull-up equivalent resistor is based on a resistive transistor (corresponding ION current characteristics described in Figure 73). This data is based on characterization results, not tested in production. 6. To guarantee the reset of the device, a minimum pulse has to be applied to RESET pin. All short pulses applied on RESET pin with a duration below th(RSTL)in can be ignored. 7. The output of the external reset circuit must have an open-drain output to drive the ST7 reset pad. Otherwise the device can be damaged when the ST7 generates an internal reset (LVD or watchdog). 114/132 ST7263B CONTROL PIN CHARACTERISTICS (Cont’d) Figure 73. Typical ION vs. VDD with VIN=VSS Figure 74. Typical VOL at VDD=5V (RESET) 1.4 1.2 120 Ion (µA) 80 -45°C 60 25°C 75°C 40 1 Vol (V) at Vdd=5V 100 0.8 0.6 0.4 20 6.00 5.75 5.50 5.25 5.00 4.75 4.50 4.25 4.00 3.75 0.2 3.50 0 0 3.5 Vdd (V) 4 4.5 5 5.5 6 6.5 7 7.5 Iio (mA) Figure 75. Typical VOL vs. VDD (RESET) 2 0.75 1.9 1.8 1.7 Vol (V) at lio=7.5mA Vol (V) at lio=5mA 0.7 0.65 0.6 1.6 1.5 1.4 1.3 1.2 0.55 1.1 1 0.5 4 4.25 4.5 4.75 Vdd (V ) 5 5.25 5.5 4 4.25 4.5 4.75 5 5.25 5.5 Vdd (V ) 115/132 ST7263B 13.10 COMMUNICATION INTERFACE CHARACTERISTICS 13.10.1 USB - Universal Bus Interface (Operating conditions TA = 0 to +70°C, VDD = 4.0 to 5.25V unless otherwise specified) USB DC Electrical Characteristics Parameter Symbol Conditions Min. Differential Input Sensitivity VDI I(D+, D-) 0.2 Max. Unit Differential Common Mode Range VCM Includes VDI range 0.8 2.5 V Single Ended Receiver Threshold VSE 0.8 2.0 V V Static Output Low VOL RL of 1.5K ohms to 3.6v 0.3 V Static Output High VOH RL of 15K ohms to VSS 2.8 3.6 V USBVCC: voltage level3 USBV VDD=5v 3.00 3.60 V Note 1: RL is the load connected on the USB drivers. Note 2: All the voltages are measured from the local ground potential. Note 3: To improve EMC performance (noise immunity), it is recommended to connect a 100nF capacitor to the USBVCC pin. Figure 76. USB: Data Signal Rise and Fall Time Differential Data Lines Crossover points VCRS VSS tr tf Table 25. USB: Low-speed Electrical Characteristics Parameter Symbol Conditions Min Rise time tr Note 1,CL=50 pF 75 Fall Time tf Rise/ Fall Time matching trfm Output signal Crossover Voltage VCRS Max Unit Driver characteristics: Note 1, CL=600 pF Note 1, CL=50 pF 300 75 Note 1, CL=600 pF tr/tf ns ns ns 300 ns 80 120 % 1.3 2.0 V Note 1: Measured from 10% to 90% of the data signal. For more detailed informations, please refer to Chapter 7 (Electrical) of the USB specification (version 1.1). 116/132 ST7263B COMMUNICATION INTERFACE CHARACTERISTICS (Cont’d) Refer to I/O port characteristics for more details on the input/output alternate function characteristics (RDI and TDO). 13.10.2 SCI - Serial Communications Interface Subject to general operating condition for V DD, fCPU, and TA unless otherwise specified. Conditions Symbol Parameter fCPU fTx Communication frequency fRx 8MHz Accuracy vs. Standard ~0.16% 13.10.3 I2C - Inter IC Control Interface Refer to I/O port characteristics for more details on the input/output alternate function characteristics (SDAI and SCLI). Standard Prescaler Conventional Mode TR (or RR)=128, PR=13 TR (or RR)= 32, PR=13 TR (or RR)= 16, PR=13 TR (or RR)= 8, PR=13 TR (or RR)= 4, PR=13 TR (or RR)= 16, PR= 3 TR (or RR)= 2, PR=13 TR (or RR)= 1, PR=13 Baud Rate Unit ~300.48 300 1200 ~1201.92 2400 ~2403.84 4800 ~4807.69 9600 ~9615.38 10400 ~10416.67 19200 ~19230.77 38400 ~38461.54 Hz The ST7 I2C interface meets the requirements of the Standard I2C communication protocol described in the following table. (Subject to general operating conditions for V DD, fOSC, and TA unless otherwise specified) Symbol Parameter Standard mode I2C Min 1) Max 1) Fast mode I2C Min 1) Max 1) Unit tw(SCLL) SCL clock low time 4.7 1.3 tw(SCLH) SCL clock high time 4.0 0.6 tsu(SDA) SDA setup time 250 100 th(SDA) SDA data hold time 0 3) 0 2) 900 3) tr(SDA) tr(SCL) SDA and SCL rise time 1000 20+0.1Cb 300 tf(SDA) tf(SCL) SDA and SCL fall time 300 20+0.1Cb 300 th(STA) START condition hold time 4.0 0.6 tsu(STA) Repeated START condition setup time 4.7 0.6 tsu(STO) STOP condition setup time 4.0 0.6 ns 4.7 1.3 ms tw(STO:STA) STOP to START condition time (bus free) Cb Capacitive load for each bus line 400 µs ns µs 400 pF Notes: 1. Data based on standard I2C protocol requirement, not tested in production. 2. The device must internally provide a hold time of at least 300ns for the SDA signal in order to bridge the undefined region of the falling edge of SCL. 3. The maximum hold time of the START condition has only to be met if the interface does not stretch the low period of SCL signal. 117/132 ST7263B COMMUNICATION INTERFACE CHARACTERISTICS (Cont’d) Figure 77. Typical Application with I2C Bus and Timing Diagram 1) VDD 4.7kΩ VDD 4.7kΩ I2C BUS 100Ω SDAI 100Ω SCLI ST72XXX REPEATED START START tsu(STA) tw(STO:STA) SDA tr(SDA) tf(SDA) tsu(SDA) STOP th(SDA) SCK th(STA) tw(SCKH) tw(SCKL) tr(SCK) tf(SCK) Note 1. Measurement points are done at CMOS levels: 0.3xVDD and 0.7xVDD. 118/132 tsu(STO) START ST7263B 13.11 8-BIT ADC CHARACTERISTICS Subject to general operating conditions for V DD, fOSC, and TA unless otherwise specified. Symbol fADC VAIN Parameter Conditions Conversion range voltage 2) RAIN External input resistor Internal sample and hold capacitor VSSA Max Unit 4 MHz VDDA 10 6 Stabilization time after ADC enable Conversion time (Sample+Hold) tADC Typ 1) ADC clock frequency CADC tSTAB Min - Sample capacitor loading time - Hold conversion time 0 V kΩ pF 4) 6 fCPU=8MHz, fADC=2MHz 3) 4 8 µs 1/fADC Figure 78. Typical Application with ADC VDD VT 0.6V RAIN AINx VAIN ADC CIO ~2pF VT 0.6V IL ±1µA VDD VDDA 0.1µF VSSA ST72XXX Notes: 1. Unless otherwise specified, typical data are based on TA=25°C and VDD-VSS=5V. They are given only as design guidelines and are not tested. 2. When VDDA and VSSA pins are not available on the pinout, the ADC refer to VDD and VSS. 3. Any added external serial resistor will downgrade the ADC accuracy (especially for resistance greater than 10kΩ). Data based on characterization results, not tested in production. 4. The stabilization time of the AD converter is masked by the first tLOAD. The first conversion after the enable is then always valid. 119/132 ST7263B 8-BIT ADC CHARACTERISTICS (Cont’d) ADC Accuracy with V DD=5V, fCPU=8 MHz, fADC=4 MHz R AIN< 10kΩ Symbol |ET| Parameter Offset error EG Gain Error 1) |EL| Differential linearity error Integral linearity Max 2 1) EO |ED| Min Total unadjusted error 1) -0.5 1 -1.5 0 1) 1.5 error 1) 1.5 Figure 79. ADC Accuracy Characteristics Digital Result ADCDR EG 255 V –V DDA SSA = ----------------------------------------1LSB IDE AL 256 254 253 (2) ET (3) 7 (1) 6 5 EO 4 EL 3 ED 2 (1) Example of an actual transfer curve (2) The ideal transfer curve (3) End point correlation line ET=Total Unadjusted Error: maximum deviation between the actual and the ideal transfer curves. EO=Offset Error: deviation between the first actual transition and the first ideal one. EG=Gain Error: deviation between the last ideal transition and the last actual one. ED=Differential Linearity Error: maximum deviation between actual steps and the ideal one. EL=Integral Linearity Error: maximum deviation between any actual transition and the end point correlation line. 1 LSBIDEAL 1 0 1 VSSA Vin (LSBIDEAL) 2 3 4 5 6 7 253 254 255 256 VDDA Notes: 1. ADC Accuracy vs. Negative Injection Current: For IINJ-=0.8mA, the typical leakage induced inside the die is 1.6µA and the effect on the ADC accuracy is a loss of 1 LSB for each 10KΩ increase of the external analog source impedance. This effect on the ADC accuracy has been observed under worst-case conditions for injection: - negative injection - injection to an Input with analog capability, adjacent to the enabled Analog Input - at 5V VDD supply, and worst case temperature. 2. Data based on characterization results with TA=25°C. 3. Data based on characterization results over the whole temperature range, monitored in production. 120/132 ST7263B 14 PACKAGE CHARACTERISTICS 14.1 PACKAGE MECHANICAL DATA Figure 80. 34-Pin Shrink Plastic Small Outline Package, 300-mil Width mm Dim. 0.10mm .004 seating plane Min inches Typ Max Min Typ Max A 2.46 2.64 0.097 0.104 A1 0.13 0.29 0.005 0.0115 B 0.36 0.48 0.014 0.019 C 0.23 0.32 0.0091 0.0125 D 17.73 18.06 0.698 0.711 E 7.42 7.59 0.292 0.299 e 1.02 0.040 H 10.16 10.41 0.400 0.410 h 0.64 0.74 0.025 0.029 0.61 1.02 0.024 K L 0° 8° 0.040 Number of Pins N 34 SO34S Figure 81. 32-Pin Shrink Plastic Dual in Line Package, 400-mil Width E Dim. See Lead Detail b inches Max Min Typ Max 3.56 3.76 5.08 0.140 0.148 0.200 A1 0.51 A2 3.05 3.56 4.57 0.120 0.140 0.180 eA b 0.36 0.46 0.58 0.014 0.018 0.023 eB b1 0.76 1.02 1.40 0.030 0.040 0.055 0.36 0.008 0.010 0.014 0.020 e3 C 0.20 0.25 D D 27.43 27.94 28.45 1.080 1.100 1.120 E 9.91 10.41 11.05 0.390 0.410 0.435 E1 7.62 8.89 A2 N E1 A1 N/2 9.40 0.300 0.350 0.370 A e 1.78 0.070 L eA 10.16 0.400 eB e 1 Typ A C b1 mm Min VR01725J L 12.70 2.54 3.05 0.500 3.81 0.100 0.120 0.150 Number of Pins N 32 121/132 ST7263B 14.2 THERMAL CHARACTERISTICS Symbol Ratings Value Unit RthJA Package thermal resistance (junction to ambient) SDIP32 SO34 60 75 °C/W Power dissipation 1) 500 mW 150 °C PD TJmax Maximum junction temperature 2) Notes: 1. The power dissipation is obtained from the formula PD=PINT+PPORT where PINT is the chip internal power (IDDxVDD) and PPORT is the port power dissipation determined by the user. 2. The average chip-junction temperature can be obtained from the formula TJ = TA + PD x RthJA. 122/132 ST7263B 14.3 SOLDERING AND GLUEABILITY INFORMATION Recommended soldering information given only as design guidelines in Figure 82 and Figure 83. Recommended glue for SMD plastic packages dedicated to molding compound with silicone: ■ Heraeus: PD945, PD955 ■ Loctite: 3615, 3298 Figure 82. Recommended Wave Soldering Profile (with 37% Sn and 63% Pb) 250 200 150 SOLDERING PHASE 80°C Temp. [°C] 100 50 COOLING PHASE (ROOM TEMPERATURE) 5 sec PREHEATING PHASE Time [sec] 0 20 40 60 80 100 120 140 160 Figure 83. Recommended Reflow Soldering Oven Profile (MID JEDEC) 250 Tmax=220+/-5°C for 25 sec 200 150 90 sec at 125°C 150 sec above 183°C Temp. [°C] 100 50 ramp down natural 2°C/sec max ramp up 2°C/sec for 50sec Time [sec] 0 100 200 300 400 123/132 ST7263B 15 DEVICE CONFIGURATION AND ORDERING INFORMATION Each device is available for production in ROM versions, in user programmable versions (FLASH) as well as in factory coded versions (FASTROM). FLASH devices are shipped to customers with a default content (FFh), while ROM factory coded parts contain the code supplied by the customer. This implies that FLASH devices have to be configured by the customer using the Option Byte while the ROM devices are factory-configured. The FASTROM or ROM contents are to be sent on diskette, or by electronic means, with the hexadecimal file in .S19 format generated by the development tool. All unused bytes must be set to FFh. The selected options are communicated to STMicroelectronics using the correctly completed OPTION LIST appended. The STMicroelectronics Sales Organization will be pleased to provide detailed information on contractual points. OPT 5 = WDGSW Hardware or Software Watchdog This option bit selects the watchdog type. 0: Hardware enabled 1: Software enabled OPT 4 = WDHALT Watchdog and HALT mode This option bit determines if a RESET is generated when entering HALT mode while the Watchdog is active. 0: No Reset generation when entering Halt mode 1: Reset generation when entering Halt mode OPT 3 = LVD Low Voltage Detector selection This option bit selects the LVD. 0: LVD enabled 1: LVD disabled OPT 2 = Reserved. 15.1 OPTION BYTE The Option Byte allows the hardware configuration of the microcontroller to be selected. The Option Byte has no address in the memory map and can be accessed only in programming mode using a standard ST7 programming tool. The default contents of the FLASH is fixed to FFh. This means that all the options have “1” as their default value. In ROM devices, the Option Byte is fixed in hardware by the ROM code. OPTION BYTE 7 -- 0 -- WDG WD SW HALT OPT 7:6 = Reserved. 124/132 LVD -- OSC FMP_ 24/12 R OPT 1 = OSC24/12 Oscillator Selection This option bit selects the clock divider used to drive the USB interface at 6MHz. 0: 24 MHz oscillator 1: 12 Mhz oscillator OPT 0 = FMP_R Flash memory read-out protection This option indicates if the user flash memory is protected against read-out piracy. This protection is based on a read and write protection of the memory in test modes and IAP. Erasing the option bytes when the FMP_R option is selected, causes the whole user memory to be erased first. 0: Read-out protection enabled 1: Read-out protection disabled ST7263B 15.2 DEVICE ORDERING INFORMATION Table 26. Supported Part Numbers Sales Type 1) ST72F63BK4M1 ST72F63BK4B1 ST72F63BK2M1 ST72F63BK2B1 ST72F63BK1M1 ST72F63BK1B1 ST7263BK2M1/xxx ST7263BK2B1/xxx ST7263BK1M1/xxx ST7263BK1B1/xxx ST72P63BK4M1 ST72P63BK4B1 ST72P63BK2M1 ST72P63BK2B1 ST72P63BK1M1 ST72P63BK1B1 Program Memory (bytes) 16K Flash 16K Flash 8K Flash 8K Flash 4K Flash 4K Flash 8K ROM 8K ROM 4K ROM 4K ROM 16K FASTROM 16K FASTROM 8K FASTROM 8K FASTROM 4K FASTROM 4K FASTROM RAM (bytes) 512 384 512 384 Package SO34 PSDIP32 SO34 PSDIP32 SO34 PSDIP32 SO34 PSDIP32 SO34 PSDIP32 SO34 PSDIP32 SO34 PSDIP32 SO34 PSDIP32 Note: /xxx stands for the ROM code name assigned by STMicroelectronics. Contact ST sales office for product availability 125/132 ST7263B 15.3 DEVELOPMENT TOOLS STmicroelectronics offers a range of hardware and software development tools for the ST7 microcontroller family. Full details of tools available for the ST7 from third party manufacturers can be obtain from the STMicroelectronics Internet site: ➟ http//mcu.st.com. Tools from these manufacturers include C compliers, emulators and gang programmers. STMicroelectronics Tools Three types of development tool are offered by ST see Table 27 and Table 28 for more details. Table 27. STMicroelectronics Tools Features In-Circuit Emulation ST7 Emulator Yes, powerful emulation features including trace/ logic analyzer ST7 Programming Board No Programming Capability1) Software Included ST7 CD ROM with: No Yes (All packages) – ST7 Assembly toolchain – STVD7 powerful Source Level Debugger for Win 3.1, Win 9x and NT – C compiler demo versions – Windows Programming Tools for Win 3.1, Win 9x and NT Note: 1. In-Circuit Programming (ICP) interface for FLASH devices. Table 28. Dedicated STMicroelectronics Development Tools Supported Products ST7263B Evaluation Board ST7 Emulator ST7MDTULS-EVAL ST7MDTU3-EMU2B ST7MDTU3-EPB 1) Note: 1. Add Suffix /EU or /US for the power supply for your region. 126/132 ST7 Programming Board Active Probe & Target Emulation Board ST7MDTU2-DBE2B ST7263B ST7263B MICROCONTROLLER OPTION LIST Customer: Address: ............................ ............................ ............................ Contact: ............................ Phone No: . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reference: . . . . . . . . . . . . . . . . . . . . . . . . . . . . ROM or FASTROM code must be sent in .S19 format. .Hex extension cannot be processed. STMicroelectronics references: Device Type/Memory Size/Package (check only one option): ----------------------------------------------------------------------------------------ROM DEVICE: | 4K | 8K | ----------------------------------------------------------------------------------------PSDIP32: | [ ] ST7263BK1B1 | [ ] ST7263BK2B1 | SO34: | [ ] ST7263BK1M1 | [ ] ST7263BK2M1 | ---------------------------------------------------------------------------------------------------------------------FASTROM DEVICE: | 4K | 8K | 16K ---------------------------------------------------------------------------------------------------------------------PSDIP32: | [ ] ST72P63BK1B1 | [ ] ST72P63BK2B1 | [ ] ST72P63BK4B1 SO34: | [ ] ST72P63BK1M1 | [ ] ST72P63BK2M1 | [ ] ST72P63BK4M1 ---------------------------------------------------------------------------------------------------------------------DIE FORM: | 4K | 8K | 16K ---------------------------------------------------------------------------------------------------------------------32-pin: | [ ] (as K1B1) | [ ] (as K2B1) | [ ] (as K4B1) 34-pin: | [ ] (as K1M1) | [ ] (as K2M1) | [ ] (as K4M1) Conditioning (check only one option): Packaged Product | Die Product (dice tested at 25°C only) ---------------------------------------------------------------------------------------------------------------------[ ] Tape & Reel (SO package only) | [ ] Tape & Reel [ ] Tube | [ ] Inked wafer | [ ] Sawn wafer on sticky foil Special Marking ( ROM only): [ ] No [ ] Yes "_ _ _ _ _ _ _ _ _ _ _ _ _" Authorized characters are letters, digits, '.', '-', '/' and spaces only. For marking, one line is possible with a maximum of 13 characters. Watchdog Selection: [ ] Software activation Halt when Watchdog on: [ ] Reset LVD Reset [ ] Disabled Oscillator Selection: [ ] 24 MHz. Readout Protection: [ ] Disabled Date ............................ Signature [ ] Hardware activation [ ] No reset [ ] Enabled [ ] 12 MHz. [ ] Enabled ............................ 127/132 ST7263B 15.4 ST7 APPLICATION NOTES IDENTIFICATION DESCRIPTION EXAMPLE DRIVERS AN 969 SCI COMMUNICATION BETWEEN ST7 AND PC AN 970 SPI COMMUNICATION BETWEEN ST7 AND EEPROM AN 971 I²C COMMUNICATING BETWEEN ST7 AND M24CXX EEPROM AN 972 ST7 SOFTWARE SPI MASTER COMMUNICATION AN 973 SCI SOFTWARE COMMUNICATION WITH A PC USING ST72251 16-BIT TIMER AN 974 REAL TIME CLOCK WITH ST7 TIMER OUTPUT COMPARE AN 976 DRIVING A BUZZER THROUGH ST7 TIMER PWM FUNCTION AN 979 DRIVING AN ANALOG KEYBOARD WITH THE ST7 ADC AN 980 ST7 KEYPAD DECODING TECHNIQUES, IMPLEMENTING WAKE-UP ON KEYSTROKE AN1017 USING THE ST7 UNIVERSAL SERIAL BUS MICROCONTROLLER AN1041 USING ST7 PWM SIGNAL TO GENERATE ANALOG OUTPUT (SINUSOID) AN1042 ST7 ROUTINE FOR I²C SLAVE MODE MANAGEMENT AN1044 MULTIPLE INTERRUPT SOURCES MANAGEMENT FOR ST7 MCUS AN1045 ST7 S/W IMPLEMENTATION OF I²C BUS MASTER AN1046 UART EMULATION SOFTWARE AN1047 MANAGING RECEPTION ERRORS WITH THE ST7 SCI PERIPHERALS AN1048 ST7 SOFTWARE LCD DRIVER AN1078 PWM DUTY CYCLE SWITCH IMPLEMENTING TRUE 0% & 100% DUTY CYCLE AN1082 DESCRIPTION OF THE ST72141 MOTOR CONTROL PERIPHERAL REGISTERS AN1083 ST72141 BLDC MOTOR CONTROL SOFTWARE AND FLOWCHART EXAMPLE AN1105 ST7 PCAN PERIPHERAL DRIVER AN1129 PERMANENT MAGNET DC MOTOR DRIVE. AN INTRODUCTION TO SENSORLESS BRUSHLESS DC MOTOR DRIVE APPLICATIONS AN1130 WITH THE ST72141 AN1148 USING THE ST7263 FOR DESIGNING A USB MOUSE AN1149 HANDLING SUSPEND MODE ON A USB MOUSE AN1180 USING THE ST7263 KIT TO IMPLEMENT A USB GAME PAD AN1276 BLDC MOTOR START ROUTINE FOR THE ST72141 MICROCONTROLLER AN1321 USING THE ST72141 MOTOR CONTROL MCU IN SENSOR MODE AN1325 USING THE ST7 USB LOW-SPEED FIRMWARE V4.X AN1445 USING THE ST7 SPI TO EMULATE A 16-BIT SLAVE AN1475 DEVELOPING AN ST7265X MASS STORAGE APPLICATION AN1504 STARTING A PWM SIGNAL DIRECTLY AT HIGH LEVEL USING THE ST7 16-BIT TIMER PRODUCT EVALUATION AN 910 PERFORMANCE BENCHMARKING AN 990 ST7 BENEFITS VERSUS INDUSTRY STANDARD AN1077 OVERVIEW OF ENHANCED CAN CONTROLLERS FOR ST7 AND ST9 MCUS AN1086 U435 CAN-DO SOLUTIONS FOR CAR MULTIPLEXING AN1150 BENCHMARK ST72 VS PC16 AN1151 PERFORMANCE COMPARISON BETWEEN ST72254 & PC16F876 AN1278 LIN (LOCAL INTERCONNECT NETWORK) SOLUTIONS PRODUCT MIGRATION AN1131 MIGRATING APPLICATIONS FROM ST72511/311/214/124 TO ST72521/321/324 AN1322 MIGRATING AN APPLICATION FROM ST7263 REV.B TO ST7263B AN1365 GUIDELINES FOR MIGRATING ST72C254 APPLICATION TO ST72F264 PRODUCT OPTIMIZATION 128/132 ST7263B IDENTIFICATION AN 982 AN1014 AN1015 AN1040 AN1070 AN1324 AN1477 AN1502 AN1529 DESCRIPTION USING ST7 WITH CERAMIC RESONATOR HOW TO MINIMIZE THE ST7 POWER CONSUMPTION SOFTWARE TECHNIQUES FOR IMPROVING MICROCONTROLLER EMC PERFORMANCE MONITORING THE VBUS SIGNAL FOR USB SELF-POWERED DEVICES ST7 CHECKSUM SELF-CHECKING CAPABILITY CALIBRATING THE RC OSCILLATOR OF THE ST7FLITE0 MCU USING THE MAINS EMULATED DATA EEPROM WITH XFLASH MEMORY EMULATED DATA EEPROM WITH ST7 HDFLASH MEMORY EXTENDING THE CURRENT & VOLTAGE CAPABILITY ON THE ST7265 VDDF SUPPLY ACCURATE TIMEBASE FOR LOW-COST ST7 APPLICATIONS WITH INTERNAL RC OSCILAN1530 LATOR PROGRAMMING AND TOOLS AN 978 KEY FEATURES OF THE STVD7 ST7 VISUAL DEBUG PACKAGE AN 983 KEY FEATURES OF THE COSMIC ST7 C-COMPILER PACKAGE AN 985 EXECUTING CODE IN ST7 RAM AN 986 USING THE INDIRECT ADDRESSING MODE WITH ST7 AN 987 ST7 SERIAL TEST CONTROLLER PROGRAMMING AN 988 STARTING WITH ST7 ASSEMBLY TOOL CHAIN AN 989 GETTING STARTED WITH THE ST7 HIWARE C TOOLCHAIN AN1039 ST7 MATH UTILITY ROUTINES AN1064 WRITING OPTIMIZED HIWARE C LANGUAGE FOR ST7 AN1071 HALF DUPLEX USB-TO-SERIAL BRIDGE USING THE ST72611 USB MICROCONTROLLER AN1106 TRANSLATING ASSEMBLY CODE FROM HC05 TO ST7 PROGRAMMING ST7 FLASH MICROCONTROLLERS IN REMOTE ISP MODE (IN-SITU PROAN1179 GRAMMING) AN1446 USING THE ST72521 EMULATOR TO DEBUG A ST72324 TARGET APPLICATION AN1478 PORTING AN ST7 PANTA PROJECT TO CODEWARRIOR IDE AN1527 DEVELOPING A USB SMARTCARD READER WITH ST7SCR AN1575 ON-BOARD PROGRAMMING METHODS FOR XFLASH AND HDFLASH ST7 MCUS 129/132 ST7263B 16 IMPORTANT NOTES 16.1 UNEXPECTED RESET FETCH If an interrupt request occurs while a "POP CC" instruction is executed, the interrupt controller does not recognise the source of the interrupt and, by default, passes the RESET vector address to the CPU. Workaround To solve this issue, a "POP CC" instruction must always be preceded by a "SIM" instruction. 130/132 16.2 HALT MODE POWER CONSUMPTION WITH ADC ON If the A/D converter is being used when Halt mode is entered, the power consumption in Halt Mode may exceed the maximum specified in the datasheet. Workaround Switch off the ADC by software (ADON=0) before executing a HALT instruction. ST7263B 17 SUMMARY OF CHANGES Description of the changes between the current release of the specification and the previous one. Revision Main Changes Date Modified option list on page 127 (removed 16K for ROM devices) Changed title of section 16 on page 130 April 03 1.5 Please read carefully the Section “IMPORTANT NOTES” on page 130 131/132 ST7263B Notes: Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without the express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics 2003 STMicroelectronics - All Rights Reserved. Purchase of I2C Components by STMicroelectronics conveys a license under the Philips I2C Patent. Rights to use these components in an I2C system is granted provided that the system conforms to the I2C Standard Specification as defined by Philips. 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