ST95P02 SERIAL ACCESS SPI BUS 2K (256 x 8) EEPROM NOT FOR NEW DESIGN 1 MILLION ERASE/WRITE CYCLES 40 YEARS DATA RETENTION SINGLE 3V to 5.5V SUPPLY VOLTAGE SPI BUS COMPATIBLE SERIAL INTERFACE 2 MHz CLOCK RATE MAX BLOCK WRITE PROTECTION STATUS REGISTER 16 BYTE PAGE MODE WRITE PROTECT SELF-TIMED PROGRAMMING CYCLE E.S.D.PROTECTION GREATER than 4000V The ST95P02 will be replaced shortly by the updated version ST95020 8 8 1 1 PSDIP8 (B) 0.25mm Frame SO8 (M) Figure 1. Logic Diagram DESCRIPTION The ST95P02 is a 2K bit Electrically Erasable Programmable Memory (EEPROM) fabricated with SGS-THOMSON’s High Endurance Single Polysilicon CMOS technology. The 2K bit memory is organised as 16 pages of 16 bytes. The memory is accessed by a simple SPI bus compatible serial interface. The bus signals are a serial clock input (C), a serial data input (D) and a serial data output (Q). The device connected to the bus is selected when the chip select input (S) goes low. Communications with the chip can be interrupted with a hold input (HOLD). The write operation is disabled by a write protect input (W). VCC D C S Table 1. Signal Names C Serial Clock D Serial Data Input Q Serial Data Output S Chip Select W Write Protect HOLD Hold VCC Supply Voltage VSS Ground June 1996 Q ST95P02 W HOLD VSS AI01256 1/16 ST95P02 Figure 2A. DIP Pin Connections Figure 2B. SO Pin Connections ST95P02 S Q W VSS 8 7 6 5 1 2 3 4 ST95P02 VCC HOLD C D S Q W VSS AI01257 1 2 3 4 8 7 6 5 VCC HOLD C D AI01258B Table 2. Absolute Maximum Ratings (1) Symbol Parameter Value Unit Ambient Operating Temperature –40 to 85 °C TSTG Storage Temperature –65 to 150 °C TLEAD Lead Temperature, Soldering 215 260 °C TA VO Output Voltage VI Input Voltage VCC VESD (SO8 package) (PSDIP8 package) Supply Voltage Electrostatic Discharge Voltage (Human Body model) Electrostatic Discharge Voltage (Machine model) (3) (2) 40 sec 10 sec –0.3 to VCC +0.6 V –0.3 to 6.5 V –0.3 to 6.5 V 4000 V 500 V Notes: 1. Except for the rating "Operating Temperature Range", stresses above those listed in the Table "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the SGS-THOMSON SURE Program and other relevant quality documents. 2. MIL-STD-883C, 3015.7 (100pF, 1500Ω) 3. EIAJ IC-121 (Condition C) (200pF, 0Ω) SIGNALS DESCRIPTION Serial Output (Q). The output pin is used to transfer data serially out of the ST95P02. Data is shifted out on the falling edge of the serial clock. Serial Input (D). The input pin is used to transfer data serially into the device. It receives instructions, addresses, and data to be written. Input is latched on the rising edge of the serial clock. Serial Clock (C). The serial clock provides the timing of the serial interface. Instructions, addresses, or data present at the input pin are latched 2/16 on the rising edge of the clock input, while data on the Q pin changes after the falling edge of the clock input. Chip Select (S). This input is used to select the ST95P02. The chip is selected by a high to low transition on the S pin when C is at ’0’ state. At any time, the chip is deselected by a low to high transition on the S pin when C is at ’0’ state. As soon as the chip is deselected, the Q pin is at high impedance state. This pin allows multiple ST95P02 to share the same SPI bus. After power up, the chip is at the deselect state. Transitions of S are ignored when C is at ’1’ state. ST95P02 Figure 3. Block Diagram HOLD W High Voltage Generator Control Logic S C D I/O Shift Register Q Address Register and Counter Data Register Status Y Decoder Block Protect 16 Bytes X Decoder AI01272 3/16 ST95P02 Figure 4. AC Testing Input Output Waveforms AC MEASUREMENT CONDITIONS Input Rise and Fall Times ≤ 50ns Input Pulse Voltages 0.2VCC to 0.8VCC Input and Output Timing Reference Voltages 0.3VCC to 0.7VCC 0.8VCC 0.7VCC 0.3VCC 0.2VCC Note that Output Hi-Z is defined as the point where data is no longer driven. AI00825 Table 3. Input Parameters (1) (TA = 25 °C, f = 1 MHz ) Symbol Parameter Min Max Unit CIN Input Capacitance (D) 8 pF CIN Input Capacitance (other pins) 6 pF tLPF Input Signal Pulse Width 10 ns Note: 1. Sampled only, not 100% tested. Table 4. DC Characteristics (TA = 0 to 70°C or –40 to 85°C; VCC = 3V to 5.5V) Symbol Test Condition Min Max Unit ILI Input Leakage Current 2 µA ILO Output Leakage Current ±2 µA ICC VCC Supply Current (Active) C = 0.1 VCC/0.9 VCC , @ 2 MHz, Q = Open 2 mA S = VCC, VIN = VSS or VCC, VCC = 5.5V 50 µA S = VCC, VIN = VSS or VCC, VCC = 3V 10 µA ICC1 4/16 Parameter VCC Supply Current (Standby) VIL Input Low Voltage – 0.3 0.3 VCC V VIH Input High Voltage 0.7 VCC VCC + 1 V VOL Output Low Voltage IOL = 2mA 0.2 VCC V VOH Output High Voltage IOH = –2mA 0.8 VCC V ST95P02 Table 5. AC Characteristics (TA = 0 to 70°C or –40 to 85°C; VCC = 3V to 5.5V) Symbol Alt Parameter Test Condition Min Max Unit fC fC Clock Frequency D.C. 2 MHz tSLCH tSU S Setup Time 50 ns tCLSH tSH S Hold Time 50 ns tCH tWH Clock High Time 200 ns tCL tWL Clock Low Time 300 ns tCLCH tRC Clock Rise Time 1 µs tCHCL tFC Clock Fall Time 1 µs tDVCH tDSU Data In Setup Time 50 ns tCHDX tDH Data In Hold Time 50 ns tDLDH tRI Data In Rise Time 1 µs tDHDL tFI Data In Fall Time 1 µs tHXCH tHSU HOLD Setup Time 50 ns tCLHX tHH HOLD Hold Time 50 ns tSHSL tCS S Deselect Time 4.5V < VCC < 5.5V 200 ns 3V < VCC < 4.5V 250 ns tSHQZ tDIS tQVCL tV tCLQX tHO Output Hold Time tQLQH tRO Output Rise Time 100 ns tQHQL tFO Output Fall Time 100 ns tHHQX tLZ HOLD High to Output Low-Z 150 ns tHLQZ tHZ HOLD Low to Output High-Z 150 ns (1) tW Write Cycle Time 10 ms tW Output Disable Time 150 ns Clock Low to Output Valid 300 ns 0 ns Note: 1. Not enough characterisation data were available on this parameter at the time of issue this Data Sheet. The typical value is well below 5ms, the maximum value will be reviewed and lowered when sufficient data is available. 5/16 ST95P02 Figure 5. Output Timing S tCH C tCL tCLQX tSHQZ tQVCL MSB OUT Q MSB-1 OUT LSB OUT tQLQH tQHQL D ADDR.LSB IN AI01070B Figure 6. Serial Input Timing tSHSL S tSLCH tCLSH C tDVCH tCHCL tCHDX D tCLCH MSB IN HIGH IMPEDANCE LSB IN tDLDH tDHDL Q AI01071 6/16 ST95P02 Figure 7. Hold Timing S tHXCH tCLHX tHXCH C tCLHX tHLQZ tHHQX Q D HOLD AI01072B Write Protect (W). This pin is for hardware write protect. When W is low, non-volatile writes to the ST95P02 are disabled but any other operation stays enabled. When W is high, all operations including non-volatile writes are available. W going low at any time before the last bit D0 of the data stream will reset the write enable latch and prevent programming. No action on W or on the write enable latch can interrupt a write cycle which has commenced. Hold (HOLD). The HOLD pin is used to pause serial communications with a ST95P02 without resetting the serial sequence. To take the Hold condition into account, the product must be selected (S = 0). Then the Hold state is validated by a high to low transition on HOLD when C is low. To resume the communications, HOLD is brought high when C is low. During Hold condition D, Q, and C are at a high impedance state. When the ST95P02 is under Hold condition, it is possible to deselect it. However, the serial communications will remain paused after a reselect, and the chip will be reset. OPERATIONS All instructions, addresses and data are shifted in and out of the chip MSB first. Data input (D) is sampled on the first rising edge of clock (C) after the chip select (S) goes low. Prior to any operation, a one-byte instruction code must be entered in the chip. This code is entered via the data input (D), and latched on the rising edge of the clock input (C). To enter an instruction code, the product must have been previously selected (S = low). Table 7 shows the instruction set and format for device operation. When an invalid instruction is sent (one not contained in Table 7), the chip is automatically deselected. Write Enable (WREN) and Write Disable (WRDI) The ST95P02 contains a write enable latch. This latch must be set prior to every WRITE or WRSR operation. The WREN instruction will set the latch and the WRDI instruction will reset the latch. The latch is reset under all the following conditions: – W pin is low – Power on – WRDI instruction executed – WRSR instruction executed – WRITE instruction executed As soon as the WREN or WRDI instruction is received by the ST95P02, the circuit executes the instruction and enters a wait mode until it is deselected. 7/16 ST95P02 Read Status Register (RDSR) The RDSR instruction provides access to the status register. The status register may be read at any time, even during a non-volatile write. As soon as the 8th bit of the status register is read out, the ST95P02 enters a wait mode (data on D are not decoded, Q is in Hi-Z) until it is deselected. The status register format is as follows: b7 1 b0 1 1 1 BP1 BP0 WEL WIP into four 512 bit blocks. The user may read the blocks but will be unable to write within the selected blocks. The blocks and respective WRSR control bits are shown in Table 6. When the WRSR instruction and the 8 bits of the Status Register are latched-in, the internal write cycle is then triggered by the rising edge of S. This rising edge of S must appear after the 8th bit of the Status Register content (it must not appear a 17th clock pulse before the rising edge of S), otherwise the internal write sequence is not performed. Read Operation BP1, BP0: Read and Write bits WEL, WIP: Read only bits. During a non-volatile write to the memory array, all bits BP1, BP0, WEL, WIP are valid and can be read. During a non volatile write to the status register, the only bits WEL and WIP are valid and can be read. The values of BP1 and BP0 read at that time correspond to the previous contents of the status register. The Write-In-Process (WIP) read only bit indicates whether the ST95P02 is busy with a write operation. When set to a ’1’ a write is in progress, when set to a ’0’ no write is in progress. The Write Enable Latch (WEL) read only bit indicates the status of the write enable latch. When set to a ’1’ the latch is set, when set to a ’0’ the latch is reset. The chip is first selected by putting S low. The serial one byte read instruction is followed by a one byte address (A7-A0), each bit being latched-in during the rising edge of the clock (C). Then, the data stored in the memory at the selected address is shifted out on the Q output pin; each bit being shifted out during the falling edge of the clock (C). The data stored in the memory at the next address can be read in sequence by continuing to provide clock pulses. The byte address is automatically incremented to the next higher address after each byte of data is shifted out. Table 6. Array Addresses Protect The Block Protect (BP0 and BP1) bits indicate the extent of the protection employed. These bits are set by the user issuing the WRSR instruction. These bits are non-volatile. Status Register Bits Array Addresses Protected BP1 BP0 0 0 none Write Status Register (WRSR) 0 1 C0h - FFh The WRSR instruction allows the user to select the size of protected memory. The ST95P02 is divided 1 0 80h - FFh 1 1 00h - FFh Table 7. Instruction Set Instruction 8/16 Description Instruction Format WREN Set Write Enable Latch 0000 0110 WRDI Reset Write Enable Latch 0000 0100 RDSR Read Status Register 0000 0101 WRSR Write Status Register 0000 0001 READ Read Data from Memory Array 0000 0011 WRITE Write Data to Memory Array 0000 0010 ST95P02 OPERATIONS (cont’d) When the highest address is reached (FFh), the address counter rolls over to 0h allowing the read cycle to be continued indefinitely. The read operation is terminated by deselecting the chip. The chip can be deselected at any time during data output. Any read attempt during a non-volatile write cycle will be rejected and will deselect the chip. Byte Write Operation Prior to any write attempt, the write enable latch must have been set by issuing the WREN instruction. First, the device is selected (S = low) and a serial WREN instruction byte is issued. Then, the product is deselected by taking S high. After the WREN instruction byte is sent, the ST95P02 will set the write enable latch and then remain in standby until it is deselected. Then, the write state is entered by selecting the chip, issuing a one byte address (A7-A0), and one byte of data. S must remain low for the entire duration of the operation. The product must be deselected just after the eigth bit of data has been latched in. If not, the write process is cancelled. As soon as the product is deselected, the self-timed write cycle is initiated. While the write is in progress, the status register may be read to check BP1, BP0, WEL and WIP. WIP is high during the self-timed write cycle. When the cycle is close to completion, the write enable latch is reset. Page Write Operation A maximum of 16 bytes of data may be written during one non-volatile write cycle. All 16 bytes must reside on the same page. The page write mode is the same as the byte write mode except that instead of deselecting after the first byte of data, up to 15 additional bytes can be shifted in prior to deselecting the chip. A page address begins with address xxxx 0000 and ends with xxxx 1111. If the address counter reaches xxxx 1111 and the clock continues, the counter will roll over to the first address of the page (xxxx 0000) and overwrite any previous written data. The programming cycle will only start if the S transition does occur at the clock low pulse just after the eigth bit of data of a word is received. Figure 8. Read Operation Sequence S 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 C INSTRUCTION BYTE ADDRESS D DATA OUT HIGH IMPEDANCE Q 7 6 5 4 3 2 1 0 MSB AI01259 9/16 ST95P02 Figure 9. Write Enable Latch Sequence S 0 1 2 3 4 5 6 7 C D HIGH IMPEDANCE Q AI01273 Figure 10. Write Operation Sequence S 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 C INSTRUCTION BYTE ADDRESS DATA BYTE 7 D 6 5 4 3 2 1 0 HIGH IMPEDANCE Q AI01260 10/16 ST95P02 Figure 11. Page Write Operation Sequence S 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 C INSTRUCTION BYTE ADDRESS DATA BYTE 1 7 D 6 5 4 3 2 1 0 7 143 142 141 140 139 138 137 136 15+8N 14+8N 13+8N 12+8N 11+8N 10+8N 9+8N 24 25 26 27 28 29 30 31 8+8N S C DATA BYTE N DATA BYTE 2 7 D 6 5 4 3 2 1 0 7 6 5 4 3 2 DATA BYTE 16 1 0 7 6 5 4 3 2 1 0 AI01261 Figure 12. RDSR: Read Status Register Sequence S 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 C INSTRUCTION D STATUS REG. OUT HIGH IMPEDANCE Q 7 6 5 4 3 2 1 0 MSB AI01116B 11/16 ST95P02 Figure 13. WRSR: Write Status Register Sequence S 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 C INSTRUCTION STATUS REG. D HIGH IMPEDANCE Q AI01117B POWER ON STATE After a Power up the ST95P02 is in the following state: – The device is in the low power standby state. – The chip is deselected. – The chip is not in hold condition. – The write enable latch is reset. – BP1 and BP0 are unchanged (non-volatile bits). DATA PROTECTION AND PROTOCOL SAFETY – All inputs are protected against noise, see Table 3. – Non valid S and HOLD transitions are not taken into account. – S must come high at the proper clock count in order to start a non-volatile write cycle (in the memory array or in the cycle status register). The Chip Select S must rise during the clock 12/16 – – – – pulse following the introduction of a multiple of 8 bits. Access to the memory array during non-volatile programming cycle is cancelled and the chip is automatically deselected; however, the programming cycle continues. After either of the following operations (WREN, WRDI, RDSR) is completed, the chip enters a wait state and waits for a deselect. The write enable latch is reset upon power-up. The write enable latch is reset when W is brought low. INITIAL DELIVERY STATE The device is delivered with the memory array in a fully erased state (all data set at all "1’s" or FFh). The block protect bits are initialized to 00. ST95P02 ORDERING INFORMATION SCHEME Example: ST95P02 Data Strobe P* D Q M Package B PSDIP8 0.25 mm Frame M SO8 150mil Width 6 TR Temperature Range 1 0 to 70 °C 6 –40 to 85 °C 3* –40 to 125 °C Option TR Tape & Reel Packing Notes: P * Data In strobed on rising edge of the clock (C) and Data Out synchronized from the falling edge of the clock. 3 * Temperature range on special request only. For a list of available options (Package, Temperature Range, etc...) refer to the current Memory Shortform catalogue. For further information on any aspect of this device, please contact the SGS-THOMSON Sales Office nearest to you. 13/16 ST95P02 PSDIP8 - 8 pin Plastic Skinny DIP, 0.25mm lead frame mm Symb Typ inches Min Max A 3.90 A1 Min Max 5.90 0.154 0.232 0.49 – 0.019 – A2 3.30 5.30 0.130 0.209 B 0.36 0.56 0.014 0.022 B1 1.15 1.65 0.045 0.065 C 0.20 0.36 0.008 0.014 D 9.20 9.90 0.362 0.390 – – – – 6.00 6.70 0.236 0.264 – – – – 7.80 – 0.307 – E 7.62 E1 e1 2.54 eA eB Typ 0.300 0.100 10.00 L 3.00 N 8 0.394 3.80 0.118 8 CP 0.10 0.004 PSDIP8 A2 A1 B A L e1 eA eB B1 D C N E1 E 1 PSDIP-a Drawing is not to scale 14/16 0.150 ST95P02 SO8 - 8 lead Plastic Small Outline, 150 mils body width mm Symb Typ inches Min Max A 1.35 A1 Min Max 1.75 0.053 0.069 0.10 0.25 0.004 0.010 B 0.33 0.51 0.013 0.020 C 0.19 0.25 0.007 0.010 D 4.80 5.00 0.189 0.197 E 3.80 4.00 0.150 0.157 – – – – H 5.80 6.20 0.228 0.244 h 0.25 0.50 0.010 0.020 L 0.40 0.90 0.016 0.035 α 0° 8° 0° 8° N 8 e 1.27 CP Typ 0.050 8 0.10 0.004 SO8 h x 45˚ A C B CP e D N E H 1 A1 α L SO-a Drawing is not to scale 15/16 ST95P02 Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. SGS-THOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of SGS-THOMSON Microelectronics. © 1996 SGS-THOMSON Microelectronics - All Rights Reserved SGS-THOMSON Microelectronics GROUP OF COMPANIES Australia - Brazil - China - France - Germany - Hong Kong - Italy - Japan - Korea - Malaysia - Malta - Morocco - The Netherlands Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A. 16/16