STMICROELECTRONICS M95M01

M95M01-R
1 Mbit serial SPI bus EEPROM
with high speed clock
Preliminary Data
Features
■
Compatible with SPI bus serial interface
(Positive Clock SPI modes)
■
Schmitt trigger inputs for enhanced noise
margin
■
Single supply voltage: 1.8 V to 5.5 V
■
High speed
– 5 MHz clock rate
– 5 ms Write time
■
Status Register
■
Hardware Protection of the Status Register
■
Byte and Page Write (up to 256 bytes)
■
Self-timed programming cycle
■
Adjustable size read-only EEPROM area
■
Enhanced ESD Protection
■
More than 1 000 000 Write cycles
■
More than 40-year data retention
■
Packages
– ECOPACK® (RoHS compliant)
July 2007
SO8N (MN)
150 mils width
SO8W (MW)
208 mils width
Rev 4
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to
change without notice.
1/39
www.st.com
1
Contents
M95M01-R
Contents
1
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2
Signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3
2.1
Serial Data Output (Q) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.2
Serial Data Input (D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.3
Serial Clock (C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.4
Chip Select (S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.5
Hold (HOLD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.6
Write Protect (W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.7
VCC supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.8
VSS ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Connecting to the SPI bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.1
4
SPI modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Operating features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.1
Supply voltage (VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.1.1
4.1.2
Operating supply voltage VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Power-up conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.1.3
Device reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.1.4
Power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.2
Active Power and Standby Power modes . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.3
Hold condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.4
Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4.5
Data protection and protocol control . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5
Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
6
Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
6.1
Write Enable (WREN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
6.2
Write Disable (WRDI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
6.3
Read Status Register (RDSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
6.3.1
2/39
WIP bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
M95M01-R
Contents
6.3.2
WEL bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
6.3.3
BP1, BP0 bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
6.3.4
SRWD bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
6.4
Write Status Register (WRSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
6.5
Read from Memory Array (READ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
6.6
Write to Memory Array (WRITE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
7
ECC (error correction code) and write cycling . . . . . . . . . . . . . . . . . . . 27
8
Power-up and delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
8.1
Power-up state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
8.2
Initial delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
9
Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
10
DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
11
Package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
12
Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
13
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
3/39
List of tables
M95M01-R
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
4/39
Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Write-protected block size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Status Register format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Protection modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Address range bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
AC measurement conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
DC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
AC characteristics (VCC ≥ 2.5 V and –40°C ≤ TA ≤ 85 °C) . . . . . . . . . . . . . . . . . . . . . . . . . 31
AC characteristics (VCC < 2.5 V and –40°C ≤ TA ≤ 85 °C) . . . . . . . . . . . . . . . . . . . . . . . . . 32
SO8 narrow – 8 lead plastic small outline, 150 mils body width,
package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
SO8W – 8 lead plastic small outline, 208 mils body width, package
mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Ordering information scheme(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
M95M01-R
List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
SO and TSSOP connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Bus master and memory devices on the SPI bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
SPI modes supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Hold condition activation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Write Enable (WREN) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Write Disable (WRDI) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Read Status Register (RDSR) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Write Status Register (WRSR) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Read from Memory Array (READ) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Byte Write (WRITE) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Page Write (WRITE) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
AC measurement I/O waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Serial input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Hold timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Output timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
SO8 narrow – 8 lead plastic small outline, 150 mils body width, package outline . . . . . . . 35
SO8W – 8 lead plastic small outline, 208 mils body width, package outline. . . . . . . . . . . . 36
5/39
Description
1
M95M01-R
Description
The M95M01-R is an electrically erasable programmable memory (EEPROM) device. It is
accessed by a high speed SPI-compatible bus. The memory array is organized as 131 072
× 8 bit. It can also be seen as 512 pages of 256 bytes each.
The device is accessed by a simple serial interface that is SPI-compatible. The bus signals
are C, D and Q, as shown in Table 1 and Figure 1.
The device is selected when Chip Select (S) is taken Low. Communications with the device
can be interrupted using Hold (HOLD).
In order to meet environmental requirements, ST offers the M95M01-R in ECOPACK®
packages. ECOPACK® packages are Lead-free and RoHS compliant.
ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com.
Figure 1.
Logic diagram
VCC
D
Q
C
S
M95xxx
W
HOLD
VSS
AI01789C
Table 1.
Signal names
Signal name
6/39
Function
Direction
C
Serial Clock
Input
D
Serial Data Input
Input
Q
Serial Data Output
Output
S
Chip Select
Input
W
Write Protect
Input
HOLD
Hold
Input
VCC
Supply voltage
VSS
Ground
M95M01-R
Description
Figure 2.
SO and TSSOP connections
M95xxx
S
Q
W
VSS
1
2
3
4
8
7
6
5
VCC
HOLD
C
D
AI01790D
1. See Section 11: Package mechanical for package dimensions, and how to identify pin-1.
7/39
Signal description
2
M95M01-R
Signal description
During all operations, VCC must be held stable and within the specified valid range:
VCC(min) to VCC(max).
All of the input and output signals must be held High or Low (according to voltages of VIH,
VOH, VIL or VOL, as specified in Table 11). These signals are described next.
2.1
Serial Data Output (Q)
This output signal is used to transfer data serially out of the device. Data is shifted out on the
falling edge of Serial Clock (C).
2.2
Serial Data Input (D)
This input signal is used to transfer data serially into the device. It receives instructions,
addresses, and the data to be written. Values are latched on the rising edge of Serial Clock
(C).
2.3
Serial Clock (C)
This input signal provides the timing of the serial interface. Instructions, addresses, or data
present at Serial Data Input (D) are latched on the rising edge of Serial Clock (C). Data on
Serial Data Output (Q) changes after the falling edge of Serial Clock (C).
2.4
Chip Select (S)
When this input signal is High, the device is deselected and Serial Data Output (Q) is at high
impedance. Unless an internal Write cycle is in progress, the device will be in the Standby
Power mode. Driving Chip Select (S) Low selects the device, placing it in the Active Power
mode.
After Power-up, a falling edge on Chip Select (S) is required prior to the start of any
instruction.
2.5
Hold (HOLD)
The Hold (HOLD) signal is used to pause any serial communications with the device without
deselecting the device.
During the Hold condition, the Serial Data Output (Q) is high impedance, and Serial Data
Input (D) and Serial Clock (C) are Don’t Care.
To start the Hold condition, the device must be selected, with Chip Select (S) driven Low.
8/39
M95M01-R
2.6
Signal description
Write Protect (W)
The main purpose of this input signal is to freeze the size of the area of memory that is
protected against Write instructions (as specified by the values in the BP1 and BP0 bits of
the Status Register).
This pin must be driven either High or Low, and must be stable during all write instructions.
2.7
VCC supply voltage
VCC is the supply voltage.
2.8
VSS ground
VSS is the reference for the VCC supply voltage.
9/39
Connecting to the SPI bus
3
M95M01-R
Connecting to the SPI bus
These devices are fully compatible with the SPI protocol.
All instructions, addresses and input data bytes are shifted in to the device, most significant
bit first. The Serial Data Input (D) is sampled on the first rising edge of the Serial Clock (C)
after Chip Select (S) goes Low.
All output data bytes are shifted out of the device, most significant bit first. The Serial Data
Output (Q) is latched on the first falling edge of the Serial Clock (C) after the instruction
(such as the Read from Memory Array and Read Status Register instructions) have been
clocked into the device.
Figure 3.
Bus master and memory devices on the SPI bus
VSS
VCC
R
SDO
SPI Interface with
(CPOL, CPHA) =
(0, 0) or (1, 1)
SDI
SCK
VCC
C Q D
SPI Bus Master
SPI Memory
Device
R
CS3
VCC
C Q D
VSS
C Q D
VCC
VSS
SPI Memory
Device
R
VSS
SPI Memory
Device
R
CS2 CS1
S
W
HOLD
S
W
HOLD
S
W
HOLD
AI12836b
1. The Write Protect (W) and Hold (HOLD) signals should be driven, High or Low as appropriate.
Figure 3 shows an example of three memory devices connected to an MCU, on an SPI bus.
Only one device is selected at a time, so only one device drives the Serial Data Output (Q)
line at a time, the other devices are high impedance.
The pull-up resistor R (represented in Figure 3) ensures that no device is selected if the Bus
Master leaves the S line in the high impedance state.
In applications where the Bus Master might enter a state where all inputs/outputs SPI lines
are in high impedance at the same time (for example, if the Bus Master is reset during the
transmission of an instruction), the clock line (C) must be connected to an external pulldown resistor so that, if all inputs/outputs become high impedance, the C line is pulled Low
(while the S line is pulled High). This ensures that S and C do not become High at the same
time, and so, that the tSHCH requirement is met.
10/39
M95M01-R
3.1
Connecting to the SPI bus
SPI modes
These devices can be driven by a microcontroller with its SPI peripheral running in either of
the two following modes:
●
CPOL=0, CPHA=0
●
CPOL=1, CPHA=1
For these two modes, input data is latched in on the rising edge of Serial Clock (C), and
output data is available from the falling edge of Serial Clock (C).
The difference between the two modes, as shown in Figure 4, is the clock polarity when the
bus master is in Standby mode and not transferring data:
●
C remains at 0 for (CPOL=0, CPHA=0)
●
C remains at 1 for (CPOL=1, CPHA=1)
Figure 4.
SPI modes supported
CPOL CPHA
0
0
C
1
1
C
D
Q
MSB
MSB
AI01438B
11/39
Operating features
M95M01-R
4
Operating features
4.1
Supply voltage (VCC)
4.1.1
Operating supply voltage VCC
Prior to selecting the memory and issuing instructions to it, a valid and stable VCC voltage
within the specified [VCC(min), VCC(max)] range must be applied (see Table 8.). In order to
secure a stable DC supply voltage, it is recommended to decouple the VCC line with a
suitable capacitor (usually of the order of 10 nF to 100 nF) close to the VCC/VSS package
pins.
This voltage must remain stable and valid until the end of the transmission of the instruction
and, for a Write instruction, until the completion of the internal write cycle (tW).
4.1.2
Power-up conditions
When the power supply is turned on, VCC rises continuously from VSS to VCC. During this
time, the Chip Select (S) line is not allowed to float but should follow the VCC voltage, it is
therefore recommended to connect the S line to VCC via a suitable pull-up resistor.
In addition, the Chip Select (S) input offers a built-in safety feature, as the S input is edge
sensitive as well as level sensitive: after power-up, the device does not become selected
until a falling edge has first been detected on Chip Select (S). This ensures that Chip Select
(S) must have been High, prior to going Low to start the first operation.
The VCC rise time must not vary faster than 1 V/µs.
4.1.3
Device reset
In order to prevent inadvertent Write operations during power-up (continuous rise of VCC), a
power on reset (POR) circuit is included. At Power-up, the device does not respond to any
instruction until VCC has reached the power on reset threshold voltage (this threshold is
lower than the minimum VCC operating voltage defined in Table 8).
When VCC has passed the POR threshold, the device is reset and in the following state:
12/39
●
Standby Power mode
●
deselected (at next Power-up, a falling edge is required on Chip Select (S) before any
instructions can be started)
●
not in the Hold condition
●
Status Register:
–
the Write Enable Latch (WEL) is reset to 0
–
Write In Progress (WIP) is reset to 0. The SRWD, BP1 and BP0 bits of the Status
Register are unchanged from the previous power-down (they are non-volatile bits)
M95M01-R
4.1.4
Operating features
Power-down
At Power-down (continuous decrease in VCC), as soon as VCC drops from the normal
operating voltage to below the power on reset threshold voltage, the device stops
responding to any instruction sent to it.
During Power-down, the device must be deselected (Chip Select (S) should be allowed to
follow the voltage applied on VCC) and in Standby Power mode (that is there should be no
internal Write cycle in progress).
4.2
Active Power and Standby Power modes
When Chip Select (S) is Low, the device is selected, and in the Active Power mode. The
device consumes ICC, as specified in Table 11.
When Chip Select (S) is High, the device is deselected. If a Write cycle is not currently in
progress, the device then goes in to the Standby Power mode, and the device consumption
drops to ICC1.
4.3
Hold condition
The Hold (HOLD) signal is used to pause any serial communications with the device without
resetting the clocking sequence.
During the Hold condition, the Serial Data Output (Q) is high impedance, and Serial Data
Input (D) and Serial Clock (C) are Don’t Care.
To enter the Hold condition, the device must be selected, with Chip Select (S) Low.
Normally, the device is kept selected, for the whole duration of the Hold condition.
Deselecting the device while it is in the Hold condition, has the effect of resetting the state of
the device, and this mechanism can be used if it is required to reset any processes that had
been in progress.
The Hold condition starts when the Hold (HOLD) signal is driven Low at the same time as
Serial Clock (C) already being Low (as shown in Figure 5).
The Hold condition ends when the Hold (HOLD) signal is driven High at the same time as
Serial Clock (C) already being Low.
Figure 5 also shows what happens if the rising and falling edges are not timed to coincide
with Serial Clock (C) being Low.
13/39
Operating features
Figure 5.
M95M01-R
Hold condition activation
C
HOLD
Hold
Condition
Hold
Condition
AI02029D
4.4
Status Register
Figure 6 shows the position of the Status Register in the control logic of the device. The
Status Register contains a number of status and control bits that can be read or set (as
appropriate) by specific instructions. See Section 6.3: Read Status Register (RDSR) for a
detailed description of the Status Register bits
4.5
Data protection and protocol control
Non-volatile memory devices can be used in environments that are particularly noisy, and
within applications that could experience problems if memory bytes are corrupted.
Consequently, the device features the following data protection mechanisms:
●
Write and Write Status Register instructions are checked that they consist of a number
of clock pulses that is a multiple of eight, before they are accepted for execution.
●
All instructions that modify data must be preceded by a Write Enable (WREN)
instruction to set the Write Enable Latch (WEL) bit. This bit is returned to its reset state
by the following events:
–
Power-up
–
Write Disable (WRDI) instruction completion
–
Write Status Register (WRSR) instruction completion
–
Write (WRITE) instruction completion
●
The Block Protect (BP1, BP0) bits in the Status Register allow part of the memory to be
configured as read-only.
●
The Write Protect (W) signal allows the Block Protect (BP1, BP0) bits of the Status
Register to be protected.
For any instruction to be accepted, and executed, Chip Select (S) must be driven High after
the rising edge of Serial Clock (C) for the last bit of the instruction, and before the next rising
edge of Serial Clock (C).
Two points need to be noted in the previous sentence:
14/39
●
The ‘last bit of the instruction’ can be the eighth bit of the instruction code, or the eighth
bit of a data byte, depending on the instruction (except for Read Status Register
(RDSR) and Read (READ) instructions).
●
The ‘next rising edge of Serial Clock (C)’ might (or might not) be the next bus
transaction for some other device on the SPI bus.
M95M01-R
Operating features
Table 2.
Write-protected block size
Status Register bits
Protected block
Array addresses
protected
BP1
BP0
0
0
none
none
0
1
Upper quarter
1 8000h - 1 FFFFh
1
0
Upper half
1 0000h - 1 FFFFh
1
1
Whole memory
0 0000h - 1 FFFFh
15/39
Memory organization
5
M95M01-R
Memory organization
The memory is organized as shown in Figure 6.
Figure 6.
Block diagram
HOLD
W
High Voltage
Generator
Control Logic
S
C
D
I/O Shift Register
Q
Address Register
and Counter
Data
Register
Size of the
Read only
EEPROM
area
Y Decoder
Status
Register
1 Page
X Decoder
AI01272C
16/39
M95M01-R
6
Instructions
Instructions
Each instruction starts with a single-byte code, as summarized in Table 3.
If an invalid instruction is sent (one not contained in Table 3), the device automatically
deselects itself.
Table 3.
Instruction set
Instruction
6.1
Description
Instruction format
WREN
Write Enable
0000 0110
WRDI
Write Disable
0000 0100
RDSR
Read Status Register
0000 0101
WRSR
Write Status Register
0000 0001
READ
Read from Memory Array
0000 0011
WRITE
Write to Memory Array
0000 0010
Write Enable (WREN)
The Write Enable Latch (WEL) bit must be set prior to each WRITE and WRSR instruction.
The only way to do this is to send a Write Enable instruction to the device.
As shown in Figure 7, to send this instruction to the device, Chip Select (S) is driven Low,
and the bits of the instruction byte are shifted in, on Serial Data Input (D). The device then
enters a wait state. It waits for a the device to be deselected, by Chip Select (S) being driven
High.
Figure 7.
Write Enable (WREN) sequence
S
0
1
2
3
4
5
6
7
C
Instruction
D
High Impedance
Q
AI02281E
17/39
Instructions
6.2
M95M01-R
Write Disable (WRDI)
One way of resetting the Write Enable Latch (WEL) bit is to send a Write Disable instruction
to the device.
As shown in Figure 8, to send this instruction to the device, Chip Select (S) is driven Low,
and the bits of the instruction byte are shifted in, on Serial Data Input (D).
The device then enters a wait state. It waits for a the device to be deselected, by Chip Select
(S) being driven High.
The Write Enable Latch (WEL) bit, in fact, becomes reset by any of the following events:
●
Power-up
●
WRDI instruction execution
●
WRSR instruction completion
●
WRITE instruction completion.
Figure 8.
Write Disable (WRDI) sequence
S
0
1
2
3
4
5
6
7
C
Instruction
D
High Impedance
Q
AI03750D
18/39
M95M01-R
6.3
Instructions
Read Status Register (RDSR)
The Read Status Register (RDSR) instruction allows the Status Register to be read. The
Status Register may be read at any time, even while a Write or Write Status Register cycle
is in progress. When one of these cycles is in progress, it is recommended to check the
Write In Progress (WIP) bit before sending a new instruction to the device. It is also possible
to read the Status Register continuously, as shown in Figure 9.
The status and control bits of the Status Register are as follows:
6.3.1
WIP bit
The Write In Progress (WIP) bit indicates whether the memory is busy with a Write or Write
Status Register cycle. When set to 1, such a cycle is in progress, when reset to 0 no such
cycle is in progress.
6.3.2
WEL bit
The Write Enable Latch (WEL) bit indicates the status of the internal Write Enable Latch.
When set to 1 the internal Write Enable Latch is set, when set to 0 the internal Write Enable
Latch is reset and no Write or Write Status Register instruction is accepted.
6.3.3
BP1, BP0 bits
The Block Protect (BP1, BP0) bits are non-volatile. They define the size of the area to be
software protected against Write instructions. These bits are written with the Write Status
Register (WRSR) instruction. When one or both of the Block Protect (BP1, BP0) bits is set to
1, the relevant memory area (as defined in Table 4) becomes protected against Write
(WRITE) instructions. The Block Protect (BP1, BP0) bits can be written provided that the
Hardware Protected mode has not been set.
6.3.4
SRWD bit
The Status Register Write Disable (SRWD) bit is operated in conjunction with the Write
Protect (W) signal. The Status Register Write Disable (SRWD) bit and Write Protect (W)
signal allow the device to be put in the Hardware Protected mode (when the Status Register
Write Disable (SRWD) bit is set to 1, and Write Protect (W) is driven Low). In this mode, the
non-volatile bits of the Status Register (SRWD, BP1, BP0) become read-only bits and the
Write Status Register (WRSR) instruction is no longer accepted for execution.
Table 4.
Status Register format
b7
SRWD
b0
0
0
0
BP1
BP0
WEL
WIP
Status Register Write Protect
Block Protect Bits
Write Enable Latch Bit
Write In Progress Bit
19/39
Instructions
M95M01-R
Figure 9.
Read Status Register (RDSR) sequence
S
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
C
Instruction
D
Status Register Out
Status Register Out
High Impedance
Q
7
MSB
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
MSB
AI02031E
20/39
M95M01-R
6.4
Instructions
Write Status Register (WRSR)
The Write Status Register (WRSR) instruction allows new values to be written to the Status
Register. Before it can be accepted, a Write Enable (WREN) instruction must previously
have been executed. After the Write Enable (WREN) instruction has been decoded and
executed, the device sets the Write Enable Latch (WEL).
The Write Status Register (WRSR) instruction is entered by driving Chip Select (S) Low,
followed by the instruction code and the data byte on Serial Data Input (D).
The instruction sequence is shown in Figure 10.
The Write Status Register (WRSR) instruction has no effect on b6, b5, b4, b1 and b0 of the
Status Register. b6, b5 and b4 are always read as 0.
Chip Select (S) must be driven High after the rising edge of Serial Clock (C) that latches in
the eighth bit of the data byte, and before the next rising edge of Serial Clock (C). Otherwise,
the Write Status Register (WRSR) instruction is not executed. As soon as Chip Select (S) is
driven High, the self-timed Write Status Register cycle (whose duration is tW) is initiated.
While the Write Status Register cycle is in progress, the Status Register may still be read to
check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1
during the self-timed Write Status Register cycle, and is 0 when it is completed. When the
cycle is completed, the Write Enable Latch (WEL) is reset.
Figure 10. Write Status Register (WRSR) sequence
S
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
C
Instruction
Status
Register In
7
D
High Impedance
6
5
4
3
2
1
0
MSB
Q
AI02282D
21/39
Instructions
M95M01-R
Table 5.
Protection modes
W
SRWD
Signal
Bit
1
0
0
0
1
1
0
1
Mode
Write Protection of the
Status Register
Memory content
Protected area(1)
Unprotected area(1)
Status Register is Writable
Software (if the WREN instruction
Protected has set the WEL bit)
Write Protected
(SPM) The values in the BP1 and
BP0 bits can be changed
Ready to accept
Write instructions
Status Register is
Hardware Hardware write protected
Protected The values in the BP1 and Write Protected
(HPM) BP0 bits cannot be
changed
Ready to accept
Write instructions
1. As defined by the values in the Block Protect (BP1, BP0) bits of the Status Register, as shown in Table 5.
The Write Status Register (WRSR) instruction allows the user to change the values of the
Block Protect (BP1, BP0) bits, to define the size of the area that is to be treated as readonly, as defined in Table 4.
The Write Status Register (WRSR) instruction also allows the user to set or reset the Status
Register Write Disable (SRWD) bit in accordance with the Write Protect (W) signal. The
Status Register Write Disable (SRWD) bit and Write Protect (W) signal allow the device to
be put in the Hardware Protected Mode (HPM). The Write Status Register (WRSR)
instruction is not executed once the Hardware Protected Mode (HPM) is entered.
The contents of the Status Register Write Disable (SRWD) and Block Protect (BP1, BP0)
bits are frozen at their current values from just before the start of the execution of Write
Status Register (WRSR) instruction. The new, updated, values take effect at the moment of
completion of the execution of Write Status Register (WRSR) instruction.
The protection features of the device are summarized in Table 2.
When the Status Register Write Disable (SRWD) bit of the Status Register is 0 (its initial
delivery state), it is possible to write to the Status Register provided that the Write Enable
Latch (WEL) bit has previously been set by a Write Enable (WREN) instruction, regardless
of the whether Write Protect (W) is driven High or Low.
When the Status Register Write Disable (SRWD) bit of the Status Register is set to 1, two
cases need to be considered, depending on the state of Write Protect (W):
22/39
●
If Write Protect (W) is driven High, it is possible to write to the Status Register provided
that the Write Enable Latch (WEL) bit has previously been set by a Write Enable
(WREN) instruction.
●
If Write Protect (W) is driven Low, it is not possible to write to the Status Register even
if the Write Enable Latch (WEL) bit has previously been set by a Write Enable (WREN)
instruction. (Attempts to write to the Status Register are rejected, and are not accepted
for execution). As a consequence, all the data bytes in the memory area that are
software protected (SPM) by the Block Protect (BP1, BP0) bits of the Status Register,
are also hardware protected against data modification.
M95M01-R
Instructions
Regardless of the order of the two events, the Hardware Protected Mode (HPM) can be
entered:
●
by setting the Status Register Write Disable (SRWD) bit after driving Write Protect (W)
Low
●
or by driving Write Protect (W) Low after setting the Status Register Write Disable
(SRWD) bit.
The only way to exit the Hardware Protected Mode (HPM) once entered is to pull Write
Protect (W) High.
If Write Protect (W) is permanently tied High, the Hardware Protected Mode (HPM) can
never be activated, and only the Software Protected Mode (SPM), using the Block Protect
(BP1, BP0) bits of the Status Register, can be used.
23/39
Instructions
6.5
M95M01-R
Read from Memory Array (READ)
As shown in Figure 11, to send this instruction to the device, Chip Select (S) is first driven
Low. The bits of the instruction byte and address bytes are then shifted in, on Serial Data
Input (D). The address is loaded into an internal address register, and the byte of data at
that address is shifted out, on Serial Data Output (Q).
If Chip Select (S) continues to be driven Low, the internal address register is automatically
incremented, and the byte of data at the new address is shifted out.
When the highest address is reached, the address counter rolls over to zero, allowing the
Read cycle to be continued indefinitely. The whole memory can, therefore, be read with a
single READ instruction.
The Read cycle is terminated by driving Chip Select (S) High. The rising edge of the Chip
Select (S) signal can occur at any time during the cycle.
The first byte addressed can be any byte within any page.
The instruction is not accepted, and is not executed, if a Write cycle is currently in progress.
Figure 11. Read from Memory Array (READ) sequence
S
0
1
2
3
4
5
6
7
8
9 10
28 29 30 31 32 33 34 35 36 37 38 39
C
Instruction
24-bit address
23 22 21
D
3
2
1
0
MSB
Data Out 1
High Impedance
7
Q
6
5
4
3
2
Data Out 2
1
0
7
MSB
AI13878
1. As shown in Table 6, the most significant address bits are Don’t Care.
Table 6.
Address range bits(1)
M95M01-R
Address bits
1. Bits A23 to A17 are Don’t Care.
24/39
A16-A0
M95M01-R
6.6
Instructions
Write to Memory Array (WRITE)
As shown in Figure 12, to send this instruction to the device, Chip Select (S) is first driven
Low. The bits of the instruction byte, address byte, and at least one data byte are then
shifted in, on Serial Data Input (D).
The instruction is terminated by driving Chip Select (S) High at a byte boundary of the input
data. In the case of Figure 12, this occurs after the eighth bit of the data byte has been
latched in, indicating that the instruction is being used to write a single byte. The self-timed
Write cycle starts, and continues for a period tWC (as specified in Table 13), at the end of
which the Write in Progress (WIP) bit is reset to 0.
If, though, Chip Select (S) continues to be driven Low, as shown in Figure 13, the next byte
of input data is shifted in, so that more than a single byte, starting from the given address
towards the end of the same page, can be written in a single internal Write cycle. The selftimed Write cycle starts, and continues, for a period tWC (as specified in Table 13), at the
end of which the Write in Progress (WIP) bit is reset to 0.
Each time a new data byte is shifted in, the least significant bits of the internal address
counter are incremented. If the number of data bytes sent to the device exceeds the page
boundary, the internal address counter rolls over to the beginning of the page, and the
previous data there are overwritten with the incoming data. (The page size is 256 bytes).
The instruction is not accepted, and is not executed, under the following conditions:
●
if the Write Enable Latch (WEL) bit has not been set to 1 (by executing a Write Enable
instruction just before)
●
if a Write cycle is already in progress
●
if the device has not been deselected, by Chip Select (S) being driven High, at a byte
boundary (after the eighth bit, b0, of the last data byte that has been latched in)
●
if the addressed page is in the region protected by the Block Protect (BP1 and BP0)
bits.
Figure 12. Byte Write (WRITE) sequence
S
0
1
2
3
4
5
6
7
8
9 10
28 29 30 31 32 33 34 35 36 37 38 39
C
Instruction
24-bit address
23 14 13
D
3
2
Data byte
1
0
7
6
5
4
3
2
1
0
High Impedance
Q
AI13879
1. As shown in Table 6, the most significant address bits are Don’t Care.
25/39
Instructions
M95M01-R
Figure 13. Page Write (WRITE) sequence
S
0
1
2
3
4
5
6
7
8
28 29 30 31 32 33 34 35 36 37 38 39
9 10
C
Instruction
24-bit address
15 14 13
D
3
2
Data byte 1
1
0
7
6
5
4
3
2
0
1
S
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
C
Data byte 2
D
7
6
5
4
3
2
Data byte 3
1
0
7
6
5
4
3
2
Data byte N
1
0
6
5
4
3
2
1
0
AI13880
1. As shown in Table 6, the most significant address bits are Don’t Care.
26/39
M95M01-R
7
ECC (error correction code) and write cycling
ECC (error correction code) and write cycling
The M95M01-R device offers an ECC (Error Correction Code) logic which compares each
4-byte word with its associated 6 EEPROM bits of ECC. As a result, if a single bit out of 4
bytes of data happens to be erroneous during a Read operation, the ECC detects it and
replaces it by the correct value. The read reliability is therefore much improved by the use of
this feature.
Note however that even if a single byte has to be written, 4 bytes are internally modified
(plus the ECC bits), that is, the addressed byte is cycled together with the other three bytes
making up the word. It is therefore recommended to write by words of 4 bytes in order to
benefit from the larger amount of Write cycles.
The M95M01-R device is qualified at 1 million (1 000 000) Write cycles, using a cycling
routine that writes to the device by multiples of 4-byte packets.
8
Power-up and delivery state
8.1
Power-up state
After Power-up, the device is in the following state:
●
Standby Power mode
●
Deselected (after Power-up, a falling edge is required on Chip Select (S) before any
instructions can be started).
●
Not in the Hold Condition
●
Write Enable Latch (WEL) is reset to 0
●
Write In Progress (WIP) is reset to 0
The SRWD, BP1 and BP0 bits of the Status Register are unchanged from the previous
power-down (they are non-volatile bits).
8.2
Initial delivery state
The device is delivered with the memory array set at all 1s (FFh). The Status Register Write
Disable (SRWD) and Block Protect (BP1 and BP0) bits are initialized to 0.
27/39
Maximum rating
9
M95M01-R
Maximum rating
Stressing the device outside the ratings listed in Table 7 may cause permanent damage to
the device. These are stress ratings only, and operation of the device at these, or any other
conditions outside those indicated in the Operating sections of this specification, is not
implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect
device reliability. Refer also to the STMicroelectronics SURE Program and other relevant
quality documents.
Table 7.
Absolute maximum ratings
Symbol
TA
TSTG
TLEAD
Parameter
Min.
Max.
Unit
Ambient operating temperature
–40
130
°C
Storage temperature
–65
150
°C
Lead temperature during soldering
See
note (1)
VO
Output voltage
–0.50
VCC+0.6
V
VI
Input voltage
–0.50
6.5
V
VCC
Supply voltage
–0.50
6.5
V
VESD
Electrostatic discharge voltage (Human Body
Model)(2)
–4000
4000
V
1. Compliant with JEDEC Std J-STD-020C (for small body, Sn-Pb or Pb assembly), the ST ECOPACK®
7191395 specification, and the European directive on Restrictions on Hazardous Substances (RoHS)
2002/95/EU
2. AEC-Q100-002 (compliant with JEDEC Std JESD22-A114A, C1=100pF, R1=1500Ω, R2=500Ω)
28/39
°C
M95M01-R
10
DC and AC parameters
DC and AC parameters
This section summarizes the operating and measurement conditions, and the DC and AC
characteristics of the device. The parameters in the DC and AC characteristic tables that
follow are derived from tests performed under the Measurement Conditions summarized in
the relevant tables. Designers should check that the operating conditions in their circuit
match the measurement conditions when relying on the quoted parameters.
Table 8.
Operating conditions
Symbol
VCC
TA
Table 9.
Parameter
Min.
Max.
Unit
Supply voltage
1.8
5.5
V
Ambient operating temperature
–40
85
°C
AC measurement conditions
Symbol
CL
Parameter
Min.
Load capacitance
Max.
100
Input rise and fall times
Unit
pF
50
ns
Input pulse voltages
0.2VCC to 0.8VCC
V
Input and output timing reference voltages
0.3VCC to 0.7VCC
V
Figure 14. AC measurement I/O waveform
Input Levels
Input and Output
Timing Reference Levels
0.8VCC
0.7VCC
0.3VCC
0.2VCC
AI00825B
Table 10.
Capacitance(1)
Symbol
COUT
CIN
Parameter
Max.
Unit
VOUT = 0 V
8
pF
Input capacitance (D)
VIN = 0 V
8
pF
Input capacitance (other pins)
VIN = 0 V
6
pF
Output capacitance (Q)
Test condition
Min.
1. Not 100% tested.
29/39
DC and AC parameters
Table 11.
Symbol
M95M01-R
DC characteristics(1)
Parameter
ILI
Input leakage current
ILO
Output leakage current
ICC
ICC0(2)
ICC1
Supply current (Read)
Supply current (Write)
Supply current (Standby
Power mode)
VIL
Input low voltage
VIH
Input high voltage
VOL
Output low voltage
VOH
Output high voltage
Test condition
Min
Max
Unit
VIN = VSS or VCC
±2
µA
S = VCC, VOUT = VSS or VCC
±2
µA
C = 0.1VCC/0.9VCC at 2 MHz,
VCC = 1.8 V, Q = open
1.5
mA
C = 0.1VCC/0.9VCC at 5 MHz,
VCC = 2.5 V, Q = open
4
mA
C = 0.1VCC/0.9VCC at 5 MHz,
VCC = 5 V, Q = open
5
mA
During tW, S = VCC,
1.8 V ≤ VCC < 2.5 V
3
mA
During tW, S = VCC,
2.5 V ≤ VCC ≤ 5.5 V
5
mA
S = VCC, VIN = VSS or VCC,
1.8 V ≤ VCC < 2.5 V
3
µA
S = VCC, VIN = VSS or VCC,
2.5 V ≤ VCC ≤ 5.5 V
5
µA
1.8 V ≤ VCC < 2.5 V
–0.45
0.25 VCC
2.5 V ≤ VCC ≤ 5.5 V
–0.45
0.3 VCC
1.8 V ≤ VCC < 2.5 V
0.75 VCC
VCC+1
2.5 V ≤ VCC ≤ 5.5 V
0.7 VCC
VCC+1
V
V
IOL = 0.15 mA, VCC = 1.8 V
0.3
V
VCC = 2.5 V, IOL = 1.5 mA or
VCC = 5 V, IOL = 2 mA
0.4
V
IOH = –0.1 mA, VCC = 1.8 V
VCC = 2.5 V, IOH = –0.4 mA or
VCC = 5 V, IOH = –2 mA
0.8 VCC
1. The information contained in this table is preliminary data. It is subject to change without previous notice.
2. Characterized value, not tested in production.
30/39
V
M95M01-R
DC and AC parameters
Table 12.
AC characteristics (VCC ≥ 2.5 V and –40°C ≤ TA ≤ 85 °C)
Test conditions specified in Table 9
Symbol
Alt.
fC
fSCK
Clock frequency
tSLCH
tCSS1
S active setup time
60
ns
tSHCH
tCSS2
S not active setup time
60
ns
tSHSL
tCS
S Deselect time
60
ns
tCHSH
tCSH
S active hold time
60
ns
S not active hold time
60
ns
tCHSL
Parameter
Min.
Max.
Unit
D.C.
5
MHz
tCH (1)
tCLH
Clock high time
90
ns
(1)
90
ns
tCLL
Clock low time
tCLCH
(2)
tRC
Clock rise time
2
µs
tCHCL
(2)
tFC
Clock fall time
2
µs
tCL
tDVCH
tDSU
Data in setup time
20
ns
tCHDX
tDH
Data in hold time
20
ns
tHHCH
Clock low hold time after HOLD not active
60
ns
tHLCH
Clock low hold time after HOLD active
60
ns
tCLHL
Clock low set-up time before HOLD active
0
ns
tCLHH
Clock low set-up time before HOLD not active
0
ns
tSHQZ
(2)
tDIS
tCLQV
tV
tCLQX
Output disable time
80
ns
Clock low to output valid
80
ns
tHO
Output hold time
tQLQH
(2)
0
ns
tRO
Output rise time
80
ns
tQHQL
(2)
tFO
Output fall time
80
ns
tHHQV
tLZ
HOLD high to output valid
80
ns
tHLQZ (2)
tHZ
HOLD low to output High-Z
80
ns
tW
tWC
Write time
5
ms
1. tCH + tCL must never be less than the shortest possible clock period, 1 / fC(max)
2. Value guaranteed by characterization, not 100% tested in production.
31/39
DC and AC parameters
Table 13.
M95M01-R
AC characteristics (VCC < 2.5 V and –40°C ≤ TA ≤ 85 °C)
Test conditions specified in Table 9
Symbol
Alt.
fC
fSCK
tSLCH
Min.
Max.
Unit
Clock frequency
D.C.
2
MHz
tCSS1
S active setup time
150
ns
tSHCH
tCSS2
S not active setup time
150
ns
tSHSL
tCS
S deselect time
200
ns
tCHSH
tCSH
S active hold time
150
ns
S not active hold time
150
ns
tCHSL
Parameter
tCH (1)
tCLH
Clock high time
200
ns
(1)
200
ns
tCLL
Clock low time
tCLCH
(2)
tRC
Clock rise time
2
µs
tCHCL
(2)
tFC
Clock fall time
2
µs
tCL
tDVCH
tDSU
Data in setup time
50
ns
tCHDX
tDH
Data in hold time
50
ns
tHHCH
Clock low hold time after HOLD not active
150
ns
tHLCH
Clock low hold time after HOLD active
150
ns
tCLHL
Clock low setup time before HOLD active
0
ns
tCLHH
Clock low setup time before HOLD not active
0
ns
tSHQZ
(2)
tDIS
tCLQV
tV
tCLQX
Output Disable time
200
ns
Clock low to output valid
200
ns
tHO
Output hold time
tQLQH
(2)
0
tRO
Output rise time
200
ns
tQHQL
(2)
tFO
Output fall time
200
ns
tHHQV
tLZ
HOLD high to output valid
200
ns
tHLQZ (2)
tHZ
HOLD low to output High-Z
200
ns
tW
tWC
Write time
5
ms
1. tCH + tCL must never be less than the shortest possible clock period, 1 / fC(max)
2. Value guaranteed by characterization, not 100% tested in production.
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ns
M95M01-R
DC and AC parameters
Figure 15. Serial input timing
tSHSL
S
tCHSL
tSLCH
tCHSH
tSHCH
C
tDVCH
tCHCL
tCHDX
LSB IN
MSB IN
D
Q
tCLCH
High Impedance
AI01447C
Figure 16. Hold timing
S
tHLCH
tCLHL
tHHCH
C
tCLHH
tHLQZ
tHHQV
Q
D
HOLD
AI01448B
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DC and AC parameters
M95M01-R
Figure 17. Output timing
S
tCH
C
tCLQV
tCLQX
tCLQV
tCL
tSHQZ
tCLQX
LSB OUT
Q
tQLQH
tQHQL
D
ADDR.LSB IN
AI01449e
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M95M01-R
11
Package mechanical
Package mechanical
Figure 18. SO8 narrow – 8 lead plastic small outline, 150 mils body width, package
outline
h x 45˚
A2
A
c
ccc
b
e
0.25 mm
GAUGE PLANE
D
k
8
E1
E
1
L
A1
L1
SO-A
1. Drawing is not to scale.
Table 14.
SO8 narrow – 8 lead plastic small outline, 150 mils body width,
package mechanical data
millimeters
inches
Symbol
Typ
Min
A
Max
Typ
Min
1.75
Max
0.069
A1
0.10
A2
1.25
b
0.28
0.48
0.011
0.019
c
0.17
0.23
0.007
0.009
ccc
0.25
0.004
0.010
0.049
0.10
0.004
D
4.90
4.80
5.00
0.193
0.189
0.197
E
6.00
5.80
6.20
0.236
0.228
0.244
E1
3.90
3.80
4.00
0.154
0.150
0.157
e
1.27
–
–
0.050
–
–
h
0.25
0.50
0.010
0.020
k
0°
8°
0°
8°
L
0.40
1.27
0.016
0.050
L1
1.04
0.041
35/39
Package mechanical
M95M01-R
Figure 19. SO8W – 8 lead plastic small outline, 208 mils body width, package outline
A2
A
c
b
CP
e
D
N
E E1
1
A1
k
L
6L_ME
1. Drawing is not to scale.
Table 15.
SO8W – 8 lead plastic small outline, 208 mils body width, package
mechanical data
millimeters
inches
Symbol
Typ
Min
A
Typ
Min
2.50
Max
0.098
A1
0.00
0.25
0.000
0.010
A2
1.51
2.00
0.059
0.079
b
0.40
0.35
0.51
0.016
0.014
0.020
c
0.20
0.10
0.35
0.008
0.004
0.014
CP
0.10
0.004
D
6.05
0.238
E
5.02
6.22
0.198
0.245
E1
7.62
8.89
0.300
0.350
–
–
–
–
k
0
10
0
10
L
0.50
0.80
0.020
0.031
e
N
36/39
Max
1.27
8
0.050
8
M95M01-R
12
Part numbering
Part numbering
Table 16.
Ordering information scheme(1)
Example:
M95M01
–
R MN
6
T
P
Device type
M95 = SPI serial access EEPROM
Device function
M01 = 1024 Kbits (131 072 × 8)
Operating voltage
R = VCC = 1.8 V to 5.5 V
Package
MN = SO8N (150 mils width)
MW = SO8W (208 mils width)
Device grade
6 = Industrial temperature range, –40 to 85 °C.
Device tested with standard test flow
Option
blank = standard packing
T = tape and reel packing
Plating technology
P or G = ECOPACK® (RoHS compliant)
1. Ordering information related to the M95M01-R identified with the process letter "A".
For a list of available options (speed, package, etc.) or for further information on any aspect
of this device, please contact your nearest ST Sales Office.
The category of second Level Interconnect is marked on the package and on the inner box
label, in compliance with JEDEC Standard JESD97. The maximum ratings related to
soldering conditions are also marked on the inner box label.
37/39
Revision history
13
M95M01-R
Revision history
Table 17.
Document revision history
Date
Revision
13-Mar-2007
1
Initial release.
15-May-2007
2
VCC conditions modified in Table 13: AC characteristics (VCC < 2.5 V
and –40°C £ TA £ 85 °C). Small text changes.
21-Jun-2007
3
The device endurance is specified at more than 1 000 000 (1 million)
cycles (corrected on page 1).
4
Schmitt trigger inputs for enhanced noise margin added to Features
on page 1.
VIL and VIH values modified according to voltage range in Table 11:
DC characteristics.
17-Jul-2007
38/39
Changes
M95M01-R
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