STA016T MPEG 2.5 LAYER III AUDIO DECODER SUPPORTING CD-ROM CAPABILITY & ADPCM PRODUCT PREVIEW ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ SINGLE CHIP MPEG LAYER 3 DECODER SUPPORTING: - All features specified for Layer III in ISO/IEC 11172-3 (MPEG 1 Audio) - All features specified for Layer III in ISO/IEC 13818-3.2 (MPEG 2 Audio) - Lower sampling frequencies syntax extension, (not specified by ISO) called MPEG 2.5 DECODES LAYER III STEREO CHANNELS, DUAL CHANNEL, SINGLE CHANNEL (MONO) SUPPORTING ALL THE MPEG 1 & 2 SAMPLING FREQUENCIES AND THE EXTENSION TO MPEG 2.5:48, 44.1,32, 24,22.05, 16, 12,11. 025, 8 KHz ACCEPTS MPEG 2.5 LAYER III ELEMENTARY COMPRESSED BITSTREAM WITH DATA RATE FROM 8 Kbit/s UP TO 320 Kbit/s BYPASS MODE FOR EXTERNAL AUXILIARY AUDIO SOURCE ADPCM ENCODING/DECODING CAPABILITY: - sample frequency from 8 kHz to 32 kHz - sample size from 8 bits to 32 bits - encoding algorithm: DVI, ITU-G726 pack (G723-24, G721,G723-40) EMBEDDED ISO9660 LAYER FOR FILESYSTEM DECODING (JOLIET) EMBEDDED CD-ROM DECODER BLOCKS INCLUDING ECC/EDC CAPABILITY FLEXIBLE I2S INPUT INTERFACE FOR EASY CONNECTION WITH MOST CD-SERVO DEVICES EMBEDDED BROWSING COMMAND INTERPRETER FOR EASY FILE-SYSTEM BROWSING CUE-SHEET CAPABILITY UP TO 100 ENTRIES BROWSER COMMAND INTERPRETER (BCI) - Parent Dir - Enter Dir - Previous Entry - Next Entry - Get Record Infos TQFP64 ORDERING NUMBER: STA016T ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ EASY PROGRAMMABLE GPSO INTERFACE (MONO/STEREO) FOR ENCODED DATA UP TO 5Mbit/s DIGITAL VOLUME BASS & TREBLE CONTROL SERIAL BITSTREAM INPUT INTERFACE EASY PROGRAMMABLE ADC INPUT INTERFACE SERIAL PCM OUTPUT INTERFACE (I2S AND OTHER FORMATS) PLL FOR INTERNAL CLOCK AND FOR OUTPUT PCM CLOCK GENERATION CRC CHECK AND SYNCHRONISATION ERROR DETECTION WITH SOFTWARE INDICATORS I2C CONTROL BUS LOW POWER 2.4V CMOS TECHNOLOGY WITH 3.3V TOLERANT AND CAPABLE I/O FAST FORWARD AND PAUSE CAPABILITIES APPLICATIONS ■ ■ ■ ■ AUDIO CD PLAYERS MULTIMEDIA PLAYERS CD-ROM PLAYERS CAR RADIO PLAYERS May 2001 This is preliminary information on a new product foreseen to be developed. Details are subject to change without notice. 1/45 STA016T DESCRIPTION The STA016 is a single chip MPEG 1, 2 and 2.5 Layer III audio decoder with embedded CDROM decoding capability. It can be easily connected to most existing CDDSP devices via a software configurable serial link. A tipical application block diagram is show in Figure 1. Besides MPEG decoding the device can also perform ADPCM encoding/decoding from different audio sources and the encoded stream, for instance, can be stored on an external flash memory. A useful bypass mode allow using this device also as an audio processor for volume and tone controls. Figure 1. Typical CD-Player application CD Mechanic TUNERMODULE OR AUX.AUDIO SOURCE CDDSPI/F I2S OUT CDDSP D/A L R STA016 I2C SDI MCU GPSO FLASHMEMORY for MP3 files or ADPCM encoded messages (optional) CD MODULE ABSOLUTE MAXIMUM RATINGS Symbol VDD Parameter Power Supply Value Unit -0.3 to 3 V Vi Voltage on Input pins -0.3 to VDD +0.3 V VO Voltage on output pins -0.3 to VDD +0.3 V Tstg Storage Temperature -40 to +150 °C Top Operative ambient temp -20 to +85 °C Value Unit 85 °C/W THERMAL DATA Symbol Parameter R th j-amb Thermal resistance Junction to Ambient 2/45 STA016T 1 OVERVIEW The device can decode/process data coming from three possible sources, as showed in Figure 2: ■ CDDSP serial link: using this input interface, besides MP3 encoded data CD, it’s possible to playback also standard Audio CD using the available volume and tone equalizer features of the device and allowing the use of only one D/A converter with no external analog switch. ■ SDI input interface: through this input interface it’s possible to decode any MP3 bitstream coming, for instance, from an external flash memory. This same interface is also used to decode ADPCM streams. ■ I2S input interface: this interface can be used both to encode an external audio source (with variable compression based on 4 different ADPCM algorithm) or to process an external audio source (tuner, for instance) through the DSP based volume and tone controls:this BYPASS mode can avoid the use of additional D/A converters or postprocessing units. 1.1 MP3 decoder engine The MP3 decoder engine is able to decode any Layer III compliant bitstream: MPEG1, MPEG2 and MPEG2.5 streams are supported. Decoded audio data goes through a software volume control and a two-band equalizer blocks before feeding the output I2S interface. This results in no need for an external audio processor. Table 1. MPEG Sampling Rates (KHz) MPEG 1 MPEG 2 MPEG 2.5 48 24 12 44.1 22.05 11.025 32 16 8 1.2 ADPCM encoder/decoder engine This device also embeds a multistandard ADPCM encoder/decoder supporting different sample rates (from 8 KHz up to 32 KHz) and different sample sizes (from 8 bit to 32 bits). During encoding process two different interfaces can be used to feed data: the serial input interface (same interface used also to feed MP3 bitstream) or the ADC input interface, which provides a seamless connection with an external A/D converter. The currently used interface is selected via I2C bus. Also to retrieve encoded data a specific interface is available: the fast GPSO output interface. GPSO interface is able to output data with a bitrate up to 5 Mbit/s and its control pins (GPSO_SCKR, GPSO_DATA and GPSO_REQ) can be configured in order to easily fit the target application. 3/45 STA016T Figure 2. Block Diagram CDROM DECODER (C3) CD_BCK CD_SDI CDDSP I/F SYNC DETECT. ECC/EDC DESCRAM. CD_LRCK SECTOR BUFFER BS_BCK BS_SDI SDI I/F INPUT SELECTOR BS_LRCK DREQ BCKI SDI I 2S IN I/F LRCKI STB MMDSP CORE - ISO9660 + JOLIET - BCI - MP3 + ADPCM BCKO I2S OUT I/F PCM OUTPUT BUFFER SDO LRCKO RQST SCL SDA GPSO_CK I2C I/F I2C REG BANK PLL OSCK OSC XTI XTO GPSO_SDO GPSO I/F GPSO_REQ D00AU1221 The basic functions of the device can be fully operated via the I2C bus. Besides that the GPSO interface can be used to move huge amount of data this fast and flexible interface can achieve transfer rates up to 5 Mbit/s. The embedded DSP firmware implements all the layers required to decode a standard data CD, as shown in the Figure 3: Figure 3. Layers performed by embedded DSP firmware FRAMES to SECTOR TRANSLATOR SYNC DETECTOR DESCRAMBLER EDC/ECC (C3) ISO9660 File System Decoding (with Joliet support) Browsing Command Interface The whole CDROM and file-system decoding task is performed by embedded firmware. The application MCU, basically, must manage CDDSP device according to STA016 requests. Three basic command flows exist: ■ MCU -> STA016: commands used to handle decoder operation and to ask for specific information like filename, filelength, sector raw data, etc. This flow will use I2C (GPSO for special operations) interface. ■ STA016 -> MCU: this channel is used to retrieve inquired information and to inform MCU that a CDDSP 4/45 STA016T specific operation must be performed (like pick-up repositioning). This flow is based on I2C link plus an additional interrupt signal in order to avoid time consuming polling techniques. ■ MCU -> CDDSP: the CDDSP management is fully up to the application MCU. This architecture allows maximum flexibility and easy migration from existing CDPlayers to MP3 CDPlayers. IODATA13 IODATA14 IODATA15 VSS_7 VDD_5 GPSO_SDO GPSO_CK GPSO_REQ VSS_8 VCC_3 RQST STB VSS_9 VDD_6 SCL SDA PIN CONNECTION 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 CD_LRCK 1 48 IODATA12 CD_BCK 2 47 IODATA11 CD_SDI 3 46 IODATA10 DREQ 4 45 IODATA9 VDD_1 5 44 IODATA8 VSS_1 6 43 VSS_6 BS_LRCK 7 42 VCC_2 BS_BCK 8 41 PLL_GND BS_SDI 9 40 FILT0 VDD_2 10 39 PLL_VCC VSS_2 11 38 FILT1 LRCK1 12 37 VSS_5 BCKI 13 36 VDD_4 SDI 14 35 IODATA7 RESET 15 34 IODATA6 TESTEN 16 33 IODATA5 IODATA4 IODATA3 VSS_4 VDD_3 IODATA2 IODATA1 IODATA0 CLKOUT VSS_3 VCC_1 SDO BCKO LRCKO OSCK XTI XTO 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 D00AU1227 PIN DESCRIPTION PIN Pin Name Type Description Sourde/Dest CDDSP interface 1 CD_LRCK I DSP Interface left/right Clock From DSP 3 CD_SDI I DSP interface serial data From DSP 2 CD_BCK I DSP interface bit clock From DSP SDI interface 9 BS_SDI I Bitstream interface serial data From MCU 7 BS_LRCK I Bitstream interface left/right Clock From MCU 8 BS_BCK I Bitstream interface clock From MCU 4 DREQ O Bitstream data request To MCU PCM IN interface 13 BCKI I ADC bit clock From ADC 5/45 STA016T PIN DESCRIPTION (continued) PIN Pin Name Type Description Sourde/Dest 14 SDI I ADC serial data From ADC 12 LRCKI I ADC left/right Clock From ADC PCM OUT interface 20 LRCKO O DAC Interface left/right Clock To DAC 22 SDO O DAC serial data To DAC 21 BCKO O DAC bit clock To DAC 19 OSCK O DAC oversampling clock To DAC/ADC GPSO interface 55 GPSO_CK I GPSO bit clock From MCU 54 GPSO_SDO O GPSO serial data To MCU 56 GPSO_REQ O GPSO request signal To MCU GPIO interface 26 IODATA0 I/O GPIODATA0 27 IODATA1 I/O GPIODATA1 28 IODATA2 I/O GPIODATA2 31 IODATA3 I/O GPIODATA3 32 IODATA4 I/O GPIODATA4 33 IODATA5 I/O GPIODATA5 34 IODATA6 I/O GPIODATA6 35 IODATA7 I/O GPIODATA7 44 IODATA8 I/O GPIODATA8 45 IODATA9 I/O GPIODATA9 46 IODATA10 I/O GPIODATA10 47 IODATA11 I/O GPIODATA11 48 IODATA12 I/O GPIODATA12 49 IODATA13 I/O GPIODATA13 50 IODATA14 I/O GPIODATA14 51 IODATA15 I/O GPIODATA15 6/45 STA016T PIN DESCRIPTION (continued) PIN Pin Name Type Description Sourde/Dest HANDSHAKE SIGNALS 60 STB I Strobe signal From MCU 59 RQST O I2C data signal To MCU 2 I C LINK 63 SCL I I2C clock signal From MCU 64 SDA I/O I2C data signal To MCU MISCELLANEOUS 17 XTI I Oscillator input 18 XTO O Oscillator output 25 CLKOUT O Buffered output clock 15 -RESET I Reset 16 -TESTEN I Reserved for test purpose 40 FILT0 I PLL external filter 38 FILT1 PLL external filter POWER SUPPLY 39 PLL_VCC 41 PLL_GND 5 VDD_1 Digital supply (2.5V Power Supply) 10 VDD_2 Digital supply (2.5V Power Supply) 29 VDD_3 Digital supply (2.5V Power Supply) 36 VDD_4 Digital supply (2.5V Power Supply) 53 VDD_5 Digital supply (2.5V Power Supply) 62 VDD_6 Digital supply (2.5V Power Supply) 23 VCC_1 Digital supply (3.3V Power Supply) 42 VCC_2 Digital supply (3.3V Power Supply) 58 VCC_3 Digital supply (3.3V Power Supply) 6 VSS_1 11 VSS_2 24 VSS_3 30 VSS_4 37 VSS_5 43 VSS_6 52 VSS_7 57 VSS_8 61 VSS_9 7/45 STA016T ELECTRICAL CHARACTERISTCS ( VDD = 3.3V ±0.3V; Tamb = 0 to 70°C; Rg = 50Ω unless otherwise specified) DC OPERATING CONDITIONS Symbol VDD Tj Parameter Value Unit 2.4 V -20 to 125 °C Power Supply Voltage Operating Junction Temperature GENERAL INTERFACE ELECTRICAL CHARACTERISTICS Symbol Parameter IIL Low Level Input CurrentWithout pull-up device Vi = 0V IIH High Level Input CurrentWithout pull-up device Vi = VDD Electrostatic Protection Leakage < 1µA Vesd Test Condition Min. Typ. Max. Unit Note -10 10 µA 1 -10 10 µA 1 V 2 2000 Note 1: The leakage currents are generally very small, < 1nA. The value given here is a maximum that can occur after an electrostatic stress on the pin. Note 2: Human Body Model. DC ELECTRICAL CHARACTERISTICS Symbol Parameter VIL Low Level Input Voltage VIH High Level Input Voltage Vol Low Level Output Voltage Voh High Level Output Voltage Test Condition Min. Typ. Max. Unit 0.2*VDD V Note V 0.8*VDD Iol = Xma 0.4V 0.85*VDD V 1, 2 V 1, 2 Note1: Takes into account 200mV voltage drop in both supply lines. Note 2: X is the source/sink current under worst case conditions and is reflected in the name of the I/O cell according to the drive capability. Symbol Parameter Ipu Pull-up current Rpu Equivalent Pull-up Resistance Test Condition Vi = 0V; pin numbers 7, 24 and 26 Min. Typ. Max. Unit Note -25 -66 -125 µA 1 50 kΩ Note 1: Min. condition: VDD = 2.7V, 125°C Min process Max. condition: VDD = 3.6V, -20°C Max. POWER DISSIPATION Symbol Parameter PD Power Dissipation@ VDD = 2.4V 8/45 Test Condition Min. Typ. Max. Unit Sampling_freq ≤24 kHz t.b.d. mW Sampling_freq ≤32 kHz t.b.d. mW Sampling_freq ≤48 kHz t.b.d. mW Note STA016T 2 HOST REGISTERS The following table gives a description of STA016 register list. The STA016 device includes 256 I2C registers. In this document, only the user-oriented registers are described. The undocumented registers are reserved or unused. These registers must never be accessed (in Read or in Write mode). The Read-Only registers must never be written We can split the data flux in different time periods (see following diagram) meanwhile host registers can be read or written : ■ DWT : During Whole Time (at any time during process). ■ DEC : During External Config (period between RUN=2 and RUN=1). ■ DBO : During Boot (period between RUN=0 and RUN=2). ■ ABO : After BOot (period after RUN=1). ■ AEC : After External Config (period after RUN=2). ■ EDF : Every Decoded Frame (each time a frame has been decoded). ■ EDB : Every Decoded Block (each time a block has been decoded). SOFT_RESET = 1 CK_CMD = 0 HR RUN==0 RUN==2 RUN==1 block1 frame1 block2 frame1 block1 frame2 time DWT DBO DEC ABO AEC D01AU1260 EDB EDB EDF EDB 9/45 STA016T REGISTER MAP BY FUNCTION Register function VERSION PLL_AUDIO_CONFIGURATION PLL_SYSTEM_CONFIGURATION I2Sout_CONFIGURATION GPSO_CONFIGURATION I2Sin_CONFIGURATION 10/45 Hex Dec 0x00 0 0x01 1 0xD3 Name Type When VERSION RO DWT IDENT RO DWT 211 SOFT_VERSION RO DWT 0xDC 220 PLL_AUDIO_PEL_192 RW DEC 0xDD 221 PLL_AUDIO_PEH_192 RW DEC 0xDE 222 PLL_AUDIO_NDIV_192 RW DEC 0xDF 223 PLL_AUDIO_XDIV_192 RW DEC 0xE0 224 PLL_AUDIO_MDIV_192 RW DEC 0xE1 225 PLL_AUDIO_PEL_176 RW DEC 0xE2 226 PLL_AUDIO_PEH_176 RW DEC 0xE3 227 PLL_AUDIO_NDIV_176 RW DEC 0xE4 228 PLL_AUDIO_XDIV_176 RW DEC 0xE5 229 PLL_AUDIO_MDIV_176 RW DEC 0xE6 230 PLL_SYSTEM_PEL_50 RW DEC 0xE7 231 PLL_SYSTEM_PEH_50 RW DEC 0xE8 232 PLL_SYSTEM_NDIV_50 RW DEC 0xE9 233 PLL_SYSTEM_XDIV_50 RW DEC 0xEA 234 PLL_SYSTEM_MDIV_50 RW DEC 0xEB 235 PLL_SYSTEM_PEL_42_5 RW DEC 0xEC 236 PLL_SYSTEM_PEH_42_5 RW DEC 0xED 237 PLL_SYSTEM_NDIV_42_5 RW DEC 0xEE 238 PLL_SYSTEM_XDIV_42_5 RW DEC 0xEF 239 PLL_SYSTEM_MDIV_42_5 RW DEC 0x66 102 OUTPUT_CONF RW DEC 0x67 103 PCM_DIV RW DEC 0x68 104 PCM_CONF RW DEC 0x69 105 PCM_CROSS RW DEC 0x66 102 OUTPUT_CONF RW DEC 0x6A 106 GPSO_CONF RW DEC 0x5A 90 INPUT_CONF RW DEC 0x5B 91 I_AUDIO_CONFIG_1 RW DEC 0x5C 92 I_AUDIO_CONFIG_2 RW DEC 0x5D 93 I_AUDIO_CONFIG_3 RW DEC STA016T Register function CDBSA_CONFIGURATION BSB_CONFIGURATION CD_CONFIGURATION Hex Dec 0x5A 90 0x5B Name Type When INPUT_CONF RW DEC 91 I_AUDIO_CONFIG_1 RW DEC 0x5C 92 I_AUDIO_CONFIG_2 RW DEC 0x5D 93 I_AUDIO_CONFIG_3 RW DEC 0x5E 94 I_AUDIO_CONFIG_4 RW DEC 0x5F 95 I_AUDIO_CONFIG_5 RW DEC 0x60 96 I_AUDIO_CONFIG_6 RW DEC 0x61 97 I_AUDIO_CONFIG_7 RW DEC 0x62 98 I_AUDIO_CONFIG_8 RW DEC 0x63 99 I_AUDIO_CONFIG_9 RW DEC 0x64 100 I_AUDIO_CONFIG_10 RW DEC 0x65 101 I_AUDIO_CONFIG_11 RW DEC 0x59 89 POL_REQ RW DEC 0x5A 90 INPUT_CONF RW DEC 0x5B 91 I_AUDIO_CONFIG_1 RW DEC 0x40 64 BASIC_COMMAND WO AEC 0x41 65 FAST_FUNCTION_VAL RW ABO 0x42 66 REQUIRED_TRACK RW ABO 0x43 67 REQUIRED_DIR RW ABO 0x44 68 PLAY_MODE RW ABO 0x46 70 TYPE _CD_EXT_REQ RO AEC 0x47 71 MINUTE_REQ RO AEC 0x48 72 SECOND_REQ RO AEC 0x49 73 SECTOR_REQ RO AEC 0x4A 74 MINUTE_SPENT RO AEC 0x4B 75 SECOND_SPENT RO AEC 0x4C 76 SCANNING_TIME RW ABO 0x4D 77 PLAY_LIST_INDEX RW ABO 0x4E 78 PLAY_LIST_VALUE RW ABO 11/45 STA016T Register function 12/45 Hex Dec 0x86 134 0x87 Name Type When CD_SONG_INFO_C1 RO AEC 135 CD_SONG_INFO_C2 RO AEC 0x88 136 CD_SONG_INFO_C3 RO AEC 0x89 137 CD_SONG_INFO_C4 RO AEC 0x8A 138 CD_SONG_INFO_C5 RO AEC 0x8B 139 CD_SONG_INFO_C6 RO AEC 0x8C 140 CD_SONG_INFO_C7 RO AEC 0x8D 141 CD_SONG_INFO_C8 RO AEC 0x8E 142 CD_SONG_INFO_C9 RO AEC 0x8F 143 CD_SONG_INFO_C10 RO AEC 0x90 144 CD_SONG_INFO_C11 RO AEC 0x91 145 CD_SONG_INFO_C12 RO AEC 0x92 146 CD_SONG_INFO_C13 RO AEC 0x93 147 CD_SONG_INFO_C14 RO AEC 0x94 148 CD_SONG_INFO_C15 RO AEC 0x95 149 CD_SONG_INFO_C16 RO AEC 0x96 150 CD_SONG_INFO_C17 RO AEC 0x97 151 CD_SONG_INFO_C18 RO AEC 0x98 152 CD_SONG_INFO_C19 RO AEC 0x99 153 CD_SONG_INFO_C20 RO AEC 0x9A 154 CD_SONG_INFO_C21 RO AEC 0x9B 155 CD_SONG_INFO_C22 RO AEC 0x9C 156 CD_SONG_INFO_C23 RO AEC 0x9D 157 CD_SONG_INFO_C24 RO AEC 0x9E 158 CD_SONG_INFO_C25 RO AEC 0x9F 159 CD_SONG_INFO_C26 RO AEC 0xA0 160 CD_SONG_INFO_C27 RO AEC 0xA1 161 CD_SONG_INFO_C28 RO AEC 0xA2 162 CD_SONG_INFO_C29 RO AEC 0xA3 163 CD_SONG_INFO_C30 RO AEC 0xA4 164 CD_SONG_INFO_C31 RO AEC 0xA5 165 CD_SONG_INFO_C32 RO AEC 0xA6 166 CD_SONG_TYPE_INFO RO AEC STA016T Register function COMMAND Hex Dec 0xA7 167 0xA8 Name Type When NB_OF_CUR_TRACK RO AEC 168 NB_OF_CUR_DIR RO AEC 0xA9 169 CD_CUR_STATUS RO AEC 0xAA 170 CD_TRACK_FORMAT RO AEC 0xAB 171 CD_NB_OF_SUB_DIR RO AEC 0xAC 172 CD_NB_OF_SUB_FILE RO AEC 0xAD 173 DIRECTORY_LEVEL RO AEC 0xAE 174 DIR_IDENTIFIER_B1 RO AEC 0xAF 175 DIR_IDENTIFIER_B2 RO AEC 0xB0 176 DIR_IDENTIFIER_B3 RO AEC 0xB1 177 DIR_IDENTIFIER_B4 RO AEC 0xB2 178 VOL_IDENTIFIER_B1 RO AEC 0xB3 179 VOL_IDENTIFIER_B2 RO AEC 0xB4 180 VOL_IDENTIFIER_B3 RO AEC 0xB5 181 VOL_IDENTIFIER_B4 RO AEC 0xB6 182 EXTRACT_BYTE_IDX_B1 RW ABO 0xB7 183 EXTRACT_BYTE_IDX_B2 RW ABO 0xB8 184 EXTRACT_BYTE_IDX_B3 RW ABO 0xB9 185 EXTRACT_BYTE_IDX_B4 RW ABO 0xBA 186 EXTRACT_ADR_MODE RW ABO 0xBC 188 CONFIG_MODULE RW DEC 0x10 16 SOFT_RESET WO DWT 0x3A 58 CK_CMD WO DBO 0x55 85 DEC_SEL RW DEC 0x56 86 RUN RW DEC 0x52 82 CRC_IGNORE RW ABO 0x53 83 MUTE RW ABO 0x57 87 SKIP RW ABO 0x58 88 PAUSE RW ABO 13/45 STA016T Register function STATUS BYPASSA_CONFIGURATION MP3_CONFIGURATION ADPCM_CONFIGURATION MIX_CONFIGURATION TONE_CONFIGURATION 14/45 Hex Dec 0xCC 204 0xCD Name Type When STATUS_MODE RO EDF 205 STATUS_CHAN_NB RO EDF 0xCE 206 STATUS_SF RO EDF 0x6F 111 STATUS_FE RO EDF 0xD4 212 HEADER_1 RO EDF 0xD5 213 HEADER_2 RO EDF 0xD6 214 HEADER_3 RO EDF 0xD7 215 HEADER_4 RO EDF 0xD8 216 HEADER_5 RO EDF 0xD9 217 HEADER_6 RO EDF 0x70 112 CHAN_NB RW DEC 0x71 113 SAMPLING_FREQ RW DEC 0xCB 203 PCMCLK_INPUT RW DEC 0x52 82 CRC_IGNORE RW ABO 0x6B 107 ERR_DEC_LEVEL RO EDB 0x6C 108 ERR_DEC_NB_1 RO EDB 0x6D 109 ERR_DEC_NB_2 RO EDB 0x70 112 CHAN_NB RW DEC 0x71 113 SAMPLING_FREQ RW DEC 0x72 114 ENC_STATE_REPEAT RW DEC 0x73 115 ENC_CODEC RW DEC 0x74 116 ENC_FRAME_LEN RW DEC 0x75 117 MIX_MODE RW ABO 0x76 118 MIX_DLA RW ABO 0x77 119 MIX_DLB RW ABO 0x78 120 MIX_DRA RW ABO 0x79 121 MIX_DRB RW ABO 0x7A 122 TONE_ON RW ABO 0x7B 123 TONE_FCUTH RW ABO 0x7C 124 TONE_FCUTL RW ABO 0x7D 125 TONE_GAINH RW ABO 0x7E 126 TONE_GAINL RW ABO 0x7F 127 TONE_GAIN_ATTEN RW ABO STA016T 3 REGISTER DESCRIPTION 3.2 PLL_AUDIO_CONFIGURATION registers description 3.1 VERSION registers description PLL_AUDIO_PEL_192 : VERSION : b7 b6 b7 b5 b4 b3 b2 b1 b0 b6 b5 b4 b3 b2 b1 b0 Address : 0xDC (220) Address : 0x00 (0) Type : RW - DEC Type : RO - DWT Software Reset : 58 Software Reset : 0x10 Hardware Reset : 0x10 Description : Description : This register must contain a PEL value that enables the audio PLL to generate a frequency of ofact*192 kHz for the PCMCK.See table 1, 2 & 3. The VERSION register is Read-only and it is used to identify the IC on the application board. ofact is the oversampling factor needed by the DAC (ofac==246 or ofac==384). Default value at soft reset assume : IDENT : – ofact == 256 b7 b6 b5 b4 b3 b2 b1 b0 1 0 1 0 1 1 0 0 Address : 0x01 (1) – external crystal provide a CRYCK running at 14.31818 MHz PLL_AUDIO_PEH_192 : Type : RO - DWT b7 Software Reset : 0xAC Hardware Reset : 0xAC b6 b5 b4 b3 b2 b1 b0 Address : 0xDD (221) Type : RW - DEC Description : Software Reset : 187 IDENT is a read-only register and it is used to identify the IC on an application board. IDENT always has the value 0xAC. This register must contain a PEH value that enables the audio PLL to generate a frequency of ofact*192 kHz for the PCMCK.See table 1, 2 & 3. SOFT_VERSION : b7 b6 b5 Description : b4 b3 b2 b1 b0 Address : 0xD3 (211) Type : RO - DWT Default value at soft reset assume : – ofact == 256 – external crystal provide a CRYCK running at 14.31818 MHz Software Reset : X PLL_AUDIO_NDIV_192 : Description : The SOFT_VERSION register is Read-only and it is used to identify the software running on the IC. b7 b6 b5 b4 b3 b2 b1 b0 Address : 0xDE (222) Type : RW - DEC Software Reset : 0 15/45 STA016T Description : Address : 0xE1 (225) This register must contain a NDIV value that enables the audio PLL to generate a frequency of ofact*192 kHz for the PCMCK.See table 1, 2 & 3. Type : RW - DEC Default value at soft reset assume : Software Reset : 54 Description : – ofact == 256 – external crystal provide a CRYCK running at 14.31818 MHz This register must contain a PEL value that enables the audio PLL to generate a frequency of ofact*176 kHz for the PCMCK.See table 1, 2 & 3. Default value at soft reset assume : PLL_AUDIO_XDIV_192 : b7 b6 b5 b4 – fact == 256 b3 b2 b1 b0 – external crystal provide a CRYCK running at 14.31818 MHz Address : 0xDF (223) PLL_AUDIO_PEH_176 : Type : RW - DEC Software Reset : 3 b7 b6 b5 Description : Address : 0xE2 (226) This register must contain a XDIV value that enables the audio PLL to generate a frequency of ofact*192 kHz for the PCMCK.See table 1, 2 & 3. Type : RW - DEC Default value at soft reset assume : b4 b3 b2 b1 b0 Software Reset : 118 Description : – ofact == 256 – external crystal provide a CRYCK running at 14.31818 MHz This register must contain a PEH value that enables the audio PLL to generate a frequency of ofact*176 kHz for the PCMCK.See table 1, 2 & 3. Default value at soft reset assume : PLL_AUDIO_MDIV_192 : b7 b6 b5 b4 – ofact == 256 b3 b2 b1 b0 – external crystal provide a CRYCK running at 14.31818 MHz Address : 0xE0 (224) PLL_AUDIO_NDIV_176 : Type : RW - DEC Software Reset : 12 b7 b6 b5 Description : Address : 0xE3 (227) This register must contain a MDIV value that enables the audio PLL to generate a frequency of ofact*192 kHz for the PCMCK.See table 1, 2 & 3. Type : RW - DEC Default value at soft reset assume : b4 b3 b2 b1 b0 Software Reset : 0 Description : – ofact == 256 – external crystal provide a CRYCK running at 14.31818 MHz This register must contain a NDIV value that enables the audio PLL to generate a frequency of ofact*176 kHz for the PCMCK.See table 1, 2 & 3. Default value at soft reset assume : PLL_AUDIO_PEL_176 : b7 16/45 b6 b5 b4 – ofact == 256 b3 b2 b1 b0 – external crystal provide a CRYCK running at 14.31818 MHz STA016T PLL_AUDIO_XDIV_176 : b7 b6 b5 b4 Description : b3 b2 b1 b0 Address : 0xE4 (228) This register must contain a PEL value that enables the system PLL to generate a frequency of 50 MHz for the SYSCK. See table 4. Default value at soft reset assume : Type : RW - DEC – external crystal provide a CRYCK running at 14.31818 MHz Software Reset : 2 Description : PLL_SYSTEM_PEH_50 : This register must contain a XDIV value that enables the audio PLL to generate a frequency of ofact*176 kHz for the PCMCK.See table 1, 2 & 3. b7 b6 b5 b4 b3 b2 b1 b0 Address : 0xE7 (231) Default value at soft reset assume : – ofact == 256 Type : RW - DEC – external crystal provide a CRYCK running at 14.31818 MHz Software Reset : 0 Description : PLL_AUDIO_MDIV_176 : b7 b6 b5 b4 b3 b2 b1 b0 This register must contain a PEH value that enables the system PLL to generate a frequency of 50 MHz for the SYSCK. See table 4. Default value at soft reset assume : Address : 0xE5 (229) – external crystal provide a CRYCK running at 14.31818 MHz Type : RW - DEC Software Reset : 8 PLL_SYSTEM_NDIV_50 : Description : b7 b6 b5 This register must contain a MDIV value that enables the audio PLL to generate a frequency of ofact*176 kHz for the PCMCK.See table 1,2 & 3. Address : 0xE8 (232) Default value at soft reset assume : Type : RW - DEC – ofact == 256 Software Reset : 0 – external crystal provide a CRYCK running at 14.31818 MHz Description : PLL_SYSTEM_CONFIGURATION registers description b6 b5 Address : 0xE6 (230) Type : RW - DEC Software Reset : 0 b4 b3 b2 b1 b0 This register must contain a NDIV value that enables the system PLL to generate a frequency of 50 MHz for the SYSCK. See table 4. Default value at soft reset assume : – external crystal provide a CRYCK running at 14.31818 MHz PLL_SYSTEM_PEL_50 : b7 b4 b3 b2 b1 b0 PLL_SYSTEM_XDIV_50 : b7 b6 b5 b4 b3 b2 b1 b0 Address : 0xE9 (233) Type : RW - DEC Software Reset : 1 17/45 STA016T Description : Description : This register must contain a XDIV value that enables the system PLL to generate a frequency of 50 MHZ for the SYSCK. See table 4. This register must contain a PEH value that enables the system PLL to generate a frequency of 42.5 MHz for the SYSCK.See table 4. Default value at soft reset assume : Default value at soft reset assume : – external crystal provide a CRYCK running at 14.31818 MHz PLL_SYSTEM_MDIV_50 : b7 b6 b5 b4 – external crystal provide a CRYCK running at 14.31818 MHz PLL_SYSTEM_NDIV_42_5 : b3 b2 b1 b0 b7 b6 b5 b4 b3 b2 b1 b0 Address : 0xEA (234) Address : 0xE8 (232) Type : RW - DEC Type : RW - DEC Software Reset : 13 Software Reset : 0 Description : Description : This register must contain a MDIV value that enables the system PLL to generate a frequency of 50 MHz for the SYSCK. See table 4. This register must contain a NDIV value that enables the system PLL to generate a frequency of 42.5 MHz for the SYSCK.See table 4. Default value at soft reset assume : Default value at soft reset assume : – external crystal provide a CRYCK running at 14.31818 MHz PLL_SYSTEM_PEL_42_5 b7 b6 b5 b4 – external crystal provide a CRYCK running at 14.31818 MHz PLL_SYSTEM_XDIV_42_5 : b3 b2 b1 b0 b7 b6 b5 b4 b3 b2 b1 b0 Address : 0xE6 (230) Address : 0xE9 (233) Type : RW - DEC Type : RW - DEC Software Reset : 126 Software Reset : 1 Description : Description : This register must contain a PEL value that enables the system PLL to generate a frequency of 42.5 MHz for the SYSCK.See table 4. This register must contain a XDIV value that enables the system PLL to generate a frequency of 42.5 MHz for the SYSCK.See table 4. Default value at soft reset assume : Default value at soft reset assume : – external crystal provide a CRYCK running at 14.31818 MHz PLL_SYSTEM_PEH_42_5 : b7 b6 b5 b4 b3 – external crystal provide a CRYCK running at 14.31818 MHz PLL_SYSTEM_MDIV_42_5 : b2 b1 b0 b7 b6 b5 Address : 0xE7 (231) Address : 0xEA (234) Type : RW - DEC Type : RW - DEC Software Reset : 223 Software Reset : 10 18/45 b4 b3 b2 b1 b0 STA016T PCM_CONF : Description : This register must contain a MDIV value that enables the system PLL to generate a frequency of 42.5 MHz for the SYSCK.See table 4. b7 b6 b5 b4 b3 b2 b1 b0 0 CO6 CO5 CO4 CO3 CO2 CO1 CO0 Default value at soft reset assume : – external crystal provide a CRYCK running at 14.31818 MHz Address : 0x68 (104) Type : RW - DEC Software Reset : 0 3.3 I2Sout_CONFIGURATION registers description Description : If OUTPUT_CONF == 1, configure the I2Sout interface according following table. OUTPUT_CONF : b7 b6 b5 b4 b3 b2 b1 b0 Address : 0x66 (102) Bit fields Comment CO[1:0 ] Type : RW - DEC 0: 1: 2: 3: Software Reset : 0 Description : If set to 1 enable the configurability of the PCMBLOCK Output thanks to following registers, else disable this configurability and take embedded default configuration for PCM-BLOCK registers. CO3 0 : I2S format is selected 1 : other format is selected CO4 Polarity of LRCKO : 0 : low->right, high->left). 1 : low->left, high->right so compliant to I2S format ). CO5 0 : data are in the last BCKO cycles of LRCKO (right aligned data). 1 : data are in the first BCKO cycles of LRCKO (left aligned data). CO6 0 : the transmission is LS bit first. 1 : the transmission is MS bit first. – PCM_CROSS = 0; PCM_DIV : b6 b5 b4 b3 b2 b1 b0 0 0 DV5 DV4 DV3 DV2 DV1 DV0 (16 slots transmitted). (18 slots transmitted). (20 slots transmitted). (24 slots transmitted). Polarity of BCKO : 0 : data are sent on the falling edge & stable on the rising). 1 : (data are sent on the rising edge & stable on the falling). – PCM_CONF = 0; b7 bits mode bits mode bits mode bits mode CO2 Note that this embedded default configuration can be retrieved by user thanks to following setting : – PCM_DIV = 3; 16 18 20 24 Address : 0x67 (103) Type : RW - DEC Software Reset : 0 Description : If OUTPUT_CONF == 1, configure the divider to generate the bit clock of the I2Sout interface, called BCK0, from PCMCK. according the following relation : BCKO = PCMCK / 2 * (PCM_DIV+1) PCM_CROSS : b7 b6 b5 b4 b3 b2 b1 b0 0 0 0 0 0 0 CR1 CR0 Address : 0x69 (105) Type : RW - DEC Software Reset : 0 19/45 STA016T GPSO_CONF : Description : If OUTPUT_CONF == 1, CR[1:0] is used to configure the output crossbar according following table. CR1 CR0 0 0 Comment b7 b6 b5 b4 b3 b2 b1 b0 CF7 CF6 CF5 CF4 CF3 CF2 CF1 CF0 Address : 0x6A (106) Left channel is mapped on the left output. Right channel is mapped on the right output. Type : RW - DEC Software Reset : 0 0 1 Left channel is duplicated on both output channels. Description : 1 0 Right channel is duplicated on both output channels. If OUTPUT_CONF == 1, this register configure the GPSO interface. 1 1 Right and left channels are toggled. Bit fields Comment CF0 Polarity of GPSO_CK : 0 : data provided on rising edge & stable on falling edge 1 : data provided on falling edge & stable on rising edge CF1 Polarity of GPSO_REQ : 0 : data are valid when GPSO_REQ is high 1 : data are valid when GPSO_REQ is low 3.4 GPSO_CONFIGURATION registers description OUTPUT_CONF : b7 b6 b5 b4 b3 b2 b1 b0 X X X X X 0C2 OC1 OC0 CF[7:2] Reserved : to be set to 0. Address : 0x66 (102) Type : RW - DEC Software Reset : 0 3.5 I2Sin_CONFIGURATION registers description Description : INPUT_CONF : Bit fields Comment OC0 Configuration of gpso : 0 : take embedded default configuration. 1 : configure gpso from register GPSO_CONF. OC1 OC2 Use of block PCM to generate clocks (PCMCK, LRCK & BCK): 0 : no use. 1 : use it. Configuration of PCM block: 0 : take embedded default configuration. 1 : configure PCM block from PCM_DIV & PCM_CONF registers. Note that embedded default configuration for GPSO can be retrieved by user thanks to following setting : – GPSO_CONF = b00000011; Note that embedded default configuration for PCM block is described at previous chapter. 20/45 b7 b6 b5 b4 b3 b2 b1 b0 Address : 0x5A (90) Type : RW - DEC Software Reset : 0 Description : If set to 1 enable the configurability of the I2Sin Input thanks to following registers, else disable this configurability and take embedded default configuration for I2Sin registers. Note that this embedded default configuration can be retrieved by user thanks to following setting : – I_AUDIO_CONFIG_1 = b00000110; – I_AUDIO_CONFIG_2 = b11100000; – I_AUDIO_CONFIG_3 = b00000001; STA016T I_AUDIO_CONFIG_1: Address : 0x5C (92) b7 b6 b5 b4 b3 b2 b1 b0 CF7 CF6 CF5 CF4 CF3 CF2 CF1 CF0 Type : RW - DEC Software Reset : 0 Address : 0x5B (91) Description : Type : RW - DEC See I_AUDIO_CONFIG_3 register description.. Software Reset : 0 I_AUDIO_CONFIG_3 : Description : If INPUT_CONF == 1, this register configure the I2Sin interface. b7 0 Bit fields Comment CF0 CF1 CF2 b5 0 0 b4 0 b3 0 b2 0 b1 b0 LR9 LR8 Address : 0x5D (93) Relative synchro : 0 : synchro with first data bit 1 : synchro one bit before first data bit Type : RW - DEC Data reception configuration : 0 : LSB first 1 : MSB first Description : Software Reset : 0 Polarity of bit clock BCK : 0 : data provided on falling edge & stable on rising edge. 1 : data provided on rising edge & stable on falling edge CF3 Polarity of LR clock LRCK : 0 : negative 1 : positive CF4 Start value of LRCK : combined with CF3, this bit enable user to determine left/right couple according to the following table. CF[7:5] b6 Reserved : to be set to 0. CF3 CF4 Left/Right couples 0 0 (data1/data2), (data3/data4),... 1 0 (data0/data1), (data2/data3),... 0 1 (data0/data1), (data2/data3),... 1 1 (data1/data2), (data3/data4),... If INPUT_CONF == 1, this register is used to configure the phase of the LRCK of the I2Sin. Bit fields Comment LR[4:0] Position of the data within the LRCK phase : - if CF1 = 0 (LSB), value must be set to[31 - SL[9:5] - bit position of the first bit of data within the LRCK phase]. - if CF1 = 1 (MSB), value must be set to bit position of the first bit of data within the LRCK phase. Note that range of value for this bit position is [0:31]. LR[9:5] Length-1 of the data. Max value is 31. LR[15:10] Reserved : to be set to 0 3.6 CDBSA_CONFIGURATION registers description INPUT_CONF : b7 I_AUDIO_CONFIG_2 : b6 b5 b4 b3 b2 b1 b0 Address : 0x5A (90) b7 b6 b5 b4 b3 b2 b1 b0 LR7 LR6 LR5 LR4 LR3 LR2 LR1 LR0 Type : RW - DEC Software Reset : 0 21/45 STA016T Description : Bit If set to 1 enable the configurability of the CD & BS input interfaces in audio mode thanks to following registers, else disable this configurability and take embedded default configuration. Comment CF0 Reserved : to be set to 0 CF1 Reserved : to be set to 1 CF2 Direction of bit clocks CD_BCK & BS_BCK: 0 : input 1 : output CF3 Polarity of bit clocks CD_BCK & BS_BCK : 0 : data provided on falling edge & stable on rising edge 1 : data provided on rising edge & stable on falling edge CF4 Reserved : to be set to 1 CF5 Direction of LR clocks CD_LRCK & BS_LRCK : 0 : input 1 : output CF6 Polarity of LR clocks CD_LRCK & BS_LRCK : 0 : left sample corresponds to the low level phase of LRCK 1 : left sample corresponds to the high level phase of LRCK CF7 Reserved : to be set to 0 Note that this embedded default configuration can be retrieved by user thanks to following setting : – I_AUDIO_CONFIG1 = b00010010; // clocks in input // & polarity negative – I_AUDIO_CONFIG2 = b00110010; // synchro with first data bit // data unsigned, MSB first – I_AUDIO_CONFIG3 = b11001111; // LRCK phase length is 1 – I_AUDIO_CONFIG4 = b00000011; // LRCK phase length is 16 – I_AUDIO_CONFIG5 = 0xFF; // received 16 bits – I_AUDIO_CONFIG6 = 0xFF; // received 16 bits – I_AUDIO_CONFIG7 = 0x00; // received 16 bits – I_AUDIO_CONFIG8 = 0x00; // received 16 bits I_AUDIO_CONFIG_2 : b7 – I_AUDIO_CONFIG9 = 16; // data size is 16 b6 b5 b4 b3 b2 b1 CF15 CF14 CF13 CF12 CF11 CF10 CF9 – I_AUDIO_CONFIG10 = 0x00; // no use because clock in input b0 CF8 Address : 0x5C (92) Type : RW - DEC – I_AUDIO_CONFIG11 = 0x00; // no use because clock in input Software Reset : 0 Description : If INPUT_CONF == 1, this register is used to configurate CD & BS input interfaces in audio mode. _AUDIO_CONFIG_1 : b7 b6 b5 b4 b3 b2 b1 b0 CF7 CF6 CF5 CF4 CF3 CF2 CF1 CF0 Bit CF8 Relative synchro : 0 : synchro with first data bit 1 : synchro one bit before first data bit CF9 Data reception configuration : 0 : LSB first 1 : MSB first CF10 Arithmetic type of the reception : 0 : unsigned data 1 : signed data Address : 0x5B (91) Type : RW - DEC Software Reset : 0 Description : If INPUT_CONF == 1, this register is used to configurate CD & BS input interfaces in audio mode. 22/45 Comment STA016T Bit Comment CF11 Bit fields Bit to select the reference clock used to generate BCK if clocks are in output (CF2=1 & CF5=1). Otherwise this bit is useless. 0 : SYSCK 1 : PCMCK Comment LR[11:6] Length-1 of phase 2 of LR clocks CD_LRCK & BS_LRCK. Max value is 31. LR[15:12] Reserved : to be set to 0 CF12 Reserved : to be set to 1 CF13 Reserved : to be set to 1 CF14 Reserved : to be set to 0 b7 b6 b5 b4 b3 b2 b1 b0 CF15 Reserved : to be set to 0 MA7 MA6 MA5 MA4 MA3 MA2 MA1 MA0 I_AUDIO_CONFIG_5: Address : 0x5F (95) Type : RW - DEC I_AUDIO_CONFIG_3 : Software Reset : 0 b7 b6 b5 b4 b3 b2 b1 b0 LR7 LR6 LR5 LR4 LR3 LR2 LR1 LR0 Description : See I_AUDIO_CONFIG_8 register description. Address : 0x5D (93) Type : RW - DEC Software Reset : 0 I_AUDIO_CONFIG_6 : b7 Description : b6 b5 b4 b3 b2 b1 MA15 MA14 MA13 MA12 MA11 MA10 MA9 See I_AUDIO_CONFIG_4 register description.. b0 MA8 Address : 0x60 (96) Type : RW - DEC I_AUDIO_CONFIG_4 : b7 b6 b5 b4 Software Reset : 0 b3 b2 LR15 LR14 LR13 LR12 LR11 LR10 b1 b0 LR9 LR8 Description : See I_AUDIO_CONFIG_8 register description.. Address : 0x5E (94) Type : RW - DEC Software Reset : 0 I_AUDIO_CONFIG_7 : b7 Description : If INPUT_CONF == 1, this register is used to configurate LR clocks (CD_LRCK & BS_LRCK) of CD & BS input interfaces in audio mode. b6 b5 b4 b3 b2 b1 b0 MA23 MA22 MA21 MA20 MA19 MA18 MA17 MA16 Address : 0x61 (97) Type : RW - DEC Bit fields LR[5:0] Comment Length-1 of phase 1 of LR clocks CD_LRCK & BS_LRCK. Max value is 31. Software Reset : 0 Description : See I_AUDIO_CONFIG_8 register description.. 23/45 STA016T I_AUDIO_CONFIG_8 : b7 b6 b5 b4 II_AUDIO_CONFIG_11 : b3 b2 b1 b0 MA31 MA30 MA29 MA28 MA27 MA26 MA25 MA24 b7 b6 b5 b4 b3 b2 DV15 DV14 DV13 DV12 DV11 DV10 b1 b0 DV9 DV8 Address : 0x62 (98) Address : 0x65 (101) Type : RW - DEC Type : RW - DEC Software Reset : 0 Software Reset : 0 Description : Description : If INPUT_CONF == 1, those registers are used to configure the MASK to be appllied to CD_LRCK & BS_LRCK phase 1 & 2. If INPUT_CONF == 1, those registers are used to create BCK if configurated in output (so if CF2=1 & CF5=1): then value of DV[15:0] is the divider factor to be applied to the selected clock (CF11 select either SYSCLK or PCMCLK) to create BCK. – if MAi set to 0, then bit i of both phases is not received. – if MAi set to 1, then bit i of both phases is received. I_AUDIO_CONFIG_9 : b7 b6 b5 b4 b3 b2 b1 b0 DL7 DL6 DL5 DL4 DL3 DL2 DL1 DL0 Note : value 0 & 1 correspond to a bypass of the dividers. 3.7 BSB_CONFIGURATION registers description POL_REQ : b7 b6 b5 b4 b3 b2 b1 b0 Address : 0x63 (99) Type : RW - DEC Address : 0x59 (89) Software Reset : 0 Type : WO - DEC Software Reset : 0 Description : If INPUT_CONF == 1, this register is used to configurate the size of the data to be received by CD & BS input interfaces in audio mode. Max is 32. Description : This register manage the polarity of the data REQ signal DREQ of the BS input interface. If set to 0, data are requested when REQ = 0. If set to 1, data are requested when REQ = 1. I_AUDIO_CONFIG_10 : b7 b6 b5 b4 b3 b2 b1 b0 DV7 DV6 DV5 DV4 DV3 DV2 DV1 DV0 INPUT_CONF : b7 b6 b5 Address : 0x64 (100) Type : RW - DEC Address : 0x5A (90) Software Reset : 0 Type : RW - DEC Software Reset : 0 Description : See I_AUDIO_CONFIG_11 register description. 24/45 Description : b4 b3 b2 b1 b0 STA016T If set to 1 enable the configurability of the BSB input interfaces in burst mode thanks to following register, else disable this configurability and take embedded default configuration. Value Note that this embedded default configuration can be retrieved by user thanks to following setting : – I_AUDIO_CONFIG1 = b00000000;// polarity choice Command 3 fast forward 4 fast rewind 5 track up 6 track down 9 directory down 10 directory up 11 play specified track 12 set a play-list index 13 edit play list 14 play current dir 15 play cd from beginning 112 start playing music 113 start searching bytes/mute navigation 124 ID3 name of song required 125 ID3 name of author required Description : 126 ID3 name of album required If INPUT_CONF == 1, this register is used to configure BSB bit clock. 127 name of file required 128 name of directory required I_AUDIO_CONFIG_1 : b7 b6 b5 b4 b3 b2 b1 b0 0 0 0 0 0 0 0 CF0 Address : 0x5B (91) Type : RW - DEC Software Reset : 0 Bit Comment CF0 Polarity of bit clock BS_BCK : 0 : data provided on falling edge & stable on rising edge. 1 : data provided on rising edge & stable on falling edge. FAST_FUNCTIONAL_VAL : b7 b6 b5 b4 b3 b2 b1 b0 Address : 0x41 (65) Type : RW - ABO 3.8 CD_CONFIGURATION registers description Software Reset : 0 BASIC_COMMAND : Description : b7 b6 b5 b4 b3 b2 b1 b0 Address : 0x40 (64) This register specifies the volume of fast function. For the “fast forward function” it is a number between 1 and 20. For the “fast rewind function” it is a number of second Type : RW - AEC Software Reset : 0 REQUIRED_TRACK : Description : Used for giving to dsp basic cd-player commands. Value Command b7 b6 b5 b4 b3 b2 b1 b0 Address : 0x42 (66) 1 stop playing music Type : RW - ABO 2 pause Software Reset : 0 25/45 STA016T TYPE_CD_EXT_REQ: Description : This specifies the number of track to play. b7 b6 b5 b4 b3 b2 b1 b0 Address : 0x46 (70) REQUIRED_DIR : b7 b6 b5 Type : RO - AEC b4 b3 b2 b1 b0 Software Reset : 0 Address : 0x43 (67) Description : Type : RW - ABO This register specifies the type of request sent to the cd module. Software Reset : 0 Description : Value Signific ation 10 application is in pause after EOT or EOD 18 request for a sector 20 begin of track reached 30 ready to receive a new command 35 dsp ready to run Address : 0x44 (68) 40 cd application stopped. Type : RW - ABO 66 time spent on track available 112 request for root 120 song information available This register specifies the number of directory to play. PLAY_MODE : b7 b6 b5 b4 b3 b2 b1 b0 Software Reset : 0 Description : This register specifies the playing mode. Bit [1:0] [3:2] Mode end of directory: 0: play next directory 1: replay same directory 2: make pause. other: reserved end of track: 0: play next track. 1: replay same track. 2: make pause. other: reserved 4 next track choice: 0: linear mode. 1: random mode. 5 playing time for track: 0: until end of track. 1: scanning mode. 6 end of CD: 0: stop. 1: replay same CD.. MINUTE_REQ : b7 b6 b5 b3 b2 b1 b0 Address : 0x47 (71) Type : RO - AEC Software Reset : 0 Description : This register specifies to the CD module the minute location requested. SECOND_REQ : b7 b6 b5 Address : 0x48 (72) Type : RO - AEC 26/45 b4 b4 b3 b2 b1 b0 STA016T SCANNING_TIME : Software Reset : 0 b7 b6 b5 b4 b3 b2 b1 b0 Description : This register specifies to the CD module the second location requested. Address : 0x4C (76) Type : RW - ABO Software Reset : 0 SECTOR_REQ : b7 b6 b5 Description : b4 b3 b2 b1 b0 This register specifies in second (<60) the playing time for each track in scanning mode. Address : 0x49 (73) Type : RO - AEC PLAY_LIST_INDEX: Software Reset : 0 Description : This register specifies to the CD module the sector location requested. b7 b6 b5 b4 b3 b2 b1 b0 Address : 0x4D (77) Type : RW - ABO Software Reset : 0 MINUTE_SPENT : b7 b6 b5 b4 b3 b2 b1 b0 Description : This register specifies the index in the play list of the song to enter in the play list, it is also a value between 1 and the maximum number of track in the directory. Address : 0x4A (74) Type : RO - AEC Software Reset : 0 PLAY_LIST_VALUE: Description : This register specifies the number of minute spent from the beginning of the track. It is reset at the beginning of a new track. b7 b6 b5 b4 b3 b2 b1 b0 Address : 0x4E (78) Type : RW - ABO Software Reset : 0 SECOND_SPENT : b7 b6 b5 Description : b4 b3 b2 b1 b0 Address : 0x4B (75) This register specifies the song index in the directory to enter in the play list, it is also a value between 1 and the maximum number of track in the directory. Type : RO - AEC Software Reset : 0 CD_SONG_INFO_Cn : Description : This register specifies the number of second spent from the beginning of the track. It is resected at the beginning of a new track. b7 b6 b5 b4 b3 b2 b1 b0 Address : 0x86 (134) to 0xA5 (165) Type : RO - AEC Software Reset : 0 27/45 STA016T NB_OF_CUR_DIR : Description : This register contains the nth character of the song info required (ASCII code). b7 b6 b5 b4 b3 b2 b1 b0 Address : 0xA8 (168) Type : RO - AEC CD_SONG_TYPE_INFO : b7 b6 b5 Software Reset : 0 b4 b3 b2 b1 b0 Description : Address : 0xA6 (166) This register specifies the number of the current directory into the CD: from 1 to max number of directory. This number is negative if going backward to the end of the CD with the command directory-down. Type : RO - AEC Software Reset : 0 Description : This register specifies the kind of current information contained in the Value b7 Signification b6 b4 information not valid Address : 0xA9 (169) 1 ID3 song name information Type : RO - ABO 2 ID3 author name information Software Reset : 0 3 ID3 album name information 4 file name information 5 directory name information 6 bytes requested 7 play list content b6 b5 b4 b3 b3 b2 b1 b0 Description : This register gives the status of the CD application. Bit NB_OF_CUR_TRACK : b2 b1 b0 Type : RO - AEC 0: unknown format. 1: recognized format 1 reserved. 2 0: searching track. 1: track founded. 3 0: ID3 present. 1: ID3 missing. 4 0: no error detected. 1: error detected. 5 0: CD application in pause. 1: CD application not in pause. 6 0: CD not playable. 1: CD playable. 7 0: music mode. 1: searching bytes mode Software Reset : 0 Description : This register specifies the number of the current track into his directory (sub-directories included): from 1 to max number of track/subdirectory. Mode 0 Address : 0xA7 (167) 28/45 b5 0 When the track has changed the previous information are declared “not valid”. New valid information should be requested by user. b7 CD_CUR_STATUS : STA016T CD_TRACK_FORMAT : b7 b6 b5 b4 Description : b3 b2 b1 b0 This register specifies the number of file in the current directory. Address : 0xAA (170) Type : RO - AEC DIRECTORY_LEVEL : Software Reset : 0 b7 Description : This register specifies the format of the played track considering the extension name. Only 1 bit can be set in the same time: Bit b6 b5 b4 b3 b2 b1 b0 Address : 0xAD (173) Type : RO - AEC Software Reset : 0 FORMAT Description : 0 0 : UNKNOWN 1 : MP3 1 1: RESERVED 2 MPEG1 3 MPEG2 4 MPG This register specifies the current directory level. DIR_IDENTIFIER_Bn : b7 b6 b5 b4 b3 b2 b1 b0 Address : 0xAE (174) to 0xB1 (177) Type : RO - AEC Software Reset : 0 NB_OF_SUBDIR : b7 b6 b5 b4 b3 b2 b1 b0 Address : 0xAB (171) Type : RO - AEC Software Reset : 0 Description : This register specifies the nth byte of the number of byte of the current directory. Considering that two directories have very few chance to have exactly the same number of byte, this number allows to identify the directory. The first byte (174) is the MSB and the last one (177) is the LSB. Description : This register specifies the number of sub-directory in the current directory. VOL_IDENTIFIER_Bn: Address : 0xB2 (178) to 0xB5 (181) Type : RO - AEC NB_OF_SUB_TRACK : b7 b6 b5 Address : 0xAC (172) Type : RO - AEC Software Reset : 0 b4 Software Reset : 0 b3 b2 b1 b0 Description : This register specifies the nth byte of the number of byte of the CD. Considering that two CD have very few chance to have exactly the same number of byte, this number allows to identify the CD. The first byte (178) is the MSB and the last one (181) is the LSB. 29/45 STA016T EXTRACT_BYTE_IDX_Bn: b7 b6 b5 b4 Bit b3 b2 b1 b0 FORMAT 1 0: ID3 tag not checked 1: ID3 tag checked Address : 0xB6 (182) to 0xB8 (185) other Type : RW - ABO reference for counting sector in minute. Software Reset : 0 Description : This register specifies the nth byte of the index of the byte block to extract from the CD. This number should be relative to the beginning of the track containing these bytes. 3.9 COMMAND registers description SOFT_RESET : b7 b6 b5 b4 b3 b2 b1 b0 Address : 0x10 (16) Type : WO - DWT EXTRACT_ADR_MODE : Software Reset : 0 b7 b6 b5 b4 b3 b2 b1 b0 Description : Address : 0xBA (186) When user write 1 in this register, a soft reset occurs. The core command register and the interrupt register are cleared. The decoder goes into idle mode. Type : RW - ABO Software Reset : 0 Description : This register specifies addressing mode type for byte extraction: if set to 0, it is a relative (to the beginning of the current file) addressing mode, if set to 1 it is an absolute addressing mode (relative to the beginning of the CD). CK_CMD : b7 b6 b5 b4 b3 b2 b1 b0 Address : 0x3A (58) Type : WO - DBO Software Reset : 1 CD_CONFIG_MODULE : b7 b6 b5 b4 Hardware Reset : 1 b3 b2 b1 b0 Description : Address : 0xBC (188) After a soft reset, user must write 0 in CK_CMD to run the core clock of the chip. This will begin the boot of the chip, and so get it out of its idle state. Type : RO - ABO Software Reset : 0xA Description : This register set some parameters describing the way the module transmit the data to the DSP. Bit 0 30/45 FORMAT 0: valid data byte swapped. 1: valid data not byte swapped. DEC_SEL : b7 b6 b5 Address : 0x55 (85) Type : RW - DEC Software Reset : 0 b4 b3 b2 b1 b0 STA016T Description : Address : 0x52 (82) This register select the decoding data flux according the mode written in following table. Type : RW - ABO Bit(7:0) Software Reset : 0 Mode 0 CD_MP3 Description : 1 CD_BYPASSA 2 RESERVED For decoders having CRC abilities (see each decoder configuration), if set to 0 enable the check of CRC, if set to 1 disable the check of the CRC. 3 BSB_MP3 4 BSB_ADPCM_DECODER 5 RESERVED 6 BSA_ADPCM_ENCODER 7 BSA_BYPASSA Address : 0x53 (83) 8 I2Sin_ADPCM_ENC Type : RW - ABO 9 I2Sin_BYPASSA Software Reset : 0 10 SINE (test mode chip alive) MUTE : b7 b6 b5 b4 b3 b2 b1 b0 Description : RUN : b7 b6 b5 b4 b3 b2 b1 b0 For decoders having MUTE abilities (see each decoder configuration), if set to 0 disable the mute of the decoder, if set to 1 enable the mute of the decoder. Note that during a MUTE the input stream keeps on entering. Address : 0x56 (86) Type : RW - DEC SKIP : Software Reset : 0 b7 Description : b6 b5 b4 b3 b2 b1 b0 Address : 0x57 (87) – When a software reset occurs, register RUN is reset (value 0) by the dsp (see I). Type : RW - ABO – When boot routines are finished, the dsp write inside RUN register the value 2 : this is the start of the external configuration period (start of DEC : see I). Description : – When the external device wants to end the external configuration period, it must write the value 1 inside the register RUN: this is the run command that starts the decoding process (see I). Software Reset : 0 For data flux using USSB Input, if SKIP == n>2, decoder skip (n-1) out of n frames. Note that maximum value for n is 8, and if n==0 or n==1, no frames is skipped. PAUSE : b7 b6 b5 b4 b3 b2 b1 b0 CRC_IGNORE : Address : 0x58 (88) b7 b6 b5 b4 b3 b2 b1 b0 Type : RW - ABO 31/45 STA016T STATUS_CHANS_NB : Software Reset : 0 b7 Description : For decoders having PAUSE abilities (see each decoder configuration), if set to 0 disable the pause of the decoder, if set to 1 enable the pause of the decoder. Note that during a PAUSE the input stream is stopped. b6 b5 b4 b3 b2 b1 b0 Address : 0xCD (205) Type : RO - EDF Software Reset : 0 Description : This register gives the number of channel currently decoded. 3.10 STATUS registers description STATUS_MODE : b7 b6 b5 b4 b3 b2 b1 b0 Address : 0xCC (204) STATUS_SF : b7 Type : RO - EDF b6 b5 Software Reset : 0 Address : 0xCE (206) Description : Type : RO - EDF This register give the type of the currently decoded bitstream according following table. Software Reset : 0 Value 32/45 Mode b4 b3 b2 b1 b0 Description : This register gives the index of the sampling frequency of the stream currently decoded. Note that sampling frequency indexes are given by table 5 0 MP3 1 MP3_25 2 RESERVED 3 RESERVED 4 RESERVED 5 ADPCM 6 RESERVED 7 BYPASS 8 RESERVED 9 RESERVED 10 RESERVED Description : 11 MPG2 12 RESERVED This register give the status of the synchronization process according following table. 13 RESERVED Value 14 RESERVED 0 Syncrho not started 15 RESERVED 1 Syncword found 16 RESERVED 2 Syncword search 17 RESERVED 3 Syncword hard to find 18 UNKNOWN STATUS_FE : b7 b6 b5 b4 b3 b2 b1 b0 Address : 0x6F (111) Type : RO - AEC Software Reset : 0 Level STA016T HEADER _n: b7 b6 Address : 0xCB (203) b5 b4 b3 b2 b1 b0 Type : RW - DEC Software Reset : 0 Address : 0xD4 (212) to 0xD9 (217) Type : RO - EDF Description : Software Reset : 0 If set to 1, the PCMCLK pad is configure as input in order to receive an external reference clock. Description : This register give the nth byte of the header of the frame currently decoded 3.12 MP3_CONFIGURATION registers description ERR_DEC_LEVEL : 3.11 BYPASSA_CONFIGURATION registers description CHAN_NB : b7 b6 b7 b6 b5 b4 b3 b2 b1 b0 Address : 0x6B (107) b5 b4 b3 b2 b1 b0 Type : RO - EDF Software Reset : 0 Address : 0x70 (112) Type : RW - DEC Description : Software Reset : 0 This register give the status of the mp3 decoding process according the error level written in following table. Description : Value User must specify the number of channel for bypassa decoder to decode. SAMPLING_FREQ: : b7 b6 b5 b4 b3 b2 b1 Level 0 No error 1 Warning while decoding 2 Error while decoding 3 Fatal error while decoding b0 Address : 0x71 (113) ERR_DEC_NB_1 : Type : RW - DEC Software Reset : 0 Description : User must specify the sampling frequency of the stream to decode if clocks direction of the input interface is input. Sampling frequency index is given by table 4. b7 b6 b5 b4 b3 b2 b1 b0 ER7 ER6 ER5 ER4 ER3 ER2 ER1 ER0 Address : 0x6C (108) Type : RO - EDF Software Reset : 0 Description : See ERR_DEC_NB_2 register description. PCMCLK_INPUT : b7 b6 b5 b4 b3 b2 b1 b0 33/45 STA016T ERR_DEC_NB_2 : b7 b6 b5 Description : b4 b3 b2 b1 ER15 ER14 ER13 ER12 ER11 ER10 ER9 b0 It allows the user to specify the number of channel of the stream to encode. ER8 Value Address : 0x6D (109) Type : RO - EDF Software Reset : 0 Codec 1 stream mono encoded as mono 2 stream stereo encoded as stereo 5 stream stereo encoded as mono with left channel. 9 stream stereo encoded as mono with right channel. Description : This register give the status of the mp3 decoding process according the error number written in following table. Event Comment stream mono stands for only 1 channel is transmitted, data are also not interleaved. Encode a stereo stream as mono reduce from an half the encoded data. ER0 == 1 crc_error ER1 == 1 cutoff_error ER2 == 1 big_value_error ER3 == 1 hufftable_error ER4 == 1 mod_buf_size_error ER5 == 1 huffman_decode_error ER6 == 1 dynpart_exchange_error Address : 0x71 (113) ER7 == 1 gr_length_error Type : RW - DEC ER8 == 1 input_bit_available_error Software Reset : 0 ER9 == 1 ch_length_error ER10 == 1 head_framelength_error ER11 == 1 dynpart_length_error ER12 == 1 block_type_error ER13 == 1 head_emphasis_error ER14 == 1 head_samp_freq_error ER15 == 1 head_layer_error SAMPLING_FREQ. : b7 b3 b2 b1 b0 It allows the user to specify the sampling frequency of the stream to encode.See table 6 of sample frequencies. b6 b5 b4 b3 b2 b1 b0 Address : 0x72 (114) Type : RW - DEC Software Reset : 0 CHAN_NB : Description : b5 Address : 0x70 (112) Type : RW - DEC Software Reset : 0 34/45 b4 ENC_STATE_REPEAT : 3.13 ADPCM_CONFIGURATION registers description b6 b5 Description : b7 b7 b6 b4 b3 b2 b1 b0 It allows the user to specify at which frequency the state of the encoder should be repeated in the stream :(1/HOST_ENC_STATE_REPEAT) frame. STA016T ENC_CODEC : : Value b7 b6 b5 b4 b3 b2 b1 b0 Mode 0 diseable mix/volume control Address : 0x73 (115) 1 volume control Type : RW - DEC 2 mono to stereo (up-mix) Software Reset : 0 3 stereo to mono (down-mix) Description : It allows the user to specify the codec to use for the encoding: Value Codec MIX_DLA: b7 b6 b5 0 Intel/DVI 1 G723_24 Address : 0x76 (118) 2 G721 Type : RW - ABO 3 G723_40 Software Reset : 0 b4 b3 b2 b1 b0 Description : This register specifies the direct left attenuation (in dB). ENC_FRAME_LEN : b7 b6 b5 b4 b3 b2 b1 b0 Address : 0x74 (116) MIX_DLB: Type : RW - DEC b7 Software Reset : 0 b6 b5 b4 b3 b2 b1 b0 Address : 0x77 (119) Description : Type : RW - ABO It allows the user to specify the number of words by channel included in 1 frame: value from 1 to 15 (multiplied by 64 inside dsp). Software Reset : 0 Description : This register specifies the left attenuation (in dB) on rigth channel. 3.14 MIX_CONFIGURATION registers description MIX_MODE: MIX_DRA: b7 b6 b5 b4 b3 b2 b1 b0 b7 b6 b5 b4 b3 b2 b1 b0 Address : 0x75 (117) Type : RW - ABO Address : 0x78 (120) Software Reset : 2 Type : RW - ABO Software Reset : 0 Description : This register selectes the mode of mix/volume control Description : This register specifies the direct right attenuation (in dB). 35/45 STA016T MIX_DRB: b7 b6 Software Reset : 10 b5 b4 b3 b2 b1 b0 Description : Address : 0x79(121) This register specifies the low cut frequency: fcut(in Hz) = (TONE_FCUTL+1)*10 Type : RW - ABO Software Reset : 0 TONE_GAINH : Description : This register specifies the rigth attenuation (in dB) on left channel. b7 b6 b5 b4 b3 b2 b1 b0 Address : 0x7D(125) Type : RW - ABO 3.15 TONE_CONFIGURATION registers description Software Reset : 12 TONE_ON: b7 b6 Description : b5 b4 b3 b2 b1 b0 This register specifies the gain on high frequencies: gain(in Db)=(TONE_GAINH-12)*1.5 Address : 0x7A(122) Type : RW - ABO Software Reset : 0 TONE_GAINL : b7 Description : This register enables/diseables (1/0) the tone control. b6 b5 b4 b3 b2 b1 b0 Address : 0x7E(126) Type : RW - ABO Software Reset : 12 TONE_FCUTH : b7 b6 b5 b4 b3 b2 b1 b0 Description : This register specifies the gain on high frequencies: gain (in Db)=(TONE_GAINL-12)*1.5. Value of register from 0 to 24. Address : 0x7B(123) Type : RW - ABO Software Reset : 20 TONE_GAIN_ATTEN : Description : This register specifies the high cut frequency: fcut(in Hz)=(TONE_FCUTH+1)*50. b7 b6 b5 b4 b3 b2 b1 b0 Address : 0x7F(127) Type : RW - ABO Software Reset : 0 TONE_FCUTL : b7 b6 b5 Address : 0x7C(124) Type : RW - ABO 36/45 b4 b3 b2 b1 b0 Description : This register specifies the attenuation on global spectrum: gain (in dB)=-TONE_GAIN_ATTEN*1.5. Value of register from 0 to 12. STA016T 3.16 TABLES Table 2. values to configure audio PLL for ofact==256. This table give values to configure the audio PLL according CRYCK so that to generate a PCMCK == 256*SF. Register CRYCK in MHz 10 CRYCK in MHz 14.31818 CRYCK in MHz 14.7456 PLL_AUDIO_PEL_192 42 58 85 PLL_AUDIO_PEH_192 169 187 85 PLL_AUDIO_NDIV_192 0 0 0 PLL_AUDIO_XDIV_192 3 3 0 PLL_AUDIO_MDIV_192 18 12 2 PLL_AUDIO_PEL_176 56 54 0 PLL_AUDIO_PEH_176 16 118 64 PLL_AUDIO_NDIV_176 0 0 0 PLL_AUDIO_XDIV_176 3 2 3 PLL_AUDIO_MDIV_176 17 8 11 Table 3. values to configure audio PLL for ofact==384 This table give values to configure the audio PLL according CRYCK so that to generate a PCMCK == 384*SF. Register CRYCK in MHz 10 CRYCK in MHz 14.31818 CRYCK in MHz 14.7456 PLL_AUDIO_PEL_192 224 108 0 PLL_AUDIO_PEH_192 190 76 0 PLL_AUDIO_NDIV_192 0 0 0 PLL_AUDIO_XDIV_192 1 1 1 PLL_AUDIO_MDIV_192 13 9 9 PLL_AUDIO_PEL_176 42 54 0 PLL_AUDIO_PEH_176 140 118 48 PLL_AUDIO_NDIV_176 0 0 0 PLL_AUDIO_XDIV_176 1 1 1 PLL_AUDIO_MDIV_176 12 8 8 37/45 STA016T Table 4. values to configure audio PLL for ofact==512. This table give values to configure the audio PLL according CRYCK so that to generate a PCMCK == 512*SF. Register CRYCK in MHz 10 CRYCK in MHz 14.31818 CRYCK in MHz 14.7456 PLL_AUDIO_PEL_192 42 58 85 PLL_AUDIO_PEH_192 169 187 85 PLL_AUDIO_NDIV_192 0 0 0 PLL_AUDIO_XDIV_192 1 0 1 PLL_AUDIO_MDIV_192 18 5 12 PLL_AUDIO_PEL_176 56 157 0 PLL_AUDIO_PEH_176 16 157 64 PLL_AUDIO_NDIV_176 0 0 0 PLL_AUDIO_XDIV_176 1 1 1 PLL_AUDIO_MDIV_176 17 11 11 Table 5. values to configure system PLL for SYSCK. This table give values to configure the system PLL according CRYCK so that to generate a SYSCK == 50MHz. or SYSCK == 42.5MHz. CRYCK in MHz 10 CRYCK in MHz 14.31818 CRYCK in MHz 14.7456 PLL_SYSTEM_PEL_50 162 0 28 PLL_SYSTEM_PEH_50 11 0 152 PLL_SYSTEM_NDIV_50 0 0 0 PLL_SYSTEM_XDIV_50 1 1 1 PLL_SYSTEM_MDIV_50 19 13 12 PLL_SYSTEM_PEL_42_5 0 126 100 PLL_SYSTEM_PEH_42_5 0 223 135 PLL_SYSTEM_NDIV_42_5 0 0 0 PLL_SYSTEM_XDIV_42_5 1 1 1 PLL_SYSTEM_MDIV_42_5 16 10 10 Register 38/45 STA016T Table 6. index of the Sampling Frequency. Index Frequency 0 48 kHz 1 44.1 kHz 2 32 kHz 4 96 kHz 5 88.2 kHz 6 64 kHz 8 24 kHz 9 22.05 kHz 10 16 kHz 12 12 kHz 13 11.025 kHz 14 8 kHz 16 192 kHz 17 176.4 kHz 18 128 kHz 3, 7, 11, 15 or 19 illegal frequency 3.17 NOTATIONS ABO : After BOot (see I). AEC : After External Config (see I). BCK : Bit ClocK BSA : BitStream input interface in Audio mode. BSB : BitStream input interface in Burst mode. BS : BitStream input interface. BYPASSA : decoder BYPASS an Audio stream. CD : input interface for CD. CK : ClocK. CRYCK : CRYstal ClocK provided to the chip by an external crystal. DBO : During BOot (see I). DEC : During External Config (see I). DWT : During Whole Time (see I). EDB : Every Decoded Block (see I). EDF : Every Decoded Frame (see I). LRCK : Left Right ClocK for an I2S interface. ofact : oversampling factor for PCMCK (PCMCK == ofact * SF). PCMCK : PCM ClocK (can be generated by the audio PLL). SF : Sampling Frequency. SYSCK : SYStem ClocK (clock of the core, can be generated by the system PLL). X : don’t care. 39/45 STA016T I/O CELL DESCRIPTION 1) TTL Tristate Output Pad Buffer, 3V capable 4mA, with Slew Rate Control Pin numbers: 4, 18, 20, 21, 22, 25, 54, 56, 59 EN Z INPUT PIN MAX LOAD Z 100pF A D98AU904 2) TTL Schmitt Trigger Bidir Pad Buffer, 3V capable, 4mA, with Slew Rate Control Pin numbers: 1, 2, 3, 7, 8, 9, 19 EN IO INPUT PIN CAPACITANCE OUTPUT PIN MAX LOAD IO TBD IO 100pF A ZI D98AU905 3) TTL Schmitt Trigger Inpud Pad Buffer, 3V capable / Pin numbers:17, 60, 63 A Z INPUT PIN CAPACITANCE A TBD D98AU906 4) TTL Inpud Pad Buffer, 3V capable with Pull-Up / Pin numbers:15, 16 A Z INPUT PIN CAPACITANCE A TBD D98AU907 5) TTL Schmitt Trigger Bidir Pad Buffer, with Pull-up, 4mA, with slew rate control / 3V capable Pin numbers: 26, 27, 28, 31, 32, 33, 34, 35, 44, 45, 46, 47, 48, 49, 50, 51, 64 EN IO INPUT PIN CAPACITANCE OUTPUT PIN MAX LOAD IO TBD IO 100pF A ZI D00AU1150 6) TTL Input Pad Buffer, 3V capable, with pull down / Pin numbers: 12, 13, 14, 55 A Z D00AU1222 40/45 INPUT PIN CAPACITANCE A TBD STA016T 4 COMMAND PROTOCOL CONFIGURATION General Information About The Command Protocol I2C protocol : CD_module & mmdsp are using an I2C protocol to communicate : CD_module is master of the I2C protocol, and can access (in read and write mode) host registers of the sta016 to write commands to the mmdsp and to read request from the mmdsp. It must use following I2C syntax : device_address, host_register_number, host_register_value where : for a write acces, device_address is 0x86. for a read acces, device_address is 0x87. Writing a command to mmdsp : CD_module write its command inside dedicated host registers (mainly H64 to H69), then it must signals the writing of this command to mmdsp by sending the interrupt IT_CMD to the core of mmdsp. Note that IT_CMD is generated by cd_module threw a falling edge on the input line number 0 of the sta016 (the INTLINE[0] pin). Reading a request from mmdsp : MMDSP write its request inside dedicated host registers (mainly H70 to H78 and H134 to H169), then it signals to cd_module that it must read a request by sending the interrupt IT_REQ. Note that IT_REQ interrupt is generated by mmdsp on the IRQB pin of sta016. Note also that once it has finished to read the message, cd_module must always acknowledge it by reading H10. 41/45 STA016T Figure 4. Block diagram for running the CD application. Hxx: host register number xx power on cd inserted ? no write 1 in SOFT_RESET write 0 in CK_CMD wait IT_REQ with 35 in H70 start cd-rom application: write 0 in H85, then 1 in H86 wait IT_REQ with 112 in H70 send play_music command : write 112 in H64 send IT_CMD send pause command : write 2 in H64 send IT_CMD run the other application yes 42/45 return to cd? yes cd ejected? yes run other application? any command? no send other command : write in H64 send IT_CMD no STA016T Figure 5. Block diagram for answer to a sector request from dsp. Hxx: host register number xx power on IT_REQ occured H70==18 please check with rest of documentation read minute in H71 read second in H72 read frame in H73 acknowledge IT_REQ acknowledge IT_REQ move the pick-up according to m,s,f 43/45 STA016T mm DIM. MIN. inch TYP. MAX. A MIN. TYP. 1.60 A1 0.05 A2 1.35 B C 0.063 0.15 0.002 0.006 1.40 1.45 0.053 0.055 0.057 0.18 0.23 0.28 0.007 0.009 0.011 0.12 0.16 0.20 0.0047 0.0063 0.0079 D 12.00 0.472 D1 10.00 0.394 D3 7.50 0.295 e 0.50 0.0197 E 12.00 0.472 E1 10.00 0.394 E3 7.50 0.295 L 0.40 0.60 L1 0.75 OUTLINE AND MECHANICAL DATA MAX. 0.0157 0.0236 0.0295 1.00 0.0393 TQFP64 0°(min.), 7°(max.) K D D1 A D3 A2 A1 48 33 49 32 0.10mm E E1 E3 B B Seating Plane 17 64 1 16 C L L1 e K TQFP64 44/45 STA016T Note:1 STA016 is a device based on an integrated DSP core. Some of the I2C registers default values are loaded after an internal DSP boot operation. The bootstrap time is 60 micro second. Only after this time lenght, the data in the register can be considered stable. Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics 2001 STMicroelectronics - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A. http:// www.st.com 45/45