STMICROELECTRONICS STD6NF10

STD6NF10
N-CHANNEL 100V - 0.22 Ω - 6A IPAK/DPAK
LOW GATE CHARGE STripFET™ POWER MOSFET
TYPE
STD6NF10
■
■
■
■
■
■
VDSS
RDS(on)
ID
100 V
<0.250 Ω
6A
TYPICAL RDS(on) = 0.22 Ω
EXCEPTIONAL dv/dt CAPABILITY
100% AVALANCHE TESTED
LOW THRESHOLD DRIVE
THROUGH-HOLE IPAK (TO-251) POWER
PACKAGE IN TUBE (SUFFIX “-1")
SURFACE-MOUNTING DPAK (TO-252)
POWER PACKAGE IN TAPE & REEL
(SUFFIX “T4")
3
3
1
2
1
IPAK
TO-251
(Suffix “-1”)
DPAK
TO-252
(Suffix “T4”)
DESCRIPTION
This MOSFET series realized with STMicroelectronics
unique STripFET process has specifically been designed
to minimize input capacitance and gate charge. It is
therefore suitable as primary switch in advanced highefficiency, high-frequency isolated DC-DC converters for
Telecom and Computer applications. It is also intended
for any applications with low gate drive requirements.
INTERNAL SCHEMATIC DIAGRAM
APPLICATIONS
■ HIGH-EFFICIENCY DC-DC CONVERTERS
■ UPS AND MOTOR CONTROL
ABSOLUTE MAXIMUM RATINGS
Symbol
VDS
VDGR
VGS
Value
Unit
Drain-source Voltage (VGS = 0)
Parameter
100
V
Drain-gate Voltage (RGS = 20 kΩ)
100
V
Gate- source Voltage
± 20
V
ID
Drain Current (continuos) at TC = 25°C
6
A
ID
Drain Current (continuos) at TC = 100°C
4
A
IDM(•)
Ptot
Drain Current (pulsed)
24
A
Total Dissipation at TC = 25°C
30
W
Derating Factor
0.2
W/°C
dv/dt (1)
Peak Diode Recovery voltage slope
40
V/ns
EAS (2)
Single Pulse Avalanche Energy
200
mJ
-65 to 175
°C
Tstg
Tj
Storage Temperature
Max. Operating Junction Temperature
(•) Pulse width limited by safe operating area.
June 2001
.
(1) ISD ≤6A, di/dt ≤300A/µs, VDD ≤ V (BR)DSS, Tj ≤ T JMAX
(2) Starting T j = 25 oC, ID = 3A, VDD= 50V
1/9
STD6NF10
THERMAL DATA
Rthj-case
Rthj-amb
Tj
Thermal Resistance Junction-case
Thermal Resistance Junction-ambient
Maximum Lead Temperature For Soldering Purpose
Max
Max
Typ
5
100
300
°C/W
°C/W
°C
ELECTRICAL CHARACTERISTICS (TCASE = 25 °C UNLESS OTHERWISE SPECIFIED)
OFF
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
Drain-source
Breakdown Voltage
ID = 250 µA, VGS = 0
IDSS
Zero Gate Voltage
Drain Current (VGS = 0)
VDS = Max Rating
VDS = Max Rating TC = 125°C
1
10
µA
µA
IGSS
Gate-body Leakage
Current (VDS = 0)
VGS = ± 20V
±1
µA
Max.
Unit
4
V
0.25
Ω
V(BR)DSS
100
V
ON (1)
Symbol
Parameter
Test Conditions
VGS(th)
Gate Threshold Voltage
VDS = VGS
ID = 250 µA
RDS(on)
Static Drain-source On
Resistance
VGS = 10 V
ID = 3 A
Min.
Typ.
2
0.22
DYNAMIC
Symbol
2/9
Parameter
gfs (*)
Forward Transconductance
Ciss
Coss
Crss
Input Capacitance
Output Capacitance
Reverse Transfer
Capacitance
Test Conditions
VDS > ID(on) x RDS(on)max,
ID = 3 A
VDS = 25V, f = 1 MHz, VGS = 0
Min.
Typ.
Max.
Unit
34
S
280
45
20
pF
pF
pF
STD6NF10
ELECTRICAL CHARACTERISTICS (continued)
SWITCHING ON
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
td(on)
tr
Turn-on Delay Time
Rise Time
ID = 3 A
VDD = 50 V
RG = 4.7 Ω
VGS = 10 V
(Resistive Load, Figure 3)
6
10
ns
ns
Qg
Qgs
Qgd
Total Gate Charge
Gate-Source Charge
Gate-Drain Charge
VDD = 80 V ID = 6 A VGS= 10 V
10
2.5
4
nC
nC
nC
SWITCHING OFF
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
td(off)
tf
Turn-off Delay Time
Fall Time
ID = 6 A
VDD = 50 V
RG = 4.7Ω,
VGS = 10 V
(Resistive Load, Figure 3)
20
3
ns
ns
td(Voff)
tf
tc
Off-voltage Rise Time
Fall Time
Cross-over Time
ID = 6 A
Vclamp = 80 V
RG = 4.7Ω,
VGS = 10 V
(Inductive Load, Figure 5)
19
8
15
ns
ns
ns
SOURCE DRAIN DIODE
Symbol
Parameter
ISD
ISDM (•)
Source-drain Current
Source-drain Current (pulsed)
VSD (*)
Forward On Voltage
ISD = 6 A
Reverse Recovery Time
Reverse Recovery Charge
Reverse Recovery Current
di/dt = 100A/µs
ISD = 6 A
VDD = 10 V
Tj = 150°C
(see test circuit, Figure 5)
trr
Qrr
IRRM
(*)Pulsed: Pulse duration = 300 µs, duty cycle
(•)Pulse width limited by safe operating area.
Safe Operating Area
Test Conditions
Min.
Typ.
VGS = 0
70
175
5
Max.
Unit
6
24
A
A
1.3
V
ns
nC
A
1.5 %.
Thermal Impedance
3/9
STD6NF10
Output Characteristics
Transfer Characteristics
Transconductance
Static Drain-source On Resistance
Gate Charge vs Gate-source Voltage
Capacitance Variations
4/9
STD6NF10
Normalized Gate Threshold Voltage vs Temperature
Normalized on Resistance vs Temperature
Source-drain Diode Forward Characteristics
.
.
.
5/9
STD6NF10
Fig. 1: Unclamped Inductive Load Test Circuit
Fig. 2: Unclamped Inductive Waveform
Fig. 3: Switching Times Test Circuits For Resistive
Load
Fig. 4: Gate Charge test Circuit
Fig. 5: Test Circuit For Inductive Load Switching
And Diode Recovery Times
6/9
STD6NF10
TO-251 (IPAK) MECHANICAL DATA
mm
DIM.
MIN.
inch
TYP.
MAX.
MIN.
TYP.
MAX.
A
2.2
2.4
0.086
0.094
A1
0.9
1.1
0.035
0.043
A3
0.7
1.3
0.027
0.051
B
0.64
0.9
0.025
0.031
B2
5.2
5.4
0.204
0.212
B3
0.85
B5
0.033
0.3
0.012
B6
0.95
0.037
C
0.45
0.6
0.017
0.023
C2
0.48
0.6
0.019
0.023
D
6
6.2
0.236
0.244
E
6.4
6.6
0.252
0.260
G
4.4
4.6
0.173
0.181
H
15.9
16.3
0.626
0.641
L
9
9.4
0.354
0.370
L1
0.8
1.2
0.031
0.047
L2
0.8
1
0.031
0.039
A1
C2
A3
A
C
H
B
B3
=
1
=
2
G
=
=
=
E
B2
=
3
B5
L
D
B6
L2
L1
0068771-E
7/9
STD6NF10
TO-252 (DPAK) MECHANICAL DATA
mm
DIM.
MIN.
inch
TYP.
MAX.
MIN.
TYP.
MAX.
A
2.2
2.4
0.086
0.094
A1
0.9
1.1
0.035
0.043
A2
0.03
0.23
0.001
0.009
B
0.64
0.9
0.025
0.035
B2
5.2
5.4
0.204
0.212
C
0.45
0.6
0.017
0.023
C2
0.48
0.6
0.019
0.023
D
6
6.2
0.236
0.244
E
6.4
6.6
0.252
0.260
G
4.4
4.6
0.173
0.181
H
9.35
10.1
0.368
0.397
L2
0.8
L4
0.031
0.6
1
0.023
0.039
A1
C2
A
H
A2
C
DETAIL "A"
L2
D
=
1
=
G
2
=
=
=
E
=
B2
3
B
DETAIL "A"
L4
0068772-B
8/9
STD6NF10
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
The ST logo is registered trademark of STMicroelectronics
 2001 STMicroelectronics - All Rights Reserved
All other names are the property of their respective owners.
STMicroelectronics GROUP OF COMPANIES
Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A.
http://www.st.com
9/9