VISHAY SQS464EEN

SQS464EEN
www.vishay.com
Vishay Siliconix
Automotive N-Channel 40 V (D-S) 175 °C MOSFET
FEATURES
PRODUCT SUMMARY
VDS (V)
• Halogen-free According to IEC 61249-2-21
Definition
• Typical ESD Protection 800 V
• TrenchFET® Power MOSFET
• AEC-Q101 Qualifiedd
• 100 % Rg and UIS Tested
• Compliant to RoHS Directive 2002/95/EC
40
RDS(on) () at VGS = 10 V
0.032
RDS(on) () at VGS = 4.5 V
0.046
ID (A)
8
Configuration
Single
PowerPAK® 1212-8
D
S
3.30 mm
3.30 mm
1
S
2
S
3
G
G
4
D
8
D
7
D
6
D
5
Bottom View
S
Part Marking Code: Q010
N-Channel MOSFET
ORDERING INFORMATION
Package
PowerPAK 1212-8
Lead (Pb)-free and Halogen-free
SQS464EEN-T1-GE3
ABSOLUTE MAXIMUM RATINGS (TC = 25 °C, unless otherwise noted)
PARAMETER
SYMBOL
LIMIT
Drain-Source Voltage
VDS
40
Gate-Source Voltage
VGS
± 20
Continuous Drain Currenta
TC = 25 °C
ID
TC = 125 °C
Continuous Source Current (Diode Conduction)a
Pulsed Drain
Currentb
Single Pulse Avalanche Current
Single Pulse Avalanche Energy
Maximum Power Dissipationb
L = 0.1 mH
TC = 25 °C
IDM
32
IAS
10
TJ, Tstg
Operating Junction and Storage Temperature Range
8
8
PD
TC = 125 °C
Soldering Recommendations (Peak Temperature)e, f
V
8
IS
EAS
UNIT
5
33
11
- 55 to + 175
260
A
mJ
W
°C
THERMAL RESISTANCE RATINGS
PARAMETER
Junction-to-Ambient
PCB Mountc
SYMBOL
LIMIT
RthJA
81
UNIT
°C/W
Junction-to-Case (Drain)
RthJC
4.5
Notes
a. Package limited.
b. Pulse test; pulse width  300 μs, duty cycle  2 %.
c. When mounted on 1" square PCB (FR4 material).
d. Parametric verification ongoing.
e. See solder profile (www.vishay.com/ppg?73257). The PowerPAK 1212-8 is a leadless package. The end of the lead terminal is exposed
copper (not plated) as a result of the singulation process in manufacturing. A solder fillet at the exposed copper tip cannot be guaranteed
and is not required to ensure adequate bottom side solder interconnection.
f. Rework conditions: manual soldering with a soldering iron is not recommended for leadless components.
S11-2129 Rev. B, 31-Oct-11
1
Document Number: 71490
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
SQS464EEN
www.vishay.com
Vishay Siliconix
SPECIFICATIONS (TC = 25 °C, unless otherwise noted)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN.
TYP.
MAX.
UNIT
Static
Drain-Source Breakdown Voltage
Gate-Source Threshold Voltage
Gate-Source Leakage
VDS
VGS = 0 V, ID = 250 μA
40
-
-
VGS(th)
VDS = VGS, ID = 250 μA
1.5
2.0
2.5
VDS = 0 V, VGS = ± 12 V
IGSS
-
-
± 100
VGS = 0 V
VDS = 40 V
-
-
1
-
-
50
Zero Gate Voltage Drain Current
IDSS
VGS = 0 V
VDS = 40 V, TJ = 125 °C
VGS = 0 V
VDS = 40 V, TJ = 175 °C
-
-
150
On-State Drain Currenta
ID(on)
VGS = 10 V
VDS5 V
20
-
-
Drain-Source On-State Resistancea
Forward Transconductanceb
RDS(on)
VGS = 10 V
ID = 5 A
-
0.022
0.032
VGS = 10 V
ID = 5 A, TJ = 125 °C
-
0.035
0.050
VGS = 10 V
ID = 5 A, TJ = 175 °C
-
0.042
0.060
VGS = 4.5 V
ID = 4 A
-
0.037
0.046
-
14
-
gfs
VDS = 10 V, ID = 5 A
V
nA
μA
A

S
Dynamicb
-
540
650
-
120
145
Crss
-
80
95
Qg
-
14
21
-
2
-
-
4
-
f = 1 MHz
1.35
2.70
4.05
-
6
8
VDD = 20 V, RL = 13.3 
ID  1.5 A, VGEN = 10 V, Rg = 1 
-
11
14
-
17
21
-
9
11
Input Capacitance
Ciss
Output Capacitance
Coss
Reverse Transfer Capacitance
Total Gate Chargec
Gate-Source
Chargec
Qgs
Gate-Drain Chargec
Qgd
Gate Resistance
Rg
Turn-On Delay
Timec
Rise Timec
Turn-Off Delay Timec
Fall Timec
VGS = 0 V
VDS = 20 V, f = 1 MHz
VGS = 10 V
VDS = 20 V, ID = 6 A
td(on)
tr
td(off)
tf
pF
nC

ns
Source-Drain Diode Ratings and Characteristicsb
Pulsed Currenta
ISM
Forward Voltage
VSD
IF = 4 A, VGS = 0 V
-
-
32
A
-
0.8
1.2
V
Notes
a. Pulse test; pulse width  300 μs, duty cycle  2 %.
b. Guaranteed by design, not subject to production testing.
c. Independent of operating temperature.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation
of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
S11-2129 Rev. B, 31-Oct-11
2
Document Number: 71490
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
SQS464EEN
www.vishay.com
Vishay Siliconix
TYPICAL CHARACTERISTICS (TA = 25 °C, unless otherwise noted)
10-2
0.005
TJ = 25 °C
IGSS - Gate Current (μA)
IGSS - Gate Current (mA)
0.004
0.003
0.002
10-4
TJ = 150 °C
10-6
TJ = 25 °C
10
-8
0.001
0.000
0
6
12
18
24
10-10
30
0
6
12
VGS - Gate-Source Voltage (V)
18
24
30
VGS - Gate-Source Voltage (V)
Gate Current vs. Gate-Source Voltage
Gate Current vs. Gate-Source Voltage
30
30
VGS = 10 V thru 5 V
24
ID - Drain Current (A)
ID - Drain Current (A)
24
18
12
VGS = 4 V
6
18
12
TC = 25 °C
6
TC = 125 °C
VGS = 3 V
0
0
2
4
6
8
0
10
0
VDS - Drain-to-Source Voltage (V)
2
6
8
10
Transfer Characteristics
Output Characteristics
0.15
TC = 25 °C
0.12
RDS(on) - On-Resistance (Ω)
20
gfs - Transconductance (S)
4
VGS - Gate-to-Source Voltage (V)
25
TC = - 55 °C
15
10
TC = 125 °C
5
0
TC = - 55 °C
0.09
VGS = 4.5 V
0.06
VGS = 10 V
0.03
0
2
4
6
8
0.00
10
ID - Drain Current (A)
6
12
18
24
30
ID - Drain Current (A)
On-Resistance vs. Drain Current
Transconductance
S11-2129 Rev. B, 31-Oct-11
0
3
Document Number: 71490
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
SQS464EEN
www.vishay.com
Vishay Siliconix
TYPICAL CHARACTERISTICS (TA = 25 °C, unless otherwise noted)
1000
10
VGS - Gate-to-Source Voltage (V)
VDS = 20 V
ID = 6 A
C - Capacitance (pF)
800
Ciss
600
400
Coss
200
8
6
4
2
Crss
0
0
5
10
15
20
25
30
35
0
40
0
3
6
9
12
15
Qg - Total Gate Charge (nC)
VDS - Drain-to-Source Voltage (V)
Gate Charge
Capacitance
2.0
100
1.7
10
IS - Source Current (A)
RDS(on) - On-Resistance (Normalized)
ID = 5 A
1.4
VGS = 10 V
1.1
0.8
1
TJ = 150 °C
TJ = 25 °C
0.1
0.01
0.5
- 50
- 25
0
25
50
75
100
125
150
0.001
0.0
175
0.2
TJ - Junction Temperature (°C)
0.6
0.8
1.0
1.2
Source-Drain Diode Forward Voltage
On-Resistance vs. Junction Temperature
0.25
0.6
0.3
VGS(th) Variance (V)
0.20
RDS(on) - On-Resistance (Ω)
0.4
VSD - Source-to-Drain Voltage (V)
0.15
0.10
0.0
- 0.3
ID = 5 mA
ID = 250 μA
- 0.6
TJ = 150 °C
0.05
- 0.9
TJ = 25 °C
0.00
0
2
4
6
8
- 1.2
- 50
10
- 25
0
25
50
75
100
125
VGS - Gate-to-Source Voltage (V)
TJ - Junction Temperature (°C)
On-Resistance vs. Gate-to-Source Voltage
Threshold Voltage
S11-2129 Rev. B, 31-Oct-11
4
150
175
Document Number: 71490
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
SQS464EEN
www.vishay.com
Vishay Siliconix
TYPICAL CHARACTERISTICS (TA = 25 °C, unless otherwise noted)
50
VDS - Drain-to-Source Voltage (V)
ID = 1 mA
48
46
44
42
40
- 50
- 25
0
25
50
75
100
125
150
175
TJ - Junction Temperature (°C)
Drain Source Breakdown vs. Junction Temperature
THERMAL RATINGS (TA = 25 °C, unless otherwise noted)
100
ID Limited
IDM Limited
ID - Drain Current (A)
100 μs
10
Limited by RDS(on)*
1 ms
10 ms
100 ms, 1 s,
10 s, DC
1
0.1
TC = 25 °C
Single Pulse
0.01
0.01
BVDSS Limited
0.1
1
10
100
VDS - Drain-to-Source Voltage (V)
* VGS > minimum VGS at which RDS(on) is specified
Safe Operating Area
S11-2129 Rev. B, 31-Oct-11
5
Document Number: 71490
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
SQS464EEN
www.vishay.com
Vishay Siliconix
THERMAL RATINGS (TA = 25 °C, unless otherwise noted)
1
Normalized Effective Transient
Thermal Impedance
Duty Cycle = 0.5
0.2
0.1
Notes:
0.1
PDM
0.05
t1
t2
1. Duty Cycle, D =
t1
t2
2. Per Unit Base = RthJA = 81 °C/W
0.02
3. TJM - TA = PDMZthJA(t)
Single Pulse
4. Surface Mounted
0.01
10 -4
10 -3
10 -2
10 -1
1
100
10
1000
Square Wave Pulse Duration (s)
Normalized Thermal Transient Impedance, Junction-to-Ambient
2
Normalized Effective Transient
Thermal Impedance
1
Duty Cycle = 0.5
0.2
0.1
0.1
Single Pulse
0.05
0.02
0.01
10-4
10-3
10-2
Square Wave Pulse Duration (s)
10-1
1
Normalized Thermal Transient Impedance, Junction-to-Case
Note
• The characteristics shown in the two graphs
- Normalized Transient Thermal Impedance Junction-to-Ambient (25 °C)
- Normalized Transient Thermal Impedance Junction-to-Case (25 °C)
are given for general guidelines only to enable the user to get a “ball park” indication of part capabilities. The data are extracted from single
pulse transient thermal impedance characteristics which are developed from empirical measurements. The latter is valid for the part
mounted on printed circuit board - FR4, size 1" x 1" x 0.062", double sided with 2 oz. copper, 100 % on both sides. The part capabilities
can widely vary depending on actual application parameters and operating conditions.
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
reliability data, see www.vishay.com/ppg?71490.
S11-2129 Rev. B, 31-Oct-11
6
Document Number: 71490
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Package Information
Vishay Siliconix
D4
PowerPAK® 1212-8, (SINGLE/DUAL)
W
H
E2
E4
L
K
M
θ
e
1
Z
D5
D
D2
2
2
D1
8
1
5
4
θ
4
b
3
L1
E3
A1
Backside View of Single Pad
H
2
E1
E
Detail Z
1
D1
2
K1
Notes:
1. Inch will govern
2
D2
Dimensions exclusive of mold gate burrs
3. Dimensions exclusive of mold flash and cutting burrs
L
K
E2
E4
D2 D3(2x) D4
c
A
H
3
4
b
θ
D5
θ
E3
Backside View of Dual Pad
MILLIMETERS
INCHES
DIM.
MIN.
NOM.
MAX.
MIN.
NOM.
A
0.97
1.04
1.12
0.038
0.041
MAX.
0.044
A1
0.00
-
0.05
0.000
-
0.002
b
0.23
0.30
0.41
0.009
0.012
0.016
0.013
c
0.23
0.28
0.33
0.009
0.011
D
3.20
3.30
3.40
0.126
0.130
0.134
D1
2.95
3.05
3.15
0.116
0.120
0.124
D2
1.98
2.11
2.24
0.078
0.083
0.088
D3
0.48
-
0.89
0.019
-
0.035
D4
0.47 TYP.
D5
2.3 TYP.
0.0185 TYP.
0.090 TYP.
E
3.20
3.30
3.40
0.126
0.130
0.134
E1
2.95
3.05
3.15
0.116
0.120
0.124
E2
1.47
1.60
1.73
0.058
0.063
0.068
E3
1.75
1.85
1.98
0.069
0.073
0.078
0.34 TYP.
E4
0.013 TYP.
e
0.65 BSC
0.026 BSC
K
0.86 TYP.
0.034 TYP.
K1
0.35
-
-
0.014
-
-
H
0.30
0.41
0.51
0.012
0.016
0.020
L
0.30
0.43
0.56
0.012
0.017
0.022
L1
0.06
0.13
0.20
0.002
0.005
0.008
θ
0°
-
12°
0°
-
12°
W
0.15
0.25
0.36
0.006
0.010
0.014
M
0.125 TYP.
0.005 TYP.
ECN: S10-0951-Rev. J, 03-May-10
DWG: 5882
Document Number: 71656
Revison: 03-May-10
www.vishay.com
1
AN822
Vishay Siliconix
PowerPAK® 1212 Mounting and Thermal Considerations
Johnson Zhao
MOSFETs for switching applications are now available
with die on resistances around 1 mΩ and with the
capability to handle 85 A. While these die capabilities
represent a major advance over what was available
just a few years ago, it is important for power MOSFET
packaging technology to keep pace. It should be obvious that degradation of a high performance die by the
package is undesirable. PowerPAK is a new package
technology that addresses these issues. The PowerPAK
1212-8 provides ultra-low thermal impedance in a
small package that is ideal for space-constrained
applications. In this application note, the PowerPAK
1212-8’s construction is described. Following this,
mounting information is presented. Finally, thermal
and electrical performance is discussed.
THE PowerPAK PACKAGE
The PowerPAK 1212-8 package (Figure 1) is a derivative of PowerPAK SO-8. It utilizes the same packaging
technology, maximizing the die area. The bottom of the
die attach pad is exposed to provide a direct, low resistance thermal path to the substrate the device is
mounted on. The PowerPAK 1212-8 thus translates
the benefits of the PowerPAK SO-8 into a smaller
package, with the same level of thermal performance.
(Please refer to application note “PowerPAK SO-8
Mounting and Thermal Considerations.”)
The PowerPAK 1212-8 has a footprint area comparable to TSOP-6. It is over 40 % smaller than standard
TSSOP-8. Its die capacity is more than twice the size
of the standard TSOP-6’s. It has thermal performance
an order of magnitude better than the SO-8, and 20
times better than TSSOP-8. Its thermal performance is
better than all current SMT packages in the market. It
will take the advantage of any PC board heat sink
capability. Bringing the junction temperature down also
increases the die efficiency by around 20 % compared
with TSSOP-8. For applications where bigger packages are typically required solely for thermal consideration, the PowerPAK 1212-8 is a good option.
Both the single and dual PowerPAK 1212-8 utilize the
same pin-outs as the single and dual PowerPAK SO-8.
The low 1.05 mm PowerPAK height profile makes both
versions an excellent choice for applications with
space constraints.
PowerPAK 1212 SINGLE MOUNTING
To take the advantage of the single PowerPAK 1212-8’s
thermal performance see Application Note 826,
Recommended Minimum Pad Patterns With Outline
Drawing Access for Vishay Siliconix MOSFETs. Click
on the PowerPAK 1212-8 single in the index of this
document.
In this figure, the drain land pattern is given to make full
contact to the drain pad on the PowerPAK package.
This land pattern can be extended to the left, right, and
top of the drawn pattern. This extension will serve to
increase the heat dissipation by decreasing the thermal resistance from the foot of the PowerPAK to the
PC board and therefore to the ambient. Note that
increasing the drain land area beyond a certain point
will yield little decrease in foot-to-board and foot-toambient thermal resistance. Under specific conditions
of board configuration, copper weight, and layer stack,
experiments have found that adding copper beyond an
area of about 0.3 to 0.5 in2 of will yield little improvement in thermal performance.
Figure 1. PowerPAK 1212 Devices
Document Number 71681
03-Mar-06
www.vishay.com
1
AN822
Vishay Siliconix
PowerPAK 1212 DUAL
To take the advantage of the dual PowerPAK 1212-8’s
thermal performance, the minimum recommended
land pattern can be found in Application Note 826,
Recommended Minimum Pad Patterns With Outline
Drawing Access for Vishay Siliconix MOSFETs. Click
on the PowerPAK 1212-8 dual in the index of this document.
The gap between the two drain pads is 10 mils. This
matches the spacing of the two drain pads on the PowerPAK 1212-8 dual package.
This land pattern can be extended to the left, right, and
top of the drawn pattern. This extension will serve to
increase the heat dissipation by decreasing the thermal resistance from the foot of the PowerPAK to the
PC board and therefore to the ambient. Note that
increasing the drain land area beyond a certain point
will yield little decrease in foot-to-board and foot-toambient thermal resistance. Under specific conditions
of board configuration, copper weight, and layer stack,
experiments have found that adding copper beyond an
area of about 0.3 to 0.5 in2 of will yield little improvement in thermal performance.
ture profile used, and the temperatures and time
duration, are shown in Figures 2 and 3. For the lead
(Pb)-free solder profile, see http://www.vishay.com/
doc?73257.
REFLOW SOLDERING
Vishay Siliconix surface-mount packages meet solder
reflow reliability requirements. Devices are subjected
to solder reflow as a preconditioning test and are then
reliability-tested using temperature cycle, bias humidity, HAST, or pressure pot. The solder reflow tempera-
Ramp-Up Rate
+ 6 °C /Second Maximum
Temperature at 155 ± 15 °C
120 Seconds Maximum
Temperature Above 180 °C
70 - 180 Seconds
Maximum Temperature
240 + 5/- 0 °C
Time at Maximum Temperature
20 - 40 Seconds
Ramp-Down Rate
+ 6 °C/Second Maximum
Figure 2. Solder Reflow Temperature Profile
10 s (max)
210 - 220 °C
3 ° C/s (max)
4 ° C/s (max)
183 °C
140 - 170 °C
50 s (max)
3° C/s (max)
60 s (min)
Pre-Heating Zone
Reflow Zone
Maximum peak temperature at 240 °C is allowed.
Figure 3. Solder Reflow Temperatures and Time Durations
www.vishay.com
2
Document Number 71681
03-Mar-06
AN822
Vishay Siliconix
TABLE 1: EQIVALENT STEADY STATE PERFORMANCE
Package
SO-8
TSSOP-8
TSOP-8
PPAK 1212
PPAK SO-8
Configuration
Single
Dual
Single
Dual
Single
Dual
Single
Dual
Single
Dual
Thermal Resiatance RthJC(C/W)
20
40
52
83
40
90
2.4
5.5
1.8
5.5
PowerPAK 1212
Standard SO-8
49.8 °C
2.4 °C/W
Standard TSSOP-8
85 °C
20 °C/W
TSOP-6
149 °C
52 °C/W
125 °C
40 °C/W
PC Board at 45 °C
Figure 4. Temperature of Devices on a PC Board
THERMAL PERFORMANCE
Introduction
Spreading Copper
A basic measure of a device’s thermal performance is
the junction-to-case thermal resistance, Rθjc, or the
junction to- foot thermal resistance, Rθjf. This parameter
is measured for the device mounted to an infinite heat
sink and is therefore a characterization of the device
only, in other words, independent of the properties of the
object to which the device is mounted. Table 1 shows a
comparison of the PowerPAK 1212-8, PowerPAK SO-8,
standard TSSOP-8 and SO-8 equivalent steady state
performance.
By minimizing the junction-to-foot thermal resistance, the
MOSFET die temperature is very close to the temperature of the PC board. Consider four devices mounted on
a PC board with a board temperature of 45 °C (Figure 4).
Suppose each device is dissipating 2 W. Using the junction-to-foot thermal resistance characteristics of the
PowerPAK 1212-8 and the other SMT packages, die
temperatures are determined to be 49.8 °C for the PowerPAK 1212-8, 85 °C for the standard SO-8, 149 °C for
standard TSSOP-8, and 125 °C for TSOP-6. This is a
4.8 °C rise above the board temperature for the PowerPAK 1212-8, and over 40 °C for other SMT packages. A
4.8 °C rise has minimal effect on rDS(ON) whereas a rise
of over 40 °C will cause an increase in rDS(ON) as high
as 20 %.
Designers add additional copper, spreading copper, to
the drain pad to aid in conducting heat from a device. It
is helpful to have some information about the thermal
performance for a given area of spreading copper.
Figure 5 and Figure 6 show the thermal resistance of a
PowerPAK 1212-8 single and dual devices mounted on
a 2-in. x 2-in., four-layer FR-4 PC boards. The two internal layers and the backside layer are solid copper. The
internal layers were chosen as solid copper to model the
large power and ground planes common in many applications. The top layer was cut back to a smaller area and
at each step junction-to-ambient thermal resistance
measurements were taken. The results indicate that an
area above 0.2 to 0.3 square inches of spreading copper
gives no additional thermal performance improvement.
A subsequent experiment was run where the copper on
the back-side was reduced, first to 50 % in stripes to
mimic circuit traces, and then totally removed. No significant effect was observed.
Document Number 71681
03-Mar-06
www.vishay.com
3
AN822
Vishay Siliconix
130
105
Spreading Copper (sq. in.)
Spreading Copper (sq. in.)
120
95
110
100
RthJ A (°C/W)
RthJA (°C/W)
85
75
65
90
80
50 %
100 %
70
100 %
55
0%
60
50 %
0%
50
45
0.00
0.25
0.50
0.75
1.00
1.25
1.50
1.75
2.00
0.00
0.25
0.50
0.75
1.00
1.25
1.50
1.75
2.00
Figure 5. Spreading Copper - Si7401DN
Figure 6. Spreading Copper - Junction-to-Ambient Performance
CONCLUSIONS
As a derivative of the PowerPAK SO-8, the PowerPAK
1212-8 uses the same packaging technology and has
been shown to have the same level of thermal performance while having a footprint that is more than 40 %
smaller than the standard TSSOP-8.
Recommended PowerPAK 1212-8 land patterns are
provided to aid in PC board layout for designs using this
new package.
The PowerPAK 1212-8 combines small size with attractive thermal characteristics. By minimizing the thermal
rise above the board temperature, PowerPAK simplifies
thermal design considerations, allows the device to run
cooler, keeps rDS(ON) low, and permits the device to
handle more current than a same- or larger-size MOSFET die in the standard TSSOP-8 or SO-8 packages.
www.vishay.com
4
Document Number 71681
03-Mar-06
Application Note 826
Vishay Siliconix
RECOMMENDED MINIMUM PADS FOR PowerPAK® 1212-8 Single
0.152
(3.860)
0.039
0.068
(0.990)
(1.725)
0.010
(0.255)
(2.390)
0.094
0.088
(2.235)
0.016
(0.405)
0.026
(0.660)
0.025
0.030
(0.635)
(0.760)
Recommended Minimum Pads
Dimensions in Inches/(mm)
Return to Index
Return to Index
APPLICATION NOTE
Document Number: 72597
Revision: 21-Jan-08
www.vishay.com
7
Legal Disclaimer Notice
www.vishay.com
Vishay
Disclaimer
ALL PRODUCT, PRODUCT SPECIFICATIONS AND DATA ARE SUBJECT TO CHANGE WITHOUT NOTICE TO IMPROVE
RELIABILITY, FUNCTION OR DESIGN OR OTHERWISE.
Vishay Intertechnology, Inc., its affiliates, agents, and employees, and all persons acting on its or their behalf (collectively,
“Vishay”), disclaim any and all liability for any errors, inaccuracies or incompleteness contained in any datasheet or in any other
disclosure relating to any product.
Vishay makes no warranty, representation or guarantee regarding the suitability of the products for any particular purpose or
the continuing production of any product. To the maximum extent permitted by applicable law, Vishay disclaims (i) any and all
liability arising out of the application or use of any product, (ii) any and all liability, including without limitation special,
consequential or incidental damages, and (iii) any and all implied warranties, including warranties of fitness for particular
purpose, non-infringement and merchantability.
Statements regarding the suitability of products for certain types of applications are based on Vishay’s knowledge of typical
requirements that are often placed on Vishay products in generic applications. Such statements are not binding statements
about the suitability of products for a particular application. It is the customer’s responsibility to validate that a particular
product with the properties described in the product specification is suitable for use in a particular application. Parameters
provided in datasheets and/or specifications may vary in different applications and performance may vary over time. All
operating parameters, including typical parameters, must be validated for each customer application by the customer’s
technical experts. Product specifications do not expand or otherwise modify Vishay’s terms and conditions of purchase,
including but not limited to the warranty expressed therein.
Except as expressly indicated in writing, Vishay products are not designed for use in medical, life-saving, or life-sustaining
applications or for any other application in which the failure of the Vishay product could result in personal injury or death.
Customers using or selling Vishay products not expressly indicated for use in such applications do so at their own risk and agree
to fully indemnify and hold Vishay and its distributors harmless from and against any and all claims, liabilities, expenses and
damages arising or resulting in connection with such use or sale, including attorneys fees, even if such claim alleges that Vishay
or its distributor was negligent regarding the design or manufacture of the part. Please contact authorized Vishay personnel to
obtain written terms and conditions regarding products designed for such applications.
No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document or by
any conduct of Vishay. Product names and markings noted herein may be trademarks of their respective owners.
Material Category Policy
Vishay Intertechnology, Inc. hereby certifies that all its products that are identified as RoHS-Compliant fulfill the
definitions and restrictions defined under Directive 2011/65/EU of The European Parliament and of the Council
of June 8, 2011 on the restriction of the use of certain hazardous substances in electrical and electronic equipment
(EEE) - recast, unless otherwise specified as non-compliant.
Please note that some Vishay documentation may still make reference to RoHS Directive 2002/95/EC. We confirm that
all the products identified as being compliant to Directive 2002/95/EC conform to Directive 2011/65/EU.
Revision: 12-Mar-12
1
Document Number: 91000