STU2071 4B3T U INTERFACE CIRCUIT PRELIMINARY DATA 4B3T TWO-WIRE U INTERFACE CIRCUIT FOR LT AND NT APPLICATION 120 kbaud LINE SYMBOL RATE (120 SYMBOLS PER FRAME) SCRAMBLER AND DESCRAMBLER ACCORDING TO CCITT REC V.29 BARKER CODE (11 SYMBOLS) SYNCHRONIZATION WORD UNSCRAMBLED 1 KBIT/S HOUSEKEEPING CHANNEL ADAPTIVE ECHO CANCELLATION WITH TRANSVERSAL FILTERING ADAPTIVE DECISION FEEDBACK EQUALIZATION AUTOMATIC GAIN CONTROL PDM AD CONVERTER AUTOMATIC ACTIVATION AND DEACTIVATION WITH POLARITY ADAPTION AUTOMATIC CODE VIOLATION DETECTION POWER FEED UNIT CONTROL ADVANCED CL3 1.5µm CMOS PROCESS 28 PIN DUAL-IN-LINE PLASTIC PACKAGE V* DIGITAL INTERFACE DIP28 ORDERING NUMBER: STU2071B1 PLCC28 ORDERING NUMBER: STU2071FN SYSTEM OVERVIEW STU2071 (UIC) provides two transparent 64 kbit/s B channels, a transparent 16 kbit/s D channel, a transparent 1 kbit/s service channel and a 1 kbit/s maintenance channel for loop and error messages on subscriber lines. UIC enables full duplex continuous data transmission via the standard twisted pair telephone cable. Adaptive Echo cancellation is used to restore the received data. An equalizer, done with an adaptive filter, restores the data which are distorted by the transmission line. The coefficient of the equalizer and echo canceller are conserved during a power down. An all digital PLL performs both bit and frame synchronization. The analog front end consists of receive path RX and transmit path TX, providing a full duplex analog interfacing to the twisted pair telephone cable. Before data are converted to analog signals, they September 1994 pass through a digital filter (TX-filter) to reduce the high frequency components. After D/A conversion the signal is amplified and sent to the hybrid. The received signal is converted back to digital data and passed through the RX matching filter to restore the line signal. The A/D convertor is a second order sigma/delta modulator which operates with a clock of 15.36 MHz. After timing recovery, achieved by a digital PLL, the received signal is equalized, in an adaptive digital filter, to correct for the frequency and group delay distortion of the line. Power supply status can be read via PFOFF. The UIC can disable its power supply (DISS), and two relay drivers outputs are provided (accessible via B2*) to control the power feed unit (RD1,RD2). 1/18 This is advanced information on a new product now in development or undergoing evaluation. Details are subject to change without notice. STU2071 Figure 1: UIC Schematic Block Diagram 2/18 LT PFOFF DVSS CLS XTAL2 XTAL1 4 3 2 1 28 27 26 DISS/COEF 5 25 LIN2 RESETN 6 24 LIN1 DIN 7 23 LOUT2 22 AGND TSP 8 BURST PLCC28 19 AVSS 12 13 14 15 16 17 18 S0 11 DVDD DOUT S1 LOUT1 S2 AVDD 20 RD2 21 10 RD1 9 FR CL DIP28 TEST PIN CONNECTION (Top view) D93TL041 STU2071 PIN DESCRIPTION Pin Name 1 DVSS(input) 2 PFOFF(input) 3 LT(input) 4 TEST(input) 5 DISS(output) 6 RESETN(input) Function Digital Ground. Power feed off. PFOFF=HIGH is coded by the A-bit indication HI accessible on DOUT. Active in LT mode only. LT/NT mode selection. Test Mode. A bit channel driven pin. Active in LT mode only. Hardware Reset. 7 DIN(input) Digital interface input. 8 TSP(input) Transmit single pulse. 1 KHz single pulse alternating positive and negative polarity is transmitted. 9 10 BURST(input) FR(in/out) 11 DOUT(output) 12 CL(in/out) 13 RD1(output) Power feeder relay driver. Power feeder relay driver. 14 RD2(output) 15, 16, 17 S2,S1,S0 18 DVDD(input) 19 20 AVSS(input) LOUT1(output) Burst mode selection. Active in LT mode only. 8KHz Digital interface frame clock; input in LT and output in NT mode. Digital interface output. Digital interface bit clock; input in LT and output in NT mode. Time slot pin strap (. Active in LT mode only. 5V +/-5% positive digital power supply. Analog Ground. Output to the line. 21 AVDD(input) 5V +/-5% positive analog power supply. 22 AGND(input) Analog Ground. 23 24,25 LOUT2(output) LIN1,LIN2(input) 26, 27 XTAL1,XTAL2(inputs) 28 CLS(output) Output to the line. Inputs from the line (UK0). System clock input;nominal frequency is 15.36MHz. Clock output synchronous to the line receive clock at 7.68MHz. In LT burst: APPLICATION AND MODES The UIC can be used in LT, LT-burst and in NT mode. Hereafter a list of the pin bias to set up the desired mode is given. In LT mode: Pins LT BURST S0 S1 S2 Value 1 0 0 0 0 Pins LT BURST S0 S1 S2 Value 1 1 time slot time slot time slot In NT: Pins LT BURST S0 S1 S2 Value 0 0 0 0 1 Test pins should always be tied to GND 3/18 STU2071 MODE DEPENDENT FUNCTIONS PIN LT input BURST input S2, S1, S0 input DIN DOUT input output CLS (MHz) output CL (KHz) input output FR (KHz) input output LT burst 1 1 static 2048 kbit/s 7.68 4096 – 8 – NT 0 0 100 256 kbit/s 7.68 – 512 – 8 MODE LT 1 0 000 256 kbit/s 7.68 512 – 8 – LTRP 0 0 001 256 kbit/s – 512 – 8 – RECOMMENDED APPLICATIONS LT mode Figure 2: LT Schematic Application Diagram DIN: DOUT: CL: FR: XTAL2: CLS: 4/18 Data input, datarate = 256 kbit/s, continuous Data output, datarate = 256 kbit/s, continuous Data clock input, f = 512 KHz Frame clock input, f = 8 KHz (1:1) System clock input, f = 15.36 MHz (Tx clock synchronous to system clock) Clock output, 7.68 MHz NTRP 0 0 010 256 kbit/s 7.68 – 512 – 8 STU2071 NT mode Figure 3: LT Schematic Application Diagram DIN: DOUT: CL: FR: XTAL1/2: CLS: Data input, datarate = 256 kbit/s, continuous Data output, datarate = 256 kbit/s, continuous Data clock input, f = 512 KHz Frame clock input, f = 8 KHz (1:1) 15.36 MHz Xtal connection (Clock not synchronous to system clock) Clock output, 7.68 MHz (used to synch S interface) 5/18 STU2071 LT burst mode Figure 4: LT Burst Mode Schematic Application Diagram. DIN: DOUT: CL: FR: XTAL2: CLS: 6/18 Data input, datarate = 2048 kbit/s, continuous Data output, datarate = 2048 kbit/s, continuous Data clock input, f = 4096 KHz Frame clock input, f = 8 KHz (1:1) System clock input, f = 15.36 MHz (Tx clock synchronous to system clock) Clock output, 7.68 MHz STU2071 Figure 5: Repeater Block Diagram. To line - NT side A-wire To line - LT side A-wire UIC LTrep DIN DOUT DOUT DIN HYBRID UIC NTrep CL CL FR FR HYBRID XTAL2 XTAL2 B-wire CLOUT 15.36MHz CLOUT 512KHz XTAL1 5V 512KHz B-wire 0V 15.36MHz VCO 15.36MHz PLL circuit PHASE COMPARATOR AND LOOP FILTER(*) DC/DC 50mH 2.2µF 2.2µF 50mH D94TL099 (*)1st order loop filter is sufficient (3dB frequency at 100Hz approx.) 7/18 STU2071 DIGITAL INTERFACE UIC is provided with a digital serial interface, named V*, which operates in two modes. In Fig. 6 the frame format for both modes is shown. The base frame consists of: B1 : 64 kbit/s transparent data channel B2 : 64 kbit/s transparent data channel B2* : Monitor channel B1* : 8 bits so set D1/D2 : 16 kbit/s D channel A1..A4 : Command/Indicate channel T : Transparent service channel E : Extension bit In Fig. 7 and 8 the timings in Continuous and in Figure 6: V* Frame Format. Figure 7: Continuous Mode. 8/18 Burst mode are given. B2* available messages (do not use in REPETER modes): Code Function 74H Set RD1 to HIGH 75H Set RD2 to HIGH 76H Set RD1 and RD2 to HIGH 77H Reset RD1 and RD2 to LOW EFH Reset frame error counter (F0-FF)H NOD All others Not defined In Fig. 7 and 8 the timings in Continuous and in Burst mode are given. STU2071 Figure 8: Burst Mode. uses the frame structure here below. The length of one frame corresponds to 120 ternary symbols being transmitted within 1 ms. LINE FRAME STRUCTURE. The information flow across the subscriber line 1 T1 2 T1 3 T1 4 T1 5 T1 6 T1 7 T1 8 T1 9 T1 10 T1 11 T1 12 T1 T1 T1 T1 T1 T1 T1 T1 T1 T1 T1 T1 T1 24 T1 T2 T1 T2 T1 T2 T2 T2 T2 T2 T2 T2 T2 T2 T2 T2 T2 T2 T2 T2 T2 T2 T2 T2 36 48 T2 T2 T2 T2 T2 T2 T3 T3 T3 T3 T3 T3 60 T3 T3 T3 T3 T3 T3 T3 T3 T3 T3 T3 T3 T3 T3 T3 T3 T3 T3 T3 T4 T3 T4 T3 T4 72 84 T4 T4 T4 T4 T4 T4 T4 T4 T4 T4 T4 T4 96 T4 T4 T4 T4 T4 T4 T4 T4 T4 T4 T4 T4 108 T4 SW1 120 1 T5 2 T5 3 T5 4 T5 5 T5 6 T5 7 T5 8 T5 9 T5 19 T5 11 T5 12 T5 T5 M2 T5 T5 T5 T5 T5 T5 T5 T6 T5 T6 T5 T6 T5 T6 T5 T6 T5 T6 T5 T6 T5 T6 24 36 T6 T6 T6 T6 T6 T6 T6 T6 T6 T6 T6 T6 48 T6 T6 T6 T6 T6 T6 T6 SW2 T7 T7 T7 T7 T7 T7 60 72 T7 T7 T7 T7 T7 T7 T7 T7 T7 T7 T7 T7 84 T7 T8 T7 T8 T7 T8 T7 T8 T7 T8 T7 T8 T7 T8 T7 T8 T7 T8 T8 T8 T8 T8 T8 T8 96 108 T8 T8 T8 T8 T8 T8 T8 T8 T8 T8 T8 T8 120 Agenda: T1. . . . . .T8 M1, M2 SW1, SW2 LT ⇒ NT NT ⇒ LT B + B + D - Data (ternary) Service Data (ternary) Synchronizing Word 9/18 STU2071 Maintenance and service channel. The ternary symbols M1 and M2 represent nonscrambled data that can be transmitted at a rate of 1 kBaud. Those symbols are used for various purposes: - Maintenance Channel (control test loops (LT → NT) and frame errors (LT → NT) - Service channel (transparent user data and transmit messages from NT to LT) Encoding. The encoding of a binary bit stream is made such that 4 binary bits correspond to 3 symbols of ternary symbol stream. The encoding follows the rules of modified monitoring state 43 (MMS43). COMMAND / INDICATE CHANNEL (A bits) Command/Indicate codes are define depending on the mode selected (LT or NT). NT mode COMMANDS (DIN) ACT 1000 Activate. Layer 1 is activated at the UK0 interface starting with a ’wake-up’ signal INFO U1W, followed by INFO U1A during synchronization and closed by INFO U1 when synch is gained. AW 0000 DC 1111 Awake. Set the module interface from the power-down to the power-up state. No signal is emitted at UK0 interface. Even DIN pin pulled LOW can have the same effect. Deactivation confirmation. The module interface is deactivated. The transmitter is disabled but the receiver is still enabled to recognize an awake signal. THe UIC is set in power down state. RES 1101 Reset. Reset the UIC to the initial state. SY 1100 Synchronize. Drive the UIC in connect through from module interface to line interface. Remark: Executing the command RES (1101) is functionally equivalent to pulling the RESETN pin (6) LOW, with one exception: a) RES command set pin DISS to HIGH (+5V) b) pulling RESETN LOW set pin DISS to LOW (0V). NT mode INDICATION (DOUT) 10/18 ACT 1000 Activate. The synchronous state of the receiver is reached. Deactivation confirmation. The transmitter is disabled but the receiver remains enabled to detect awake signals at UK0 UIC is set in power down state. DC 1111 DEAC 0000 Deactivate. A request to deactivate INFO U0 has been detected. CT 1100 Connection Through. The UIC is fully activated. CTL2 1110 L2 1010 Connection through with loop 2. A loop 2 command has been detected at UK0. Loop 2. Synchronization has been reached during a Loop 2 activation procedure. RSYN 0100 Resynchronization. The receiver has lost framing and is attempting to resynchronize. STU2071 LT mode COMMANDS (DIN) ACT 1000 Activate. UIC is set in power-up state, executing the complete activation of Layer 1. The transparent channel transmission is enabled. AL 1001 Analog Loop. The analog transmitter output is looped back to the receiver input which is disconnected from UK0 interface. A pseudo wake-up procedure is executed. L2 1010 Loop 2. Command to close Loop 2 in NT. LTD 0011 Line Transmission Disabled. UIC stops transmitting signals on the line and is powered down. DEAC 0000 Deactivate. Request to deactivate UK0. RES 1101 Reset. Reset the UIC to the initial state. SSP 0101 Send Single Pulse. The UIC transmits single pulse at 1 ms time intervals with alternate polarity. L4 1011 Repeter loop LT mode INDICATION (DOUT) ACT 1000 Activation running. UIC is powered-up and the activation procedure is running. RDS 0111 Running Digital Sum. Given during activation procedure. The receiver has reached synchronization. CT 1100 Connection Through. Layer 1 activation procedure has been completed. B and D channels are transparently connected. DEAC 0001 Deactivation running. UIC is deactivating in response of a DEAC, RES or LTD command. DC 1111 Deactivation confirmation. UIC has completed the deactivation procedure. RSYN 0100 Resynchronization. The receiver has lost framing and is attempting to resynchronize. HI 0011 High Impedance. When pin PFOFF is HIGH indication HI is output and UIC starts transmitting INFO U0. Normally used to indicate that remote feeding has been switched off. POWER DOWN STATE Power consumption of most functions is reduced; module interface is not active; C/I messages cannot be exchanged. OSCILLATOR Oscillators of 15.36 MHz are required. When in NT a tollerances of +/-30 ppm is allowed, it is advisable to use in LT a tollerances of +/-20 ppm. ACTIVATION DEACTIVATION The ACTIVATION procedure consists of three steps: AWAKE, SYNCHRONIZE and CONNECT THROUGH. Activation times are (max): COLDSTART 1 sec WARMSTART 170 msec LINE RANGE The LINE RANGE depends on the cable section. Typically: up to 4.2Km with 0.4mm cable - 5.5Km - 0.5mm - 8.0Km - 0.6mm Assumed noise level for such performances is 10uV/SQRT(Hz) on a 200KHz bandwidth. The DEACTIVATION procedure consists of two steps: line DEACTIVATION and POWER DOWN. Deactivation time is (typ) 4 ms. LT CLOCK JITTER The phase jitter between Master Clock (15.36MHz) and interface clock (4.096MHz) should not exceed 50ns. 11/18 STU2071 ELECTRICAL CHARACTERISTICS Supply Voltages: DVDD = 5V +/- 5% AVDD = 5V +/- 5% AGND = 2.5V +/- 5% (max curr 0.25mA) Power consumption Active = max 280mW (line loaded at 150Ohm) Power down = Typ. 30mW = Max. 50mW DIGITAL INTERFACE STATIC CHARACTERISTICS Symbol Parameter VIH High Level Input Voltage VIL Low Level Input Voltage Test Condition Min. Typ. Max. 3.5 Unit V 1.0 V VOH1 High Level Output Voltage all outputs except DOUT IOH1 = 0.4mA VOH2 High Level Output Voltage DOUT, (Open Drain) R to DVDD R = 1KΩ VOL1 Low Level Output Voltage all outputs except DOUT IOL1 = 0.4mA 0.33 V VOL2 Low Level Output Voltage DOUT, (Open Drain) IOL1 = 0.7mA 0.4 V CIN Inputs Capacitance, all inputs at DOUT if output is off 10 10 pF pF COUT Load Capacitance at all outputs except at DOUT 25 pF COUT IIN Load Capacitance at DOUT Input Leakage Current 150 1 pF µA 12/18 VDD0.66 V 4 V STU2071 DIGITAL INTERFACE DYNAMIC CHARACTERISTICS Burst mode. Conditions Parameter Port from to Rise Time tr Fall Time tf Setup Time ts Setup Time ts Setup Time ts Setup Time ts FR, CL FR, CL FR FR DIN MPF 1.0V 3.5V FR, i – FR, i + DIN +/– MPF +/– 3.5V 1.0V CL, i + CL, i + CL, i + CL, i + Hold Time th Hold Time th Hold Time th Hold Time th FR FR DIN MPF CL, i + CL, i + CL, i + CL, i + FR, i – FR, i + DIN +/– MPF +/– Delay Time td Delay Time td DOUT DOUT CL, i – CL, i – DOUT +/– DOUT +/– Clock Width tc Clock Width tc CL, i CL, i CL +/– CL +/– CL +/– CL –/+ C R to DVDD Min. Max. pF KΩ ns ns 10 10 30 30 30 30 50 50 50 50 60 60 50 150 1 1 0 0 150 200 239 100 249 144 + = rising edge – = falling edge 13/18 STU2071 DIGITAL INTERFACE DYNAMIC CHARACTERISTICS (continued) Continuous mode. Conditions Parameter Rise Time tr Fall Time tf Rise Time tr Fall Time tf Port from to FR, CL, i FR, CL, i FR, CL, o FR, CL, o 1.0V 3.5V 10% 90% 3.5V 1.0V 90% 10% Setup Time ts Setup Time ts Delay Time td Hold Time th Hold Time th Delay Time td DIN MPF FR DIN MPF DOUT DIN +/– MPF +/– CL, i + CL, i – CL, i – CL, i + CL, i + CL, i + FR, i + DIN +/– DIN +/– DOUT +/– Setup Time ts Setup Time th Delay Time td Delay Time td Clock Width tc Clock Width tp Pulse Width tp Pulse Width tp DIN DIN DOUT FR DIN +/–1 CL, o – CL. o + CL, o + CL, o + DIN +/– DOUT +/– FR,o + CL, i CL, i CL, i CL, i CL +/– CL +/– CL +/– CL +/– CL +/– CL +/– CL –/+ CL –/+ + = rising edge – = falling edge 14/18 C R to DVDD Min. Max. pF KΩ ns ns 10 10 25 25 30 30 30 30 50 50 -200 100 100 25 10 200 500 50 100 25 25 25 25 10 -150 500 150 1830 1830 850 850 2080 2080 1100 1100 STU2071 DIGITAL INTERFACE DYNAMIC CHARACTERISTICS (continued) Master clock. Conditions Parameter Port from to C Min. Max. pF ns ns Rise Time tr Fall Time tf Rise Time tr Fall Time tf XTAL2 XTAL2 CLS CLS 1.0V 3.5V 10% 90% 3.5V 1.0V 90% 10% 10 10 25 25 Pulse Width CLS CLS +/– CLS –/+ 25 15 15 15 15 20 + = rising edge – = falling edge Setup Time ts Hold Time th Delay min. td Delay max. td Delay min. td (negative) Delay max. td DIN, FR, i +/– CL, i + CL, i + CL, i – CL, i + CL, i – CL, i + 2.5V 2.5V 2.5V 2.5V 2.5V CL, i + DIN, FR, i +/– DOUT +/– DOUT +/– FR, i + 2.5V 2.5V 0.4 / 4V 4 / 0.4V 3.5V CL, i + 2.5V FR, i + 1V Setup Time ts Hold Time ts Delay max. td Delay min. td (negative) Delay max. td DIN, +/– CL, o + CL, o + CL, o + 2.5V 2.5V 2.5V 2.5V CL, o + DIN +/– DOUT +/– FR, o + 2.5V 2.5V 4 / 0.4V 0.33V CL, o + 2.5V FR, o + VDD - 0.66V Pulse Width tp Clock Width tc CL, o +/– CL, o +/– 2.5V 2.5V CL, o –/+ CL, o +/– 2.5V 2.5V Pulse Width tp Clock Width tc CLS, MXCL +/– CLS, MXCL +/– 2.5V 2.5V CL, o –/+ CL, o +/– 2.5V 2.5V 15/18 STU2071 DIP28 PACKAGE MECHANICAL DATA mm DIM. MIN. TYP. MAX. MIN. TYP. a1 0.63 0.025 b 0.45 0.018 b1 0.23 b2 0.31 E 0.009 1.27 D 15.2 MAX. 0.012 0.050 37.34 16.68 1.470 0.598 0.657 e 2.54 0.100 e3 33.02 1.300 F 16/18 inch 14.1 0.555 I 4.445 0.175 L 3.3 0.130 STU2071 PLCC28 PACKAGE MECHANICAL DATA mm DIM. MIN. TYP. inch MAX. MIN. TYP. MAX. A 12.32 12.57 0.485 0.495 B 11.43 11.58 0.450 0.456 D 4.2 4.57 0.165 0.180 D1 2.29 3.04 0.090 0.120 D2 0.51 E 9.91 0.020 10.92 0.390 0.430 e 1.27 0.050 e3 7.62 0.300 F 0.46 0.018 F1 0.71 0.028 G 0.101 0.004 M 1.24 0.049 M1 1.143 0.045 17/18 STU2071 Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. SGS-THOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of SGS-THOMSON Microelectronics. © 1994 SGS-THOMSON Microelectronics - All Rights Reserved SGS-THOMSON Microelectronics GROUP OF COMPANIES Australia - Brazil - France - Germany - Hong Kong - Italy - Japan - Korea - Malaysia - Malta - Morocco - The Netherlands - Singapore Spain - Sweden - Switzerland - Taiwan - Thaliand - United Kingdom - U.S.A. 18/18