STV0674 ® Tri-mode CMOS digital camera co-processor Description Features The STV0674 is a flexible, scalable digital camera co-processor for use with the range of CMOS imaging sensor products from STMicroelectronics. ■ VGA or CIF CMOS sensor support The same chipset can be used for a wide range of digital imaging products with unique features and price/performance points. ■ Still image capture ■ Hardware color processing and JPEG compression of image data ■ Tethered video operation over USB ● The STV0674 is designed for use with CIF (352x288) or VGA (640x480) ST CMOS image sensors and provides full exposure control, color processing and mode control for these sensors. Simultaneous video and audio capture ■ USB ● USB for PC and MacOS (in development) ■ Flexible external memory options The STV0674 can be used to implement any of the following products: Low cost USB Webcam Camera - a two-chip solution providing up to 30 frames per second VGA simultaneous video and audio capture. ● SDRAM for lower cost, (8 or 16 bit) ● FLASH for non volatile storage (Data + Code) ● Smartmedia Card for removable data storage ● EEPROM for code storage Dual-Mode Camera - USB webcam and CIF or VGA digital still camera in a single product. ■ Record simultaneous video and audio direct to memory while untethered Tri-Mode Camera - USB webcam and digital still camera with the addition of a ‘camcorder’ mode to allow simultaneous video and audio capture directly to external memory for later upload to the PC. ■ Drivers for PC operating systems Win98, WinME, Win2K and WIn XP. Application Block Diagram STMicroelectonics CMOS Sensor Image Array STV0674 100TQFP USB Cable to Host PC 5 Video Processor Video Compression Hardware Enabled GPIO Interface Audio Playback Buzzer OR Memory SOCKET OEM Flashgun Module BOOT EE-PROM Micro Processor Audio POWER User Interface Buttons/ Switches NAND FLASH USB Interface SDRAM + x16 or x8 Microphone Firmware enabled SmartMedia Removable Flash card LCD Driver Chip LCD Icon Display OR LCD Driver Chip AMP LCD Image Display July 2003 ADCS 7269750C 1/35 STV0674 Table of Contents Chapter 1 1.1 Webcam Mode ..................................................................................................................... 5 1.2 Dual-Mode (Webcam plus Digital Still Camera) ................................................................... 5 1.3 Tri-Mode (Webcam plus Digital Still Camera plus Digital Movie/Audio Recorder) ............... 5 Chapter 2 STV0674 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 2.1 Sensor interface ................................................................................................................... 6 2.2 Video processor ................................................................................................................... 6 2.3 Video compressor ................................................................................................................ 6 2.4 Microcontroller ...................................................................................................................... 7 2.5 Memory interfaces ................................................................................................................ 7 2.6 Audio record ......................................................................................................................... 8 2.7 Audio playback ..................................................................................................................... 8 2.8 USB PC interface ................................................................................................................. 8 2.9 Power requirements ............................................................................................................. 8 Chapter 3 STV0674 Application Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 3.1 Webcam with audio .............................................................................................................. 9 3.2 Tri-mode camera ................................................................................................................ 10 Chapter 4 Detailed Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 4.1 Absolute maximum ratings ................................................................................................. 11 4.2 DC characteristics .............................................................................................................. 11 4.3 SDRAM interface ............................................................................................................... 13 4.4 NAND flash interface .......................................................................................................... 15 4.5 USB interface ..................................................................................................................... 20 4.6 Audio .................................................................................................................................. 21 4.7 SFP AC parameters ........................................................................................................... 22 4.8 Sensor interface ................................................................................................................. 22 4.9 Device current consumption in run and suspend modes ................................................... 23 Chapter 5 5.1 2/35 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 Pinout and Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 Device pinout ..................................................................................................................... 24 STV0674 5.2 Pin description .................................................................................................................... 26 5.3 Package outline and mechanical data ............................................................................... 31 5.4 External circuits .................................................................................................................. 32 Chapter 6 Evaluation Kit and Reference Design Manuals . . . . . . . . . . . . . . . . . . . . . . . . .33 6.1 Evaluation kit ...................................................................................................................... 33 6.2 Reference design manuals ................................................................................................ 33 Chapter 7 Ordering Details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 3/35 STV0674 Revision History Revision Date Changes A 03/10/2001 Initial release B 16/08/2002 Expansion of AC /DC specifications section 7 Added Figures 11 and 14, “Signals identified by functional group” Detail added to Table 10, pull down on SFP 19 required Detail added to Table 10, pull down on SFP 14 required C 4/35 17/04/2003 Deletion of any reference to 64TQFP package. 26/05/2003 DC charascteristics - Changed value for I/O high power current: 2 mA instead of 5.7 mA previously. STV0674 1 Overview Overview The STV0674 can be used to implement 3 different low-cost CMOS camera products as detailed here below. 1.1 Webcam Mode STV0674 allows a two-chip solution to provide a USB webcam, which can acquire and display images on the host system at frame rates of up to 30fps VGA. The addition of an external microphone allows simultaneous audio acquisition. Custom drivers require an additional low cost EEPROM which allows USB parameters such as Vendor ID /Product ID to be customised. 1.2 Dual-Mode (Webcam plus Digital Still Camera) While retaining all the features of the webcam, the addition of external storage memory allows the functionality of a digital still camera. On-chip JPEG compression permits high-density picture storage. 16Mbit to 128Mbit of SDRAM (8 or 16 bit) and/or 32Mbit to 1Gbit NAND flash memory are supported by the device. Also supported are the popular Smart Media Cards (SMC) to extend nonvolatile storage capability. The wide range of memory support allows the camera builder to tailor the system cost to suit their target market. A continuous image acquisition mode allows untethered (no host connection) video clips to be taken. As an example, with 15:1 compression ratio and 128Mbit memory over two minutes (QVGA @10fps) worth of video can be stored and up-loaded for display on the host. Full Direct Show driver support for Windows 98SE, ME, Windows 2000, Win XP is available. MacOS is currently in development. 1.3 Tri-Mode (Webcam plus Digital Still Camera plus Digital Movie/Audio Recorder) Again, retaining the features of the dual mode camera, the inclusion of audio record and playback circuitry adds another dimension to the product. An in-system microphone allows audio to be recorded and played back either via a speaker on the camera or via the host sound system. Audio can either be recorded simultaneously with video (camcorder) or independently of image acquisition (dictaphone). Audio data can also be downloaded from the host and played back on the camera when events take place. This allows any sampled soundbites to be played back on cameras, as opposed to the normal beeps from traditional cameras, which offers many possibilities for language customisation or licensed “character” cameras. As well as the memory and audio options already described, the GPIO and firmware emulation make it possible to support other custom peripherals such as icon or area displays. Other custom peripherals such as icon or area displays can be support via uncommitted general purpose I/O under firmware control. ST Microelectronics provides a software development kit (SDK) allowing OEMs to create custom PC applications, and an OEM pack to modify drivers to their specific requirements. 5/35 STV0674 Functional Description 2 STV0674 STV0674 Functional Description The STV0674 uses a combination of hardware functions and firmware to implement the required features. While the following features are selected and controlled via firmware their operation is carried out by dedicated hardware core. All dedicated hardware functions use fixed pin numbers which are detailed in Section 5.2. 2.1 Sensor interface The sensor interface is compatible with ST Microelectronics CIF and VGA sensors. This interface consists of a 5-wire sensor data output with additional sync signals, clocking, and I2C interface for configuration. All sensor communications, exposure/gain control, color processing, white balance control, and clocking are handled automatically by STV0674. 2.2 Video processor The video processor (VP) provides formatted YCbCr 4:2:2-sampled digital video at frame rates up to 30 frames per second to the video compressor (VC) module or internal video FIFO. The VP also interfaces directly to the image sensors. The interface to the sensor incorporates: ● a 5-wire data bus SDATA[4:0] that receives both video data and embedded timing references. ● a 2-wire serial interface SSDA,SSCL that controls the sensor and the sensor register configuration. ● the sensor clock SCLK. The video processing engine performs the following functions on incoming data 2.3 ● full colour restoration at each pixel site from Bayer-patterned input data ● defect correction ● matrixing/gain on each colour channel for colour purity ● auto white balance, exposure and gain control ● peaking for image clarity ● gamma correction ● colour space conversion (including hue and saturation control) from raw RGB to YCbCr[4:2:2]. Video compressor The video compression engine performs 3 main functions: ● Up scaling of input YCbCr 4:2:2 video stream from the VP (typically to scale from QVGA to CIF image formats), ● Compression and encoding of YCbCr stream into Motion-JPEG (M-JPEG) format, ● FIFO monitoring. The data stream from the VP can be up to VGA size. The scaler in VC can downsize this image. Once scaled, the video stream is then converted into M-JPEG format. M-JPEG treats video as a series of JPEG still images. The conversion is released via a sequential DCT (Discrete Cosine Transform) with Huffman encoding. After transfer through the digiport or over USB, the M-JPEG stream can be decoded in the host. 6/35 STV0674 STV0674 Functional Description The VC module varies the compression ratio to match the scene and selected frame rate, to the FIFO fill state. The VC module is capable of compression ratios of up to 100:1. Thumbnails can also be generated within the VC for potential display on an image LCD. The final stage of the VC block manages the data transfer rate from the local VC FIFO store to the memory or USB core. The VC can perform this management automatically, by employing long-term (frame-level) and short-term (block-level) compression management. 2.4 Microcontroller The STV0674 has an embedded high-performance 8052 8-bit microcontroller with 32 Kbytes of ROM and 32 Kbytes of SRAM available for program memory. The device functionality provided by default program ROM is generally sufficient to address all needs of a USB-tethered camera. In STV0674, code can be executed from the local SRAM as well as default ROM. The default ROM provides basic functions such as USB control, memory control, VP setup, systems installation, and the transfer of application specific code into the local SRAM. In non-tethered applications, the SRAM can be loaded from off-chip EEPROM via I2C or from an external flash device. If required in tethered applications, the SRAM can be loaded from the host PC via the USB. The ROM bootloader will load the application specific firmware code from one of the following sources, in order of priority: 1 EEPROM. 2 NAND FLASH. 3 PC host (in the case of a webcam). 2.5 Memory interfaces 2.5.1 NAND FLASH memory/SmartMedia card interface The NAND FLASH module for the STV0674 provides a dedicated interface to an external 32 Mbit to 1 Gbit NAND FLASH chip, and/or 4 Mbyte to 128 Mbyte SmartMedia card. NAND flash devices can contain a number of bit errors, and the core may deteriorate over time. Both occurrences are handled automatically by STV0674. A camera using NAND flash for image storage has the advantage that it can be powered off (e.g. auto power off, or for changing batteries) without losing images. No serial EEPROM is required as the application specific programme code can be stored in NAND flash memory. Note: 1 Support for SMC is for 3V3 cards. 5V cards are not supported. 2 Standard digital camera file formats (e.g. DOS file format, SSFDC) are not supported on SMC cards at this time. 2.5.2 SDRAM interface The STV0674 can use SDRAM for image storage and is designed to operate with PC66 or better compliant devices and supports 16Mbit, 64Mbit and 128Mbit parts in both the x16 SDRAM or x8 DRAM word widths. It is recommended that any SDRAM used have low self refresh Idd. 7/35 STV0674 Functional Description 2.5.3 STV0674 EEPROM interface The STV0674 supports up to 512Kbit EEPROM to hold application specific firmware code. Also, in the case of a tethered only web cam, lower density EEPROMs (down to 1Kbit) can be used to store information regarding custom USB Product ID, Vendor ID and power consumption. 2.6 Audio record The audio record block consists of a 16bit delta-sigma ADC using sampling frequencies of 8 kHz, 11.025 kHz, 16 kHz, 22.05 kHz, 32 kHz, 44.1 kHz and 48 kHz, with either differential or single ended inputs. The sampled output can be 8 or 16 bit. 2.7 Audio playback Audio playback is achieved by an internal Pulse Width Modulator with sample rates of 8kHz, 11.025kHz, 16kHz, 22.05kHz, 32kHz or 44.1kHz, connected to either an external amplifier chip and loudspeaker/ headphone socket or to a simple piezo buzzer. 2.8 USB PC interface The STV0674 includes a USB version 1.1 compliant Universal Serial Bus interface which requires the minimum of additional hardware. The interface key features are listed here below. ● Compliant with USB protocol revision 1.1 ● USB audio class compliant ● USB protocol handling ● USB device state handling ● Clock and data recovery from USB ● Bit stripping and bit stuffing functions ● CRC5 checking, CRC16 generation and checking ● Serial to parallel conversion ● Twin bulk end points (in/out) USB drivers are supplied by ST. For USB timing information, please refer to the USB specification version 1.1. 2.9 Power requirements STV0674 requires a 3V3 supply for I/O and a 1V8 supply for the core. 8/35 STV0674 3 STV0674 Application Examples STV0674 Application Examples The initial STV0674 released by ST Microelectronics is supplied with generic firmware application code to realise one of the following camera types. 3.1 Webcam with audio 3.1.1 Overview This camera uses the minimum of external components and has no user interface, batteries or memory for image storage. It is used as a tethered video capture camera over USB, with simultaneous audio and video. It is controlled entirely through PC drivers. The application specific firmware is downloaded from the PC. Note: A custom USB PID/VID can be configured by the use of an EEPROM, if required. 3.1.2 Application diagram Figure 1: Application diagram when using STV0674 as webcam with audio lens + IR filter STV0674 CMOS Sensor CIF or VGA image array Audio pre-amp microphone video processor audio interface video compression micro processor USB interface USB Cable to host PC external memory interface EEPROM embedded memory (not for image store) 9/35 STV0674 Application Examples 3.2 Tri-mode camera 3.2.1 Overview STV0674 Applications with the tri-mode camera based on STV0674 range from low-cost cameras containing an icon LCD status display, microphone/speaker and small SDRAM chip (for example 16Mbit), to an enhanced feature set camera containing a graphical image LCD display for image review, flashgun, audio record/playback, NAND flash on the PCB and a SmartMedia flash memory socket. 3.2.2 Application diagram Figure 2: Application diagram when using STV0674 as tri-mode camera Lens + IR Filter CMOS Sensor CIF or VGA Memory STV0674 100TQFP USB Cable to Host PC Image Array 5 Video Processor Video Compression Audio Interface Micro Processor External Memory Interface EEPROM only required if no NAND Flash Audio Playback POWER AMP Buzzer OR Embedded Memory (not for image store) LCD Interface Buttons/ Switches USB Interface Microphone OEM Flashgun Module NAND FLASH SDRAM + BOOT EEx16 or x8 -PROM Flash Enable/ Trigger User Interface Buttons Interface SOCKET SmartMedia Removable Flash card QUALITY LCD Driver Chip PICTURES SECONDS MBYTES MED LCD Status Icon Display OR LCD Driver Chip 23 PICS 640x480 LCD Image Display 10/35 HIGH LOW STV0674 Detailed Specifications 4 Detailed Specifications 4.1 Absolute maximum ratings Description Operating Temperature Storage Temperature Range Unit 0 to 70a oC -50 to 150 oC a. Refer to the sensor datasheet to determine operating temperature range of complete application 4.2 DC characteristics Table 1: DC characteristics Parameter Description Min Typ. Max Units Notes Note 4 VDDC Primary power supply (core) 1.55 1.8 1.95 V VDDI 3.3V power supply for on-chip USB transceiver and IO 3.0 3.3 3.6 V VDDP Analog supply to the PLL 1.60 1.8 2.0 V VDDA Analog supply to the audio front end 3.0 3.3 3.6 V core suspend current 6 µA I/O suspend current 31.5 µA PLL suspend current 0 µA Audio suspend current 1.5 µA Core low power current 12.5 mA Note 6 I/O low power current 0.9 mA Note 6 PLL low power current 0.5 mA Note 6 Audio low power current 1.5 µA Note 6 Core high power current 50.4 mA Note 6 I/O high power current 2 mA Note 6 PLL high power current 0.5 mA Note 6 Audio high power current 5.1 mA Note 6 Isuspend Ilowpower Ihighpower VILU USB differential pad D+/D- input low 0.8 VIHU USB differential pad D+/D- input high (driven) 2.0 VIHUZ USB differential pad D+/D- input high (floating) 2.7 VDI USB differential pad D+/D- input sensitivity 0.2 Note 5 V V 3.6 V V Note 1 11/35 Detailed Specifications STV0674 Table 1: DC characteristics Parameter Description Min Typ. Max Units Notes Note 2 VCM USB differential pad D+/D- common mode voltage 0.8 2.5 V VOLU USB differential pad D+/D- output low voltage 0.0 0.3 V VOHU USB differential pad D+/D- output high voltage 2.8 3.6 V VOHU USB differential pad D+/D- output high voltage 2.8 3.6 V VCRS USB differential pad D+/D- output signal cross over voltage 1.3 2.0 V Zdrv Driver output resistance 28 44 Ω VIl CMOS input low voltage (XTAL_IN) 0.631 V VIH CMOS input high voltage (XTAL_IN) VHYS Hysteresis (XTAL_IN) VIl CMOS input low voltage (TC pad) VIH CMOS input high voltage (TC pad) Vhyst Schmitt trigger hysteresis VT+ CMOS schmitt input low to high threshold voltage (TC pad) VT- 1.123 V 0.492 V V Note 3 0.65VD D V Note 3 0.4 V Note 3 2.15 V Note 3 CMOS schmitt input high to low threshold voltage (TC pad) 1.05 V Note 3 VT Threshold point (TC pad) 1.65 V Note 3 VOH Output high voltage (TC pad) VOL Output low voltage (TC pad) 0.35VDD 2.4 V 0.4 V Note: 1 VDI = |(D+) - (D-)| 2 VCM includes VDI range. 3 These figures apply to sfp, sensor_clk, sensor_scl, sensor_sda, test_mode and sensor_db. They do not apply to the XTAL_IN pad, these are specified separately. 4 In normal operation the actual device operating voltage is the worst case figure of the PLL and Core supplies, or 1.60V to 1.95V. 5 Below measurable limits. 6 See Section 4.9 12/35 STV0674 4.3 Detailed Specifications SDRAM interface Read/write timing diagrams for external synchronous DRAM Figure 3: SDRAM read timing tCK tCL tCH DCLK CKE tCMS tCMH Command A0-9,BA A10 ACTIVE READ NOP ROW PRECHARGE NOP COLUMN ROW tAS tAH tCMS tCMH tAC tOH DQM DQ DOUT M tRCD DOUT M + 1 DOUT M + 2 DOUT M + 3 CAS Latency tRC tRAS DQ sample tRP DQ sample DQ sample DQ sample 13/35 Detailed Specifications STV0674 Figure 4: SDRAM write timing tCK tCL tCH DCLK CKE tCMS Command tCMH WRITE ACTIVE A0-9,BA NOP ROW A10 PRECHARGE NOP COLUMN ROW tAS tCMS tAH tCMH tDS DQM DQ DIN M DIN M + 1 tDH DIN M + 2 tRCD DIN M + 3 tRC tRAS tRP Table 2: SDRAM timing Symbol Min tCK Typ. Max 41.67 Units Symbol Min Typ. Max Units ns tDS 20.12 ns tCH 20.11 20.83 21.55 tCK tDH 21.82 ns tCL 20.11 20.83 21.55 tCK tRCD 1 tCK 24.76 ns tRAS 2 tCK tAC tOH 0 ns tRC 4 tCK tCMS 20.27 ns tRP 2 tCK tCMH 20.02 ns tRRD 2 tCK tAS 20.67 ns tAH 19.79 ns Note: 1 The SDRAM interface is designed to operate with SDRAM devices which are compliant with the Intel SDRAM Specification Revision 1.7 November 1999. Speed grades 66, 100 and 133MHz are compatible. 2 Above timing assumes 20pF load per pad. 14/35 STV0674 Detailed Specifications 4.4 NAND flash interface 4.4.1 Command latch cycle for NAND flash interface Figure 5: Command latch cycle CLE tCLS tCLH CE_n tWP WE_n tALS tALH ALE tDS Command IO[7:0] 4.4.2 tDH Address Latch Cycle for NAND Flash Interface Figure 6: Address latch cycle CLE tCLS tWC CE_n tWP tWH WE_n tALH ALE tDS tDH IO[0:7] A0-A7 A9-A16 A17-A21 15/35 Detailed Specifications 4.4.3 STV0674 Input data latch cycles for NAND Flash interface Figure 7: Input data latch cycle CLE tCLH CE_n tALS tWC ALE tWP tWH WE_n tDS tDH DIN0 IO[0:7] 4.4.4 DIN1 DIN511 Sequential output cycle after read for NAND Flash interface Figure 8: Sequential output cycle after read tRC CE_n tRP tREH RE_n tREA IO[0:7] Dout tRR RB_n 16/35 Dout Dout STV0674 4.4.5 Detailed Specifications Status read cycle for NAND flash interface Figure 9: Status read cycle CLE tCLS tCLH tCLS CE_n tWP WE_n tWHR RE_n tDS tRSTO Status 70h IO[0:7] 4.4.6 tDH Read operation for NAND flash interface Figure 10: Read operation CLE CE_n WE_n tWB ALE tR RE_n tRR IO[0:7] 00H A0-7 A9-16 A17-21 Dout0 Dout1 Dout2 RB_n 17/35 Detailed Specifications 4.4.7 STV0674 Reset operation for NAND flash interface Figure 11: Reset operation CLE CE_n WE_n IO[0:7] FFh RB_n tRST 18/35 STV0674 4.4.8 Detailed Specifications AC characteristics for operation Table 3: AC characteristics Symbol Parameter Min Typical 62.4 Max Unit tCLS CLE set-up time 61.36 tCLH CLE hold time 83.2 ns tWP WE-n pulse width 83.2 ns tALS ALE set-up time 82.64 83.2 ns tALH ALE hold time 82.44 83.2 ns tDS Data set-up time 82.65 83.2 ns tDH Data hold time 61.85 62.4 ns tWC Write cycle time 145.09 145.6 ns tWH WE_n high hold time 61.89 62.4 ns tRR Ready to RE_n low 80.99 83.2 ns tRP RE_n pulse width 83.2 ns tRC Read cycle time 187.2 ns tREA RE_n access time tREH RE_n high hold time 103.47 104 ns tWHR WE_n high to RE_n low 124.22 124.8 ns tR Data transfer from cell to register tWB WE_n high to busy tRST Device resetting (Read) 35 41.6 ns 43.2 ns 25.015 µs 215.28 ns 5.015 µs Note: 1 All parameters relating to the CE_n signal are omitted as it is not enabled/disabled during execution of any NAND flash operation. 2 All timings are worst case. 3 Conforms to both Samsung and Toshiba specifications as outlined in datasheets 19/35 Detailed Specifications STV0674 4.5 USB interface 4.5.1 AC electrical characteristics of USB transceiver All measurements are fully electrically compliant to Chapter 7 (Electrical requirements) of revision 2 of the USB specification for full-speed devices (V1.1). The transceiver has been tested with external impedance-matching series resistors (27 Ω +/-5%) between the pads and the USB cable. Table 4: AC characteristics of USB transceiver Parameter Description Min Typ. Max Units TRANSMIT /OUTPUT STAGE tlr fall time 4.45 5.82 7.31 ns tlf rise time 4.55 5.77 6.81 ns tlrfm rise and fall time matching 90 111 % SYSTEM 20/35 Rpu USB differential pad Dp, Dn pullup Resistor 1.425 1.575 kΩ Rpd USB differential pad Dp, Dn pulldown Resistor 14.25 15.75 kΩ STV0674 Detailed Specifications 4.6 Audio 4.6.1 Audio ADC electrical parameters Table 5: Audio/ADC electrical characteristics Symbol Parameter Test conditions Min. Typ. Max. 12 Unit Fclk Clock frequency MHz Dutymclk Clk duty cycle 40 60 % Fs Sample frequency 8 48 kHz Vbias Bias reference voltage Vbias / Vcc = 3V Rbias Vbias impedance RIN 1.5 V Vbias 5 kΩ Input impedance IN+ / IN- 50 kΩ Cin Input capacitance IN+ / IN- 10 pF Dyn In Input dynamic range ADC Out Full scale IN+ / IN- Gain 0dB (AGC off) 1.5 Vpp SNR* Signal / Noise ratio Sinewave @FS - 3dB Gain 0dB 82 dB Offset Offset error After automatic calibration Harma Signal to peak harmonics Sinewave @FS - 3dB Gain 0dB 75 dB Sinewave @FS - 3dB Gain 24dB 50 dB PSRR Power supply rejection Measured on ADC output with a 1kHz 100mVpp sinewave added to the 3.3V supply LFc Low cut-off frequency Gain 0dB HFc High cut-off frequency ADC out 100 40 LSB LSBpp 15 0.45 Hz Fs a. Input sine wave 1kHz, Fmclk 11.289 MHz, BW = 10Hz-20 kHz, A-weighting filters, output 16 bits RAW PCM 4.6.2 Audio anti-aliasing filter characteristics Table 6: Audio anti-aliasing filter characteristics Symbol Parameter Fpassband Passband frequency Ripplepass Passband ripple 0->0.376Fs Fstopband Stopband frequency Test conditions Min. Fs is sampling frequency 0.45 -0.25 Fs is sampling frequency Typ. Max. Unit Fs 0.25 dB 0.6 Fs 21/35 Detailed Specifications 4.7 STV0674 SFP AC parameters Each SFP is a TTL schmitt trigger bidirectional pad Buffer, 3v3 capable with 2mA drive capability and Slew-rate Control. The 3.3V IOs comply to the EIA/JEDEC standard JESD8-B. For sake of convenience the most important parameters for measurement have been extracted and presented below. Table 7: SFP AC parameters Symbol 4.8 Description Min. Typ. Max. Unit Slew_rise 0.3Vcc to 0.6Vcc, CL = 10pF, balanced RL = 1KR to Vdd with RL = 1KR to Vss 1.63 1.83 1.97 V/ns Slew_fall 0.3Vcc to 0.6Vcc, CL = 10pF, balanced RL = 1KR to Vdd with RL = 1KR to Vss 2.05 2.32 2.62 V/ns Sensor interface Figure 12: Sensor interface timing tCK tCL sensor_clk tCH sensor_db[4:0] tAC tDH tDS Table 8: Sensor interface timing Symbol Min. Typ. Max. Unit 24 MHz tCK 0.1875 tCH 40.02 tCK tCL 40.02 tCK tDS 7.71 ns tDH 0 ns tAC 32.39 ns Note: 1 The above timings assume that the sensor_clk load is 20pF. 2 The sensor data setup and hold times are requirements of the STV0674. 3 tAC represents the maximum allowed clock to data delay from STV0674 sensor_clk pad to the STV0674 sensor data pads. (i.e. STV0674 pad to sensor PCB delay + sensor clock to data delay + sensor data pad to STV0674 pad PCB delay). 22/35 STV0674 4.9 Detailed Specifications Device current consumption in run and suspend modes The STV0674 power consumption has been estimated based on a webcam configuration. In this way, the analysis can specifically consider the device’s intrinsic power consumption rather than that associated with other system-level components. As STV0674 typically ends up in very low USB or battery powered applications, it is important device power consumption is measured in three different operating modes representing typical operating conditions in the real application. These three modes shall be referred to as low power mode, high power mode and suspend mode. Suspend mode is the is the lowest power mode of the device. For the core current, it can be effectively equated to ‘static’ power consumption. In this mode, all embedded clocks are stopped and all embedded logic blocks, macros, IP, etc. are reset into their low power modes. The XTAL oscillator pads (providing main clock source to entire STV0674) are also stopped. The name ‘Suspend’ mode historically comes from the device’s requirement to comply with USB ‘suspend’ mode where the total current drawn from the host PC by the USB peripheral is not allowed to exceed 500 µA. In low power mode, the embedded VP and VC module clocks are disabled and held in reset. The VP and VC are the two most power-hungry modules in the STV0674. A limited number of modules are enabled in this mode to allow USB enumeration, system-level self-configuration or camera userinterface functions. Such modules include the embedded microcontroller, USB core, memory subsystems and SFP core. In high power mode. The VP and VC module clocks is enabled and are brought out of reset. This is more typical of the real device application in that video data is being generated and processed. In measured cases the VP and VC are set up to their fastest (worst-case power) modes of operation processing VGA source data from the sensor at full 30 frames-per-second. Note: The baseline device power model presented here can be extended to cover other system-level configurations. In such cases the core IDD will remain as measured here (30fps/VGA) but the i/o IDD is more likely to vary depending for example on which memory type (sdram/nand) is being used. The power associated with each pin can be calculated based on its frequency (MHz), capacitive (C) and resistive (R) loading. 23/35 Pinout and Pin Description STV0674 5 Pinout and Pin Description 5.1 Device pinout Figure 13: STV0674 pinout in 100TQFP SFP38 SFP36 SFP37 SFP12 SFP35 VSS_3 SFP11 VDDI_2 SFP10 SFP8 SFP9 SFP7 SFP5 SFP6 SFP3 SFP4 SFP2 VSS_2 SFP1 VDDC_2 SFP33 SFP34 SFP32 SFP30 SFP31 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 1 SFP29 SFP39 75 2 SFP28 SFP40 74 3 SFP27 SFP41 73 4 SFP26 SFP42 72 5 SFP25 SFP43 71 6 SFP0 SFP13 70 7 VSS_1 SFP14 69 8 VDDI_1 VDDC_3 68 9 SCLK VSS_4 67 10 SDATA4 SFP15 66 11 SDATA3 SFP16 65 12 SDATA2 SFP17 64 13 SDATA1 SFP18 63 14 SDATA0 SFP19 62 15 SSDA VDDI_3 61 16 SSCL DP/RXD 60 17 VDDA DN 59 18 AP VSS_5 58 19 CBS RESET 57 20 AN SFP20 56 21 VSSA WAKEUP 55 22 SFP60 SFP44 54 23 SFP59 SFP45 53 24 SFP58 SFP46 52 25 SFP57 SFP47 51 SFP48 SFP49 SFP50 SFP51 SFP21 SFP22 SFP23 VSS_6 VDDI_4 XTALO XTALI TM2 VSSP VDDP TM1 VC TM0 SFP24 VSS_7 VDDC_1 SFP52 SFP54 SFP53 SFP55 SFP56 STV0674-100TQFP (14x14) 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 24/35 STV0674 Pinout and Pin Description Figure 14: Signals identified by functional group STV0674 VDDC VDDI 3 4 Power inputs Core I/O VDDP PLL VDDA Audio VSS 7 Grounds Common VSSP PLL VSSA Audio PLL and clock XTLI XTLO VC Audio AP AN CBS 3 Test RESET SCLK SSDA SSCL SDATA DP DN TM Interrupt/control WAKEUP Sensor interface 5 USB interface Special Function Pins 61 SFP 25/35 Pinout and Pin Description 5.2 STV0674 Pin description Table 9: 100TQFP pin description Pin Pin name Type Description CLOCKS AND RESETS 40, 41 57 XTLI, XTLO RESET OSC IS Crystal oscillator pad pair, see Figure 16 Reset input (Schmitt input level, active low) POWER SUPPLIES 31, 94, 68 VDDC_1, VDDC_2, VDDC_3 PWR Core power supply - 1V8 8, 82, 61, 42 VDDI_1, VDDI_2,VDDI_3, VDDI4 PWR I/O power supply - 3v3 7, 93, 81, 67, 58, 43, 32 VSS_1, VSS_2, VSS_3, GND Common ground. VSS_4, VSS_5, VSS_6, VSS_7 PLL POWER AND FILTER PINS 37 VDDP PWR Master and audio PLL supplies - 1V8 38 VSSP GND Master and audio PLL supplies - 0V 35 VC ANA Audio PLL filter, see Figure 17 AUDIO FRONT-END (ADC) POWER 17 VDDA PWR Audio front end supply - 3v3 21 VSSA GND Audio front-end supply - 0v SCLK O Camera clock (2mA CMOS) SDATA[4:0] I 5-bit sensor video data SENSOR INTERFACE 9 10, 11, 12, 13, 14 15 SSDA I/O Sensor I2C data (Schmitt input level) 16 SSCL O Sensor I2C clock USB INTERFACES 60 DP I/O USB differential D+ 59 DN I/O USB differential D- TEST PINS 39, 36, 34 TM[2:0] I Test mode pins - Must be pulled high I Could be used as “wake-up” button on SDRAM camera while untethered. USER BUTTON INPUTS/WAKEUP 55 26/35 WAKEUP STV0674 Pinout and Pin Description Table 9: 100TQFP pin description Pin Pin name Type Description AUDIO FRONT-END INPUT, AND BIAS PINS 18 AP ANA VIN+ 20 AN ANA VIN- 19 CBS ANA VBIAS, see Figure 17 SPECIAL FUNCTION PINS 87, 88, 89, 90, 91, 92, 95,6 SFP[7:0] SFP Special function pin operation is firmware specific. 66, 69, 70, 80, 83, 84, 85,86 SFP[15:8] SFP Special function pin operation is firmware specific. 44, 45, 46, 56, 62, 63, 64, 65 SFP[23:16] SFP Special function pin operation is firmware specific. 99, 100, 1, 2, 3, 4, 5, 33 SFP[31:24] SFP Special function pin operation is firmware specific. 75, 76, 77, 78,79, 96, 97, 98 SFP[39:32] SFP Special function pin operation is firmware specific. 51, 52, 53, 54, 71, 72, 73, 74 SFP[47:40] SFP Special function pin operation is firmware specific. 27, 28, 29, 30, 47, 48, 49, 50 SFP[55:48] SFP Special function pin operation is firmware specific 22, 23, 24, 25, 26, SFP[60:56] SFP Special function pin operation is firmware specific. 27/35 Pinout and Pin Description STV0674 Table 10: Hardware specific - Special function pins SPECIAL FUNCTION PINSa Pin 28/35 Pin Name SDRAM x8 SDRAM x16 FLASH Other PWM0/ TQFP_SEL Description 6 SFP[0] 95 SFP[1] GPIO 92 SFP[2] GPIO 91 SFP[3] 90 SFP[4] GPIO 89 SFP[5] GPIO 88 SFP[6] GPIO 87 SFP[7] GPIO 86 SFP[8] GPIO 85 SFP[9] 84 SFP[10] GPIO 83 SFP[11] GPIO 80 SFP[12] GPIO 70 SFP[13] GPIO 69 SFP[14] 66 SFP[15] 65 SFP[16] 64 SFP[17] GPIO 63 SFP[18] GPIO 62 SFP[19] GPIO 56 SFP[20] GPIO 46 SFP[21] GPIO 45 SFP[22] 44 SFP[23] DQ1 GPIO /SDRAMx16 33 SFP[24] DQ3 GPIO /SDRAMx16 5 SFP[25] DQ5 IO0 GPIO /NAND FLASH /SDRAMx16 4 SFP[26] DQ7 IO1 GPIO /NAND FLASH /SDRAMx16 3 SFP[27] DQ8 IO2 GPIO /NAND FLASH /SDRAMx16 2 SFP[28] DQ10 IO3 GPIO /NAND FLASH /SDRAMx16 1 SFP[29] DQ12 IO4 GPIO /NAND FLASH /SDRAMx16 100 SFP[30] DQ14 IO5 GPIO /NAND FLASH /SDRAMx16 99 SFP[31] DQML IO6 GPIO /NAND FLASH /SDRAMx16 CS_NAND SHUTTER POWER_ON Audio Playback output b NAND/SMC detectc GPIOd Output reserved for power latchinge GPIO CS_SMC Chip select for SMCf STV0674 Pinout and Pin Description Table 10: Hardware specific - Special function pins SPECIAL FUNCTION PINSa Pin Pin Name SDRAM x8 SDRAM x16 FLASH IO7 Other Description 98 SFP[32] DQ0 DQ0 GPIO /NAND FLASH /SDRAMx16 / SDRAMx8 97 SFP[33] DQ1 DQ2 GPIO /SDRAMx16 /SDRAMx8 96 SFP[34] DQ2 DQ4 GPIO /SDRAMx16 /SDRAMx8 79 SFP[35] DQ3 DQ6 WE GPIO /NAND FLASH /SDRAMx16 / SDRAMx8 78 SFP[36] DQ4 DQ9 ALE GPIO /NAND FLASH /SDRAMx16 / SDRAMx8 77 SFP[37] DQ5 DQ11 CLE GPIO /NAND FLASH /SDRAMx16 / SDRAMx8 76 SFP[38] DQ6 DQ13 RB GPIO /NAND FLASH /SDRAMx16 / SDRAMx8 (open drain)g 75 SFP[39] DQ7 DQ15 RE GPIO /NAND FLASH /SDRAMx16 / SDRAMx8 74 SFP[40] A0 A0 GPIO /SDRAMx16 /SDRAMx8 73 SFP[41] A1 A1 GPIO /SDRAMx16 /SDRAMx8 72 SFP[42] A2 A2 GPIO /SDRAMx16 /SDRAMx8 71 SFP[43] A3 A3 GPIO /SDRAMx16 /SDRAMx8 54 SFP[44] A4 A4 GPIO /SDRAMx16 /SDRAMx8 53 SFP[45] A5 A5 GPIO /SDRAMx16 /SDRAMx8 52 SFP[46] A6 A6 GPIO /SDRAMx16 /SDRAMx8 51 SFP[47] A7 A7 GPIO /SDRAMx16 /SDRAMx8 50 SFP[48] A8 A8 GPIO /SDRAMx16 /SDRAMx8 49 SFP[49] A9 A9 GPIO /SDRAMx16 /SDRAMx8 48 SFP[50] A10 A10 GPIO /SDRAMx16 /SDRAMx8 47 SFP[51] A11 A11 GPIO /SDRAMx16 /SDRAMx8 30 SFP[52] A12 A12 GPIO /SDRAMx16 /SDRAMx8 29 SFP[53] A13 A13 GPIO /SDRAMx16 /SDRAMx8 28 SFP[54] CLK CLK GPIO /SDRAMx16 /SDRAMx8 27 SFP[55] CKE CKE GPIO /SDRAMx16 /SDRAMx8 26 SFP[56] DQM DQMH GPIO /SDRAMx16 /SDRAMx8 25 SFP[57] RAS RAS GPIO /SDRAMx16 /SDRAMx8 24 SFP[58] CAS CAS GPIO /SDRAMx16 /SDRAMx8 23 SFP[59] WE WE GPIO /SDRAMx16 /SDRAMx8 22 SFP[60] CS CS SDRAM detect and Chip Select for SDRAMh 29/35 Pinout and Pin Description STV0674 a. SFP 0-22 default to inputs on reset and in low power states. SFP 0-22 should therefore not be left floating and must be configured by external circuit. See Section 5.2.1 for state of SFP 23-60 b. Pull Up required. See Section 5.2.1. c. SFP 3> Pull Up if NAND or SMC present /Down if not, See Section 5.2.1. d. SFP 9> Pull down required if pin not used, must be held low at power on. e. SFP 14> Pull down required for power latching otherwise pull up required. f. SFP 16> Pull Up required, if SMC present. (SFP 3 must also be pulled up) g. SFP 38> Pull resistor required if NAND present, value 10kΩ. h. SFP 60> Pull Up if SDRAM present /Down if not, See Section 5.2.1 5.2.1 Power on/ low power default pin states The initial state of SFP pins varies depending on the power on state of the NAND flash / SMC detect pin, SDRAM detect pin and package detect pin. The default pin states are detailed in Table 11. Table 11: Power-on/low-power default pin states Pin state at power on 30/35 Initial state TQFP_SEL CS_NAND CS_SDRAM Flash Port Non-Flash SDRAM GPIO SFP0 SFP3 SFP60 SFP 25-32, 35-39 SFP 23, 24, 33, 34, 40-60 SFP0-22 0 X X 1 1 0 Ouput Input Input 1 X 1 Output Output Input 1 0 0 Input Input Input Reserved STV0674 5.3 Pinout and Pin Description Package outline and mechanical data Figure 15: 100TQFP package outline and mechanical data mm DIM. MIN. inch TYP. A MAX. MIN. TYP. 1.60 A1 0.05 A2 1.35 B 0.17 C 0.09 0.15 0.002 0.006 1.40 1.45 0.053 0.055 0.057 0.22 0.27 0.007 0.009 0.011 0.20 0.003 0.008 16.00 0.630 D1 14.00 0.551 D3 12.00 0.472 e 0.50 0.019 E 16.00 0.630 E1 14.00 0.551 E3 12.00 0.472 0.45 0.60 L1 0.75 0.018 1.00 K ® 0.063 D L OUTLINE AND MECHANICAL DATA MAX. 0.024 0.030 TQFP100 0.0393 3.5°(min.), 7°(max.) D A D1 A2 D3 A1 75 51 76 50 0.076mm .003 inch Seating Plane e E3 E1 E B PIN 1 IDENTIFICATION 26 100 1 25 K TQFP100M C L L1 October 1997 0086901 31/35 Pinout and Pin Description 5.4 External circuits 5.4.1 Crystal oscillator STV0674 There are 2 crystal oscillator pins XTAL_IN, XTAL_OUT, as shown in Figure 16. The oscillator cell architecture is a single stage oscillator with an inverter working as an amplifier. The oscillator stage is biased by an internal resistor (>1MΩ). It also requires an external PI network consisting of a crystal and two capacitors. Note: The clock accuracy of the oscillator circuit must be within the USB compliance data signaling rate tolerance of 12.000Mb/s ± 0.25%. Figure 16: Oscillator support circuit XTALI XTALO Crystal 15pF 5.4.2 15pF Audio Figure 17: Audio PLL filter and CBS CBS VC + 10K 680 pF - 10µF 10nF If the record audio section of the STV0674 is not required, AP, CBS, VC and AN can be left unconnected. VDDA must however be connected to a 3V3 supply. 5.4.3 Recommended power supply decoupling A 0.1µF bypass capacitor located as close as possible to the chip package connecting between all VDD pins and GND and at least one bulk decoupling capacitor on each of the supply rails VDDA, VDDC, VDDI and VDDP. 32/35 STV0674 Evaluation Kit and Reference Design Manuals 6 Evaluation Kit and Reference Design Manuals 6.1 Evaluation kit STMicroelectronics recommends the use of their evaluation kit (EVK) for initial evaluation and design-in. The kit contains all the hardware functionality required to implement a webcam, dual mode and tri mode camera and is populated with SDRAM, NAND FLASH as well as a Smartmedia connector. The EVK content is the following: 6.2 ● STV0674 Evaluation board with both CIF and VGA sensor plug-in ● USB cable ● PC software ● User manual Reference design manuals The STMicroelectronics STV0674 reference design manuals include complete schematics, BOM and design recommendations. For products based on the STV0674, STMicroelectronics recommends that all designers refer to the reference design manuals before starting a new design. Please contact STMicroelectronics for more details. 33/35 Ordering Details 7 STV0674 Ordering Details Table 12 : Ordering details Part number Description Device STV0674T100 Digital video co-processor (100TQFP package) Evaluation Kit (EVK) STV-674/100T-E01 100TQFP STV0674 + CIF and VGA sensors Technical support Technical support information, such as datasheets, software downloads, etc. can be found at http://www.st.com under “Imaging Products”. 34/35 STV0674 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics © 2003 STMicroelectronics - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A. www.st.com 35/35