TSM006 Primary PWM Controller ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ Current-mode PWM Controller High-current output drive suitable for Power MOSFET Automatic burst mode in zero-load condition Primary overcurrent protection (hiccup mode) Internal leading edge blanking on current sense External slope compensation capability Programmable soft start Frequency modulation for low emi Accurate oscillator frequency 77% duty cycle limitation 5V reference Under voltage protection Thermal shutdown at 130°C 2kV ESD protection D SO-14 (Plastic MicroPackage) PIN CONNECTIONS (top view) DESCRIPTION 1 Rt/Ct Dis The TSM006 integrated circuits incorporate all circuitry to implement off line or DC-DC power supply applications using a fixed frequency current mode control. 2 Fm Rex 13 3 Cs Based on a standard current mode PWM controller, these devices include additional features for higher integration. ■ Vref 12 4 Bl Vin 11 5 Ss Out 10 Pgnd 9 Cslope 8 6 Comp 7 Bs APPLICATION 14 AC/DC adapter D = Small Outline Package (SO) - also available in Tape & Reel (DT) ORDER CODES Part Number Temperature Range Package Packaging Marking TSM006ID TSM006IDT 0, +105°C SO Tube Tape & Reel TSM006 TSM006 July 2004 Revision 1 1/13 TSM006 1 Block Diagram Block Diagram 14 Standby UVLO DIS Vref Vref Disable_Latch 12 Thermal Shutdown Cref Vin Hiccup_Latch Icomp 600µA Vref_Status BS 4 6 BL Burst_Latch 2R Comp R Comp_Cs 1V 3 28V Cs Comp Clamp = Vss Vref 8 7 LEB Cslope Slop_Compensation Rt Vin 11 1 Cs_Latch Rt/Ct Comp_Osc Ct Idct1 300µA R Q S !Q R Q S !Q Out 10 Rb Fm 2 Vref 0.5V Frequency mod. Comp_Hiccup Cfm Iiss 10µA 5 Css 9 Pgnd Start up_Latch Soft start Ss Idss1 1µA Idss2 1mA Current source REX 13 Rex PIN DESCRIPTION Name SO14 RT/CT FM CS BL SS COMP BS CSLOPE PGND OUT VIN VREF REX DIS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 2/13 Type Timing capacitor Analog input Analog input Analog output Timing capacitor Analog input Output input Analog output Power supply Analog output Power supply Analog output Analog input Analog input Function Sets the oscillator frequency and maximum duty cycle Frequency modulation Current sense. Burst level Soft start and hiccup timing, latched disable input. Current comparator for current mode control. Burst mode status Slope compensation Power ground Totem pole output to direct drive a power MOSFET. Supply input voltage. +5V Voltage reference External resistor for internal constant current Latched disable Absolute Maximum Ratings 2 TSM006 Absolute Maximum Ratings Symbol DC Supply Voltage DC Supply Voltage (Iin<50mA) 1 Io DC output current Iopeak Peak output current Vcomp COMP terminal voltage Isinkcomp COMP terminal sink current Vss SS terminal voltage Vout OUT terminal voltage Other terminal voltage (CT, VREF, BS, BL, CSLOPE REX, CS, Vter FM, DIS) Pt Power dissipation at 25°C Tstg Storage temperature Tj Junction temperature ESD Electrostatic Discharge Vin 1) Value Unit -0.3 to self limit V 0.1 1 -0.3 to 6.5 6 -0.3 to 8 -0.3 to Vin A A V mA V V -0.3 to Vref V 500 -40 to 150 150 2 mW °C °C kV All voltage values, except differential voltage are with respect to network ground terminal (GND). OPERATING CONDITIONS Symbol Vcc Toper Parameter DC Supply Conditions Operating Free Air Temperature Range Value Unit 8 to 20 0 to 105 V °C 3/13 TSM006 3 Electrical Characteristics Electrical Characteristics Tamb = 25°C, Vin=15V, Rt=39k, Ct=470pF, Rex=27k, Cfm=1nF unless otherwise specified Symbol Parameter Test Condition Min Typ Max Unit Main oscillator 8≤Vin≤20V, 0≤Ta≤105°C Fosco Lower oscillating frequency Vfm=GND 63 68 73 kHz FoscL Fjit Ffm Vthct Vtlct ∆Vct Idct1 Idct2 Upper oscillating frequency Frequency jitter Frequency modulation Upper trip point Lower trip point Amplitude Discharge current Current at Ct in UVLO Vfm=Vref Fjit=Fosco - FoscL 57.6 6 66.4 8 Vfm=GND Vfm=GND Vfm=GND Vct=2V Vct=1V 1 62 7 4.5 3.0 1.4 1.6 300 3 kHz kHz kHz V V V µA mA 2.5 2.65 2.8 V 4.91 5.00 5 10 5.00 5.09 10 20 5.15 V mV mV V mA Disable Vdis Voltage threshold Vref reference pin Vref ∆Vline ∆Vload ∆Vtotal Ios Voltage reference Line regulation Load regulation Total variation Short circuit current 12V ≤ Vin ≤ 20V 1mA ≤ Iref ≤ 5mA Line, load, temp Vref=0 4.85 10 Sink current Source current Vct=2.2V, VCslope=1V Vct=2.2V, VCslope=0V 2 Source current Vcomp=5V 0.5 0.6 0.7 0V ≤ Vcs ≤ 0.8V Vcomp=5V 8V ≤ Vin ≤ 20V 2.85 0.9 3.00 1.0 70 3.15 1.1 Slope Compensation IsinkCP IsrcCP µA mA 90 Comp Icomp mA Current sense Avcs Vz1 PSRR Gain Maximum sensing voltage Power supply voltage rejection ratio V dB Leading edge blanking LEB Delay to output Vcs = 0 to 2 V Vcomp = 2 V 280 ns Output VOL1 VOL2 VOH1 VOH2 tr tf VOL3 Fout DCmax 4/13 Output low voltage 1 Output low voltage 2 Output high voltage 1 Output high voltage 2 Rise time Fall time UVLO saturation Output frequency Maximum Duty Cycle Iosink=20mA Iosink=200mA Iosource=20mA Iosource=200mA CL=1nF, 10% to 90% CL=1nF, 90% to 10% Vin=5V, Iosink=1mA Option 1 Option 1 0.8 1.0 2.2 Vin-2.0 Vin-3.0 70 40 Fosc 77.5 100 60 0.5 V V V V ns ns V kHz % Electrical Characteristics Symbol Parameter TSM006 Test Condition Min Typ Max Unit Vss=2V 0°C ≤ Ta ≤ 105°C Vss=2V, Vcs=2V Vss=2V, Vin=7V 8 7 10 10 1 12 13 1.2 µA µA µA mA 10 11 Soft start Iiss dIiss Idss1 Idss2 Iiss/Idss1 VHss VLss Charge current Temperature stability Discharge current (hiccup) Sink current (uvlo) Charge/discharge ratio Clamp voltage Low voltage (uvlo) 3 4 Vin=7V, Idss=1mA 0.5 V V Under Voltage Lockout (UVLO) VH VL UVLO top threshold UVLO bottom threshold 11.5 8.0 12 8.4 12.5 8.8 V V 22 4.5 3.3 40 25 5.0 3.8 60 30 mA mA µA V Supply current Iin Iidle Istby Vclamp Operating current Supply current in idle mode Supply current in standby mode Clamp voltage CL=1nF Vcomp=1V Vin<VH Iin=50mA Output low voltage Leakage current Threshold level on Comp to enter Burst mode Vbl1 Hysteresis Threshold level on Comp to exit burst mode Iobs=1mA Vbs=5V Burst Vbsol Iohbs Vbl1 Vbl1hyst Vbl2 BL pin left unconnected 0.3 2 V µA 1.25 V 0.3 V 1.75 V Hiccup Vz2 Vhicc Threshold level on Cs to enter Hiccup mode Threshold level on Ss to exit Hiccup mode 1.15 1.25 0.5 1.35 V V 5/13 TSM006 4 Functional Description Functional Description TSM006: PWM Controller IC. Output driver UVLO function The OUT totem pole output is capable to sink and source more than 1.0A (peak) in order to direct drive a power MOSFET. The Under Voltage Lock Out function disables the whole device when supply voltage is lower than the threshold. Vref block The Vref block provides a 5V reference voltage. An internal Vref status signal is active when Vref is lower than 4.7V and is used to drive the output driver low when Vref is not valid. Current sense input A voltage proportional to the output inductor current is applied to the CS pin. The control IC uses this information to perform current mode control. The PWM function will be stopped if the CS pin voltage is greater than 1.0V. Current leading edge blanking An internal delay is built into the IC to mask the first 100ns of the current sense signal. This delay is made of a capacitor charged with a current source. The capacitor is discharged when CT reaches its maximum level. COMP input This pin is connected to the current comparator for current mode control. The pin should be connected to the collector (primary side) of an optocoupler which anode (secondary side) is driven by the output of error amplifier. The COMP input is used to set the reference level for the current sense comparator. The current sense threshold is set to (Vcomp - 2 * Vbe) / 3. During the soft start period, COMP voltage is clamped to the SS pin plus two Vbe voltage. Startup latch The startup latch is set when the IC exits from standby mode or UVLO state. It is reset when the CT capacitor is discharged for the first time. 6/13 Oscillator A capacitor from the RT/CT pin to GND and a resistor to the VREF set the oscillating frequency. The maximum duty cycle at the OUT pin is limited at 77%. Frequency modulation A FM generator adds a small amount of jitter on the oscillator frequency in a way that reduces the conducted and radiated EMI. The FM frequency is set by an external capacitor connected to the FM pin. Slope compensation A buffered Rt/Ct voltage is brought to the Cslope pin. This signal is used to provide the necessary slope compensation. Soft start A capacitor from the SS pin to GND provides the soft start function. The capacitor starts to charge when VIN reaches the UVLO threshold and Vref is good. The soft start block enables the IC to start with a progressive PWM duty cycle. The soft start comparator drives the output driver low when the SS pin voltage is greater than the CT pin voltage minus one Vbe voltage. During soft start, the COMP pin voltage is clamped to the SS pin voltage plus two Vbe voltage, limiting the maximum peak current. External reference pin An external resistor at REX pin sets the internal current reference. Functional Description TSM006 Automatic burst mode OverCurrent detection and Hiccup mode Burst mode is used during light load condition to reduce the number of MOS switching, and thus reducing overall power dissipation. Light load condition is detected when COMP voltage is low. When COMP voltage is lower than a threshold VBL1 set by the external BL pin, the device output is forced to off state, providing minimum duty cycle and pulse skipping. The burst status is available on the BS pin to put other devices in standby mode when in light load condition. Overcurrent is detected when voltage at the CS pin is greater than Vz2=1.2V. To avoid false triggering, the overcurrent detection is delayed in the same way than the normal pulse by pulse current limitation. When COMP voltage (Vcomp) is higher than VBL2, the device operates in normal mode. Current is limited to (Vcomp-2*Vbe)/3 / Rshunt (Rshunt is the shunt resistor used to measure the primary current, Vbe is the forward voltage of a diode, and 3 is the R/2R network attenuation). Maximum current is 1V/Rshunt. When Vcomp becomes lower than VBL, device enters burst mode, PWM is stopped while Comp voltage is lower than VBL. As PWM is stopped, no more energy is transferred to the secondary side, output voltage is decreasing, and Vcomp (which is an image of the error comparator) tends to increase. As soon as Vcomp becomes just higher than VBL, PWM operation can resume for some cycles, so current in burst mode is limited to (VBL2*Vbe)/3 / Rshunt. When overcurrent is detected, the device enters the hiccup mode. Output is switched off immediately and the soft start capacitor is discharged slowly. When the SS pin voltage goes below 0.5V, normal soft start is started. If the overcurrent is no more present, device operation is resumed normally, otherwise, overcurrent is detected again and the cycle is repeated until the overcurrent situation disappears. Duty cycle of the hiccup mode is set by the ratio of SS pin discharge and charge currents: 10% typ. With a typical capacitor Css=100nF, soft start delay is about 40ms and hiccup off-time is 400ms. Latched disable function Disable mode is entered when the DIS pin voltage is driven above 2.5V. Disable state is latched and can only be exit by driving the Vin power supply voltage under the UVLO level. Thermal shutdown The device operation is shut down when the internal temperature exceed 130°C. Hysteresis provides stable working and shutdown states. 7/13 TSM006 Functional Description Fig. 1: Detailed Internal Schematic 2.5V Comp_Dis R Q S !Q Standby UVLO 14 Vref Vref Thermal Shutdown Dis 12 Cref Disable_Latch Vz2=1.2V Comp_0cp R Q S !Q Hiccup_Latch Vin Vref_Status Comp_burst Bs Bs_latch Icomp 600µA R Q S !Q 28V Vbl2 4 BL 7 Comp_burst Vbl1 6 Comp VF VF 2R Comp_Cs R 1V Vref Rt LEB 3 1 Cs Rt/Ct Comp_Osc Idct1 300µA Ct Cs_Latch R Q S !Q Vin Idct2 1mA Out 11 10 1.4V-3.0V Rb Vref Pgnd Start up_Latch 8 Frequency Modulation Cslope Vref 0.5V 11k R Q S !Q Comp_Hiccup Iiss 10µA FM Comp_ss Current source 5 Css 8/13 9 Rex CFm 2 13 Ss Idss1 1µA Idss2 1mA Rex Timing Diagram 5 TSM006 Timing Diagram Timing for PWM function RT/CT COMP (COMP-2VF)/3 CS OUT Driving by maximum duty cycle Driving by PWM No output Timing at Vref rise up and shut down VH VL 12V 8.4V 2V Vin UVLO 4.7V Vref VrefStatus RT/CT Startup OUT 9/13 TSM006 Timing Diagram Timing for soft start function RT/CT 2VBE COMP CT-1VBE SS OUT Soft start period Max. duty cycle Timing for latched disable function VH VL VIN 2.5V DIS SS Disable Latch nQ OUT Soft start 10/13 Active Shut-down Soft start Active Timing Diagram TSM006 Timing for burst mode function COMP VBL1 VBL Max Current Current Level in Burst Mode CS BS OUT Normal mode Burst Mode Normal mode Timing for hiccup function OverCurrent Level Max Current CS Hiccup latch nQ SS 0.5V OUT Normal mode Hiccup mode Normal mode 11/13 TSM006 Timing Diagram Timing for oscillator function Vref FM (DAP009A only) Gnd RT/CT FM oscillation (Ffm=4.5kHz typ.) Foscl Fosco 62kHz typ. 68kHz typ. Fjit = Fosco - Foscl (6kHz typ.) 12/13 Timing Diagram TSM006 PACKAGE MECHANICAL DATA SO-14 MECHANICAL DATA DIM. mm. MIN. TYP A a1 inch MAX. MIN. TYP. 1.75 0.1 0.068 0.2 a2 0.003 0.007 0.46 0.013 0.018 0.25 0.007 1.65 b 0.35 b1 0.19 C MAX. 0.064 0.5 0.010 0.019 c1 45˚ (typ.) D 8.55 8.75 0.336 E 5.8 6.2 0.228 e 1.27 e3 0.344 0.244 0.050 7.62 0.300 F 3.8 4.0 0.149 0.157 G 4.6 5.3 0.181 0.208 L 0.5 1.27 0.019 0.050 M S 0.68 0.026 8 ˚ (max.) PO13G Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. 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