Order this document by MC34023/D The MC34023 series are high speed, fixed frequency, single–ended pulse width modulator controllers optimized for high frequency operation. They are specifically designed for Off–Line and DC–to–DC converter applications offering the designer a cost–effective solution with minimal external components. These integrated circuits feature an oscillator, a temperature compensated reference, a wide bandwidth error amplifier, a high speed current sensing comparator, and a high current totem pole output ideally suited for driving a power MOSFET. Also included are protective features consisting of input and reference undervoltage lockouts each with hysteresis, cycle–by–cycle current limiting, and a latch for single pulse metering. The flexibility of this series allows it to be easily configured for either current mode or voltage mode control. • 50 ns Propagation Delay to Output • • • • • • • • • • • • 16 1 P SUFFIX PLASTIC PACKAGE CASE 648 16 High Current Totem Pole Output 1 Wide Bandwidth Error Amplifier DW SUFFIX PLASTIC PACKAGE CASE 751G (SO–16L) Fully–Latched Logic with Double Pulse Suppression Latching PWM for Cycle–By–Cycle Current Limiting Soft–Start Control with Latched Overcurrent Reset Input Undervoltage Lockout with Hysteresis Low Start–Up Current (500 µA Typ) Internally Trimmed Reference with Undervoltage Lockout 90% Maximum Duty Cycle (Externally Adjustable) Precision Trimmed Oscillator PIN CONNECTIONS Voltage or Current Mode Operation to 1.0 MHz Functionally Similar to the UC3823 Error Amp Inverting Input 1 Error Amp 2 Noninverting Input Error Amp Output 3 Simplified Application 16 Vref 15 VCC 14 Output 13 VC Clock 4 Vref Clock RT CT 16 5.1V Reference 4 5 6 15 RT 5 VCC CT 6 (Top View) VC 14 Error Amp Latching PWM Output 12 Power Ground ORDERING INFORMATION Inverting Input 1 Soft–Start 9 Current Limit/ Shutdown Soft–Start 8 Oscillator 13 8 11 Current Limit Reference 10 Ground Ramp 7 UVLO 7 Ramp Error Amp 3 Output Noninverting Input 2 12 Power Ground 11 Current 9 Limit Ref Current Limit/ Shutdown Soft–Start 10 Ground This device contains 176 active transistors. Device MC33023P MC33023DW Operating Temperature Range TA = – 40° to +105°C MC34023P Motorola, Inc. 1996 MOTOROLA ANALOG IC DEVICE DATA TA = 0° to +70°C Package Plastic DIP SO–16L Plastic DIP Rev 2 1 MC34023 MC33023 MAXIMUM RATINGS Rating Symbol Value Unit VCC 30 V Output Driver Supply Voltage VC 20 V Output Current, Source or Sink (Note 1) DC Pulsed (0.5 µs) IO Current Sense, Soft–Start, Ramp, and Error Amp Inputs Vin – 0.3 to +7.0 V Error Amp Output and Soft–Start Sink Current IO 10 mA ICO 5.0 mA PD RθJA 862 145 mW °C/W PD RθJA 1.25 100 W °C/W Operating Junction Temperature TJ +150 °C Operating Ambient Temperature (Note 2) MC34023 MC33023 TA 0 to +70 – 40 to +105 Tstg – 55 to +150 Power Supply Voltage Clock and RT Output Current Power Dissipation and Thermal Characteristics SO–16L Package (Case 751G) Maximum Power Dissipation @ TA = + 25°C Thermal Resistance, Junction–to–Air DIP Package (Case 648) Maximum Power Dissipation @ TA = + 25°C Thermal Resistance, Junction–to–Air Storage Temperature Range A 0.5 2.0 °C °C ELECTRICAL CHARACTERISTICS (VCC = 15 V, RT = 3.65 kΩ, CT = 1.0 nF, for typical values TA = + 25°C, for min/max values TA is the operating ambient temperature range that applies [Note 2], unless otherwise noted.) Characteristic Symbol Min Typ Max Unit REFERENCE SECTION Reference Output Voltage (IO = 1.0 mA, TJ = + 25°C) Vref 5.05 5.1 5.15 V Line Regulation (VCC = 10 V to 30 V) Regline – 2.0 15 mV Load Regulation (IO = 1.0 mA to 10 mA) Regload – 2.0 15 mV Temperature Stability TS – 0.2 – mV/°C Total Output Variation over Line, Load, and Temperature Vref 4.95 – 5.25 V Output Noise Voltage (f = 10 Hz to 10 kHz, TJ = + 25°C) Vn – 50 – µV Long Term Stability (TA = +125°C for 1000 Hours) S – 5.0 – mV ISC – 30 – 65 –100 mA fosc 380 370 400 400 420 430 ∆fosc/∆V – 0.2 1.0 % Output Short Circuit Current OSCILLATOR SECTION Frequency TJ = + 25°C Line (VCC = 10 V to 30 V) and Temperature (TA = Tlow to Thigh) Frequency Change with Voltage (VCC = 10 V to 30 V) kHz Frequency Change with Temperature (TA = Tlow to Thigh) ∆fosc/∆T – 2.0 – % Sawtooth Peak Voltage VOSC(P) 2.6 2.8 3.0 V Sawtooth Valley Voltage VOSC(V) 0.7 1.0 1.25 V VOH VOL 3.9 – 4.5 2.3 – 2.9 Clock Output Voltage High State Low State V NOTES: 1. Maximum package power dissipation limits must be observed. 2. Low duty cycle pulse techniques are used during test to maintain junction temperature as close to ambient as possible. Tlow = 0°C for MC34023 Thigh = +70°C for MC34023 Tlow = – 40°C for MC33023 Thigh = +105°C for MC33023 2 MOTOROLA ANALOG IC DEVICE DATA MC34023 MC33023 ELECTRICAL CHARACTERISTICS (VCC = 15 V, RT = 3.65 kΩ, CT = 1.0 nF, for typical values TA = + 25°C, for min/max values TA is the operating ambient temperature range that applies [Note 2], unless otherwise noted.) Characteristic Symbol Min Typ Max Unit VIO – – 15 mV Input Bias Current IIB – 0.6 3.0 µA Input Offset Current IIO – 0.1 1.0 µA AVOL 60 95 – dB ERROR AMPLIFIER SECTION Input Offset Voltage Open–Loop Voltage Gain (VO = 1.0 V to 4.0 V) Gain Bandwidth Product (TJ = + 25°C) GBW 4.0 8.3 – MHz Common Mode Rejection Ratio (VCM = 1.5 V to 5.5 V) CMRR 75 95 – dB Power Supply Rejection Ratio (VCC = 10 V to 30 V) PSRR 85 110 – dB ISource ISink 0.5 1.0 3.0 3.6 – – mA VOH VOL 4.5 0 4.75 0.4 5.0 1.0 V SR 6.0 12 – V/µs IIB – – 0.5 – 5.0 µA DC(max) DC(min) 80 – 90 – – 0 % Vth 1.1 1.25 1.4 V tPLH(in/out) – 60 100 ns Ichg 3.0 9.0 20 µA Idischg 1.0 4.0 – mA Input Bias Current (Pin 9(12) = 0 V to 4.0 V) IIB – – 15 µA Current Limit Comparator Input Offset Voltage (Pin 11(14) = 1.1 V) VIO – – 45 mV Current Limit Reference Input Common Mode Range (Pin 11(14)) VCMR 1.0 – 1.25 V Output Current, Source (VO = 4.0 V) Output Current, Sink (VO = 1.0 V) Output Voltage Swing, High State (IO = – 0.5 mA) Output Voltage Swing, Low State (IO = 1 mA) Slew Rate PWM COMPARATOR SECTION Ramp Input Bias Current Duty Cycle, Maximum Duty Cycle, Minimum Zero Duty Cycle Threshold Voltage Pin 3(4) (Pin 7(9) = 0 V) Propagation Delay (Ramp Input to Output, TJ = + 25°C) SOFT–START SECTION Charge Current (VSoft–Start = 0.5 V) Discharge Current (VSoft–Start = 1.5 V) CURRENT SENSE SECTION Shutdown Comparator Threshold Vth 1.25 1.40 1.55 V tPLH(in/out) – 50 80 ns VOL – – 13 12 0.25 1.2 13.5 13 0.4 2.2 – – VOL(UVLO) – 0.25 1.0 V Output Leakage Current (VC = 20 V) IL – 100 500 µA Output Voltage Rise Time (CL = 1.0 nF, TJ = + 25°C) tr – 30 60 ns Output Voltage Fall Time (CL = 1.0 nF, TJ = + 25°C) tf – 30 60 ns Vth(on) 8.8 9.2 9.6 V VH 0.4 0.8 1.2 V – – 0.5 20 1.2 30 Propagation Delay (Current Limit/Shutdown to Output, TJ = + 25°C) OUTPUT SECTION Output Voltage Low State (ISink = 20 mA) (ISink = 200 mA) High State (ISource = 20 mA) (ISource = 200 mA) Output Voltage with UVLO Activated (VCC = 6.0 V, ISink = 0.5 mA) V VOH UNDERVOLTAGE LOCKOUT SECTION Start–Up Threshold (VCC Increasing) UVLO Hysteresis Voltage (VCC Decreasing After Turn–On) TOTAL DEVICE Power Supply Current Start–Up (VCC = 8.0 V) Operating ICC mA NOTES: 1. Maximum package power dissipation limits must be observed. 2. Low duty cycle pulse techniques are used during test to maintain junction temperature as close to ambient as possible. Tlow = 0°C for MC34023 Thigh = +70°C for MC34023 Tlow = – 40°C for MC33023 Thigh = +105°C for MC33023 MOTOROLA ANALOG IC DEVICE DATA 3 MC34023 MC33023 Figure 1. Timing Resistor versus Oscillator Frequency R T , TIMING RESISTOR ( Ω ) 1 3 5 2 4 7 6 9 Figure 2. Oscillator Frequency versus Temperature 1200 VCC = 15 V TA = + 25°C f osc , OSCILLATOR FREQUENCY (kHz) 100 k 8 CT = 10 k 1. 100 nF 2. 47 nF 3. 22 nF 4. 10 nF 5. 4.7 nF 6. 2.2 nF 1.0 k 7. 1.0 nF 8. 470 pF 9. 220 pF 470 104 105 106 100 1000 fosc, OSCILLATOR FREQUENCY (Hz) 1000 60 Phase 90 20 θ , EXCESS PHASE (°C) Gain 135 – 20 10 100 1.0 k 10 k 100 k f, FREQUENCY (Hz) 1.0 M 10 M VTH, ZERO DUTY CYCLE (V) A VOL, OPEN LOOP VOLTAGE GAIN (dB) 45 0 – 25 0 25 50 75 TA, AMBIENT TEMPERATURE (°C) 100 125 1.28 VCC = 15 V Pin 7(9) = 0 V 1.26 1.24 1.22 1.20 – 55 – 25 0 25 50 75 TA, AMBIENT TEMPERATURE (°C) 100 125 Figure 6. Error Amp Large Signal Transient Response 2.55 V 3.0 V 2.5 V 2.5 V 2.45 V 2.0 V 4 RT = 36 k CT = 1.0 nF 200 Figure 5. Error Amp Small Signal Transient Response 0.1 µs/DIV 50 kHz 400 1.30 100 40 RT = 3.6 k CT = 1.0 nF Figure 4. PWM Comparator Zero Duty Cycle Threshold Voltage versus Temperature 0 80 400 kHz VCC = 15 V 600 Figure 3. Error Amp Open Loop Gain and Phase versus Frequency 120 RT = 1.2 k CT = 1.0 nF 800 0 – 55 107 1.0 MHz 0.1 µs/DIV MOTOROLA ANALOG IC DEVICE DATA Vref , REFERENCE VOLTAGE CHANGE (mV) Figure 7. Reference Voltage Change versus Source Current 0 – 5.0 VCC = 15 V – 10 TA = – 55°C TA = +125°C TA = + 25°C – 15 – 20 – 25 – 30 10 0 20 30 40 ISource, SOURCE CURRENT (mA) 50 I SC , REFERENCE SHORT CIRCUIT CURRENT (mA) MC34023 MC33023 Figure 8. Reference Short Circuit Current versus Temperature 66 65.6 65.2 64.8 64.4 64 – 55 100 125 2.0 mV/DIV Vref LOAD REGULATION 1.0 mA to 10 mA (2.0 ms/DIV) Figure 11. Current Limit Comparator Input Offset Voltage versus Temperature Figure 12. Shutdown Comparator Threshold Voltage versus Temperature 1.50 Vth, THRESHOLD VOLTAGE (V) VIO , CURRENT LIMIT INPUT OFFSET VOLTAGE (mV) 0 25 50 75 TA, AMBIENT TEMPERATURE (°C) Vref LINE REGULATION 10 V to 24 V (2.0 ms/DIV) 100 VCC = 15 V Pin 11(14) = 1.1 V 20 – 20 – 60 – 100 – 55 – 25 Figure 10. Reference Load Regulation 2.0 mV/DIV Figure 9. Reference Line Regulation 60 VCC = 15 V – 25 0 25 50 75 TA, AMBIENT TEMPERATURE (°C) MOTOROLA ANALOG IC DEVICE DATA 100 125 1.46 VCC = 15 V 1.42 1.38 1.34 1.30 – 55 – 25 0 25 50 75 TA, AMBIENT TEMPERATURE (°C) 100 125 5 MC34023 MC33023 Figure 14. Output Saturation Voltage versus Load Current 10 Vsat , OUTPUT SATURATION VOLTAGE (V) I chg , SOFT-START CHARGE CURRENT ( µ A) Figure 13. Soft–Start Charge Current versus Temperature VCC = 15 V VCC – 1.0 9.5 Source Saturation (Load to Ground) VCC = 15 V 80 µs Pulsed Load – 2.0 120 Hz Rate TA = 25°C 9.0 8.5 8.0 7.5 7.0 – 55 0 – 25 0 25 50 75 TA, AMBIENT TEMPERATURE (°C) 100 125 Figure 15. Drive Output Rise and Fall Time 2.0 1.0 Ground 0 0 0.2 Sink Saturation (Load to VCC) 0.4 0.6 0.8 IO, OUTPUT LOAD CURRENT (A) 1.0 Figure 16. Drive Output Rise and Fall Time OUTPUT RISE & FALL TIME 1.0 nF LOAD 50 ns/DIV OUTPUT RISE & FALL TIME 10 nF LOAD 50 ns/DIV Figure 17. Supply Voltage versus Supply Current I CC , SUPPLY CURRENT (mA) 30 RT = 3.65 kΩ CT = 1.0 nF 25 20 VCC Increasing 15 VCC Decreasing 10 5.0 0 0 6 4.0 8.0 12 VCC, SUPPLY VOLTAGE (V) 16 20 MOTOROLA ANALOG IC DEVICE DATA MC34023 MC33023 Figure 18. Representative Block Diagram VCC 16 Reference Regulator Vref Clock 4 4.2 V 5 Oscillator RT 15 VCC UVLO VCC 9.2 V 13 Vref UVLO VC 14 6 CT Ramp 7 S Q PWM Latch Error Amp Output 3 2 Noninverting Input Inverting Input Output 12 Power Ground R PWM Comparator 1.25 V Vin Error Amp Current Limit + 11 Current Limit Reference 9.0 µA 1 8 9 Current Limit/Shutdown Soft–Start 0.5 V R CSS Soft–Start Latch Q S 10 1.4 V Shutdown Ground Figure 19. Current Limit Operating Waveforms CT Clock Soft–Start Error Amp Output Ramp PWM Comparator Output MOTOROLA ANALOG IC DEVICE DATA 7 MC34023 MC33023 OPERATING DESCRIPTION The MC33023 and MC34023 series are high speed, fixed frequency, single–ended pulse width modulator controllers optimized for high frequency operation. They are specifically designed for Off–Line and DC–to–DC converter applications offering the designer a cost effective solution with minimal external components. A representative block diagram is shown in Figure 18. Oscillator The oscillator frequency is programmed by the values selected for the timing components RT and CT. The RT pin is set to a temperature compensated 3.0 V. By selecting the value of RT, the charge current is set through a current mirror for the timing capacitor CT. This charge current runs continuously through CT. The discharge current is ratioed to be 10 times the charge current, which yields the maximum duty cycle of 90%. CT is charged to 2.8 V and discharged to 1.0 V. During the discharge of CT, the oscillator generates an internal blanking pulse that resets the PWM Latch and, inhibits the outputs. The threshold voltage on the oscillator comparator is trimmed to guarantee an oscillator accuracy of 5.0% at 25°C. Additional dead time can be added by externally increasing the charge current to CT as shown in Figure 23. This changes the charge to discharge ratio of CT which is set internally to Icharge/10 Icharge. The new charge to discharge ratio will be: % Deadtime ) Icharge + I additional 10 (I charge) A bidirectional clock pin is provided for synchronization or for master/slave operation. As a master, the clock pin provides a positive output pulse during the discharge of CT. As a slave, the clock pin is an input that resets the PWM latch and blanks the drive output, but does not discharge CT. Therefore, the oscillator is not synchronized by driving the clock pin alone. Figures 27, 28 and 29 provide suggested synchronization. Error Amplifier A fully compensated Error Amplifier is provided. It features a typical DC voltage gain of 95 dB and a gain bandwidth product of 8.3 MHz with 75 degrees of phase margin (Figure 3). Typical application circuits will have the noninverting input tied to the reference. The inverting input will typically be connected to a feedback voltage generated from the output of the switching power supply. Both inputs have a common mode voltage (VCM) input range of 1.5 V to 5.5 V. The Error Amplifier Output is provided for external loop compensation. Soft–Start Latch Soft–Start is accomplished in conjunction with an external capacitor. The Soft–Start capacitor is charged by an internal 9.0 µA current source. This capacitor clamps the output of the error amplifier to less than its normal output voltage, thus 8 limiting the duty cycle. The time it takes for a capacitor to reach full charge is given by: t [ (4.5 • 105) CSoft-Start A Soft–Start latch is incorporated to prevent erratic operation of this circuitry. Two conditions can cause the Soft–Start circuit to latch so that the Soft–Start capacitor stays discharged. The first condition is activation of an undervoltage lockout of either VCC or Vref. The second condition is when current sense input exceeds 1.4 V. Since this latch is “set dominant”, it cannot be reset until either of these signals is removed and, the voltage at CSoft–Start is less than 0.5 V. PWM Comparator and Latch A PWM circuit typically compares an error voltage with a ramp signal. The outcome of this comparison determines the state of the output. In voltage mode operation the ramp signal is the voltage ramp of the timing capacitor. In current mode operation the ramp signal is the voltage ramp induced in a current sensing element. The ramp input of the PWM comparator is pinned out so that the user can decide which mode of operation best suits the application requirements. The ramp input has a 1.25 V offset such that whenever the voltage at this pin exceeds the error amplifier output voltage minus 1.25 V, the PWM comparator will cause the PWM latch to set, disabling the outputs. Once the PWM latch is set, only a blanking pulse by the oscillator can reset it, thus initiating the next cycle. Current Limiting and Shutdown A pin is provided to perform current limiting and shutdown operations. Two comparators are connected to the input of this pin. The reference voltage for the current limit comparator is not set internally. A pin is provided so the user can set the voltage. When the voltage at the current limit input pin exceeds the externally set voltage, the PWM latch is set, disabling the output. In this way cycle–by–cycle current limiting is accomplished. If a current limit resistor is used in series with the power devices, the value of the resistor is found by: R Sense + I Limit Reference Voltage I pk (switch) If the voltage at this pin exceeds 1.4 V, the second comparator is activated. This comparator sets a latch which, in turn, causes the soft start capacitor to be discharged. In this way a “hiccup” mode of recovery is possible in the case of output short circuits. If a current limit resistor is used in series with the output devices, the peak current at which the controller will enter a “hiccup” mode is given by: I shutdown + R1.4 V Sense MOTOROLA ANALOG IC DEVICE DATA MC34023 MC33023 Undervoltage Lockout There are two undervoltage lockout circuits within the IC. The first senses VCC and the second Vref. During power–up, VCC must exceed 9.2 V and Vref must exceed 4.2 V before the outputs can be enabled and the Soft–Start latch released. If VCC falls below 8.4 V or Vref falls below 3.6 V, the outputs are disabled and the Soft–Start latch is activated. When the UVLO is active, the part is in a low current standby mode allowing the IC to have an off–line bootstrap start–up circuit. Typical start–up current is 500 µA. current feedback loop. It has been shown that the instability is caused by a double pole at half the switching frequency. If an external ramp (Se) is added to the on–time ramp (Sn) of the current–sense waveform, stability can be achieved. One must be careful not to add too much ramp compensation. If too much is added the system will start to perform like a voltage mode regulator. All benefits of current mode control will be lost. Figure 25 is an example of one way in which external ramp compensation can be implemented. Output The MC34023 has a high current totem pole output specifically designed for direct drive of power MOSFETs. It is capable of up to ± 2.0 A peak drive current with a typical rise and fall time of 30 ns driving a 1.0 nF load. Separate pins for VC and Power Ground are provided. With proper implementation, a significant reduction of switching transient noise imposed on the control circuitry is possible. The separate VC supply input also allows the designer added flexibility in tailoring the drive voltage independent of VCC. Figure 20. Ramp Compensation Reference A 5.1 V bandgap reference is pinned out and is trimmed to an initial accuracy of ±1.0% at 25°C. This reference has short circuit protection and can source in excess of 10 mA for powering additional control system circuitry. Design Considerations Do not attempt to construct the converter on wire–wrap or plug–in prototype boards. With high frequency, high power, switching power supplies it is imperative to have separate current loops for the signal paths and for the power paths. The printed circuit layout should contain a ground plane with low current signal and high current switch and output grounds returning on separate paths back to the input filter capacitor. Shown in Figure 35 is a printed circuit layout of the application circuit. Note how the power and ground traces are run. All bypass capacitors and snubbers should be connected as close as possible to the specific part in question. The PC board lead lengths must be less than 0.5 inches for effective bypassing for snubbing. Instabilities In current mode control, an instability can be encountered at any given duty cycle. The instability is caused by the MOTOROLA ANALOG IC DEVICE DATA Ramp Compensation Ramp Input 1.25 V Ramp Compensation Se Current Signal Sn A simple equation can be used to calculate the amount of external ramp slope necessary to add that will achieve stability in the current loop. For the following equations, the calculated values for the application circuit in Figure 34 are also shown. Se where: VO = NP, NS = = Ai = = L= RS = + VO L ǒǓ NS NP (R S)A i DC output voltage number of power transformer primary or secondary turns gain of the current sense network (see Figures 23 and 24) output inductor current sense resistance For the application circuit: S e + 1.85 µ ǒǓ 2 (0.3)(0.55) 8 = 0.115 V/ms 9 MC34023 MC33023 PIN FUNCTION DESCRIPTION Pin DIP/SOIC Function Description 1 Error Amp Inverting Input This pin is usually used for feedback from the output of the power supply. 2 Error Amp Noninverting Input This pin is used to provide a reference in which an error signal can be produced on the output of the error amp. Usually this is connected to Vref, however an external reference can also be used. 3 Error Amp Output This pin is provided for compensating the error amp for poles and zeros encountered in the power supply system, mostly the output LC filter. 4 Clock This is a bidirectional pin used for synchronization. 5 RT The value of RT sets the charge current through timing Capacitor, CT. 6 CT In conjunction with RT, the timing Capacitor sets the switching frequency. 7 Ramp Input For voltage mode operation this pin is connected to CT. For current mode operation this pin is connected through a filter to the current sensing element. 8 Soft–Start A capacitor at this pin sets the Soft–Start time. 9 Current Limit/ Shutdown This pin has two functions. First, it provides cycle–by–cycle current limiting. Second, if the current is excessive, this pin will reinitiate a Soft–Start cycle. 10 Ground This pin is the ground for the control circuitry. 11 Current Limit Reference Input This pin voltage sets the threshold for cycle–by–cycle current limiting. 12 Power Ground This is a separate power ground return that is connected back to the power source. It is used to reduce the effects of switching transient noise on the control circuitry. 13 VC This is a separate power source connection for the outputs that is connected back to the power source input. With a separate power source connection, it can reduce the effects of switching transient noise on the control circuitry. 14 Output This is a high current totem pole output. 15 VCC This pin is the positive supply of the control IC. 16 Vref This is a 5.1 V reference. It is usually connected to the noninverting input of the error amplifier. Figure 21. Voltage Mode Operation Figure 22. Current Mode Operation 4 4 5 5 Oscillator Oscillator 6 CT 7 CT 1.25 V From Current Sense Element 7 Vref 2 In voltage mode operation, the control range on the output of the Error Amplifier from 0% to 90% duty cycle is from 2.25 V to 4.05 V. 10 1.25 V 3 1 3 1 Output Voltage Feedback Input 6 Output Voltage Feedback Input Vref 2 In current mode control, an RC filter should be placed at the ramp input to filter the leading edge spike caused by turn–on of a power MOSFET. MOTOROLA ANALOG IC DEVICE DATA MC34023 MC33023 Figure 23. Resistive Current Sensing Figure 24. Primary Side Current Sensing 9 9 i + ISense The addition of an RC filter will eliminate instability caused by the leading edge spike on the current waveform. This sense signal can also be used at the ramp input pin for current mode control. For ramp compensation it is necessary to know the gain of the current feedback loop. The gain can be calculated by: The addition of an RC filter will eliminate instability caused by the leading edge spike on the current waveform. This sense signal can also be used at the ramp input pin for current mode control. For ramp compensation it is necessary to know the gain of the current feedback loop. If a transformer is used, the gain can be calculated by: A Rw ISense R Sense A i turns ratio + Rw turns ratio Figure 25A. Slope Compensation (Noise Sensitive) 4 5 Oscillator 6 CT Current Sense Information C1 R1 R2 7 1.25 V 3 This method of slope compensation is easy to implement, however, it is noise sensitive. Capacitor C1 provides AC coupling. The oscillator signal is added to the current signal by a voltage divider consisting of resistors R1 and R2. Figure 25B. Slope Compensation (Noise Immune) Output Current Sense Transformer Rw Rf Output RM CM Ramp Input Figure 25. RM Ramp Input 7 1.25 V Cf 3 CM Current Sense Resistor Rf 7 1.25 V 3 Cf When only one output is used, this method of slope compensation can be used and it is relatively noise immune. Resistor RM and capacitor CM provide the added slope necessary. By choosing RM and CM with a larger time constant than the switching frequency, you can assume that its charge is linear. First choose CM, then RM can be adjusted to achieve the required slope. The diode provides a reset pulse at the ramp input at the end of every cycle. The charge current IM can be calculated by IM = CMSe. Then RM can be calculated by RM = VCC/IM. MOTOROLA ANALOG IC DEVICE DATA 11 MC34023 MC33023 Figure 27. External Clock Synchronization Figure 26. Dead Time Addition Vref 5.0 V 0V 4 RDT 4 5 5 6 6 RT Oscillator RT Oscillator CT CT Additional dead time can be added by the addition of a dead time resistor from Vref to CT. See text on Oscillator section for more information. The sync pulse fed into the clock pin must be at least 3.9 V. RT and CT need to be set 10% slower than the sync frequency. This circuit is also used in Voltage Mode operation for master/slave operation. The clock signal would be coming from the master which is set at the desired operating frequency, while the slave is set 10% slower. Figure 28. Current Mode Master/Slave Operation Over Short Distances 4 4 Vref 5 Master Oscillator Slave Oscillator 6 6 CT 5 RT Figure 29. Synchronization Over Long Distances Reference 20 16 MMBT3906 1.0 k 4 NC 4.7 k 4 2200 430 6 MMBT3904 CT 12 1.15 RT 5 6 5 Master Oscillator MMBD0914 RT Slave Oscillator CT MOTOROLA ANALOG IC DEVICE DATA MC34023 MC33023 Figure 30. Buffered Maximum Clamp Level Figure 31. Bipolar Transistor Drive IB 1 + 2 Vref R1 R2 – 8 Vin VC 0 + Base Charge Removal 15 CSS 14 12 In voltage mode operation, the maximum duty cycle can be clamped. By the addition of a PNP transistor to buffer the clamp voltage, the Soft–Start current is not affected by R1. RS The totem pole output can furnish negative base current for enhanced transistor turn–off, with the addition of the capacitor in series with the base. ) 0.6 (C SS) 9.0 µA In current mode operation, this circuit will limit the maximum voltage allowed at the ramp input to end a cycle. The new equation for Soft–Start is t [ V clamp To Current Sense Input Figure 33. Isolated MOSFET Drive Figure 32. MOSFET Parasitic Oscillations VC Vin VC 15 15 14 14 12 To Current Sense Input RS A series gate resistor may be needed to dampen high frequency parasitic oscillation caused by the MOSFET’s input capacitance and any series wiring inductance in the gate–source circuit. The series resistor will also decrease the MOSFET switching speed. A Schottky diode can reduce the driver’s power dissipation due to excessive ringing, by preventing the output pin from being driven below ground. The Schottky diode also prevents substrate injection when the output pin is driven below ground. MOTOROLA ANALOG IC DEVICE DATA 12 The totem pole output can easily drive pulse transformers. A Schottky diode is recommended when driving inductive loads at high frequencies. The diode can reduce the driver’s power dissipation due to excessive ringing, by preventing the output pin from being driven below ground. 13 14 2.0 k 22 k 0.01 8 Error Amp Q S R 9.0 µA PWM Comparator 4.2 V L1 – 2 turns #48 AWG (1300 strands litz wire) Core: Philips 3F3, part #EP10–3F3 Bobbin: Philips part #EP10PCB1–8 L = 1.8 µ H Coilcraft P3270–A S R Q 10 Soft–Start Latch 0.5 V PWM Latch Vref UVLO Reference Regulator T1 – Primary: 8 turns #48 AWG (1300 strands litz wire) Secondary: 2 turns 0.003’’ (2 layers) copper foil Bootstrap: 1 turn added to secondary #36 AWG Core: Philips 3F3, part #4312 020 4124 Bobbin: Philips part #4322 021 3525 Coilcraft P3269–A 0.1 Soft–Start 2 1 1.25 V Oscillator + 2 – 5(1.5 Ω ) resistors in parallel 1 – 10(1.0 µF) ceramic capacitors in parallel Insulators – All power devices are insulated with Berquist Sil–Pad 150 Heatsinks – Power FET: AAVID Heatsink #533902B02552 with clip Output Rectifiers: AAVID Heatsink #533402B02552 with clip 47 k Vref 3 6 1000 pF 0.015 µF 5 1.2 k 7 4 16 1.0 Vref 1.4 V Shutdown Current Limit 9.2 V VCC UVLO Condition V in = 48 V, IO = 7.5 A V in = 48 V, IO = 7.5 A Output Ripple Efficiency V in = 48 V, IO = 4.0 A to 7.5 A 220 pF 1.0 k 3.9 k MUR410 Result 10 µF L1 22 1500 pF 1 1.8 69.8% 10 mVp–p 54 mV = ± 1.0% 14 mV = ± 0.275% MBR2535 CTL 1500 pF 22 Load Regulation 100 T1 1600 pF 50 0.3 Ω 2 100 47 k V in = 40 V to 56 V, I O = 7.5A Test 47 100 47 IRF640 1N5819 4.7 10 10 4.7 1N5819 V in = 40 V to 56 V Line Regulation 9 11 12 14 13 15 Figure 34. Application Circuit VO = 5.0 V MC34023 MC33023 Figure 34. MOTOROLA ANALOG IC DEVICE DATA MC34023 MC33023 Figure 35. PC Board With Components MBR 2535CTI 1N5819 1N5819 +10 1000 pF 4.0″ 1N5819 MC34023 100 pF 100 pF 1500 pF 0.01 0.01 0.01 2200 pF MBR 2535CTI 100 1500 pF 6.5″ (Top View) MOTOROLA ANALOG IC DEVICE DATA 15 MC34023 MC33023 Figure 36. PC Board Without Components (Top View) 4.0″ 6.5″ (Bottom View) 16 MOTOROLA ANALOG IC DEVICE DATA MC34023 MC33023 OUTLINE DIMENSIONS P SUFFIX PLASTIC PACKAGE CASE 648–08 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL. –A– 16 9 1 8 B F C DIM A B C D F G H J K L M S L S –T– SEATING PLANE K H D 16 PL 0.25 (0.010) M M J G T A M INCHES MIN MAX 0.740 0.770 0.250 0.270 0.145 0.175 0.015 0.021 0.040 0.070 0.100 BSC 0.050 BSC 0.008 0.015 0.110 0.130 0.295 0.305 0° 10° 0.020 0.040 MILLIMETERS MIN MAX 18.80 19.55 6.35 6.85 3.69 4.44 0.39 0.53 1.02 1.77 2.54 BSC 1.27 BSC 0.21 0.38 2.80 3.30 7.50 7.74 0° 10° 0.51 1.01 DW SUFFIX PLASTIC PACKAGE CASE 751G–02 (SO–16L) –A– 16 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.13 (0.005) TOTAL IN EXCESS OF D DIMENSION AT MAXIMUM MATERIAL CONDITION. 9 –B– P 8 PL 0.25 (0.010) 1 M B M 8 G 14 PL J F R X 45° C –T– D 16 PL 0.25 (0.010) M K SEATING PLANE T A S MOTOROLA ANALOG IC DEVICE DATA B M DIM A B C D F G J K M P R INCHES MIN MAX 0.400 0.411 0.292 0.299 0.093 0.104 0.014 0.019 0.020 0.035 0.050 BSC 0.010 0.012 0.004 0.009 7° 0° 0.395 0.415 0.010 0.029 MILLIMETERS MIN MAX 10.15 10.45 7.60 7.40 2.65 2.35 0.49 0.35 0.90 0.50 1.27 BSC 0.32 0.25 0.25 0.10 7° 0° 10.05 10.55 0.25 0.75 S 17 MC34023 MC33023 OUTLINE DIMENSIONS FN SUFFIX PLASTIC PACKAGE CASE 775–02 (PLCC) B Y BRK –N– 0.007 (0.180) M T L –M D –L– U N S 0.007 (0.180) M T L –M S S N S –M– Z W D 1 20 V G1 X 0.010 (0.250) S T L –M N S S VIEW D–D A 0.007 (0.180) M T L –M S N S R 0.007 (0.180) M T L –M S N S Z C J PLANE F G1 S 0.007 (0.180) M T L –M S N S VIEW S S N S NOTES: 1. DATUMS –L–, –M–, AND –N– DETERMINED WHERE TOP OF LEAD SHOULDER EXITS PLASTIC BODY AT MOLD PARTING LINE. 2. DIM G1, TRUE POSITION TO BE MEASURED AT DATUM –T–, SEATING PLANE. 3. DIM R AND U DO NOT INCLUDE MOLD FLASH. ALLOWABLE MOLD FLASH IS 0.010 (0.250) PER SIDE. 4. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 5. CONTROLLING DIMENSION: INCH. 6. THE PACKAGE TOP MAY BE SMALLER THAN THE PACKAGE BOTTOM BY UP TO 0.012 (0.300). DIMENSIONS R AND U ARE DETERMINED AT THE OUTERMOST EXTREMES OF THE PLASTIC BODY EXCLUSIVE OF MOLD FLASH, TIE BAR BURRS, GATE BURRS AND INTERLEAD FLASH, BUT INCLUDING ANY MISMATCH BETWEEN THE TOP AND BOTTOM OF THE PLASTIC BODY. 7. DIMENSION H DOES NOT INCLUDE DAMBAR PROTRUSION OR INTRUSION. THE DAMBAR PROTRUSION(S) SHALL NOT CAUSE THE H DIMENSION TO BE GREATER THAN 0.037 (0.940). THE DAMBAR INTRUSION(S) SHALL NOT CAUSE THE H DIMENSION TO BE SMALLER THAN 0.025 (0.635). 18 N K 0.004 (0.100) SEATING –T– VIEW S 0.010 (0.250) S T L –M S K1 E G 0.007 (0.180) M T L –M H DIM A B C E F G H J K R U V W X Y Z G1 K1 INCHES MIN MAX 0.385 0.395 0.385 0.395 0.165 0.180 0.090 0.110 0.013 0.019 0.050 BSC 0.026 0.032 0.020 – 0.025 – 0.350 0.356 0.350 0.356 0.042 0.048 0.042 0.048 0.042 0.056 – 0.020 2° 10° 0.310 0.330 0.040 – MILLIMETERS MIN MAX 9.78 10.03 9.78 10.03 4.20 4.57 2.29 2.79 0.33 0.48 1.27 BSC 0.66 0.81 0.51 – 0.64 – 8.89 9.04 8.89 9.04 1.07 1.21 1.07 1.21 1.07 1.42 – 0.50 2° 10° 7.88 8.38 1.02 – MOTOROLA ANALOG IC DEVICE DATA MC34023 MC33023 Motorola reserves the right to make changes without further notice to any products herein. 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Mfax is a trademark of Motorola, Inc. How to reach us: USA / EUROPE / Locations Not Listed: Motorola Literature Distribution; P.O. Box 5405, Denver, Colorado 80217. 303–675–2140 or 1–800–441–2447 JAPAN: Nippon Motorola Ltd.: SPD, Strategic Planning Office, 4–32–1, Nishi–Gotanda, Shinagawa–ku, Tokyo 141, Japan. 81–3–5487–8488 Mfax: [email protected] – TOUCHTONE 602–244–6609 ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park, – US & Canada ONLY 1–800–774–1848 51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852–26629298 INTERNET: http://motorola.com/sps MOTOROLA ANALOG IC DEVICE ◊ DATA 19 MC34023/D